2 * Copyright (C) 2014-2015 Toradex AG
3 * Author: Stefan Agner <stefan@agner.ch>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 * IRQ chip driver for MSCM interrupt router available on Vybrid SoC's.
11 * The interrupt router is between the CPU's interrupt controller and the
12 * peripheral. The router allows to route the peripheral interrupts to
13 * one of the two available CPU's on Vybrid VF6xx SoC's (Cortex-A5 or
14 * Cortex-M4). The router will be configured transparently on a IRQ
17 * o All peripheral interrupts of the Vybrid SoC can be routed to
18 * CPU 0, CPU 1 or both. The routing is useful for dual-core
19 * variants of Vybrid SoC such as VF6xx. This driver routes the
20 * requested interrupt to the CPU currently running on.
22 * o It is required to setup the interrupt router even on single-core
26 #include <linux/cpu_pm.h>
28 #include <linux/irq.h>
29 #include <linux/irqchip.h>
30 #include <linux/irqdomain.h>
31 #include <linux/mfd/syscon.h>
32 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <linux/of_address.h>
35 #include <linux/slab.h>
36 #include <linux/regmap.h>
38 #define MSCM_CPxNUM 0x4
40 #define MSCM_IRSPRC(n) (0x80 + 2 * (n))
41 #define MSCM_IRSPRC_CPEN_MASK 0x3
43 #define MSCM_IRSPRC_NUM 112
45 struct vf610_mscm_ir_chip_data
{
46 void __iomem
*mscm_ir_base
;
48 u16 saved_irsprc
[MSCM_IRSPRC_NUM
];
52 static struct vf610_mscm_ir_chip_data
*mscm_ir_data
;
54 static inline void vf610_mscm_ir_save(struct vf610_mscm_ir_chip_data
*data
)
58 for (i
= 0; i
< MSCM_IRSPRC_NUM
; i
++)
59 data
->saved_irsprc
[i
] = readw_relaxed(data
->mscm_ir_base
+ MSCM_IRSPRC(i
));
62 static inline void vf610_mscm_ir_restore(struct vf610_mscm_ir_chip_data
*data
)
66 for (i
= 0; i
< MSCM_IRSPRC_NUM
; i
++)
67 writew_relaxed(data
->saved_irsprc
[i
], data
->mscm_ir_base
+ MSCM_IRSPRC(i
));
70 static int vf610_mscm_ir_notifier(struct notifier_block
*self
,
71 unsigned long cmd
, void *v
)
74 case CPU_CLUSTER_PM_ENTER
:
75 vf610_mscm_ir_save(mscm_ir_data
);
77 case CPU_CLUSTER_PM_ENTER_FAILED
:
78 case CPU_CLUSTER_PM_EXIT
:
79 vf610_mscm_ir_restore(mscm_ir_data
);
86 static struct notifier_block mscm_ir_notifier_block
= {
87 .notifier_call
= vf610_mscm_ir_notifier
,
90 static void vf610_mscm_ir_enable(struct irq_data
*data
)
92 irq_hw_number_t hwirq
= data
->hwirq
;
93 struct vf610_mscm_ir_chip_data
*chip_data
= data
->chip_data
;
96 irsprc
= readw_relaxed(chip_data
->mscm_ir_base
+ MSCM_IRSPRC(hwirq
));
97 irsprc
&= MSCM_IRSPRC_CPEN_MASK
;
99 WARN_ON(irsprc
& ~chip_data
->cpu_mask
);
101 writew_relaxed(chip_data
->cpu_mask
,
102 chip_data
->mscm_ir_base
+ MSCM_IRSPRC(hwirq
));
104 irq_chip_enable_parent(data
);
107 static void vf610_mscm_ir_disable(struct irq_data
*data
)
109 irq_hw_number_t hwirq
= data
->hwirq
;
110 struct vf610_mscm_ir_chip_data
*chip_data
= data
->chip_data
;
112 writew_relaxed(0x0, chip_data
->mscm_ir_base
+ MSCM_IRSPRC(hwirq
));
114 irq_chip_disable_parent(data
);
117 static struct irq_chip vf610_mscm_ir_irq_chip
= {
119 .irq_mask
= irq_chip_mask_parent
,
120 .irq_unmask
= irq_chip_unmask_parent
,
121 .irq_eoi
= irq_chip_eoi_parent
,
122 .irq_enable
= vf610_mscm_ir_enable
,
123 .irq_disable
= vf610_mscm_ir_disable
,
124 .irq_retrigger
= irq_chip_retrigger_hierarchy
,
125 .irq_set_affinity
= irq_chip_set_affinity_parent
,
128 static int vf610_mscm_ir_domain_alloc(struct irq_domain
*domain
, unsigned int virq
,
129 unsigned int nr_irqs
, void *arg
)
132 irq_hw_number_t hwirq
;
133 struct of_phandle_args
*irq_data
= arg
;
134 struct of_phandle_args gic_data
;
136 if (irq_data
->args_count
!= 2)
139 hwirq
= irq_data
->args
[0];
140 for (i
= 0; i
< nr_irqs
; i
++)
141 irq_domain_set_hwirq_and_chip(domain
, virq
+ i
, hwirq
+ i
,
142 &vf610_mscm_ir_irq_chip
,
145 gic_data
.np
= irq_domain_get_of_node(domain
->parent
);
147 if (mscm_ir_data
->is_nvic
) {
148 gic_data
.args_count
= 1;
149 gic_data
.args
[0] = irq_data
->args
[0];
151 gic_data
.args_count
= 3;
152 gic_data
.args
[0] = GIC_SPI
;
153 gic_data
.args
[1] = irq_data
->args
[0];
154 gic_data
.args
[2] = irq_data
->args
[1];
157 return irq_domain_alloc_irqs_parent(domain
, virq
, nr_irqs
, &gic_data
);
160 static const struct irq_domain_ops mscm_irq_domain_ops
= {
161 .xlate
= irq_domain_xlate_twocell
,
162 .alloc
= vf610_mscm_ir_domain_alloc
,
163 .free
= irq_domain_free_irqs_common
,
166 static int __init
vf610_mscm_ir_of_init(struct device_node
*node
,
167 struct device_node
*parent
)
169 struct irq_domain
*domain
, *domain_parent
;
170 struct regmap
*mscm_cp_regmap
;
173 domain_parent
= irq_find_host(parent
);
174 if (!domain_parent
) {
175 pr_err("vf610_mscm_ir: interrupt-parent not found\n");
179 mscm_ir_data
= kzalloc(sizeof(*mscm_ir_data
), GFP_KERNEL
);
183 mscm_ir_data
->mscm_ir_base
= of_io_request_and_map(node
, 0, "mscm-ir");
184 if (IS_ERR(mscm_ir_data
->mscm_ir_base
)) {
185 pr_err("vf610_mscm_ir: unable to map mscm register\n");
186 ret
= PTR_ERR(mscm_ir_data
->mscm_ir_base
);
190 mscm_cp_regmap
= syscon_regmap_lookup_by_phandle(node
, "fsl,cpucfg");
191 if (IS_ERR(mscm_cp_regmap
)) {
192 ret
= PTR_ERR(mscm_cp_regmap
);
193 pr_err("vf610_mscm_ir: regmap lookup for cpucfg failed\n");
197 regmap_read(mscm_cp_regmap
, MSCM_CPxNUM
, &cpuid
);
198 mscm_ir_data
->cpu_mask
= 0x1 << cpuid
;
200 domain
= irq_domain_add_hierarchy(domain_parent
, 0,
201 MSCM_IRSPRC_NUM
, node
,
202 &mscm_irq_domain_ops
, mscm_ir_data
);
208 if (of_device_is_compatible(irq_domain_get_of_node(domain
->parent
),
210 mscm_ir_data
->is_nvic
= true;
212 cpu_pm_register_notifier(&mscm_ir_notifier_block
);
217 iounmap(mscm_ir_data
->mscm_ir_base
);
222 IRQCHIP_DECLARE(vf610_mscm_ir
, "fsl,vf610-mscm-ir", vf610_mscm_ir_of_init
);