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mISDN: Allow to set a minimum length for transparent data
[deliverable/linux.git] / drivers / isdn / hardware / mISDN / hfcpci.c
1 /*
2 *
3 * hfcpci.c low level driver for CCD's hfc-pci based cards
4 *
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 * based on existing driver for CCD hfc ISA cards
7 * type approval valid for HFC-S PCI A based card
8 *
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil <kkeil@novell.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Module options:
27 *
28 * debug:
29 * NOTE: only one poll value must be given for all cards
30 * See hfc_pci.h for debug flags.
31 *
32 * poll:
33 * NOTE: only one poll value must be given for all cards
34 * Give the number of samples for each fifo process.
35 * By default 128 is used. Decrease to reduce delay, increase to
36 * reduce cpu load. If unsure, don't mess with it!
37 * A value of 128 will use controller's interrupt. Other values will
38 * use kernel timer, because the controller will not allow lower values
39 * than 128.
40 * Also note that the value depends on the kernel timer frequency.
41 * If kernel uses a frequency of 1000 Hz, steps of 8 samples are possible.
42 * If the kernel uses 100 Hz, steps of 80 samples are possible.
43 * If the kernel uses 300 Hz, steps of about 26 samples are possible.
44 *
45 */
46
47 #include <linux/interrupt.h>
48 #include <linux/module.h>
49 #include <linux/pci.h>
50 #include <linux/delay.h>
51 #include <linux/mISDNhw.h>
52 #include <linux/slab.h>
53
54 #include "hfc_pci.h"
55
56 static const char *hfcpci_revision = "2.0";
57
58 static int HFC_cnt;
59 static uint debug;
60 static uint poll, tics;
61 static struct timer_list hfc_tl;
62 static unsigned long hfc_jiffies;
63
64 MODULE_AUTHOR("Karsten Keil");
65 MODULE_LICENSE("GPL");
66 module_param(debug, uint, S_IRUGO | S_IWUSR);
67 module_param(poll, uint, S_IRUGO | S_IWUSR);
68
69 enum {
70 HFC_CCD_2BD0,
71 HFC_CCD_B000,
72 HFC_CCD_B006,
73 HFC_CCD_B007,
74 HFC_CCD_B008,
75 HFC_CCD_B009,
76 HFC_CCD_B00A,
77 HFC_CCD_B00B,
78 HFC_CCD_B00C,
79 HFC_CCD_B100,
80 HFC_CCD_B700,
81 HFC_CCD_B701,
82 HFC_ASUS_0675,
83 HFC_BERKOM_A1T,
84 HFC_BERKOM_TCONCEPT,
85 HFC_ANIGMA_MC145575,
86 HFC_ZOLTRIX_2BD0,
87 HFC_DIGI_DF_M_IOM2_E,
88 HFC_DIGI_DF_M_E,
89 HFC_DIGI_DF_M_IOM2_A,
90 HFC_DIGI_DF_M_A,
91 HFC_ABOCOM_2BD1,
92 HFC_SITECOM_DC105V2,
93 };
94
95 struct hfcPCI_hw {
96 unsigned char cirm;
97 unsigned char ctmt;
98 unsigned char clkdel;
99 unsigned char states;
100 unsigned char conn;
101 unsigned char mst_m;
102 unsigned char int_m1;
103 unsigned char int_m2;
104 unsigned char sctrl;
105 unsigned char sctrl_r;
106 unsigned char sctrl_e;
107 unsigned char trm;
108 unsigned char fifo_en;
109 unsigned char bswapped;
110 unsigned char protocol;
111 int nt_timer;
112 unsigned char __iomem *pci_io; /* start of PCI IO memory */
113 dma_addr_t dmahandle;
114 void *fifos; /* FIFO memory */
115 int last_bfifo_cnt[2];
116 /* marker saving last b-fifo frame count */
117 struct timer_list timer;
118 };
119
120 #define HFC_CFG_MASTER 1
121 #define HFC_CFG_SLAVE 2
122 #define HFC_CFG_PCM 3
123 #define HFC_CFG_2HFC 4
124 #define HFC_CFG_SLAVEHFC 5
125 #define HFC_CFG_NEG_F0 6
126 #define HFC_CFG_SW_DD_DU 7
127
128 #define FLG_HFC_TIMER_T1 16
129 #define FLG_HFC_TIMER_T3 17
130
131 #define NT_T1_COUNT 1120 /* number of 3.125ms interrupts (3.5s) */
132 #define NT_T3_COUNT 31 /* number of 3.125ms interrupts (97 ms) */
133 #define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
134 #define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
135
136
137 struct hfc_pci {
138 u_char subtype;
139 u_char chanlimit;
140 u_char initdone;
141 u_long cfg;
142 u_int irq;
143 u_int irqcnt;
144 struct pci_dev *pdev;
145 struct hfcPCI_hw hw;
146 spinlock_t lock; /* card lock */
147 struct dchannel dch;
148 struct bchannel bch[2];
149 };
150
151 /* Interface functions */
152 static void
153 enable_hwirq(struct hfc_pci *hc)
154 {
155 hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
156 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
157 }
158
159 static void
160 disable_hwirq(struct hfc_pci *hc)
161 {
162 hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
163 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
164 }
165
166 /*
167 * free hardware resources used by driver
168 */
169 static void
170 release_io_hfcpci(struct hfc_pci *hc)
171 {
172 /* disable memory mapped ports + busmaster */
173 pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
174 del_timer(&hc->hw.timer);
175 pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
176 iounmap(hc->hw.pci_io);
177 }
178
179 /*
180 * set mode (NT or TE)
181 */
182 static void
183 hfcpci_setmode(struct hfc_pci *hc)
184 {
185 if (hc->hw.protocol == ISDN_P_NT_S0) {
186 hc->hw.clkdel = CLKDEL_NT; /* ST-Bit delay for NT-Mode */
187 hc->hw.sctrl |= SCTRL_MODE_NT; /* NT-MODE */
188 hc->hw.states = 1; /* G1 */
189 } else {
190 hc->hw.clkdel = CLKDEL_TE; /* ST-Bit delay for TE-Mode */
191 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
192 hc->hw.states = 2; /* F2 */
193 }
194 Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
195 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
196 udelay(10);
197 Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
198 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
199 }
200
201 /*
202 * function called to reset the HFC PCI chip. A complete software reset of chip
203 * and fifos is done.
204 */
205 static void
206 reset_hfcpci(struct hfc_pci *hc)
207 {
208 u_char val;
209 int cnt = 0;
210
211 printk(KERN_DEBUG "reset_hfcpci: entered\n");
212 val = Read_hfc(hc, HFCPCI_CHIP_ID);
213 printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
214 /* enable memory mapped ports, disable busmaster */
215 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
216 disable_hwirq(hc);
217 /* enable memory ports + busmaster */
218 pci_write_config_word(hc->pdev, PCI_COMMAND,
219 PCI_ENA_MEMIO + PCI_ENA_MASTER);
220 val = Read_hfc(hc, HFCPCI_STATUS);
221 printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
222 hc->hw.cirm = HFCPCI_RESET; /* Reset On */
223 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
224 set_current_state(TASK_UNINTERRUPTIBLE);
225 mdelay(10); /* Timeout 10ms */
226 hc->hw.cirm = 0; /* Reset Off */
227 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
228 val = Read_hfc(hc, HFCPCI_STATUS);
229 printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
230 while (cnt < 50000) { /* max 50000 us */
231 udelay(5);
232 cnt += 5;
233 val = Read_hfc(hc, HFCPCI_STATUS);
234 if (!(val & 2))
235 break;
236 }
237 printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
238
239 hc->hw.fifo_en = 0x30; /* only D fifos enabled */
240
241 hc->hw.bswapped = 0; /* no exchange */
242 hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
243 hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
244 hc->hw.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
245 hc->hw.sctrl_r = 0;
246 hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE; /* S/T Auto awake */
247 hc->hw.mst_m = 0;
248 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
249 hc->hw.mst_m |= HFCPCI_MASTER; /* HFC Master Mode */
250 if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
251 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
252 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
253 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
254 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
255 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
256
257 hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
258 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
259 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
260
261 /* Clear already pending ints */
262 val = Read_hfc(hc, HFCPCI_INT_S1);
263
264 /* set NT/TE mode */
265 hfcpci_setmode(hc);
266
267 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
268 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
269
270 /*
271 * Init GCI/IOM2 in master mode
272 * Slots 0 and 1 are set for B-chan 1 and 2
273 * D- and monitor/CI channel are not enabled
274 * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
275 * STIO2 is used as data input, B1+B2 from IOM->ST
276 * ST B-channel send disabled -> continuous 1s
277 * The IOM slots are always enabled
278 */
279 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
280 /* set data flow directions: connect B1,B2: HFC to/from PCM */
281 hc->hw.conn = 0x09;
282 } else {
283 hc->hw.conn = 0x36; /* set data flow directions */
284 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
285 Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
286 Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
287 Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
288 Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
289 } else {
290 Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
291 Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
292 Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
293 Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
294 }
295 }
296 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
297 val = Read_hfc(hc, HFCPCI_INT_S2);
298 }
299
300 /*
301 * Timer function called when kernel timer expires
302 */
303 static void
304 hfcpci_Timer(struct hfc_pci *hc)
305 {
306 hc->hw.timer.expires = jiffies + 75;
307 /* WD RESET */
308 /*
309 * WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
310 * add_timer(&hc->hw.timer);
311 */
312 }
313
314
315 /*
316 * select a b-channel entry matching and active
317 */
318 static struct bchannel *
319 Sel_BCS(struct hfc_pci *hc, int channel)
320 {
321 if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
322 (hc->bch[0].nr & channel))
323 return &hc->bch[0];
324 else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
325 (hc->bch[1].nr & channel))
326 return &hc->bch[1];
327 else
328 return NULL;
329 }
330
331 /*
332 * clear the desired B-channel rx fifo
333 */
334 static void
335 hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
336 {
337 u_char fifo_state;
338 struct bzfifo *bzr;
339
340 if (fifo) {
341 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
342 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
343 } else {
344 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
345 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
346 }
347 if (fifo_state)
348 hc->hw.fifo_en ^= fifo_state;
349 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
350 hc->hw.last_bfifo_cnt[fifo] = 0;
351 bzr->f1 = MAX_B_FRAMES;
352 bzr->f2 = bzr->f1; /* init F pointers to remain constant */
353 bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
354 bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
355 le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
356 if (fifo_state)
357 hc->hw.fifo_en |= fifo_state;
358 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
359 }
360
361 /*
362 * clear the desired B-channel tx fifo
363 */
364 static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
365 {
366 u_char fifo_state;
367 struct bzfifo *bzt;
368
369 if (fifo) {
370 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
371 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
372 } else {
373 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
374 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
375 }
376 if (fifo_state)
377 hc->hw.fifo_en ^= fifo_state;
378 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
379 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
380 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
381 "z1(%x) z2(%x) state(%x)\n",
382 fifo, bzt->f1, bzt->f2,
383 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
384 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
385 fifo_state);
386 bzt->f2 = MAX_B_FRAMES;
387 bzt->f1 = bzt->f2; /* init F pointers to remain constant */
388 bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
389 bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
390 if (fifo_state)
391 hc->hw.fifo_en |= fifo_state;
392 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
393 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
394 printk(KERN_DEBUG
395 "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
396 fifo, bzt->f1, bzt->f2,
397 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
398 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
399 }
400
401 /*
402 * read a complete B-frame out of the buffer
403 */
404 static void
405 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
406 u_char *bdata, int count)
407 {
408 u_char *ptr, *ptr1, new_f2;
409 int maxlen, new_z2;
410 struct zt *zp;
411
412 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
413 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
414 zp = &bz->za[bz->f2]; /* point to Z-Regs */
415 new_z2 = le16_to_cpu(zp->z2) + count; /* new position in fifo */
416 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
417 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
418 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
419 if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
420 (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
421 if (bch->debug & DEBUG_HW)
422 printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
423 "invalid length %d or crc\n", count);
424 #ifdef ERROR_STATISTIC
425 bch->err_inv++;
426 #endif
427 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
428 bz->f2 = new_f2; /* next buffer */
429 } else {
430 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
431 if (!bch->rx_skb) {
432 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
433 return;
434 }
435 count -= 3;
436 ptr = skb_put(bch->rx_skb, count);
437
438 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
439 maxlen = count; /* complete transfer */
440 else
441 maxlen = B_FIFO_SIZE + B_SUB_VAL -
442 le16_to_cpu(zp->z2); /* maximum */
443
444 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
445 /* start of data */
446 memcpy(ptr, ptr1, maxlen); /* copy data */
447 count -= maxlen;
448
449 if (count) { /* rest remaining */
450 ptr += maxlen;
451 ptr1 = bdata; /* start of buffer */
452 memcpy(ptr, ptr1, count); /* rest */
453 }
454 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
455 bz->f2 = new_f2; /* next buffer */
456 recv_Bchannel(bch, MISDN_ID_ANY, false);
457 }
458 }
459
460 /*
461 * D-channel receive procedure
462 */
463 static int
464 receive_dmsg(struct hfc_pci *hc)
465 {
466 struct dchannel *dch = &hc->dch;
467 int maxlen;
468 int rcnt, total;
469 int count = 5;
470 u_char *ptr, *ptr1;
471 struct dfifo *df;
472 struct zt *zp;
473
474 df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
475 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
476 zp = &df->za[df->f2 & D_FREG_MASK];
477 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
478 if (rcnt < 0)
479 rcnt += D_FIFO_SIZE;
480 rcnt++;
481 if (dch->debug & DEBUG_HW_DCHANNEL)
482 printk(KERN_DEBUG
483 "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
484 df->f1, df->f2,
485 le16_to_cpu(zp->z1),
486 le16_to_cpu(zp->z2),
487 rcnt);
488
489 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
490 (df->data[le16_to_cpu(zp->z1)])) {
491 if (dch->debug & DEBUG_HW)
492 printk(KERN_DEBUG
493 "empty_fifo hfcpci paket inv. len "
494 "%d or crc %d\n",
495 rcnt,
496 df->data[le16_to_cpu(zp->z1)]);
497 #ifdef ERROR_STATISTIC
498 cs->err_rx++;
499 #endif
500 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
501 (MAX_D_FRAMES + 1); /* next buffer */
502 df->za[df->f2 & D_FREG_MASK].z2 =
503 cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) &
504 (D_FIFO_SIZE - 1));
505 } else {
506 dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
507 if (!dch->rx_skb) {
508 printk(KERN_WARNING
509 "HFC-PCI: D receive out of memory\n");
510 break;
511 }
512 total = rcnt;
513 rcnt -= 3;
514 ptr = skb_put(dch->rx_skb, rcnt);
515
516 if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
517 maxlen = rcnt; /* complete transfer */
518 else
519 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
520 /* maximum */
521
522 ptr1 = df->data + le16_to_cpu(zp->z2);
523 /* start of data */
524 memcpy(ptr, ptr1, maxlen); /* copy data */
525 rcnt -= maxlen;
526
527 if (rcnt) { /* rest remaining */
528 ptr += maxlen;
529 ptr1 = df->data; /* start of buffer */
530 memcpy(ptr, ptr1, rcnt); /* rest */
531 }
532 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
533 (MAX_D_FRAMES + 1); /* next buffer */
534 df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
535 le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
536 recv_Dchannel(dch);
537 }
538 }
539 return 1;
540 }
541
542 /*
543 * check for transparent receive data and read max one 'poll' size if avail
544 */
545 static void
546 hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *rxbz,
547 struct bzfifo *txbz, u_char *bdata)
548 {
549 __le16 *z1r, *z2r, *z1t, *z2t;
550 int new_z2, fcnt_rx, fcnt_tx, maxlen;
551 u_char *ptr, *ptr1;
552
553 z1r = &rxbz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
554 z2r = z1r + 1;
555 z1t = &txbz->za[MAX_B_FRAMES].z1;
556 z2t = z1t + 1;
557
558 fcnt_rx = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
559 if (!fcnt_rx)
560 return; /* no data avail */
561
562 if (fcnt_rx <= 0)
563 fcnt_rx += B_FIFO_SIZE; /* bytes actually buffered */
564 new_z2 = le16_to_cpu(*z2r) + fcnt_rx; /* new position in fifo */
565 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
566 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
567
568 if (fcnt_rx > MAX_DATA_SIZE) { /* flush, if oversized */
569 *z2r = cpu_to_le16(new_z2); /* new position */
570 return;
571 }
572
573 fcnt_tx = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
574 if (fcnt_tx <= 0)
575 fcnt_tx += B_FIFO_SIZE;
576 /* fcnt_tx contains available bytes in tx-fifo */
577 fcnt_tx = B_FIFO_SIZE - fcnt_tx;
578 /* remaining bytes to send (bytes in tx-fifo) */
579
580 maxlen = bchannel_get_rxbuf(bch, fcnt_rx);
581 if (maxlen < 0) {
582 pr_warning("B%d: No bufferspace for %d bytes\n",
583 bch->nr, fcnt_rx);
584 } else {
585 ptr = skb_put(bch->rx_skb, fcnt_rx);
586 if (le16_to_cpu(*z2r) + fcnt_rx <= B_FIFO_SIZE + B_SUB_VAL)
587 maxlen = fcnt_rx; /* complete transfer */
588 else
589 maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
590 /* maximum */
591
592 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
593 /* start of data */
594 memcpy(ptr, ptr1, maxlen); /* copy data */
595 fcnt_rx -= maxlen;
596
597 if (fcnt_rx) { /* rest remaining */
598 ptr += maxlen;
599 ptr1 = bdata; /* start of buffer */
600 memcpy(ptr, ptr1, fcnt_rx); /* rest */
601 }
602 recv_Bchannel(bch, fcnt_tx, false); /* bch, id, !force */
603 }
604 *z2r = cpu_to_le16(new_z2); /* new position */
605 }
606
607 /*
608 * B-channel main receive routine
609 */
610 static void
611 main_rec_hfcpci(struct bchannel *bch)
612 {
613 struct hfc_pci *hc = bch->hw;
614 int rcnt, real_fifo;
615 int receive = 0, count = 5;
616 struct bzfifo *txbz, *rxbz;
617 u_char *bdata;
618 struct zt *zp;
619
620 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
621 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
622 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
623 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
624 real_fifo = 1;
625 } else {
626 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
627 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
628 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
629 real_fifo = 0;
630 }
631 Begin:
632 count--;
633 if (rxbz->f1 != rxbz->f2) {
634 if (bch->debug & DEBUG_HW_BCHANNEL)
635 printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
636 bch->nr, rxbz->f1, rxbz->f2);
637 zp = &rxbz->za[rxbz->f2];
638
639 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
640 if (rcnt < 0)
641 rcnt += B_FIFO_SIZE;
642 rcnt++;
643 if (bch->debug & DEBUG_HW_BCHANNEL)
644 printk(KERN_DEBUG
645 "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
646 bch->nr, le16_to_cpu(zp->z1),
647 le16_to_cpu(zp->z2), rcnt);
648 hfcpci_empty_bfifo(bch, rxbz, bdata, rcnt);
649 rcnt = rxbz->f1 - rxbz->f2;
650 if (rcnt < 0)
651 rcnt += MAX_B_FRAMES + 1;
652 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
653 rcnt = 0;
654 hfcpci_clear_fifo_rx(hc, real_fifo);
655 }
656 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
657 if (rcnt > 1)
658 receive = 1;
659 else
660 receive = 0;
661 } else if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
662 hfcpci_empty_fifo_trans(bch, rxbz, txbz, bdata);
663 return;
664 } else
665 receive = 0;
666 if (count && receive)
667 goto Begin;
668
669 }
670
671 /*
672 * D-channel send routine
673 */
674 static void
675 hfcpci_fill_dfifo(struct hfc_pci *hc)
676 {
677 struct dchannel *dch = &hc->dch;
678 int fcnt;
679 int count, new_z1, maxlen;
680 struct dfifo *df;
681 u_char *src, *dst, new_f1;
682
683 if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
684 printk(KERN_DEBUG "%s\n", __func__);
685
686 if (!dch->tx_skb)
687 return;
688 count = dch->tx_skb->len - dch->tx_idx;
689 if (count <= 0)
690 return;
691 df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
692
693 if (dch->debug & DEBUG_HW_DFIFO)
694 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
695 df->f1, df->f2,
696 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
697 fcnt = df->f1 - df->f2; /* frame count actually buffered */
698 if (fcnt < 0)
699 fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
700 if (fcnt > (MAX_D_FRAMES - 1)) {
701 if (dch->debug & DEBUG_HW_DCHANNEL)
702 printk(KERN_DEBUG
703 "hfcpci_fill_Dfifo more as 14 frames\n");
704 #ifdef ERROR_STATISTIC
705 cs->err_tx++;
706 #endif
707 return;
708 }
709 /* now determine free bytes in FIFO buffer */
710 maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
711 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
712 if (maxlen <= 0)
713 maxlen += D_FIFO_SIZE; /* count now contains available bytes */
714
715 if (dch->debug & DEBUG_HW_DCHANNEL)
716 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
717 count, maxlen);
718 if (count > maxlen) {
719 if (dch->debug & DEBUG_HW_DCHANNEL)
720 printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
721 return;
722 }
723 new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
724 (D_FIFO_SIZE - 1);
725 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
726 src = dch->tx_skb->data + dch->tx_idx; /* source pointer */
727 dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
728 maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
729 /* end fifo */
730 if (maxlen > count)
731 maxlen = count; /* limit size */
732 memcpy(dst, src, maxlen); /* first copy */
733
734 count -= maxlen; /* remaining bytes */
735 if (count) {
736 dst = df->data; /* start of buffer */
737 src += maxlen; /* new position */
738 memcpy(dst, src, count);
739 }
740 df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
741 /* for next buffer */
742 df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
743 /* new pos actual buffer */
744 df->f1 = new_f1; /* next frame */
745 dch->tx_idx = dch->tx_skb->len;
746 }
747
748 /*
749 * B-channel send routine
750 */
751 static void
752 hfcpci_fill_fifo(struct bchannel *bch)
753 {
754 struct hfc_pci *hc = bch->hw;
755 int maxlen, fcnt;
756 int count, new_z1;
757 struct bzfifo *bz;
758 u_char *bdata;
759 u_char new_f1, *src, *dst;
760 __le16 *z1t, *z2t;
761
762 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
763 printk(KERN_DEBUG "%s\n", __func__);
764 if ((!bch->tx_skb) || bch->tx_skb->len <= 0)
765 return;
766 count = bch->tx_skb->len - bch->tx_idx;
767 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
768 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
769 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
770 } else {
771 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
772 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
773 }
774
775 if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
776 z1t = &bz->za[MAX_B_FRAMES].z1;
777 z2t = z1t + 1;
778 if (bch->debug & DEBUG_HW_BCHANNEL)
779 printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
780 "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
781 le16_to_cpu(*z1t), le16_to_cpu(*z2t));
782 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
783 if (fcnt <= 0)
784 fcnt += B_FIFO_SIZE;
785 /* fcnt contains available bytes in fifo */
786 fcnt = B_FIFO_SIZE - fcnt;
787 /* remaining bytes to send (bytes in fifo) */
788
789 /* "fill fifo if empty" feature */
790 if (test_bit(FLG_FILLEMPTY, &bch->Flags) && !fcnt) {
791 /* printk(KERN_DEBUG "%s: buffer empty, so we have "
792 "underrun\n", __func__); */
793 /* fill buffer, to prevent future underrun */
794 count = HFCPCI_FILLEMPTY;
795 new_z1 = le16_to_cpu(*z1t) + count;
796 /* new buffer Position */
797 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
798 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
799 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
800 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
801 /* end of fifo */
802 if (bch->debug & DEBUG_HW_BFIFO)
803 printk(KERN_DEBUG "hfcpci_FFt fillempty "
804 "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
805 fcnt, maxlen, new_z1, dst);
806 fcnt += count;
807 if (maxlen > count)
808 maxlen = count; /* limit size */
809 memset(dst, 0x2a, maxlen); /* first copy */
810 count -= maxlen; /* remaining bytes */
811 if (count) {
812 dst = bdata; /* start of buffer */
813 memset(dst, 0x2a, count);
814 }
815 *z1t = cpu_to_le16(new_z1); /* now send data */
816 }
817
818 next_t_frame:
819 count = bch->tx_skb->len - bch->tx_idx;
820 /* maximum fill shall be poll*2 */
821 if (count > (poll << 1) - fcnt)
822 count = (poll << 1) - fcnt;
823 if (count <= 0)
824 return;
825 /* data is suitable for fifo */
826 new_z1 = le16_to_cpu(*z1t) + count;
827 /* new buffer Position */
828 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
829 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
830 src = bch->tx_skb->data + bch->tx_idx;
831 /* source pointer */
832 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
833 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
834 /* end of fifo */
835 if (bch->debug & DEBUG_HW_BFIFO)
836 printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
837 "maxl(%d) nz1(%x) dst(%p)\n",
838 fcnt, maxlen, new_z1, dst);
839 fcnt += count;
840 bch->tx_idx += count;
841 if (maxlen > count)
842 maxlen = count; /* limit size */
843 memcpy(dst, src, maxlen); /* first copy */
844 count -= maxlen; /* remaining bytes */
845 if (count) {
846 dst = bdata; /* start of buffer */
847 src += maxlen; /* new position */
848 memcpy(dst, src, count);
849 }
850 *z1t = cpu_to_le16(new_z1); /* now send data */
851 if (bch->tx_idx < bch->tx_skb->len)
852 return;
853 dev_kfree_skb(bch->tx_skb);
854 if (get_next_bframe(bch))
855 goto next_t_frame;
856 return;
857 }
858 if (bch->debug & DEBUG_HW_BCHANNEL)
859 printk(KERN_DEBUG
860 "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
861 __func__, bch->nr, bz->f1, bz->f2,
862 bz->za[bz->f1].z1);
863 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
864 if (fcnt < 0)
865 fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
866 if (fcnt > (MAX_B_FRAMES - 1)) {
867 if (bch->debug & DEBUG_HW_BCHANNEL)
868 printk(KERN_DEBUG
869 "hfcpci_fill_Bfifo more as 14 frames\n");
870 return;
871 }
872 /* now determine free bytes in FIFO buffer */
873 maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
874 le16_to_cpu(bz->za[bz->f1].z1) - 1;
875 if (maxlen <= 0)
876 maxlen += B_FIFO_SIZE; /* count now contains available bytes */
877
878 if (bch->debug & DEBUG_HW_BCHANNEL)
879 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
880 bch->nr, count, maxlen);
881
882 if (maxlen < count) {
883 if (bch->debug & DEBUG_HW_BCHANNEL)
884 printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
885 return;
886 }
887 new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
888 /* new buffer Position */
889 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
890 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
891
892 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
893 src = bch->tx_skb->data + bch->tx_idx; /* source pointer */
894 dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
895 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
896 /* end fifo */
897 if (maxlen > count)
898 maxlen = count; /* limit size */
899 memcpy(dst, src, maxlen); /* first copy */
900
901 count -= maxlen; /* remaining bytes */
902 if (count) {
903 dst = bdata; /* start of buffer */
904 src += maxlen; /* new position */
905 memcpy(dst, src, count);
906 }
907 bz->za[new_f1].z1 = cpu_to_le16(new_z1); /* for next buffer */
908 bz->f1 = new_f1; /* next frame */
909 dev_kfree_skb(bch->tx_skb);
910 get_next_bframe(bch);
911 }
912
913
914
915 /*
916 * handle L1 state changes TE
917 */
918
919 static void
920 ph_state_te(struct dchannel *dch)
921 {
922 if (dch->debug)
923 printk(KERN_DEBUG "%s: TE newstate %x\n",
924 __func__, dch->state);
925 switch (dch->state) {
926 case 0:
927 l1_event(dch->l1, HW_RESET_IND);
928 break;
929 case 3:
930 l1_event(dch->l1, HW_DEACT_IND);
931 break;
932 case 5:
933 case 8:
934 l1_event(dch->l1, ANYSIGNAL);
935 break;
936 case 6:
937 l1_event(dch->l1, INFO2);
938 break;
939 case 7:
940 l1_event(dch->l1, INFO4_P8);
941 break;
942 }
943 }
944
945 /*
946 * handle L1 state changes NT
947 */
948
949 static void
950 handle_nt_timer3(struct dchannel *dch) {
951 struct hfc_pci *hc = dch->hw;
952
953 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
954 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
955 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
956 hc->hw.nt_timer = 0;
957 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
958 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
959 hc->hw.mst_m |= HFCPCI_MASTER;
960 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
961 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
962 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
963 }
964
965 static void
966 ph_state_nt(struct dchannel *dch)
967 {
968 struct hfc_pci *hc = dch->hw;
969
970 if (dch->debug)
971 printk(KERN_DEBUG "%s: NT newstate %x\n",
972 __func__, dch->state);
973 switch (dch->state) {
974 case 2:
975 if (hc->hw.nt_timer < 0) {
976 hc->hw.nt_timer = 0;
977 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
978 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
979 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
980 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
981 /* Clear already pending ints */
982 (void) Read_hfc(hc, HFCPCI_INT_S1);
983 Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
984 udelay(10);
985 Write_hfc(hc, HFCPCI_STATES, 4);
986 dch->state = 4;
987 } else if (hc->hw.nt_timer == 0) {
988 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
989 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
990 hc->hw.nt_timer = NT_T1_COUNT;
991 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
992 hc->hw.ctmt |= HFCPCI_TIM3_125;
993 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
994 HFCPCI_CLTIMER);
995 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
996 test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
997 /* allow G2 -> G3 transition */
998 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
999 } else {
1000 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
1001 }
1002 break;
1003 case 1:
1004 hc->hw.nt_timer = 0;
1005 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1006 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1007 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1008 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1009 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1010 hc->hw.mst_m &= ~HFCPCI_MASTER;
1011 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1012 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1013 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
1014 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1015 break;
1016 case 4:
1017 hc->hw.nt_timer = 0;
1018 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1019 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1020 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1021 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1022 break;
1023 case 3:
1024 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
1025 if (!test_and_clear_bit(FLG_L2_ACTIVATED,
1026 &dch->Flags)) {
1027 handle_nt_timer3(dch);
1028 break;
1029 }
1030 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1031 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
1032 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1033 hc->hw.nt_timer = NT_T3_COUNT;
1034 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
1035 hc->hw.ctmt |= HFCPCI_TIM3_125;
1036 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
1037 HFCPCI_CLTIMER);
1038 }
1039 break;
1040 }
1041 }
1042
1043 static void
1044 ph_state(struct dchannel *dch)
1045 {
1046 struct hfc_pci *hc = dch->hw;
1047
1048 if (hc->hw.protocol == ISDN_P_NT_S0) {
1049 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
1050 hc->hw.nt_timer < 0)
1051 handle_nt_timer3(dch);
1052 else
1053 ph_state_nt(dch);
1054 } else
1055 ph_state_te(dch);
1056 }
1057
1058 /*
1059 * Layer 1 callback function
1060 */
1061 static int
1062 hfc_l1callback(struct dchannel *dch, u_int cmd)
1063 {
1064 struct hfc_pci *hc = dch->hw;
1065
1066 switch (cmd) {
1067 case INFO3_P8:
1068 case INFO3_P10:
1069 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1070 hc->hw.mst_m |= HFCPCI_MASTER;
1071 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1072 break;
1073 case HW_RESET_REQ:
1074 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1075 /* HFC ST 3 */
1076 udelay(6);
1077 Write_hfc(hc, HFCPCI_STATES, 3); /* HFC ST 2 */
1078 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1079 hc->hw.mst_m |= HFCPCI_MASTER;
1080 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1081 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1082 HFCPCI_DO_ACTION);
1083 l1_event(dch->l1, HW_POWERUP_IND);
1084 break;
1085 case HW_DEACT_REQ:
1086 hc->hw.mst_m &= ~HFCPCI_MASTER;
1087 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1088 skb_queue_purge(&dch->squeue);
1089 if (dch->tx_skb) {
1090 dev_kfree_skb(dch->tx_skb);
1091 dch->tx_skb = NULL;
1092 }
1093 dch->tx_idx = 0;
1094 if (dch->rx_skb) {
1095 dev_kfree_skb(dch->rx_skb);
1096 dch->rx_skb = NULL;
1097 }
1098 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1099 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1100 del_timer(&dch->timer);
1101 break;
1102 case HW_POWERUP_REQ:
1103 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1104 break;
1105 case PH_ACTIVATE_IND:
1106 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1107 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1108 GFP_ATOMIC);
1109 break;
1110 case PH_DEACTIVATE_IND:
1111 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1112 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1113 GFP_ATOMIC);
1114 break;
1115 default:
1116 if (dch->debug & DEBUG_HW)
1117 printk(KERN_DEBUG "%s: unknown command %x\n",
1118 __func__, cmd);
1119 return -1;
1120 }
1121 return 0;
1122 }
1123
1124 /*
1125 * Interrupt handler
1126 */
1127 static inline void
1128 tx_birq(struct bchannel *bch)
1129 {
1130 if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1131 hfcpci_fill_fifo(bch);
1132 else {
1133 if (bch->tx_skb)
1134 dev_kfree_skb(bch->tx_skb);
1135 if (get_next_bframe(bch))
1136 hfcpci_fill_fifo(bch);
1137 }
1138 }
1139
1140 static inline void
1141 tx_dirq(struct dchannel *dch)
1142 {
1143 if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1144 hfcpci_fill_dfifo(dch->hw);
1145 else {
1146 if (dch->tx_skb)
1147 dev_kfree_skb(dch->tx_skb);
1148 if (get_next_dframe(dch))
1149 hfcpci_fill_dfifo(dch->hw);
1150 }
1151 }
1152
1153 static irqreturn_t
1154 hfcpci_int(int intno, void *dev_id)
1155 {
1156 struct hfc_pci *hc = dev_id;
1157 u_char exval;
1158 struct bchannel *bch;
1159 u_char val, stat;
1160
1161 spin_lock(&hc->lock);
1162 if (!(hc->hw.int_m2 & 0x08)) {
1163 spin_unlock(&hc->lock);
1164 return IRQ_NONE; /* not initialised */
1165 }
1166 stat = Read_hfc(hc, HFCPCI_STATUS);
1167 if (HFCPCI_ANYINT & stat) {
1168 val = Read_hfc(hc, HFCPCI_INT_S1);
1169 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1170 printk(KERN_DEBUG
1171 "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1172 } else {
1173 /* shared */
1174 spin_unlock(&hc->lock);
1175 return IRQ_NONE;
1176 }
1177 hc->irqcnt++;
1178
1179 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1180 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1181 val &= hc->hw.int_m1;
1182 if (val & 0x40) { /* state machine irq */
1183 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1184 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1185 printk(KERN_DEBUG "ph_state chg %d->%d\n",
1186 hc->dch.state, exval);
1187 hc->dch.state = exval;
1188 schedule_event(&hc->dch, FLG_PHCHANGE);
1189 val &= ~0x40;
1190 }
1191 if (val & 0x80) { /* timer irq */
1192 if (hc->hw.protocol == ISDN_P_NT_S0) {
1193 if ((--hc->hw.nt_timer) < 0)
1194 schedule_event(&hc->dch, FLG_PHCHANGE);
1195 }
1196 val &= ~0x80;
1197 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1198 }
1199 if (val & 0x08) { /* B1 rx */
1200 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1201 if (bch)
1202 main_rec_hfcpci(bch);
1203 else if (hc->dch.debug)
1204 printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1205 }
1206 if (val & 0x10) { /* B2 rx */
1207 bch = Sel_BCS(hc, 2);
1208 if (bch)
1209 main_rec_hfcpci(bch);
1210 else if (hc->dch.debug)
1211 printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1212 }
1213 if (val & 0x01) { /* B1 tx */
1214 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1215 if (bch)
1216 tx_birq(bch);
1217 else if (hc->dch.debug)
1218 printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1219 }
1220 if (val & 0x02) { /* B2 tx */
1221 bch = Sel_BCS(hc, 2);
1222 if (bch)
1223 tx_birq(bch);
1224 else if (hc->dch.debug)
1225 printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1226 }
1227 if (val & 0x20) /* D rx */
1228 receive_dmsg(hc);
1229 if (val & 0x04) { /* D tx */
1230 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1231 del_timer(&hc->dch.timer);
1232 tx_dirq(&hc->dch);
1233 }
1234 spin_unlock(&hc->lock);
1235 return IRQ_HANDLED;
1236 }
1237
1238 /*
1239 * timer callback for D-chan busy resolution. Currently no function
1240 */
1241 static void
1242 hfcpci_dbusy_timer(struct hfc_pci *hc)
1243 {
1244 }
1245
1246 /*
1247 * activate/deactivate hardware for selected channels and mode
1248 */
1249 static int
1250 mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1251 {
1252 struct hfc_pci *hc = bch->hw;
1253 int fifo2;
1254 u_char rx_slot = 0, tx_slot = 0, pcm_mode;
1255
1256 if (bch->debug & DEBUG_HW_BCHANNEL)
1257 printk(KERN_DEBUG
1258 "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1259 bch->state, protocol, bch->nr, bc);
1260
1261 fifo2 = bc;
1262 pcm_mode = (bc >> 24) & 0xff;
1263 if (pcm_mode) { /* PCM SLOT USE */
1264 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1265 printk(KERN_WARNING
1266 "%s: pcm channel id without HFC_CFG_PCM\n",
1267 __func__);
1268 rx_slot = (bc >> 8) & 0xff;
1269 tx_slot = (bc >> 16) & 0xff;
1270 bc = bc & 0xff;
1271 } else if (test_bit(HFC_CFG_PCM, &hc->cfg) && (protocol > ISDN_P_NONE))
1272 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1273 __func__);
1274 if (hc->chanlimit > 1) {
1275 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1276 hc->hw.sctrl_e &= ~0x80;
1277 } else {
1278 if (bc & 2) {
1279 if (protocol != ISDN_P_NONE) {
1280 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1281 hc->hw.sctrl_e |= 0x80;
1282 } else {
1283 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1284 hc->hw.sctrl_e &= ~0x80;
1285 }
1286 fifo2 = 1;
1287 } else {
1288 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1289 hc->hw.sctrl_e &= ~0x80;
1290 }
1291 }
1292 switch (protocol) {
1293 case (-1): /* used for init */
1294 bch->state = -1;
1295 bch->nr = bc;
1296 case (ISDN_P_NONE):
1297 if (bch->state == ISDN_P_NONE)
1298 return 0;
1299 if (bc & 2) {
1300 hc->hw.sctrl &= ~SCTRL_B2_ENA;
1301 hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1302 } else {
1303 hc->hw.sctrl &= ~SCTRL_B1_ENA;
1304 hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1305 }
1306 if (fifo2 & 2) {
1307 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1308 hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS +
1309 HFCPCI_INTS_B2REC);
1310 } else {
1311 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1312 hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS +
1313 HFCPCI_INTS_B1REC);
1314 }
1315 #ifdef REVERSE_BITORDER
1316 if (bch->nr & 2)
1317 hc->hw.cirm &= 0x7f;
1318 else
1319 hc->hw.cirm &= 0xbf;
1320 #endif
1321 bch->state = ISDN_P_NONE;
1322 bch->nr = bc;
1323 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1324 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1325 break;
1326 case (ISDN_P_B_RAW):
1327 bch->state = protocol;
1328 bch->nr = bc;
1329 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1330 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1331 if (bc & 2) {
1332 hc->hw.sctrl |= SCTRL_B2_ENA;
1333 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1334 #ifdef REVERSE_BITORDER
1335 hc->hw.cirm |= 0x80;
1336 #endif
1337 } else {
1338 hc->hw.sctrl |= SCTRL_B1_ENA;
1339 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1340 #ifdef REVERSE_BITORDER
1341 hc->hw.cirm |= 0x40;
1342 #endif
1343 }
1344 if (fifo2 & 2) {
1345 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1346 if (!tics)
1347 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1348 HFCPCI_INTS_B2REC);
1349 hc->hw.ctmt |= 2;
1350 hc->hw.conn &= ~0x18;
1351 } else {
1352 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1353 if (!tics)
1354 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1355 HFCPCI_INTS_B1REC);
1356 hc->hw.ctmt |= 1;
1357 hc->hw.conn &= ~0x03;
1358 }
1359 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1360 break;
1361 case (ISDN_P_B_HDLC):
1362 bch->state = protocol;
1363 bch->nr = bc;
1364 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1365 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1366 if (bc & 2) {
1367 hc->hw.sctrl |= SCTRL_B2_ENA;
1368 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1369 } else {
1370 hc->hw.sctrl |= SCTRL_B1_ENA;
1371 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1372 }
1373 if (fifo2 & 2) {
1374 hc->hw.last_bfifo_cnt[1] = 0;
1375 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1376 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1377 HFCPCI_INTS_B2REC);
1378 hc->hw.ctmt &= ~2;
1379 hc->hw.conn &= ~0x18;
1380 } else {
1381 hc->hw.last_bfifo_cnt[0] = 0;
1382 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1383 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1384 HFCPCI_INTS_B1REC);
1385 hc->hw.ctmt &= ~1;
1386 hc->hw.conn &= ~0x03;
1387 }
1388 test_and_set_bit(FLG_HDLC, &bch->Flags);
1389 break;
1390 default:
1391 printk(KERN_DEBUG "prot not known %x\n", protocol);
1392 return -ENOPROTOOPT;
1393 }
1394 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1395 if ((protocol == ISDN_P_NONE) ||
1396 (protocol == -1)) { /* init case */
1397 rx_slot = 0;
1398 tx_slot = 0;
1399 } else {
1400 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1401 rx_slot |= 0xC0;
1402 tx_slot |= 0xC0;
1403 } else {
1404 rx_slot |= 0x80;
1405 tx_slot |= 0x80;
1406 }
1407 }
1408 if (bc & 2) {
1409 hc->hw.conn &= 0xc7;
1410 hc->hw.conn |= 0x08;
1411 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1412 __func__, tx_slot);
1413 printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1414 __func__, rx_slot);
1415 Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1416 Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1417 } else {
1418 hc->hw.conn &= 0xf8;
1419 hc->hw.conn |= 0x01;
1420 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1421 __func__, tx_slot);
1422 printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1423 __func__, rx_slot);
1424 Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1425 Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1426 }
1427 }
1428 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1429 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1430 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1431 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1432 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1433 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1434 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1435 #ifdef REVERSE_BITORDER
1436 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1437 #endif
1438 return 0;
1439 }
1440
1441 static int
1442 set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1443 {
1444 struct hfc_pci *hc = bch->hw;
1445
1446 if (bch->debug & DEBUG_HW_BCHANNEL)
1447 printk(KERN_DEBUG
1448 "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1449 bch->state, protocol, bch->nr, chan);
1450 if (bch->nr != chan) {
1451 printk(KERN_DEBUG
1452 "HFCPCI rxtest wrong channel parameter %x/%x\n",
1453 bch->nr, chan);
1454 return -EINVAL;
1455 }
1456 switch (protocol) {
1457 case (ISDN_P_B_RAW):
1458 bch->state = protocol;
1459 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1460 if (chan & 2) {
1461 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1462 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1463 if (!tics)
1464 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1465 hc->hw.ctmt |= 2;
1466 hc->hw.conn &= ~0x18;
1467 #ifdef REVERSE_BITORDER
1468 hc->hw.cirm |= 0x80;
1469 #endif
1470 } else {
1471 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1472 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1473 if (!tics)
1474 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1475 hc->hw.ctmt |= 1;
1476 hc->hw.conn &= ~0x03;
1477 #ifdef REVERSE_BITORDER
1478 hc->hw.cirm |= 0x40;
1479 #endif
1480 }
1481 break;
1482 case (ISDN_P_B_HDLC):
1483 bch->state = protocol;
1484 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1485 if (chan & 2) {
1486 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1487 hc->hw.last_bfifo_cnt[1] = 0;
1488 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1489 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1490 hc->hw.ctmt &= ~2;
1491 hc->hw.conn &= ~0x18;
1492 } else {
1493 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1494 hc->hw.last_bfifo_cnt[0] = 0;
1495 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1496 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1497 hc->hw.ctmt &= ~1;
1498 hc->hw.conn &= ~0x03;
1499 }
1500 break;
1501 default:
1502 printk(KERN_DEBUG "prot not known %x\n", protocol);
1503 return -ENOPROTOOPT;
1504 }
1505 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1506 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1507 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1508 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1509 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1510 #ifdef REVERSE_BITORDER
1511 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1512 #endif
1513 return 0;
1514 }
1515
1516 static void
1517 deactivate_bchannel(struct bchannel *bch)
1518 {
1519 struct hfc_pci *hc = bch->hw;
1520 u_long flags;
1521
1522 spin_lock_irqsave(&hc->lock, flags);
1523 mISDN_clear_bchannel(bch);
1524 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1525 spin_unlock_irqrestore(&hc->lock, flags);
1526 }
1527
1528 /*
1529 * Layer 1 B-channel hardware access
1530 */
1531 static int
1532 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1533 {
1534 int ret = 0;
1535
1536 switch (cq->op) {
1537 case MISDN_CTRL_GETOP:
1538 ret = mISDN_ctrl_bchannel(bch, cq);
1539 cq->op |= MISDN_CTRL_FILL_EMPTY;
1540 break;
1541 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
1542 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
1543 if (debug & DEBUG_HW_OPEN)
1544 printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
1545 "off=%d)\n", __func__, bch->nr, !!cq->p1);
1546 break;
1547 default:
1548 ret = mISDN_ctrl_bchannel(bch, cq);
1549 break;
1550 }
1551 return ret;
1552 }
1553 static int
1554 hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1555 {
1556 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1557 struct hfc_pci *hc = bch->hw;
1558 int ret = -EINVAL;
1559 u_long flags;
1560
1561 if (bch->debug & DEBUG_HW)
1562 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1563 switch (cmd) {
1564 case HW_TESTRX_RAW:
1565 spin_lock_irqsave(&hc->lock, flags);
1566 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1567 spin_unlock_irqrestore(&hc->lock, flags);
1568 break;
1569 case HW_TESTRX_HDLC:
1570 spin_lock_irqsave(&hc->lock, flags);
1571 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1572 spin_unlock_irqrestore(&hc->lock, flags);
1573 break;
1574 case HW_TESTRX_OFF:
1575 spin_lock_irqsave(&hc->lock, flags);
1576 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1577 spin_unlock_irqrestore(&hc->lock, flags);
1578 ret = 0;
1579 break;
1580 case CLOSE_CHANNEL:
1581 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1582 deactivate_bchannel(bch);
1583 ch->protocol = ISDN_P_NONE;
1584 ch->peer = NULL;
1585 module_put(THIS_MODULE);
1586 ret = 0;
1587 break;
1588 case CONTROL_CHANNEL:
1589 ret = channel_bctrl(bch, arg);
1590 break;
1591 default:
1592 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1593 __func__, cmd);
1594 }
1595 return ret;
1596 }
1597
1598 /*
1599 * Layer2 -> Layer 1 Dchannel data
1600 */
1601 static int
1602 hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1603 {
1604 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1605 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1606 struct hfc_pci *hc = dch->hw;
1607 int ret = -EINVAL;
1608 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1609 unsigned int id;
1610 u_long flags;
1611
1612 switch (hh->prim) {
1613 case PH_DATA_REQ:
1614 spin_lock_irqsave(&hc->lock, flags);
1615 ret = dchannel_senddata(dch, skb);
1616 if (ret > 0) { /* direct TX */
1617 id = hh->id; /* skb can be freed */
1618 hfcpci_fill_dfifo(dch->hw);
1619 ret = 0;
1620 spin_unlock_irqrestore(&hc->lock, flags);
1621 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1622 } else
1623 spin_unlock_irqrestore(&hc->lock, flags);
1624 return ret;
1625 case PH_ACTIVATE_REQ:
1626 spin_lock_irqsave(&hc->lock, flags);
1627 if (hc->hw.protocol == ISDN_P_NT_S0) {
1628 ret = 0;
1629 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1630 hc->hw.mst_m |= HFCPCI_MASTER;
1631 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1632 if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1633 spin_unlock_irqrestore(&hc->lock, flags);
1634 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1635 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1636 break;
1637 }
1638 test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1639 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1640 HFCPCI_DO_ACTION | 1);
1641 } else
1642 ret = l1_event(dch->l1, hh->prim);
1643 spin_unlock_irqrestore(&hc->lock, flags);
1644 break;
1645 case PH_DEACTIVATE_REQ:
1646 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1647 spin_lock_irqsave(&hc->lock, flags);
1648 if (hc->hw.protocol == ISDN_P_NT_S0) {
1649 /* prepare deactivation */
1650 Write_hfc(hc, HFCPCI_STATES, 0x40);
1651 skb_queue_purge(&dch->squeue);
1652 if (dch->tx_skb) {
1653 dev_kfree_skb(dch->tx_skb);
1654 dch->tx_skb = NULL;
1655 }
1656 dch->tx_idx = 0;
1657 if (dch->rx_skb) {
1658 dev_kfree_skb(dch->rx_skb);
1659 dch->rx_skb = NULL;
1660 }
1661 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1662 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1663 del_timer(&dch->timer);
1664 #ifdef FIXME
1665 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1666 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1667 #endif
1668 hc->hw.mst_m &= ~HFCPCI_MASTER;
1669 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1670 ret = 0;
1671 } else {
1672 ret = l1_event(dch->l1, hh->prim);
1673 }
1674 spin_unlock_irqrestore(&hc->lock, flags);
1675 break;
1676 }
1677 if (!ret)
1678 dev_kfree_skb(skb);
1679 return ret;
1680 }
1681
1682 /*
1683 * Layer2 -> Layer 1 Bchannel data
1684 */
1685 static int
1686 hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1687 {
1688 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1689 struct hfc_pci *hc = bch->hw;
1690 int ret = -EINVAL;
1691 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1692 unsigned long flags;
1693
1694 switch (hh->prim) {
1695 case PH_DATA_REQ:
1696 spin_lock_irqsave(&hc->lock, flags);
1697 ret = bchannel_senddata(bch, skb);
1698 if (ret > 0) { /* direct TX */
1699 hfcpci_fill_fifo(bch);
1700 ret = 0;
1701 }
1702 spin_unlock_irqrestore(&hc->lock, flags);
1703 return ret;
1704 case PH_ACTIVATE_REQ:
1705 spin_lock_irqsave(&hc->lock, flags);
1706 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1707 ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1708 else
1709 ret = 0;
1710 spin_unlock_irqrestore(&hc->lock, flags);
1711 if (!ret)
1712 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1713 NULL, GFP_KERNEL);
1714 break;
1715 case PH_DEACTIVATE_REQ:
1716 deactivate_bchannel(bch);
1717 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1718 NULL, GFP_KERNEL);
1719 ret = 0;
1720 break;
1721 }
1722 if (!ret)
1723 dev_kfree_skb(skb);
1724 return ret;
1725 }
1726
1727 /*
1728 * called for card init message
1729 */
1730
1731 static void
1732 inithfcpci(struct hfc_pci *hc)
1733 {
1734 printk(KERN_DEBUG "inithfcpci: entered\n");
1735 hc->dch.timer.function = (void *) hfcpci_dbusy_timer;
1736 hc->dch.timer.data = (long) &hc->dch;
1737 init_timer(&hc->dch.timer);
1738 hc->chanlimit = 2;
1739 mode_hfcpci(&hc->bch[0], 1, -1);
1740 mode_hfcpci(&hc->bch[1], 2, -1);
1741 }
1742
1743
1744 static int
1745 init_card(struct hfc_pci *hc)
1746 {
1747 int cnt = 3;
1748 u_long flags;
1749
1750 printk(KERN_DEBUG "init_card: entered\n");
1751
1752
1753 spin_lock_irqsave(&hc->lock, flags);
1754 disable_hwirq(hc);
1755 spin_unlock_irqrestore(&hc->lock, flags);
1756 if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1757 printk(KERN_WARNING
1758 "mISDN: couldn't get interrupt %d\n", hc->irq);
1759 return -EIO;
1760 }
1761 spin_lock_irqsave(&hc->lock, flags);
1762 reset_hfcpci(hc);
1763 while (cnt) {
1764 inithfcpci(hc);
1765 /*
1766 * Finally enable IRQ output
1767 * this is only allowed, if an IRQ routine is already
1768 * established for this HFC, so don't do that earlier
1769 */
1770 enable_hwirq(hc);
1771 spin_unlock_irqrestore(&hc->lock, flags);
1772 /* Timeout 80ms */
1773 current->state = TASK_UNINTERRUPTIBLE;
1774 schedule_timeout((80 * HZ) / 1000);
1775 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1776 hc->irq, hc->irqcnt);
1777 /* now switch timer interrupt off */
1778 spin_lock_irqsave(&hc->lock, flags);
1779 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1780 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1781 /* reinit mode reg */
1782 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1783 if (!hc->irqcnt) {
1784 printk(KERN_WARNING
1785 "HFC PCI: IRQ(%d) getting no interrupts "
1786 "during init %d\n", hc->irq, 4 - cnt);
1787 if (cnt == 1)
1788 break;
1789 else {
1790 reset_hfcpci(hc);
1791 cnt--;
1792 }
1793 } else {
1794 spin_unlock_irqrestore(&hc->lock, flags);
1795 hc->initdone = 1;
1796 return 0;
1797 }
1798 }
1799 disable_hwirq(hc);
1800 spin_unlock_irqrestore(&hc->lock, flags);
1801 free_irq(hc->irq, hc);
1802 return -EIO;
1803 }
1804
1805 static int
1806 channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1807 {
1808 int ret = 0;
1809 u_char slot;
1810
1811 switch (cq->op) {
1812 case MISDN_CTRL_GETOP:
1813 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1814 MISDN_CTRL_DISCONNECT | MISDN_CTRL_L1_TIMER3;
1815 break;
1816 case MISDN_CTRL_LOOP:
1817 /* channel 0 disabled loop */
1818 if (cq->channel < 0 || cq->channel > 2) {
1819 ret = -EINVAL;
1820 break;
1821 }
1822 if (cq->channel & 1) {
1823 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1824 slot = 0xC0;
1825 else
1826 slot = 0x80;
1827 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1828 __func__, slot);
1829 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1830 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1831 hc->hw.conn = (hc->hw.conn & ~7) | 6;
1832 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1833 }
1834 if (cq->channel & 2) {
1835 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1836 slot = 0xC1;
1837 else
1838 slot = 0x81;
1839 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1840 __func__, slot);
1841 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1842 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1843 hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1844 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1845 }
1846 if (cq->channel & 3)
1847 hc->hw.trm |= 0x80; /* enable IOM-loop */
1848 else {
1849 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1850 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1851 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1852 }
1853 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1854 break;
1855 case MISDN_CTRL_CONNECT:
1856 if (cq->channel == cq->p1) {
1857 ret = -EINVAL;
1858 break;
1859 }
1860 if (cq->channel < 1 || cq->channel > 2 ||
1861 cq->p1 < 1 || cq->p1 > 2) {
1862 ret = -EINVAL;
1863 break;
1864 }
1865 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1866 slot = 0xC0;
1867 else
1868 slot = 0x80;
1869 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1870 __func__, slot);
1871 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1872 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1873 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1874 slot = 0xC1;
1875 else
1876 slot = 0x81;
1877 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1878 __func__, slot);
1879 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1880 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1881 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1882 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1883 hc->hw.trm |= 0x80;
1884 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1885 break;
1886 case MISDN_CTRL_DISCONNECT:
1887 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1888 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1889 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1890 break;
1891 case MISDN_CTRL_L1_TIMER3:
1892 ret = l1_event(hc->dch.l1, HW_TIMER3_VALUE | (cq->p1 & 0xff));
1893 break;
1894 default:
1895 printk(KERN_WARNING "%s: unknown Op %x\n",
1896 __func__, cq->op);
1897 ret = -EINVAL;
1898 break;
1899 }
1900 return ret;
1901 }
1902
1903 static int
1904 open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1905 struct channel_req *rq)
1906 {
1907 int err = 0;
1908
1909 if (debug & DEBUG_HW_OPEN)
1910 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1911 hc->dch.dev.id, __builtin_return_address(0));
1912 if (rq->protocol == ISDN_P_NONE)
1913 return -EINVAL;
1914 if (rq->adr.channel == 1) {
1915 /* TODO: E-Channel */
1916 return -EINVAL;
1917 }
1918 if (!hc->initdone) {
1919 if (rq->protocol == ISDN_P_TE_S0) {
1920 err = create_l1(&hc->dch, hfc_l1callback);
1921 if (err)
1922 return err;
1923 }
1924 hc->hw.protocol = rq->protocol;
1925 ch->protocol = rq->protocol;
1926 err = init_card(hc);
1927 if (err)
1928 return err;
1929 } else {
1930 if (rq->protocol != ch->protocol) {
1931 if (hc->hw.protocol == ISDN_P_TE_S0)
1932 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1933 if (rq->protocol == ISDN_P_TE_S0) {
1934 err = create_l1(&hc->dch, hfc_l1callback);
1935 if (err)
1936 return err;
1937 }
1938 hc->hw.protocol = rq->protocol;
1939 ch->protocol = rq->protocol;
1940 hfcpci_setmode(hc);
1941 }
1942 }
1943
1944 if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1945 ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1946 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1947 0, NULL, GFP_KERNEL);
1948 }
1949 rq->ch = ch;
1950 if (!try_module_get(THIS_MODULE))
1951 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1952 return 0;
1953 }
1954
1955 static int
1956 open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1957 {
1958 struct bchannel *bch;
1959
1960 if (rq->adr.channel == 0 || rq->adr.channel > 2)
1961 return -EINVAL;
1962 if (rq->protocol == ISDN_P_NONE)
1963 return -EINVAL;
1964 bch = &hc->bch[rq->adr.channel - 1];
1965 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1966 return -EBUSY; /* b-channel can be only open once */
1967 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1968 bch->ch.protocol = rq->protocol;
1969 rq->ch = &bch->ch; /* TODO: E-channel */
1970 if (!try_module_get(THIS_MODULE))
1971 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1972 return 0;
1973 }
1974
1975 /*
1976 * device control function
1977 */
1978 static int
1979 hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1980 {
1981 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1982 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1983 struct hfc_pci *hc = dch->hw;
1984 struct channel_req *rq;
1985 int err = 0;
1986
1987 if (dch->debug & DEBUG_HW)
1988 printk(KERN_DEBUG "%s: cmd:%x %p\n",
1989 __func__, cmd, arg);
1990 switch (cmd) {
1991 case OPEN_CHANNEL:
1992 rq = arg;
1993 if ((rq->protocol == ISDN_P_TE_S0) ||
1994 (rq->protocol == ISDN_P_NT_S0))
1995 err = open_dchannel(hc, ch, rq);
1996 else
1997 err = open_bchannel(hc, rq);
1998 break;
1999 case CLOSE_CHANNEL:
2000 if (debug & DEBUG_HW_OPEN)
2001 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
2002 __func__, hc->dch.dev.id,
2003 __builtin_return_address(0));
2004 module_put(THIS_MODULE);
2005 break;
2006 case CONTROL_CHANNEL:
2007 err = channel_ctrl(hc, arg);
2008 break;
2009 default:
2010 if (dch->debug & DEBUG_HW)
2011 printk(KERN_DEBUG "%s: unknown command %x\n",
2012 __func__, cmd);
2013 return -EINVAL;
2014 }
2015 return err;
2016 }
2017
2018 static int
2019 setup_hw(struct hfc_pci *hc)
2020 {
2021 void *buffer;
2022
2023 printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
2024 hc->hw.cirm = 0;
2025 hc->dch.state = 0;
2026 pci_set_master(hc->pdev);
2027 if (!hc->irq) {
2028 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
2029 return 1;
2030 }
2031 hc->hw.pci_io =
2032 (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
2033
2034 if (!hc->hw.pci_io) {
2035 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
2036 return 1;
2037 }
2038 /* Allocate memory for FIFOS */
2039 /* the memory needs to be on a 32k boundary within the first 4G */
2040 pci_set_dma_mask(hc->pdev, 0xFFFF8000);
2041 buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
2042 /* We silently assume the address is okay if nonzero */
2043 if (!buffer) {
2044 printk(KERN_WARNING
2045 "HFC-PCI: Error allocating memory for FIFO!\n");
2046 return 1;
2047 }
2048 hc->hw.fifos = buffer;
2049 pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
2050 hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
2051 printk(KERN_INFO
2052 "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
2053 (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos,
2054 (u_long) hc->hw.dmahandle, hc->irq, HZ);
2055 /* enable memory mapped ports, disable busmaster */
2056 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
2057 hc->hw.int_m2 = 0;
2058 disable_hwirq(hc);
2059 hc->hw.int_m1 = 0;
2060 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
2061 /* At this point the needed PCI config is done */
2062 /* fifos are still not enabled */
2063 hc->hw.timer.function = (void *) hfcpci_Timer;
2064 hc->hw.timer.data = (long) hc;
2065 init_timer(&hc->hw.timer);
2066 /* default PCM master */
2067 test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2068 return 0;
2069 }
2070
2071 static void
2072 release_card(struct hfc_pci *hc) {
2073 u_long flags;
2074
2075 spin_lock_irqsave(&hc->lock, flags);
2076 hc->hw.int_m2 = 0; /* interrupt output off ! */
2077 disable_hwirq(hc);
2078 mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2079 mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2080 if (hc->dch.timer.function != NULL) {
2081 del_timer(&hc->dch.timer);
2082 hc->dch.timer.function = NULL;
2083 }
2084 spin_unlock_irqrestore(&hc->lock, flags);
2085 if (hc->hw.protocol == ISDN_P_TE_S0)
2086 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2087 if (hc->initdone)
2088 free_irq(hc->irq, hc);
2089 release_io_hfcpci(hc); /* must release after free_irq! */
2090 mISDN_unregister_device(&hc->dch.dev);
2091 mISDN_freebchannel(&hc->bch[1]);
2092 mISDN_freebchannel(&hc->bch[0]);
2093 mISDN_freedchannel(&hc->dch);
2094 pci_set_drvdata(hc->pdev, NULL);
2095 kfree(hc);
2096 }
2097
2098 static int
2099 setup_card(struct hfc_pci *card)
2100 {
2101 int err = -EINVAL;
2102 u_int i;
2103 char name[MISDN_MAX_IDLEN];
2104
2105 card->dch.debug = debug;
2106 spin_lock_init(&card->lock);
2107 mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2108 card->dch.hw = card;
2109 card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2110 card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2111 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2112 card->dch.dev.D.send = hfcpci_l2l1D;
2113 card->dch.dev.D.ctrl = hfc_dctrl;
2114 card->dch.dev.nrbchan = 2;
2115 for (i = 0; i < 2; i++) {
2116 card->bch[i].nr = i + 1;
2117 set_channelmap(i + 1, card->dch.dev.channelmap);
2118 card->bch[i].debug = debug;
2119 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM, poll >> 1);
2120 card->bch[i].hw = card;
2121 card->bch[i].ch.send = hfcpci_l2l1B;
2122 card->bch[i].ch.ctrl = hfc_bctrl;
2123 card->bch[i].ch.nr = i + 1;
2124 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2125 }
2126 err = setup_hw(card);
2127 if (err)
2128 goto error;
2129 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
2130 err = mISDN_register_device(&card->dch.dev, &card->pdev->dev, name);
2131 if (err)
2132 goto error;
2133 HFC_cnt++;
2134 printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2135 return 0;
2136 error:
2137 mISDN_freebchannel(&card->bch[1]);
2138 mISDN_freebchannel(&card->bch[0]);
2139 mISDN_freedchannel(&card->dch);
2140 kfree(card);
2141 return err;
2142 }
2143
2144 /* private data in the PCI devices list */
2145 struct _hfc_map {
2146 u_int subtype;
2147 u_int flag;
2148 char *name;
2149 };
2150
2151 static const struct _hfc_map hfc_map[] =
2152 {
2153 {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2154 {HFC_CCD_B000, 0, "Billion B000"},
2155 {HFC_CCD_B006, 0, "Billion B006"},
2156 {HFC_CCD_B007, 0, "Billion B007"},
2157 {HFC_CCD_B008, 0, "Billion B008"},
2158 {HFC_CCD_B009, 0, "Billion B009"},
2159 {HFC_CCD_B00A, 0, "Billion B00A"},
2160 {HFC_CCD_B00B, 0, "Billion B00B"},
2161 {HFC_CCD_B00C, 0, "Billion B00C"},
2162 {HFC_CCD_B100, 0, "Seyeon B100"},
2163 {HFC_CCD_B700, 0, "Primux II S0 B700"},
2164 {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2165 {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2166 {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2167 {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2168 {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2169 {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2170 {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2171 {HFC_DIGI_DF_M_IOM2_E, 0,
2172 "Digi International DataFire Micro V IOM2 (Europe)"},
2173 {HFC_DIGI_DF_M_E, 0,
2174 "Digi International DataFire Micro V (Europe)"},
2175 {HFC_DIGI_DF_M_IOM2_A, 0,
2176 "Digi International DataFire Micro V IOM2 (North America)"},
2177 {HFC_DIGI_DF_M_A, 0,
2178 "Digi International DataFire Micro V (North America)"},
2179 {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2180 {},
2181 };
2182
2183 static struct pci_device_id hfc_ids[] =
2184 {
2185 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_2BD0),
2186 (unsigned long) &hfc_map[0] },
2187 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B000),
2188 (unsigned long) &hfc_map[1] },
2189 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B006),
2190 (unsigned long) &hfc_map[2] },
2191 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B007),
2192 (unsigned long) &hfc_map[3] },
2193 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B008),
2194 (unsigned long) &hfc_map[4] },
2195 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B009),
2196 (unsigned long) &hfc_map[5] },
2197 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00A),
2198 (unsigned long) &hfc_map[6] },
2199 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00B),
2200 (unsigned long) &hfc_map[7] },
2201 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00C),
2202 (unsigned long) &hfc_map[8] },
2203 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B100),
2204 (unsigned long) &hfc_map[9] },
2205 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B700),
2206 (unsigned long) &hfc_map[10] },
2207 { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B701),
2208 (unsigned long) &hfc_map[11] },
2209 { PCI_VDEVICE(ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1),
2210 (unsigned long) &hfc_map[12] },
2211 { PCI_VDEVICE(ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675),
2212 (unsigned long) &hfc_map[13] },
2213 { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT),
2214 (unsigned long) &hfc_map[14] },
2215 { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_A1T),
2216 (unsigned long) &hfc_map[15] },
2217 { PCI_VDEVICE(ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575),
2218 (unsigned long) &hfc_map[16] },
2219 { PCI_VDEVICE(ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0),
2220 (unsigned long) &hfc_map[17] },
2221 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E),
2222 (unsigned long) &hfc_map[18] },
2223 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_E),
2224 (unsigned long) &hfc_map[19] },
2225 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A),
2226 (unsigned long) &hfc_map[20] },
2227 { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_A),
2228 (unsigned long) &hfc_map[21] },
2229 { PCI_VDEVICE(SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2),
2230 (unsigned long) &hfc_map[22] },
2231 {},
2232 };
2233
2234 static int __devinit
2235 hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2236 {
2237 int err = -ENOMEM;
2238 struct hfc_pci *card;
2239 struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2240
2241 card = kzalloc(sizeof(struct hfc_pci), GFP_ATOMIC);
2242 if (!card) {
2243 printk(KERN_ERR "No kmem for HFC card\n");
2244 return err;
2245 }
2246 card->pdev = pdev;
2247 card->subtype = m->subtype;
2248 err = pci_enable_device(pdev);
2249 if (err) {
2250 kfree(card);
2251 return err;
2252 }
2253
2254 printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2255 m->name, pci_name(pdev));
2256
2257 card->irq = pdev->irq;
2258 pci_set_drvdata(pdev, card);
2259 err = setup_card(card);
2260 if (err)
2261 pci_set_drvdata(pdev, NULL);
2262 return err;
2263 }
2264
2265 static void __devexit
2266 hfc_remove_pci(struct pci_dev *pdev)
2267 {
2268 struct hfc_pci *card = pci_get_drvdata(pdev);
2269
2270 if (card)
2271 release_card(card);
2272 else
2273 if (debug)
2274 printk(KERN_DEBUG "%s: drvdata already removed\n",
2275 __func__);
2276 }
2277
2278
2279 static struct pci_driver hfc_driver = {
2280 .name = "hfcpci",
2281 .probe = hfc_probe,
2282 .remove = __devexit_p(hfc_remove_pci),
2283 .id_table = hfc_ids,
2284 };
2285
2286 static int
2287 _hfcpci_softirq(struct device *dev, void *arg)
2288 {
2289 struct hfc_pci *hc = dev_get_drvdata(dev);
2290 struct bchannel *bch;
2291 if (hc == NULL)
2292 return 0;
2293
2294 if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) {
2295 spin_lock(&hc->lock);
2296 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
2297 if (bch && bch->state == ISDN_P_B_RAW) { /* B1 rx&tx */
2298 main_rec_hfcpci(bch);
2299 tx_birq(bch);
2300 }
2301 bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2);
2302 if (bch && bch->state == ISDN_P_B_RAW) { /* B2 rx&tx */
2303 main_rec_hfcpci(bch);
2304 tx_birq(bch);
2305 }
2306 spin_unlock(&hc->lock);
2307 }
2308 return 0;
2309 }
2310
2311 static void
2312 hfcpci_softirq(void *arg)
2313 {
2314 (void) driver_for_each_device(&hfc_driver.driver, NULL, arg,
2315 _hfcpci_softirq);
2316
2317 /* if next event would be in the past ... */
2318 if ((s32)(hfc_jiffies + tics - jiffies) <= 0)
2319 hfc_jiffies = jiffies + 1;
2320 else
2321 hfc_jiffies += tics;
2322 hfc_tl.expires = hfc_jiffies;
2323 add_timer(&hfc_tl);
2324 }
2325
2326 static int __init
2327 HFC_init(void)
2328 {
2329 int err;
2330
2331 if (!poll)
2332 poll = HFCPCI_BTRANS_THRESHOLD;
2333
2334 if (poll != HFCPCI_BTRANS_THRESHOLD) {
2335 tics = (poll * HZ) / 8000;
2336 if (tics < 1)
2337 tics = 1;
2338 poll = (tics * 8000) / HZ;
2339 if (poll > 256 || poll < 8) {
2340 printk(KERN_ERR "%s: Wrong poll value %d not in range "
2341 "of 8..256.\n", __func__, poll);
2342 err = -EINVAL;
2343 return err;
2344 }
2345 }
2346 if (poll != HFCPCI_BTRANS_THRESHOLD) {
2347 printk(KERN_INFO "%s: Using alternative poll value of %d\n",
2348 __func__, poll);
2349 hfc_tl.function = (void *)hfcpci_softirq;
2350 hfc_tl.data = 0;
2351 init_timer(&hfc_tl);
2352 hfc_tl.expires = jiffies + tics;
2353 hfc_jiffies = hfc_tl.expires;
2354 add_timer(&hfc_tl);
2355 } else
2356 tics = 0; /* indicate the use of controller's timer */
2357
2358 err = pci_register_driver(&hfc_driver);
2359 if (err) {
2360 if (timer_pending(&hfc_tl))
2361 del_timer(&hfc_tl);
2362 }
2363
2364 return err;
2365 }
2366
2367 static void __exit
2368 HFC_cleanup(void)
2369 {
2370 if (timer_pending(&hfc_tl))
2371 del_timer(&hfc_tl);
2372
2373 pci_unregister_driver(&hfc_driver);
2374 }
2375
2376 module_init(HFC_init);
2377 module_exit(HFC_cleanup);
2378
2379 MODULE_DEVICE_TABLE(pci, hfc_ids);
Linux kernel - Deliverables
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