drivers/kvm/i8259.c

   1 /*
   2  * 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2007 Intel Corporation
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  * Authors:
  25  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
  26  *   Port from Qemu.
  27  */
  28 #include <linux/mm.h>
  29 #include "irq.h"
  30 #include "kvm.h"
  31
  32 /*
  33  * set irq level. If an edge is detected, then the IRR is set to 1
  34  */
  35 static inline void pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
  36 {
  37         int mask;
  38         mask = 1 << irq;
  39         if (s->elcr & mask)     /* level triggered */
  40                 if (level) {
  41                         s->irr |= mask;
  42                         s->last_irr |= mask;
  43                 } else {
  44                         s->irr &= ~mask;
  45                         s->last_irr &= ~mask;
  46                 }
  47         else    /* edge triggered */
  48                 if (level) {
  49                         if ((s->last_irr & mask) == 0)
  50                                 s->irr |= mask;
  51                         s->last_irr |= mask;
  52                 } else
  53                         s->last_irr &= ~mask;
  54 }
  55
  56 /*
  57  * return the highest priority found in mask (highest = smallest
  58  * number). Return 8 if no irq
  59  */
  60 static inline int get_priority(struct kvm_kpic_state *s, int mask)
  61 {
  62         int priority;
  63         if (mask == 0)
  64                 return 8;
  65         priority = 0;
  66         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
  67                 priority++;
  68         return priority;
  69 }
  70
  71 /*
  72  * return the pic wanted interrupt. return -1 if none
  73  */
  74 static int pic_get_irq(struct kvm_kpic_state *s)
  75 {
  76         int mask, cur_priority, priority;
  77
  78         mask = s->irr & ~s->imr;
  79         priority = get_priority(s, mask);
  80         if (priority == 8)
  81                 return -1;
  82         /*
  83          * compute current priority. If special fully nested mode on the
  84          * master, the IRQ coming from the slave is not taken into account
  85          * for the priority computation.
  86          */
  87         mask = s->isr;
  88         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
  89                 mask &= ~(1 << 2);
  90         cur_priority = get_priority(s, mask);
  91         if (priority < cur_priority)
  92                 /*
  93                  * higher priority found: an irq should be generated
  94                  */
  95                 return (priority + s->priority_add) & 7;
  96         else
  97                 return -1;
  98 }
  99
 100 /*
 101  * raise irq to CPU if necessary. must be called every time the active
 102  * irq may change
 103  */
 104 static void pic_update_irq(struct kvm_pic *s)
 105 {
 106         int irq2, irq;
 107
 108         irq2 = pic_get_irq(&s->pics[1]);
 109         if (irq2 >= 0) {
 110                 /*
 111                  * if irq request by slave pic, signal master PIC
 112                  */
 113                 pic_set_irq1(&s->pics[0], 2, 1);
 114                 pic_set_irq1(&s->pics[0], 2, 0);
 115         }
 116         irq = pic_get_irq(&s->pics[0]);
 117         if (irq >= 0)
 118                 s->irq_request(s->irq_request_opaque, 1);
 119         else
 120                 s->irq_request(s->irq_request_opaque, 0);
 121 }
 122
 123 void kvm_pic_update_irq(struct kvm_pic *s)
 124 {
 125         pic_update_irq(s);
 126 }
 127
 128 void kvm_pic_set_irq(void *opaque, int irq, int level)
 129 {
 130         struct kvm_pic *s = opaque;
 131
 132         pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 133         pic_update_irq(s);
 134 }
 135
 136 /*
 137  * acknowledge interrupt 'irq'
 138  */
 139 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
 140 {
 141         if (s->auto_eoi) {
 142                 if (s->rotate_on_auto_eoi)
 143                         s->priority_add = (irq + 1) & 7;
 144         } else
 145                 s->isr |= (1 << irq);
 146         /*
 147          * We don't clear a level sensitive interrupt here
 148          */
 149         if (!(s->elcr & (1 << irq)))
 150                 s->irr &= ~(1 << irq);
 151 }
 152
 153 int kvm_pic_read_irq(struct kvm_pic *s)
 154 {
 155         int irq, irq2, intno;
 156
 157         irq = pic_get_irq(&s->pics[0]);
 158         if (irq >= 0) {
 159                 pic_intack(&s->pics[0], irq);
 160                 if (irq == 2) {
 161                         irq2 = pic_get_irq(&s->pics[1]);
 162                         if (irq2 >= 0)
 163                                 pic_intack(&s->pics[1], irq2);
 164                         else
 165                                 /*
 166                                  * spurious IRQ on slave controller
 167                                  */
 168                                 irq2 = 7;
 169                         intno = s->pics[1].irq_base + irq2;
 170                         irq = irq2 + 8;
 171                 } else
 172                         intno = s->pics[0].irq_base + irq;
 173         } else {
 174                 /*
 175                  * spurious IRQ on host controller
 176                  */
 177                 irq = 7;
 178                 intno = s->pics[0].irq_base + irq;
 179         }
 180         pic_update_irq(s);
 181
 182         return intno;
 183 }
 184
 185 void kvm_pic_reset(struct kvm_kpic_state *s)
 186 {
 187         s->last_irr = 0;
 188         s->irr = 0;
 189         s->imr = 0;
 190         s->isr = 0;
 191         s->priority_add = 0;
 192         s->irq_base = 0;
 193         s->read_reg_select = 0;
 194         s->poll = 0;
 195         s->special_mask = 0;
 196         s->init_state = 0;
 197         s->auto_eoi = 0;
 198         s->rotate_on_auto_eoi = 0;
 199         s->special_fully_nested_mode = 0;
 200         s->init4 = 0;
 201 }
 202
 203 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
 204 {
 205         struct kvm_kpic_state *s = opaque;
 206         int priority, cmd, irq;
 207
 208         addr &= 1;
 209         if (addr == 0) {
 210                 if (val & 0x10) {
 211                         kvm_pic_reset(s);       /* init */
 212                         /*
 213                          * deassert a pending interrupt
 214                          */
 215                         s->pics_state->irq_request(s->pics_state->
 216                                                    irq_request_opaque, 0);
 217                         s->init_state = 1;
 218                         s->init4 = val & 1;
 219                         if (val & 0x02)
 220                                 printk(KERN_ERR "single mode not supported");
 221                         if (val & 0x08)
 222                                 printk(KERN_ERR
 223                                        "level sensitive irq not supported");
 224                 } else if (val & 0x08) {
 225                         if (val & 0x04)
 226                                 s->poll = 1;
 227                         if (val & 0x02)
 228                                 s->read_reg_select = val & 1;
 229                         if (val & 0x40)
 230                                 s->special_mask = (val >> 5) & 1;
 231                 } else {
 232                         cmd = val >> 5;
 233                         switch (cmd) {
 234                         case 0:
 235                         case 4:
 236                                 s->rotate_on_auto_eoi = cmd >> 2;
 237                                 break;
 238                         case 1: /* end of interrupt */
 239                         case 5:
 240                                 priority = get_priority(s, s->isr);
 241                                 if (priority != 8) {
 242                                         irq = (priority + s->priority_add) & 7;
 243                                         s->isr &= ~(1 << irq);
 244                                         if (cmd == 5)
 245                                                 s->priority_add = (irq + 1) & 7;
 246                                         pic_update_irq(s->pics_state);
 247                                 }
 248                                 break;
 249                         case 3:
 250                                 irq = val & 7;
 251                                 s->isr &= ~(1 << irq);
 252                                 pic_update_irq(s->pics_state);
 253                                 break;
 254                         case 6:
 255                                 s->priority_add = (val + 1) & 7;
 256                                 pic_update_irq(s->pics_state);
 257                                 break;
 258                         case 7:
 259                                 irq = val & 7;
 260                                 s->isr &= ~(1 << irq);
 261                                 s->priority_add = (irq + 1) & 7;
 262                                 pic_update_irq(s->pics_state);
 263                                 break;
 264                         default:
 265                                 break;  /* no operation */
 266                         }
 267                 }
 268         } else
 269                 switch (s->init_state) {
 270                 case 0:         /* normal mode */
 271                         s->imr = val;
 272                         pic_update_irq(s->pics_state);
 273                         break;
 274                 case 1:
 275                         s->irq_base = val & 0xf8;
 276                         s->init_state = 2;
 277                         break;
 278                 case 2:
 279                         if (s->init4)
 280                                 s->init_state = 3;
 281                         else
 282                                 s->init_state = 0;
 283                         break;
 284                 case 3:
 285                         s->special_fully_nested_mode = (val >> 4) & 1;
 286                         s->auto_eoi = (val >> 1) & 1;
 287                         s->init_state = 0;
 288                         break;
 289                 }
 290 }
 291
 292 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
 293 {
 294         int ret;
 295
 296         ret = pic_get_irq(s);
 297         if (ret >= 0) {
 298                 if (addr1 >> 7) {
 299                         s->pics_state->pics[0].isr &= ~(1 << 2);
 300                         s->pics_state->pics[0].irr &= ~(1 << 2);
 301                 }
 302                 s->irr &= ~(1 << ret);
 303                 s->isr &= ~(1 << ret);
 304                 if (addr1 >> 7 || ret != 2)
 305                         pic_update_irq(s->pics_state);
 306         } else {
 307                 ret = 0x07;
 308                 pic_update_irq(s->pics_state);
 309         }
 310
 311         return ret;
 312 }
 313
 314 static u32 pic_ioport_read(void *opaque, u32 addr1)
 315 {
 316         struct kvm_kpic_state *s = opaque;
 317         unsigned int addr;
 318         int ret;
 319
 320         addr = addr1;
 321         addr &= 1;
 322         if (s->poll) {
 323                 ret = pic_poll_read(s, addr1);
 324                 s->poll = 0;
 325         } else
 326                 if (addr == 0)
 327                         if (s->read_reg_select)
 328                                 ret = s->isr;
 329                         else
 330                                 ret = s->irr;
 331                 else
 332                         ret = s->imr;
 333         return ret;
 334 }
 335
 336 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
 337 {
 338         struct kvm_kpic_state *s = opaque;
 339         s->elcr = val & s->elcr_mask;
 340 }
 341
 342 static u32 elcr_ioport_read(void *opaque, u32 addr1)
 343 {
 344         struct kvm_kpic_state *s = opaque;
 345         return s->elcr;
 346 }
 347
 348 static int picdev_in_range(struct kvm_io_device *this, gpa_t addr)
 349 {
 350         switch (addr) {
 351         case 0x20:
 352         case 0x21:
 353         case 0xa0:
 354         case 0xa1:
 355         case 0x4d0:
 356         case 0x4d1:
 357                 return 1;
 358         default:
 359                 return 0;
 360         }
 361 }
 362
 363 static void picdev_write(struct kvm_io_device *this,
 364                          gpa_t addr, int len, const void *val)
 365 {
 366         struct kvm_pic *s = this->private;
 367         unsigned char data = *(unsigned char *)val;
 368
 369         if (len != 1) {
 370                 if (printk_ratelimit())
 371                         printk(KERN_ERR "PIC: non byte write\n");
 372                 return;
 373         }
 374         switch (addr) {
 375         case 0x20:
 376         case 0x21:
 377         case 0xa0:
 378         case 0xa1:
 379                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
 380                 break;
 381         case 0x4d0:
 382         case 0x4d1:
 383                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
 384                 break;
 385         }
 386 }
 387
 388 static void picdev_read(struct kvm_io_device *this,
 389                         gpa_t addr, int len, void *val)
 390 {
 391         struct kvm_pic *s = this->private;
 392         unsigned char data = 0;
 393
 394         if (len != 1) {
 395                 if (printk_ratelimit())
 396                         printk(KERN_ERR "PIC: non byte read\n");
 397                 return;
 398         }
 399         switch (addr) {
 400         case 0x20:
 401         case 0x21:
 402         case 0xa0:
 403         case 0xa1:
 404                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
 405                 break;
 406         case 0x4d0:
 407         case 0x4d1:
 408                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
 409                 break;
 410         }
 411         *(unsigned char *)val = data;
 412 }
 413
 414 /*
 415  * callback when PIC0 irq status changed
 416  */
 417 static void pic_irq_request(void *opaque, int level)
 418 {
 419         struct kvm *kvm = opaque;
 420         struct kvm_vcpu *vcpu = kvm->vcpus[0];
 421
 422         pic_irqchip(kvm)->output = level;
 423         if (vcpu)
 424                 kvm_vcpu_kick(vcpu);
 425 }
 426
 427 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
 428 {
 429         struct kvm_pic *s;
 430         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
 431         if (!s)
 432                 return NULL;
 433         s->pics[0].elcr_mask = 0xf8;
 434         s->pics[1].elcr_mask = 0xde;
 435         s->irq_request = pic_irq_request;
 436         s->irq_request_opaque = kvm;
 437         s->pics[0].pics_state = s;
 438         s->pics[1].pics_state = s;
 439
 440         /*
 441          * Initialize PIO device
 442          */
 443         s->dev.read = picdev_read;
 444         s->dev.write = picdev_write;
 445         s->dev.in_range = picdev_in_range;
 446         s->dev.private = s;
 447         kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev);
 448         return s;
 449 }