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KVM: VMX: Add printk_ratelimit in vmx_intr_assist
[deliverable/linux.git] / drivers / kvm / lapic.c
1
2 /*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 *
9 * Authors:
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
13 *
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 */
19
20 #include "kvm.h"
21 #include "x86.h"
22
23 #include <linux/kvm.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/smp.h>
27 #include <linux/hrtimer.h>
28 #include <linux/io.h>
29 #include <linux/module.h>
30 #include <asm/processor.h>
31 #include <asm/msr.h>
32 #include <asm/page.h>
33 #include <asm/current.h>
34 #include <asm/apicdef.h>
35 #include <asm/atomic.h>
36 #include <asm/div64.h>
37 #include "irq.h"
38
39 #define PRId64 "d"
40 #define PRIx64 "llx"
41 #define PRIu64 "u"
42 #define PRIo64 "o"
43
44 #define APIC_BUS_CYCLE_NS 1
45
46 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
47 #define apic_debug(fmt, arg...)
48
49 #define APIC_LVT_NUM 6
50 /* 14 is the version for Xeon and Pentium 8.4.8*/
51 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
52 #define LAPIC_MMIO_LENGTH (1 << 12)
53 /* followed define is not in apicdef.h */
54 #define APIC_SHORT_MASK 0xc0000
55 #define APIC_DEST_NOSHORT 0x0
56 #define APIC_DEST_MASK 0x800
57 #define MAX_APIC_VECTOR 256
58
59 #define VEC_POS(v) ((v) & (32 - 1))
60 #define REG_POS(v) (((v) >> 5) << 4)
61
62 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
63 {
64 return *((u32 *) (apic->regs + reg_off));
65 }
66
67 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
68 {
69 *((u32 *) (apic->regs + reg_off)) = val;
70 }
71
72 static inline int apic_test_and_set_vector(int vec, void *bitmap)
73 {
74 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
75 }
76
77 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
78 {
79 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
80 }
81
82 static inline void apic_set_vector(int vec, void *bitmap)
83 {
84 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
85 }
86
87 static inline void apic_clear_vector(int vec, void *bitmap)
88 {
89 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
90 }
91
92 static inline int apic_hw_enabled(struct kvm_lapic *apic)
93 {
94 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
95 }
96
97 static inline int apic_sw_enabled(struct kvm_lapic *apic)
98 {
99 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
100 }
101
102 static inline int apic_enabled(struct kvm_lapic *apic)
103 {
104 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
105 }
106
107 #define LVT_MASK \
108 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
109
110 #define LINT_MASK \
111 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
112 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
113
114 static inline int kvm_apic_id(struct kvm_lapic *apic)
115 {
116 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
117 }
118
119 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
120 {
121 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
122 }
123
124 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
125 {
126 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
127 }
128
129 static inline int apic_lvtt_period(struct kvm_lapic *apic)
130 {
131 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
132 }
133
134 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
135 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
136 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
137 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
138 LINT_MASK, LINT_MASK, /* LVT0-1 */
139 LVT_MASK /* LVTERR */
140 };
141
142 static int find_highest_vector(void *bitmap)
143 {
144 u32 *word = bitmap;
145 int word_offset = MAX_APIC_VECTOR >> 5;
146
147 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
148 continue;
149
150 if (likely(!word_offset && !word[0]))
151 return -1;
152 else
153 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
154 }
155
156 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
157 {
158 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
159 }
160
161 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
162 {
163 apic_clear_vector(vec, apic->regs + APIC_IRR);
164 }
165
166 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
167 {
168 int result;
169
170 result = find_highest_vector(apic->regs + APIC_IRR);
171 ASSERT(result == -1 || result >= 16);
172
173 return result;
174 }
175
176 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
177 {
178 struct kvm_lapic *apic = vcpu->arch.apic;
179 int highest_irr;
180
181 if (!apic)
182 return 0;
183 highest_irr = apic_find_highest_irr(apic);
184
185 return highest_irr;
186 }
187 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
188
189 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig)
190 {
191 struct kvm_lapic *apic = vcpu->arch.apic;
192
193 if (!apic_test_and_set_irr(vec, apic)) {
194 /* a new pending irq is set in IRR */
195 if (trig)
196 apic_set_vector(vec, apic->regs + APIC_TMR);
197 else
198 apic_clear_vector(vec, apic->regs + APIC_TMR);
199 kvm_vcpu_kick(apic->vcpu);
200 return 1;
201 }
202 return 0;
203 }
204
205 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
206 {
207 int result;
208
209 result = find_highest_vector(apic->regs + APIC_ISR);
210 ASSERT(result == -1 || result >= 16);
211
212 return result;
213 }
214
215 static void apic_update_ppr(struct kvm_lapic *apic)
216 {
217 u32 tpr, isrv, ppr;
218 int isr;
219
220 tpr = apic_get_reg(apic, APIC_TASKPRI);
221 isr = apic_find_highest_isr(apic);
222 isrv = (isr != -1) ? isr : 0;
223
224 if ((tpr & 0xf0) >= (isrv & 0xf0))
225 ppr = tpr & 0xff;
226 else
227 ppr = isrv & 0xf0;
228
229 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
230 apic, ppr, isr, isrv);
231
232 apic_set_reg(apic, APIC_PROCPRI, ppr);
233 }
234
235 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
236 {
237 apic_set_reg(apic, APIC_TASKPRI, tpr);
238 apic_update_ppr(apic);
239 }
240
241 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
242 {
243 return kvm_apic_id(apic) == dest;
244 }
245
246 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
247 {
248 int result = 0;
249 u8 logical_id;
250
251 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
252
253 switch (apic_get_reg(apic, APIC_DFR)) {
254 case APIC_DFR_FLAT:
255 if (logical_id & mda)
256 result = 1;
257 break;
258 case APIC_DFR_CLUSTER:
259 if (((logical_id >> 4) == (mda >> 0x4))
260 && (logical_id & mda & 0xf))
261 result = 1;
262 break;
263 default:
264 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
265 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
266 break;
267 }
268
269 return result;
270 }
271
272 static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
273 int short_hand, int dest, int dest_mode)
274 {
275 int result = 0;
276 struct kvm_lapic *target = vcpu->arch.apic;
277
278 apic_debug("target %p, source %p, dest 0x%x, "
279 "dest_mode 0x%x, short_hand 0x%x",
280 target, source, dest, dest_mode, short_hand);
281
282 ASSERT(!target);
283 switch (short_hand) {
284 case APIC_DEST_NOSHORT:
285 if (dest_mode == 0) {
286 /* Physical mode. */
287 if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
288 result = 1;
289 } else
290 /* Logical mode. */
291 result = kvm_apic_match_logical_addr(target, dest);
292 break;
293 case APIC_DEST_SELF:
294 if (target == source)
295 result = 1;
296 break;
297 case APIC_DEST_ALLINC:
298 result = 1;
299 break;
300 case APIC_DEST_ALLBUT:
301 if (target != source)
302 result = 1;
303 break;
304 default:
305 printk(KERN_WARNING "Bad dest shorthand value %x\n",
306 short_hand);
307 break;
308 }
309
310 return result;
311 }
312
313 /*
314 * Add a pending IRQ into lapic.
315 * Return 1 if successfully added and 0 if discarded.
316 */
317 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
318 int vector, int level, int trig_mode)
319 {
320 int orig_irr, result = 0;
321 struct kvm_vcpu *vcpu = apic->vcpu;
322
323 switch (delivery_mode) {
324 case APIC_DM_FIXED:
325 case APIC_DM_LOWEST:
326 /* FIXME add logic for vcpu on reset */
327 if (unlikely(!apic_enabled(apic)))
328 break;
329
330 orig_irr = apic_test_and_set_irr(vector, apic);
331 if (orig_irr && trig_mode) {
332 apic_debug("level trig mode repeatedly for vector %d",
333 vector);
334 break;
335 }
336
337 if (trig_mode) {
338 apic_debug("level trig mode for vector %d", vector);
339 apic_set_vector(vector, apic->regs + APIC_TMR);
340 } else
341 apic_clear_vector(vector, apic->regs + APIC_TMR);
342
343 if (vcpu->arch.mp_state == VCPU_MP_STATE_RUNNABLE)
344 kvm_vcpu_kick(vcpu);
345 else if (vcpu->arch.mp_state == VCPU_MP_STATE_HALTED) {
346 vcpu->arch.mp_state = VCPU_MP_STATE_RUNNABLE;
347 if (waitqueue_active(&vcpu->wq))
348 wake_up_interruptible(&vcpu->wq);
349 }
350
351 result = (orig_irr == 0);
352 break;
353
354 case APIC_DM_REMRD:
355 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
356 break;
357
358 case APIC_DM_SMI:
359 printk(KERN_DEBUG "Ignoring guest SMI\n");
360 break;
361 case APIC_DM_NMI:
362 printk(KERN_DEBUG "Ignoring guest NMI\n");
363 break;
364
365 case APIC_DM_INIT:
366 if (level) {
367 if (vcpu->arch.mp_state == VCPU_MP_STATE_RUNNABLE)
368 printk(KERN_DEBUG
369 "INIT on a runnable vcpu %d\n",
370 vcpu->vcpu_id);
371 vcpu->arch.mp_state = VCPU_MP_STATE_INIT_RECEIVED;
372 kvm_vcpu_kick(vcpu);
373 } else {
374 printk(KERN_DEBUG
375 "Ignoring de-assert INIT to vcpu %d\n",
376 vcpu->vcpu_id);
377 }
378
379 break;
380
381 case APIC_DM_STARTUP:
382 printk(KERN_DEBUG "SIPI to vcpu %d vector 0x%02x\n",
383 vcpu->vcpu_id, vector);
384 if (vcpu->arch.mp_state == VCPU_MP_STATE_INIT_RECEIVED) {
385 vcpu->arch.sipi_vector = vector;
386 vcpu->arch.mp_state = VCPU_MP_STATE_SIPI_RECEIVED;
387 if (waitqueue_active(&vcpu->wq))
388 wake_up_interruptible(&vcpu->wq);
389 }
390 break;
391
392 default:
393 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
394 delivery_mode);
395 break;
396 }
397 return result;
398 }
399
400 static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
401 unsigned long bitmap)
402 {
403 int last;
404 int next;
405 struct kvm_lapic *apic = NULL;
406
407 last = kvm->arch.round_robin_prev_vcpu;
408 next = last;
409
410 do {
411 if (++next == KVM_MAX_VCPUS)
412 next = 0;
413 if (kvm->vcpus[next] == NULL || !test_bit(next, &bitmap))
414 continue;
415 apic = kvm->vcpus[next]->arch.apic;
416 if (apic && apic_enabled(apic))
417 break;
418 apic = NULL;
419 } while (next != last);
420 kvm->arch.round_robin_prev_vcpu = next;
421
422 if (!apic)
423 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
424
425 return apic;
426 }
427
428 struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
429 unsigned long bitmap)
430 {
431 struct kvm_lapic *apic;
432
433 apic = kvm_apic_round_robin(kvm, vector, bitmap);
434 if (apic)
435 return apic->vcpu;
436 return NULL;
437 }
438
439 static void apic_set_eoi(struct kvm_lapic *apic)
440 {
441 int vector = apic_find_highest_isr(apic);
442
443 /*
444 * Not every write EOI will has corresponding ISR,
445 * one example is when Kernel check timer on setup_IO_APIC
446 */
447 if (vector == -1)
448 return;
449
450 apic_clear_vector(vector, apic->regs + APIC_ISR);
451 apic_update_ppr(apic);
452
453 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
454 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector);
455 }
456
457 static void apic_send_ipi(struct kvm_lapic *apic)
458 {
459 u32 icr_low = apic_get_reg(apic, APIC_ICR);
460 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
461
462 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
463 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
464 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
465 unsigned int level = icr_low & APIC_INT_ASSERT;
466 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
467 unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
468 unsigned int vector = icr_low & APIC_VECTOR_MASK;
469
470 struct kvm_vcpu *target;
471 struct kvm_vcpu *vcpu;
472 unsigned long lpr_map = 0;
473 int i;
474
475 apic_debug("icr_high 0x%x, icr_low 0x%x, "
476 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
477 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
478 icr_high, icr_low, short_hand, dest,
479 trig_mode, level, dest_mode, delivery_mode, vector);
480
481 for (i = 0; i < KVM_MAX_VCPUS; i++) {
482 vcpu = apic->vcpu->kvm->vcpus[i];
483 if (!vcpu)
484 continue;
485
486 if (vcpu->arch.apic &&
487 apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
488 if (delivery_mode == APIC_DM_LOWEST)
489 set_bit(vcpu->vcpu_id, &lpr_map);
490 else
491 __apic_accept_irq(vcpu->arch.apic, delivery_mode,
492 vector, level, trig_mode);
493 }
494 }
495
496 if (delivery_mode == APIC_DM_LOWEST) {
497 target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map);
498 if (target != NULL)
499 __apic_accept_irq(target->arch.apic, delivery_mode,
500 vector, level, trig_mode);
501 }
502 }
503
504 static u32 apic_get_tmcct(struct kvm_lapic *apic)
505 {
506 u64 counter_passed;
507 ktime_t passed, now;
508 u32 tmcct;
509
510 ASSERT(apic != NULL);
511
512 now = apic->timer.dev.base->get_time();
513 tmcct = apic_get_reg(apic, APIC_TMICT);
514
515 /* if initial count is 0, current count should also be 0 */
516 if (tmcct == 0)
517 return 0;
518
519 if (unlikely(ktime_to_ns(now) <=
520 ktime_to_ns(apic->timer.last_update))) {
521 /* Wrap around */
522 passed = ktime_add(( {
523 (ktime_t) {
524 .tv64 = KTIME_MAX -
525 (apic->timer.last_update).tv64}; }
526 ), now);
527 apic_debug("time elapsed\n");
528 } else
529 passed = ktime_sub(now, apic->timer.last_update);
530
531 counter_passed = div64_64(ktime_to_ns(passed),
532 (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
533
534 if (counter_passed > tmcct) {
535 if (unlikely(!apic_lvtt_period(apic))) {
536 /* one-shot timers stick at 0 until reset */
537 tmcct = 0;
538 } else {
539 /*
540 * periodic timers reset to APIC_TMICT when they
541 * hit 0. The while loop simulates this happening N
542 * times. (counter_passed %= tmcct) would also work,
543 * but might be slower or not work on 32-bit??
544 */
545 while (counter_passed > tmcct)
546 counter_passed -= tmcct;
547 tmcct -= counter_passed;
548 }
549 } else {
550 tmcct -= counter_passed;
551 }
552
553 return tmcct;
554 }
555
556 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
557 {
558 u32 val = 0;
559
560 if (offset >= LAPIC_MMIO_LENGTH)
561 return 0;
562
563 switch (offset) {
564 case APIC_ARBPRI:
565 printk(KERN_WARNING "Access APIC ARBPRI register "
566 "which is for P6\n");
567 break;
568
569 case APIC_TMCCT: /* Timer CCR */
570 val = apic_get_tmcct(apic);
571 break;
572
573 default:
574 apic_update_ppr(apic);
575 val = apic_get_reg(apic, offset);
576 break;
577 }
578
579 return val;
580 }
581
582 static void apic_mmio_read(struct kvm_io_device *this,
583 gpa_t address, int len, void *data)
584 {
585 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
586 unsigned int offset = address - apic->base_address;
587 unsigned char alignment = offset & 0xf;
588 u32 result;
589
590 if ((alignment + len) > 4) {
591 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
592 (unsigned long)address, len);
593 return;
594 }
595 result = __apic_read(apic, offset & ~0xf);
596
597 switch (len) {
598 case 1:
599 case 2:
600 case 4:
601 memcpy(data, (char *)&result + alignment, len);
602 break;
603 default:
604 printk(KERN_ERR "Local APIC read with len = %x, "
605 "should be 1,2, or 4 instead\n", len);
606 break;
607 }
608 }
609
610 static void update_divide_count(struct kvm_lapic *apic)
611 {
612 u32 tmp1, tmp2, tdcr;
613
614 tdcr = apic_get_reg(apic, APIC_TDCR);
615 tmp1 = tdcr & 0xf;
616 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
617 apic->timer.divide_count = 0x1 << (tmp2 & 0x7);
618
619 apic_debug("timer divide count is 0x%x\n",
620 apic->timer.divide_count);
621 }
622
623 static void start_apic_timer(struct kvm_lapic *apic)
624 {
625 ktime_t now = apic->timer.dev.base->get_time();
626
627 apic->timer.last_update = now;
628
629 apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
630 APIC_BUS_CYCLE_NS * apic->timer.divide_count;
631 atomic_set(&apic->timer.pending, 0);
632 hrtimer_start(&apic->timer.dev,
633 ktime_add_ns(now, apic->timer.period),
634 HRTIMER_MODE_ABS);
635
636 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
637 PRIx64 ", "
638 "timer initial count 0x%x, period %lldns, "
639 "expire @ 0x%016" PRIx64 ".\n", __FUNCTION__,
640 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
641 apic_get_reg(apic, APIC_TMICT),
642 apic->timer.period,
643 ktime_to_ns(ktime_add_ns(now,
644 apic->timer.period)));
645 }
646
647 static void apic_mmio_write(struct kvm_io_device *this,
648 gpa_t address, int len, const void *data)
649 {
650 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
651 unsigned int offset = address - apic->base_address;
652 unsigned char alignment = offset & 0xf;
653 u32 val;
654
655 /*
656 * APIC register must be aligned on 128-bits boundary.
657 * 32/64/128 bits registers must be accessed thru 32 bits.
658 * Refer SDM 8.4.1
659 */
660 if (len != 4 || alignment) {
661 if (printk_ratelimit())
662 printk(KERN_ERR "apic write: bad size=%d %lx\n",
663 len, (long)address);
664 return;
665 }
666
667 val = *(u32 *) data;
668
669 /* too common printing */
670 if (offset != APIC_EOI)
671 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
672 "0x%x\n", __FUNCTION__, offset, len, val);
673
674 offset &= 0xff0;
675
676 switch (offset) {
677 case APIC_ID: /* Local APIC ID */
678 apic_set_reg(apic, APIC_ID, val);
679 break;
680
681 case APIC_TASKPRI:
682 apic_set_tpr(apic, val & 0xff);
683 break;
684
685 case APIC_EOI:
686 apic_set_eoi(apic);
687 break;
688
689 case APIC_LDR:
690 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
691 break;
692
693 case APIC_DFR:
694 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
695 break;
696
697 case APIC_SPIV:
698 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
699 if (!(val & APIC_SPIV_APIC_ENABLED)) {
700 int i;
701 u32 lvt_val;
702
703 for (i = 0; i < APIC_LVT_NUM; i++) {
704 lvt_val = apic_get_reg(apic,
705 APIC_LVTT + 0x10 * i);
706 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
707 lvt_val | APIC_LVT_MASKED);
708 }
709 atomic_set(&apic->timer.pending, 0);
710
711 }
712 break;
713
714 case APIC_ICR:
715 /* No delay here, so we always clear the pending bit */
716 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
717 apic_send_ipi(apic);
718 break;
719
720 case APIC_ICR2:
721 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
722 break;
723
724 case APIC_LVTT:
725 case APIC_LVTTHMR:
726 case APIC_LVTPC:
727 case APIC_LVT0:
728 case APIC_LVT1:
729 case APIC_LVTERR:
730 /* TODO: Check vector */
731 if (!apic_sw_enabled(apic))
732 val |= APIC_LVT_MASKED;
733
734 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
735 apic_set_reg(apic, offset, val);
736
737 break;
738
739 case APIC_TMICT:
740 hrtimer_cancel(&apic->timer.dev);
741 apic_set_reg(apic, APIC_TMICT, val);
742 start_apic_timer(apic);
743 return;
744
745 case APIC_TDCR:
746 if (val & 4)
747 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
748 apic_set_reg(apic, APIC_TDCR, val);
749 update_divide_count(apic);
750 break;
751
752 default:
753 apic_debug("Local APIC Write to read-only register %x\n",
754 offset);
755 break;
756 }
757
758 }
759
760 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr)
761 {
762 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
763 int ret = 0;
764
765
766 if (apic_hw_enabled(apic) &&
767 (addr >= apic->base_address) &&
768 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
769 ret = 1;
770
771 return ret;
772 }
773
774 void kvm_free_lapic(struct kvm_vcpu *vcpu)
775 {
776 if (!vcpu->arch.apic)
777 return;
778
779 hrtimer_cancel(&vcpu->arch.apic->timer.dev);
780
781 if (vcpu->arch.apic->regs_page)
782 __free_page(vcpu->arch.apic->regs_page);
783
784 kfree(vcpu->arch.apic);
785 }
786
787 /*
788 *----------------------------------------------------------------------
789 * LAPIC interface
790 *----------------------------------------------------------------------
791 */
792
793 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
794 {
795 struct kvm_lapic *apic = vcpu->arch.apic;
796
797 if (!apic)
798 return;
799 apic_set_tpr(apic, ((cr8 & 0x0f) << 4));
800 }
801
802 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
803 {
804 struct kvm_lapic *apic = vcpu->arch.apic;
805 u64 tpr;
806
807 if (!apic)
808 return 0;
809 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
810
811 return (tpr & 0xf0) >> 4;
812 }
813 EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
814
815 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
816 {
817 struct kvm_lapic *apic = vcpu->arch.apic;
818
819 if (!apic) {
820 value |= MSR_IA32_APICBASE_BSP;
821 vcpu->arch.apic_base = value;
822 return;
823 }
824 if (apic->vcpu->vcpu_id)
825 value &= ~MSR_IA32_APICBASE_BSP;
826
827 vcpu->arch.apic_base = value;
828 apic->base_address = apic->vcpu->arch.apic_base &
829 MSR_IA32_APICBASE_BASE;
830
831 /* with FSB delivery interrupt, we can restart APIC functionality */
832 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
833 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
834
835 }
836
837 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
838 {
839 return vcpu->arch.apic_base;
840 }
841 EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
842
843 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
844 {
845 struct kvm_lapic *apic;
846 int i;
847
848 apic_debug("%s\n", __FUNCTION__);
849
850 ASSERT(vcpu);
851 apic = vcpu->arch.apic;
852 ASSERT(apic != NULL);
853
854 /* Stop the timer in case it's a reset to an active apic */
855 hrtimer_cancel(&apic->timer.dev);
856
857 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
858 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
859
860 for (i = 0; i < APIC_LVT_NUM; i++)
861 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
862 apic_set_reg(apic, APIC_LVT0,
863 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
864
865 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
866 apic_set_reg(apic, APIC_SPIV, 0xff);
867 apic_set_reg(apic, APIC_TASKPRI, 0);
868 apic_set_reg(apic, APIC_LDR, 0);
869 apic_set_reg(apic, APIC_ESR, 0);
870 apic_set_reg(apic, APIC_ICR, 0);
871 apic_set_reg(apic, APIC_ICR2, 0);
872 apic_set_reg(apic, APIC_TDCR, 0);
873 apic_set_reg(apic, APIC_TMICT, 0);
874 for (i = 0; i < 8; i++) {
875 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
876 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
877 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
878 }
879 update_divide_count(apic);
880 atomic_set(&apic->timer.pending, 0);
881 if (vcpu->vcpu_id == 0)
882 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
883 apic_update_ppr(apic);
884
885 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
886 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __FUNCTION__,
887 vcpu, kvm_apic_id(apic),
888 vcpu->arch.apic_base, apic->base_address);
889 }
890 EXPORT_SYMBOL_GPL(kvm_lapic_reset);
891
892 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
893 {
894 struct kvm_lapic *apic = vcpu->arch.apic;
895 int ret = 0;
896
897 if (!apic)
898 return 0;
899 ret = apic_enabled(apic);
900
901 return ret;
902 }
903 EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
904
905 /*
906 *----------------------------------------------------------------------
907 * timer interface
908 *----------------------------------------------------------------------
909 */
910
911 /* TODO: make sure __apic_timer_fn runs in current pCPU */
912 static int __apic_timer_fn(struct kvm_lapic *apic)
913 {
914 int result = 0;
915 wait_queue_head_t *q = &apic->vcpu->wq;
916
917 atomic_inc(&apic->timer.pending);
918 if (waitqueue_active(q)) {
919 apic->vcpu->arch.mp_state = VCPU_MP_STATE_RUNNABLE;
920 wake_up_interruptible(q);
921 }
922 if (apic_lvtt_period(apic)) {
923 result = 1;
924 apic->timer.dev.expires = ktime_add_ns(
925 apic->timer.dev.expires,
926 apic->timer.period);
927 }
928 return result;
929 }
930
931 static int __inject_apic_timer_irq(struct kvm_lapic *apic)
932 {
933 int vector;
934
935 vector = apic_lvt_vector(apic, APIC_LVTT);
936 return __apic_accept_irq(apic, APIC_DM_FIXED, vector, 1, 0);
937 }
938
939 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
940 {
941 struct kvm_lapic *apic;
942 int restart_timer = 0;
943
944 apic = container_of(data, struct kvm_lapic, timer.dev);
945
946 restart_timer = __apic_timer_fn(apic);
947
948 if (restart_timer)
949 return HRTIMER_RESTART;
950 else
951 return HRTIMER_NORESTART;
952 }
953
954 int kvm_create_lapic(struct kvm_vcpu *vcpu)
955 {
956 struct kvm_lapic *apic;
957
958 ASSERT(vcpu != NULL);
959 apic_debug("apic_init %d\n", vcpu->vcpu_id);
960
961 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
962 if (!apic)
963 goto nomem;
964
965 vcpu->arch.apic = apic;
966
967 apic->regs_page = alloc_page(GFP_KERNEL);
968 if (apic->regs_page == NULL) {
969 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
970 vcpu->vcpu_id);
971 goto nomem_free_apic;
972 }
973 apic->regs = page_address(apic->regs_page);
974 memset(apic->regs, 0, PAGE_SIZE);
975 apic->vcpu = vcpu;
976
977 hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
978 apic->timer.dev.function = apic_timer_fn;
979 apic->base_address = APIC_DEFAULT_PHYS_BASE;
980 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
981
982 kvm_lapic_reset(vcpu);
983 apic->dev.read = apic_mmio_read;
984 apic->dev.write = apic_mmio_write;
985 apic->dev.in_range = apic_mmio_range;
986 apic->dev.private = apic;
987
988 return 0;
989 nomem_free_apic:
990 kfree(apic);
991 nomem:
992 return -ENOMEM;
993 }
994 EXPORT_SYMBOL_GPL(kvm_create_lapic);
995
996 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
997 {
998 struct kvm_lapic *apic = vcpu->arch.apic;
999 int highest_irr;
1000
1001 if (!apic || !apic_enabled(apic))
1002 return -1;
1003
1004 apic_update_ppr(apic);
1005 highest_irr = apic_find_highest_irr(apic);
1006 if ((highest_irr == -1) ||
1007 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1008 return -1;
1009 return highest_irr;
1010 }
1011
1012 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1013 {
1014 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1015 int r = 0;
1016
1017 if (vcpu->vcpu_id == 0) {
1018 if (!apic_hw_enabled(vcpu->arch.apic))
1019 r = 1;
1020 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1021 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1022 r = 1;
1023 }
1024 return r;
1025 }
1026
1027 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1028 {
1029 struct kvm_lapic *apic = vcpu->arch.apic;
1030
1031 if (apic && apic_lvt_enabled(apic, APIC_LVTT) &&
1032 atomic_read(&apic->timer.pending) > 0) {
1033 if (__inject_apic_timer_irq(apic))
1034 atomic_dec(&apic->timer.pending);
1035 }
1036 }
1037
1038 void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
1039 {
1040 struct kvm_lapic *apic = vcpu->arch.apic;
1041
1042 if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec)
1043 apic->timer.last_update = ktime_add_ns(
1044 apic->timer.last_update,
1045 apic->timer.period);
1046 }
1047
1048 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1049 {
1050 int vector = kvm_apic_has_interrupt(vcpu);
1051 struct kvm_lapic *apic = vcpu->arch.apic;
1052
1053 if (vector == -1)
1054 return -1;
1055
1056 apic_set_vector(vector, apic->regs + APIC_ISR);
1057 apic_update_ppr(apic);
1058 apic_clear_irr(vector, apic);
1059 return vector;
1060 }
1061
1062 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1063 {
1064 struct kvm_lapic *apic = vcpu->arch.apic;
1065
1066 apic->base_address = vcpu->arch.apic_base &
1067 MSR_IA32_APICBASE_BASE;
1068 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1069 apic_update_ppr(apic);
1070 hrtimer_cancel(&apic->timer.dev);
1071 update_divide_count(apic);
1072 start_apic_timer(apic);
1073 }
1074
1075 void kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1076 {
1077 struct kvm_lapic *apic = vcpu->arch.apic;
1078 struct hrtimer *timer;
1079
1080 if (!apic)
1081 return;
1082
1083 timer = &apic->timer.dev;
1084 if (hrtimer_cancel(timer))
1085 hrtimer_start(timer, timer->expires, HRTIMER_MODE_ABS);
1086 }
1087 EXPORT_SYMBOL_GPL(kvm_migrate_apic_timer);
Linux kernel - Deliverables
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