drivers/kvm/paging_tmpl.h

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * MMU support
   8  *
   9  * Copyright (C) 2006 Qumranet, Inc.
  10  *
  11  * Authors:
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *
  15  * This work is licensed under the terms of the GNU GPL, version 2.  See
  16  * the COPYING file in the top-level directory.
  17  *
  18  */
  19
  20 /*
  21  * We need the mmu code to access both 32-bit and 64-bit guest ptes,
  22  * so the code in this file is compiled twice, once per pte size.
  23  */
  24
  25 #if PTTYPE == 64
  26         #define pt_element_t u64
  27         #define guest_walker guest_walker64
  28         #define FNAME(name) paging##64_##name
  29         #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
  30         #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
  31         #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
  32         #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
  33         #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
  34         #define PT_LEVEL_BITS PT64_LEVEL_BITS
  35         #ifdef CONFIG_X86_64
  36         #define PT_MAX_FULL_LEVELS 4
  37         #else
  38         #define PT_MAX_FULL_LEVELS 2
  39         #endif
  40 #elif PTTYPE == 32
  41         #define pt_element_t u32
  42         #define guest_walker guest_walker32
  43         #define FNAME(name) paging##32_##name
  44         #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
  45         #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
  46         #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
  47         #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
  48         #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
  49         #define PT_LEVEL_BITS PT32_LEVEL_BITS
  50         #define PT_MAX_FULL_LEVELS 2
  51 #else
  52         #error Invalid PTTYPE value
  53 #endif
  54
  55 #define gpte_to_gfn FNAME(gpte_to_gfn)
  56 #define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
  57
  58 /*
  59  * The guest_walker structure emulates the behavior of the hardware page
  60  * table walker.
  61  */
  62 struct guest_walker {
  63         int level;
  64         gfn_t table_gfn[PT_MAX_FULL_LEVELS];
  65         pt_element_t pte;
  66         pt_element_t inherited_ar;
  67         gfn_t gfn;
  68         u32 error_code;
  69 };
  70
  71 static gfn_t gpte_to_gfn(pt_element_t gpte)
  72 {
  73         return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
  74 }
  75
  76 static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
  77 {
  78         return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
  79 }
  80
  81 /*
  82  * Fetch a guest pte for a guest virtual address
  83  */
  84 static int FNAME(walk_addr)(struct guest_walker *walker,
  85                             struct kvm_vcpu *vcpu, gva_t addr,
  86                             int write_fault, int user_fault, int fetch_fault)
  87 {
  88         pt_element_t pte;
  89         gfn_t table_gfn;
  90         unsigned index;
  91         gpa_t pte_gpa;
  92
  93         pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
  94         walker->level = vcpu->mmu.root_level;
  95         pte = vcpu->cr3;
  96 #if PTTYPE == 64
  97         if (!is_long_mode(vcpu)) {
  98                 pte = vcpu->pdptrs[(addr >> 30) & 3];
  99                 if (!is_present_pte(pte))
 100                         goto not_present;
 101                 --walker->level;
 102         }
 103 #endif
 104         ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
 105                (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
 106
 107         walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;
 108
 109         for (;;) {
 110                 index = PT_INDEX(addr, walker->level);
 111
 112                 table_gfn = gpte_to_gfn(pte);
 113                 pte_gpa = table_gfn << PAGE_SHIFT;
 114                 pte_gpa += index * sizeof(pt_element_t);
 115                 walker->table_gfn[walker->level - 1] = table_gfn;
 116                 pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
 117                          walker->level - 1, table_gfn);
 118
 119                 kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
 120
 121                 if (!is_present_pte(pte))
 122                         goto not_present;
 123
 124                 if (write_fault && !is_writeble_pte(pte))
 125                         if (user_fault || is_write_protection(vcpu))
 126                                 goto access_error;
 127
 128                 if (user_fault && !(pte & PT_USER_MASK))
 129                         goto access_error;
 130
 131 #if PTTYPE == 64
 132                 if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
 133                         goto access_error;
 134 #endif
 135
 136                 if (!(pte & PT_ACCESSED_MASK)) {
 137                         mark_page_dirty(vcpu->kvm, table_gfn);
 138                         pte |= PT_ACCESSED_MASK;
 139                         kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
 140                 }
 141
 142                 if (walker->level == PT_PAGE_TABLE_LEVEL) {
 143                         walker->gfn = gpte_to_gfn(pte);
 144                         break;
 145                 }
 146
 147                 if (walker->level == PT_DIRECTORY_LEVEL
 148                     && (pte & PT_PAGE_SIZE_MASK)
 149                     && (PTTYPE == 64 || is_pse(vcpu))) {
 150                         walker->gfn = gpte_to_gfn_pde(pte);
 151                         walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
 152                         if (PTTYPE == 32 && is_cpuid_PSE36())
 153                                 walker->gfn += pse36_gfn_delta(pte);
 154                         break;
 155                 }
 156
 157                 walker->inherited_ar &= pte;
 158                 --walker->level;
 159         }
 160
 161         if (write_fault && !is_dirty_pte(pte)) {
 162                 mark_page_dirty(vcpu->kvm, table_gfn);
 163                 pte |= PT_DIRTY_MASK;
 164                 kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
 165                 kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
 166         }
 167
 168         walker->pte = pte;
 169         pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)pte);
 170         return 1;
 171
 172 not_present:
 173         walker->error_code = 0;
 174         goto err;
 175
 176 access_error:
 177         walker->error_code = PFERR_PRESENT_MASK;
 178
 179 err:
 180         if (write_fault)
 181                 walker->error_code |= PFERR_WRITE_MASK;
 182         if (user_fault)
 183                 walker->error_code |= PFERR_USER_MASK;
 184         if (fetch_fault)
 185                 walker->error_code |= PFERR_FETCH_MASK;
 186         return 0;
 187 }
 188
 189 static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
 190                            u64 *shadow_pte, u64 access_bits,
 191                            int user_fault, int write_fault,
 192                            int *ptwrite, struct guest_walker *walker,
 193                            gfn_t gfn)
 194 {
 195         int dirty = gpte & PT_DIRTY_MASK;
 196         u64 spte;
 197         int was_rmapped = is_rmap_pte(*shadow_pte);
 198         struct page *page;
 199
 200         pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
 201                  " user_fault %d gfn %lx\n",
 202                  __FUNCTION__, *shadow_pte, (u64)gpte, access_bits,
 203                  write_fault, user_fault, gfn);
 204
 205         access_bits &= gpte;
 206         /*
 207          * We don't set the accessed bit, since we sometimes want to see
 208          * whether the guest actually used the pte (in order to detect
 209          * demand paging).
 210          */
 211         spte = PT_PRESENT_MASK | PT_DIRTY_MASK;
 212         spte |= gpte & PT64_NX_MASK;
 213         if (!dirty)
 214                 access_bits &= ~PT_WRITABLE_MASK;
 215
 216         page = gfn_to_page(vcpu->kvm, gfn);
 217
 218         spte |= PT_PRESENT_MASK;
 219         if (access_bits & PT_USER_MASK)
 220                 spte |= PT_USER_MASK;
 221
 222         if (is_error_page(page)) {
 223                 set_shadow_pte(shadow_pte,
 224                                shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK);
 225                 kvm_release_page_clean(page);
 226                 return;
 227         }
 228
 229         spte |= page_to_phys(page);
 230
 231         if ((access_bits & PT_WRITABLE_MASK)
 232             || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
 233                 struct kvm_mmu_page *shadow;
 234
 235                 spte |= PT_WRITABLE_MASK;
 236                 if (user_fault) {
 237                         mmu_unshadow(vcpu->kvm, gfn);
 238                         goto unshadowed;
 239                 }
 240
 241                 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
 242                 if (shadow) {
 243                         pgprintk("%s: found shadow page for %lx, marking ro\n",
 244                                  __FUNCTION__, gfn);
 245                         access_bits &= ~PT_WRITABLE_MASK;
 246                         if (is_writeble_pte(spte)) {
 247                                 spte &= ~PT_WRITABLE_MASK;
 248                                 kvm_x86_ops->tlb_flush(vcpu);
 249                         }
 250                         if (write_fault)
 251                                 *ptwrite = 1;
 252                 }
 253         }
 254
 255 unshadowed:
 256
 257         if (access_bits & PT_WRITABLE_MASK)
 258                 mark_page_dirty(vcpu->kvm, gfn);
 259
 260         pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
 261         set_shadow_pte(shadow_pte, spte);
 262         page_header_update_slot(vcpu->kvm, shadow_pte, gfn);
 263         if (!was_rmapped) {
 264                 rmap_add(vcpu, shadow_pte, gfn);
 265                 if (!is_rmap_pte(*shadow_pte))
 266                         kvm_release_page_clean(page);
 267         }
 268         else
 269                 kvm_release_page_clean(page);
 270         if (!ptwrite || !*ptwrite)
 271                 vcpu->last_pte_updated = shadow_pte;
 272 }
 273
 274 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
 275                               u64 *spte, const void *pte, int bytes,
 276                               int offset_in_pte)
 277 {
 278         pt_element_t gpte;
 279
 280         gpte = *(const pt_element_t *)pte;
 281         if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
 282                 if (!offset_in_pte && !is_present_pte(gpte))
 283                         set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
 284                 return;
 285         }
 286         if (bytes < sizeof(pt_element_t))
 287                 return;
 288         pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
 289         FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0,
 290                        0, NULL, NULL, gpte_to_gfn(gpte));
 291 }
 292
 293 /*
 294  * Fetch a shadow pte for a specific level in the paging hierarchy.
 295  */
 296 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
 297                          struct guest_walker *walker,
 298                          int user_fault, int write_fault, int *ptwrite)
 299 {
 300         hpa_t shadow_addr;
 301         int level;
 302         u64 *shadow_ent;
 303         u64 *prev_shadow_ent = NULL;
 304
 305         if (!is_present_pte(walker->pte))
 306                 return NULL;
 307
 308         shadow_addr = vcpu->mmu.root_hpa;
 309         level = vcpu->mmu.shadow_root_level;
 310         if (level == PT32E_ROOT_LEVEL) {
 311                 shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
 312                 shadow_addr &= PT64_BASE_ADDR_MASK;
 313                 --level;
 314         }
 315
 316         for (; ; level--) {
 317                 u32 index = SHADOW_PT_INDEX(addr, level);
 318                 struct kvm_mmu_page *shadow_page;
 319                 u64 shadow_pte;
 320                 int metaphysical;
 321                 gfn_t table_gfn;
 322                 unsigned hugepage_access = 0;
 323
 324                 shadow_ent = ((u64 *)__va(shadow_addr)) + index;
 325                 if (is_shadow_present_pte(*shadow_ent)) {
 326                         if (level == PT_PAGE_TABLE_LEVEL)
 327                                 break;
 328                         shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
 329                         prev_shadow_ent = shadow_ent;
 330                         continue;
 331                 }
 332
 333                 if (level == PT_PAGE_TABLE_LEVEL)
 334                         break;
 335
 336                 if (level - 1 == PT_PAGE_TABLE_LEVEL
 337                     && walker->level == PT_DIRECTORY_LEVEL) {
 338                         metaphysical = 1;
 339                         hugepage_access = walker->pte;
 340                         hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK;
 341                         if (!is_dirty_pte(walker->pte))
 342                                 hugepage_access &= ~PT_WRITABLE_MASK;
 343                         hugepage_access >>= PT_WRITABLE_SHIFT;
 344                         if (walker->pte & PT64_NX_MASK)
 345                                 hugepage_access |= (1 << 2);
 346                         table_gfn = gpte_to_gfn(walker->pte);
 347                 } else {
 348                         metaphysical = 0;
 349                         table_gfn = walker->table_gfn[level - 2];
 350                 }
 351                 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
 352                                                metaphysical, hugepage_access,
 353                                                shadow_ent);
 354                 shadow_addr = __pa(shadow_page->spt);
 355                 shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
 356                         | PT_WRITABLE_MASK | PT_USER_MASK;
 357                 *shadow_ent = shadow_pte;
 358                 prev_shadow_ent = shadow_ent;
 359         }
 360
 361         FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
 362                        walker->inherited_ar, user_fault, write_fault,
 363                        ptwrite, walker, walker->gfn);
 364
 365         return shadow_ent;
 366 }
 367
 368 /*
 369  * Page fault handler.  There are several causes for a page fault:
 370  *   - there is no shadow pte for the guest pte
 371  *   - write access through a shadow pte marked read only so that we can set
 372  *     the dirty bit
 373  *   - write access to a shadow pte marked read only so we can update the page
 374  *     dirty bitmap, when userspace requests it
 375  *   - mmio access; in this case we will never install a present shadow pte
 376  *   - normal guest page fault due to the guest pte marked not present, not
 377  *     writable, or not executable
 378  *
 379  *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 380  *           a negative value on error.
 381  */
 382 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
 383                                u32 error_code)
 384 {
 385         int write_fault = error_code & PFERR_WRITE_MASK;
 386         int user_fault = error_code & PFERR_USER_MASK;
 387         int fetch_fault = error_code & PFERR_FETCH_MASK;
 388         struct guest_walker walker;
 389         u64 *shadow_pte;
 390         int write_pt = 0;
 391         int r;
 392
 393         pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
 394         kvm_mmu_audit(vcpu, "pre page fault");
 395
 396         r = mmu_topup_memory_caches(vcpu);
 397         if (r)
 398                 return r;
 399
 400         /*
 401          * Look up the shadow pte for the faulting address.
 402          */
 403         r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
 404                              fetch_fault);
 405
 406         /*
 407          * The page is not mapped by the guest.  Let the guest handle it.
 408          */
 409         if (!r) {
 410                 pgprintk("%s: guest page fault\n", __FUNCTION__);
 411                 inject_page_fault(vcpu, addr, walker.error_code);
 412                 vcpu->last_pt_write_count = 0; /* reset fork detector */
 413                 return 0;
 414         }
 415
 416         shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
 417                                   &write_pt);
 418         pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
 419                  shadow_pte, *shadow_pte, write_pt);
 420
 421         if (!write_pt)
 422                 vcpu->last_pt_write_count = 0; /* reset fork detector */
 423
 424         /*
 425          * mmio: emulate if accessible, otherwise its a guest fault.
 426          */
 427         if (is_io_pte(*shadow_pte))
 428                 return 1;
 429
 430         ++vcpu->stat.pf_fixed;
 431         kvm_mmu_audit(vcpu, "post page fault (fixed)");
 432
 433         return write_pt;
 434 }
 435
 436 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
 437 {
 438         struct guest_walker walker;
 439         gpa_t gpa = UNMAPPED_GVA;
 440         int r;
 441
 442         r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
 443
 444         if (r) {
 445                 gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
 446                 gpa |= vaddr & ~PAGE_MASK;
 447         }
 448
 449         return gpa;
 450 }
 451
 452 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
 453                                  struct kvm_mmu_page *sp)
 454 {
 455         int i, offset = 0;
 456         pt_element_t *gpt;
 457         struct page *page;
 458
 459         if (sp->role.metaphysical
 460             || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
 461                 nonpaging_prefetch_page(vcpu, sp);
 462                 return;
 463         }
 464
 465         if (PTTYPE == 32)
 466                 offset = sp->role.quadrant << PT64_LEVEL_BITS;
 467         page = gfn_to_page(vcpu->kvm, sp->gfn);
 468         gpt = kmap_atomic(page, KM_USER0);
 469         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
 470                 if (is_present_pte(gpt[offset + i]))
 471                         sp->spt[i] = shadow_trap_nonpresent_pte;
 472                 else
 473                         sp->spt[i] = shadow_notrap_nonpresent_pte;
 474         kunmap_atomic(gpt, KM_USER0);
 475         kvm_release_page_clean(page);
 476 }
 477
 478 #undef pt_element_t
 479 #undef guest_walker
 480 #undef FNAME
 481 #undef PT_BASE_ADDR_MASK
 482 #undef PT_INDEX
 483 #undef SHADOW_PT_INDEX
 484 #undef PT_LEVEL_MASK
 485 #undef PT_DIR_BASE_ADDR_MASK
 486 #undef PT_LEVEL_BITS
 487 #undef PT_MAX_FULL_LEVELS
 488 #undef gpte_to_gfn
 489 #undef gpte_to_gfn_pde