drivers/kvm/paging_tmpl.h

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * MMU support
   8  *
   9  * Copyright (C) 2006 Qumranet, Inc.
  10  *
  11  * Authors:
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *   Avi Kivity   <avi@qumranet.com>
  14  *
  15  * This work is licensed under the terms of the GNU GPL, version 2.  See
  16  * the COPYING file in the top-level directory.
  17  *
  18  */
  19
  20 /*
  21  * We need the mmu code to access both 32-bit and 64-bit guest ptes,
  22  * so the code in this file is compiled twice, once per pte size.
  23  */
  24
  25 #if PTTYPE == 64
  26         #define pt_element_t u64
  27         #define guest_walker guest_walker64
  28         #define FNAME(name) paging##64_##name
  29         #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
  30         #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
  31         #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
  32         #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
  33         #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
  34         #define PT_LEVEL_BITS PT64_LEVEL_BITS
  35         #ifdef CONFIG_X86_64
  36         #define PT_MAX_FULL_LEVELS 4
  37         #else
  38         #define PT_MAX_FULL_LEVELS 2
  39         #endif
  40 #elif PTTYPE == 32
  41         #define pt_element_t u32
  42         #define guest_walker guest_walker32
  43         #define FNAME(name) paging##32_##name
  44         #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
  45         #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
  46         #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
  47         #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
  48         #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
  49         #define PT_LEVEL_BITS PT32_LEVEL_BITS
  50         #define PT_MAX_FULL_LEVELS 2
  51 #else
  52         #error Invalid PTTYPE value
  53 #endif
  54
  55 /*
  56  * The guest_walker structure emulates the behavior of the hardware page
  57  * table walker.
  58  */
  59 struct guest_walker {
  60         int level;
  61         gfn_t table_gfn[PT_MAX_FULL_LEVELS];
  62         pt_element_t pte;
  63         pt_element_t inherited_ar;
  64         gfn_t gfn;
  65         u32 error_code;
  66 };
  67
  68 /*
  69  * Fetch a guest pte for a guest virtual address
  70  */
  71 static int FNAME(walk_addr)(struct guest_walker *walker,
  72                             struct kvm_vcpu *vcpu, gva_t addr,
  73                             int write_fault, int user_fault, int fetch_fault)
  74 {
  75         hpa_t hpa;
  76         struct kvm_memory_slot *slot;
  77         struct page *page;
  78         pt_element_t *table;
  79         pt_element_t pte;
  80         gfn_t table_gfn;
  81         unsigned index;
  82         gpa_t pte_gpa;
  83
  84         pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
  85         walker->level = vcpu->mmu.root_level;
  86         pte = vcpu->cr3;
  87 #if PTTYPE == 64
  88         if (!is_long_mode(vcpu)) {
  89                 pte = vcpu->pdptrs[(addr >> 30) & 3];
  90                 if (!is_present_pte(pte))
  91                         goto not_present;
  92                 --walker->level;
  93         }
  94 #endif
  95         ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
  96                (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
  97
  98         walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;
  99
 100         for (;;) {
 101                 index = PT_INDEX(addr, walker->level);
 102
 103                 table_gfn = (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
 104                 walker->table_gfn[walker->level - 1] = table_gfn;
 105                 pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
 106                          walker->level - 1, table_gfn);
 107
 108                 slot = gfn_to_memslot(vcpu->kvm, table_gfn);
 109                 hpa = safe_gpa_to_hpa(vcpu->kvm, pte & PT64_BASE_ADDR_MASK);
 110                 page = pfn_to_page(hpa >> PAGE_SHIFT);
 111
 112                 table = kmap_atomic(page, KM_USER0);
 113                 pte = table[index];
 114                 kunmap_atomic(table, KM_USER0);
 115
 116                 if (!is_present_pte(pte))
 117                         goto not_present;
 118
 119                 if (write_fault && !is_writeble_pte(pte))
 120                         if (user_fault || is_write_protection(vcpu))
 121                                 goto access_error;
 122
 123                 if (user_fault && !(pte & PT_USER_MASK))
 124                         goto access_error;
 125
 126 #if PTTYPE == 64
 127                 if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
 128                         goto access_error;
 129 #endif
 130
 131                 if (!(pte & PT_ACCESSED_MASK)) {
 132                         mark_page_dirty(vcpu->kvm, table_gfn);
 133                         pte |= PT_ACCESSED_MASK;
 134                         table = kmap_atomic(page, KM_USER0);
 135                         table[index] = pte;
 136                         kunmap_atomic(table, KM_USER0);
 137                 }
 138
 139                 if (walker->level == PT_PAGE_TABLE_LEVEL) {
 140                         walker->gfn = (pte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
 141                         break;
 142                 }
 143
 144                 if (walker->level == PT_DIRECTORY_LEVEL
 145                     && (pte & PT_PAGE_SIZE_MASK)
 146                     && (PTTYPE == 64 || is_pse(vcpu))) {
 147                         walker->gfn = (pte & PT_DIR_BASE_ADDR_MASK)
 148                                 >> PAGE_SHIFT;
 149                         walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
 150                         break;
 151                 }
 152
 153                 walker->inherited_ar &= pte;
 154                 --walker->level;
 155         }
 156
 157         if (write_fault && !is_dirty_pte(pte)) {
 158                 mark_page_dirty(vcpu->kvm, table_gfn);
 159                 pte |= PT_DIRTY_MASK;
 160                 table = kmap_atomic(page, KM_USER0);
 161                 table[index] = pte;
 162                 kunmap_atomic(table, KM_USER0);
 163                 pte_gpa = table_gfn << PAGE_SHIFT;
 164                 pte_gpa += index * sizeof(pt_element_t);
 165                 kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
 166         }
 167
 168         walker->pte = pte;
 169         pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)pte);
 170         return 1;
 171
 172 not_present:
 173         walker->error_code = 0;
 174         goto err;
 175
 176 access_error:
 177         walker->error_code = PFERR_PRESENT_MASK;
 178
 179 err:
 180         if (write_fault)
 181                 walker->error_code |= PFERR_WRITE_MASK;
 182         if (user_fault)
 183                 walker->error_code |= PFERR_USER_MASK;
 184         if (fetch_fault)
 185                 walker->error_code |= PFERR_FETCH_MASK;
 186         return 0;
 187 }
 188
 189 static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu,
 190                                   u64 *shadow_pte,
 191                                   gpa_t gaddr,
 192                                   pt_element_t gpte,
 193                                   u64 access_bits,
 194                                   int user_fault,
 195                                   int write_fault,
 196                                   int *ptwrite,
 197                                   struct guest_walker *walker,
 198                                   gfn_t gfn)
 199 {
 200         hpa_t paddr;
 201         int dirty = gpte & PT_DIRTY_MASK;
 202         u64 spte;
 203         int was_rmapped = is_rmap_pte(*shadow_pte);
 204
 205         pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
 206                  " user_fault %d gfn %lx\n",
 207                  __FUNCTION__, *shadow_pte, (u64)gpte, access_bits,
 208                  write_fault, user_fault, gfn);
 209
 210         /*
 211          * We don't set the accessed bit, since we sometimes want to see
 212          * whether the guest actually used the pte (in order to detect
 213          * demand paging).
 214          */
 215         spte = PT_PRESENT_MASK | PT_DIRTY_MASK;
 216         spte |= gpte & PT64_NX_MASK;
 217         if (!dirty)
 218                 access_bits &= ~PT_WRITABLE_MASK;
 219
 220         paddr = gpa_to_hpa(vcpu->kvm, gaddr & PT64_BASE_ADDR_MASK);
 221
 222         spte |= PT_PRESENT_MASK;
 223         if (access_bits & PT_USER_MASK)
 224                 spte |= PT_USER_MASK;
 225
 226         if (is_error_hpa(paddr)) {
 227                 set_shadow_pte(shadow_pte,
 228                                shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK);
 229                 return;
 230         }
 231
 232         spte |= paddr;
 233
 234         if ((access_bits & PT_WRITABLE_MASK)
 235             || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
 236                 struct kvm_mmu_page *shadow;
 237
 238                 spte |= PT_WRITABLE_MASK;
 239                 if (user_fault) {
 240                         mmu_unshadow(vcpu->kvm, gfn);
 241                         goto unshadowed;
 242                 }
 243
 244                 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
 245                 if (shadow) {
 246                         pgprintk("%s: found shadow page for %lx, marking ro\n",
 247                                  __FUNCTION__, gfn);
 248                         access_bits &= ~PT_WRITABLE_MASK;
 249                         if (is_writeble_pte(spte)) {
 250                                 spte &= ~PT_WRITABLE_MASK;
 251                                 kvm_x86_ops->tlb_flush(vcpu);
 252                         }
 253                         if (write_fault)
 254                                 *ptwrite = 1;
 255                 }
 256         }
 257
 258 unshadowed:
 259
 260         if (access_bits & PT_WRITABLE_MASK)
 261                 mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT);
 262
 263         pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
 264         set_shadow_pte(shadow_pte, spte);
 265         page_header_update_slot(vcpu->kvm, shadow_pte, gaddr);
 266         if (!was_rmapped)
 267                 rmap_add(vcpu, shadow_pte, (gaddr & PT64_BASE_ADDR_MASK)
 268                          >> PAGE_SHIFT);
 269         if (!ptwrite || !*ptwrite)
 270                 vcpu->last_pte_updated = shadow_pte;
 271 }
 272
 273 static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
 274                            u64 *shadow_pte, u64 access_bits,
 275                            int user_fault, int write_fault, int *ptwrite,
 276                            struct guest_walker *walker, gfn_t gfn)
 277 {
 278         access_bits &= gpte;
 279         FNAME(set_pte_common)(vcpu, shadow_pte, gpte & PT_BASE_ADDR_MASK,
 280                               gpte, access_bits, user_fault, write_fault,
 281                               ptwrite, walker, gfn);
 282 }
 283
 284 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
 285                               u64 *spte, const void *pte, int bytes,
 286                               int offset_in_pte)
 287 {
 288         pt_element_t gpte;
 289
 290         gpte = *(const pt_element_t *)pte;
 291         if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
 292                 if (!offset_in_pte && !is_present_pte(gpte))
 293                         set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
 294                 return;
 295         }
 296         if (bytes < sizeof(pt_element_t))
 297                 return;
 298         pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
 299         FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0,
 300                        0, NULL, NULL,
 301                        (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT);
 302 }
 303
 304 static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t gpde,
 305                            u64 *shadow_pte, u64 access_bits,
 306                            int user_fault, int write_fault, int *ptwrite,
 307                            struct guest_walker *walker, gfn_t gfn)
 308 {
 309         gpa_t gaddr;
 310
 311         access_bits &= gpde;
 312         gaddr = (gpa_t)gfn << PAGE_SHIFT;
 313         if (PTTYPE == 32 && is_cpuid_PSE36())
 314                 gaddr |= (gpde & PT32_DIR_PSE36_MASK) <<
 315                         (32 - PT32_DIR_PSE36_SHIFT);
 316         FNAME(set_pte_common)(vcpu, shadow_pte, gaddr,
 317                               gpde, access_bits, user_fault, write_fault,
 318                               ptwrite, walker, gfn);
 319 }
 320
 321 /*
 322  * Fetch a shadow pte for a specific level in the paging hierarchy.
 323  */
 324 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
 325                          struct guest_walker *walker,
 326                          int user_fault, int write_fault, int *ptwrite)
 327 {
 328         hpa_t shadow_addr;
 329         int level;
 330         u64 *shadow_ent;
 331         u64 *prev_shadow_ent = NULL;
 332
 333         if (!is_present_pte(walker->pte))
 334                 return NULL;
 335
 336         shadow_addr = vcpu->mmu.root_hpa;
 337         level = vcpu->mmu.shadow_root_level;
 338         if (level == PT32E_ROOT_LEVEL) {
 339                 shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
 340                 shadow_addr &= PT64_BASE_ADDR_MASK;
 341                 --level;
 342         }
 343
 344         for (; ; level--) {
 345                 u32 index = SHADOW_PT_INDEX(addr, level);
 346                 struct kvm_mmu_page *shadow_page;
 347                 u64 shadow_pte;
 348                 int metaphysical;
 349                 gfn_t table_gfn;
 350                 unsigned hugepage_access = 0;
 351
 352                 shadow_ent = ((u64 *)__va(shadow_addr)) + index;
 353                 if (is_shadow_present_pte(*shadow_ent)) {
 354                         if (level == PT_PAGE_TABLE_LEVEL)
 355                                 break;
 356                         shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
 357                         prev_shadow_ent = shadow_ent;
 358                         continue;
 359                 }
 360
 361                 if (level == PT_PAGE_TABLE_LEVEL)
 362                         break;
 363
 364                 if (level - 1 == PT_PAGE_TABLE_LEVEL
 365                     && walker->level == PT_DIRECTORY_LEVEL) {
 366                         metaphysical = 1;
 367                         hugepage_access = walker->pte;
 368                         hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK;
 369                         if (!is_dirty_pte(walker->pte))
 370                                 hugepage_access &= ~PT_WRITABLE_MASK;
 371                         hugepage_access >>= PT_WRITABLE_SHIFT;
 372                         if (walker->pte & PT64_NX_MASK)
 373                                 hugepage_access |= (1 << 2);
 374                         table_gfn = (walker->pte & PT_BASE_ADDR_MASK)
 375                                 >> PAGE_SHIFT;
 376                 } else {
 377                         metaphysical = 0;
 378                         table_gfn = walker->table_gfn[level - 2];
 379                 }
 380                 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
 381                                                metaphysical, hugepage_access,
 382                                                shadow_ent);
 383                 shadow_addr = __pa(shadow_page->spt);
 384                 shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
 385                         | PT_WRITABLE_MASK | PT_USER_MASK;
 386                 *shadow_ent = shadow_pte;
 387                 prev_shadow_ent = shadow_ent;
 388         }
 389
 390         if (walker->level == PT_DIRECTORY_LEVEL) {
 391                 FNAME(set_pde)(vcpu, walker->pte, shadow_ent,
 392                                walker->inherited_ar, user_fault, write_fault,
 393                                ptwrite, walker, walker->gfn);
 394         } else {
 395                 ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
 396                 FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
 397                                walker->inherited_ar, user_fault, write_fault,
 398                                ptwrite, walker, walker->gfn);
 399         }
 400         return shadow_ent;
 401 }
 402
 403 /*
 404  * Page fault handler.  There are several causes for a page fault:
 405  *   - there is no shadow pte for the guest pte
 406  *   - write access through a shadow pte marked read only so that we can set
 407  *     the dirty bit
 408  *   - write access to a shadow pte marked read only so we can update the page
 409  *     dirty bitmap, when userspace requests it
 410  *   - mmio access; in this case we will never install a present shadow pte
 411  *   - normal guest page fault due to the guest pte marked not present, not
 412  *     writable, or not executable
 413  *
 414  *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 415  *           a negative value on error.
 416  */
 417 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
 418                                u32 error_code)
 419 {
 420         int write_fault = error_code & PFERR_WRITE_MASK;
 421         int user_fault = error_code & PFERR_USER_MASK;
 422         int fetch_fault = error_code & PFERR_FETCH_MASK;
 423         struct guest_walker walker;
 424         u64 *shadow_pte;
 425         int write_pt = 0;
 426         int r;
 427
 428         pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
 429         kvm_mmu_audit(vcpu, "pre page fault");
 430
 431         r = mmu_topup_memory_caches(vcpu);
 432         if (r)
 433                 return r;
 434
 435         /*
 436          * Look up the shadow pte for the faulting address.
 437          */
 438         r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
 439                              fetch_fault);
 440
 441         /*
 442          * The page is not mapped by the guest.  Let the guest handle it.
 443          */
 444         if (!r) {
 445                 pgprintk("%s: guest page fault\n", __FUNCTION__);
 446                 inject_page_fault(vcpu, addr, walker.error_code);
 447                 vcpu->last_pt_write_count = 0; /* reset fork detector */
 448                 return 0;
 449         }
 450
 451         shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
 452                                   &write_pt);
 453         pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
 454                  shadow_pte, *shadow_pte, write_pt);
 455
 456         if (!write_pt)
 457                 vcpu->last_pt_write_count = 0; /* reset fork detector */
 458
 459         /*
 460          * mmio: emulate if accessible, otherwise its a guest fault.
 461          */
 462         if (is_io_pte(*shadow_pte))
 463                 return 1;
 464
 465         ++vcpu->stat.pf_fixed;
 466         kvm_mmu_audit(vcpu, "post page fault (fixed)");
 467
 468         return write_pt;
 469 }
 470
 471 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
 472 {
 473         struct guest_walker walker;
 474         gpa_t gpa = UNMAPPED_GVA;
 475         int r;
 476
 477         r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
 478
 479         if (r) {
 480                 gpa = (gpa_t)walker.gfn << PAGE_SHIFT;
 481                 gpa |= vaddr & ~PAGE_MASK;
 482         }
 483
 484         return gpa;
 485 }
 486
 487 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
 488                                  struct kvm_mmu_page *sp)
 489 {
 490         int i;
 491         pt_element_t *gpt;
 492
 493         if (sp->role.metaphysical || PTTYPE == 32) {
 494                 nonpaging_prefetch_page(vcpu, sp);
 495                 return;
 496         }
 497
 498         gpt = kmap_atomic(gfn_to_page(vcpu->kvm, sp->gfn), KM_USER0);
 499         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
 500                 if (is_present_pte(gpt[i]))
 501                         sp->spt[i] = shadow_trap_nonpresent_pte;
 502                 else
 503                         sp->spt[i] = shadow_notrap_nonpresent_pte;
 504         kunmap_atomic(gpt, KM_USER0);
 505 }
 506
 507 #undef pt_element_t
 508 #undef guest_walker
 509 #undef FNAME
 510 #undef PT_BASE_ADDR_MASK
 511 #undef PT_INDEX
 512 #undef SHADOW_PT_INDEX
 513 #undef PT_LEVEL_MASK
 514 #undef PT_DIR_BASE_ADDR_MASK
 515 #undef PT_LEVEL_BITS
 516 #undef PT_MAX_FULL_LEVELS