projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
KVM: Generalize exception injection mechanism
[deliverable/linux.git] / drivers / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include "x86.h"
17 #include "kvm_svm.h"
18 #include "x86_emulate.h"
19 #include "irq.h"
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/vmalloc.h>
24 #include <linux/highmem.h>
25 #include <linux/sched.h>
26
27 #include <asm/desc.h>
28
29 MODULE_AUTHOR("Qumranet");
30 MODULE_LICENSE("GPL");
31
32 #define IOPM_ALLOC_ORDER 2
33 #define MSRPM_ALLOC_ORDER 1
34
35 #define DB_VECTOR 1
36 #define UD_VECTOR 6
37 #define GP_VECTOR 13
38
39 #define DR7_GD_MASK (1 << 13)
40 #define DR6_BD_MASK (1 << 13)
41
42 #define SEG_TYPE_LDT 2
43 #define SEG_TYPE_BUSY_TSS16 3
44
45 #define SVM_FEATURE_NPT (1 << 0)
46 #define SVM_FEATURE_LBRV (1 << 1)
47 #define SVM_DEATURE_SVML (1 << 2)
48
49 static void kvm_reput_irq(struct vcpu_svm *svm);
50
51 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
52 {
53 return container_of(vcpu, struct vcpu_svm, vcpu);
54 }
55
56 unsigned long iopm_base;
57 unsigned long msrpm_base;
58
59 struct kvm_ldttss_desc {
60 u16 limit0;
61 u16 base0;
62 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
63 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
64 u32 base3;
65 u32 zero1;
66 } __attribute__((packed));
67
68 struct svm_cpu_data {
69 int cpu;
70
71 u64 asid_generation;
72 u32 max_asid;
73 u32 next_asid;
74 struct kvm_ldttss_desc *tss_desc;
75
76 struct page *save_area;
77 };
78
79 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80 static uint32_t svm_features;
81
82 struct svm_init_data {
83 int cpu;
84 int r;
85 };
86
87 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
88
89 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
90 #define MSRS_RANGE_SIZE 2048
91 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
92
93 #define MAX_INST_SIZE 15
94
95 static inline u32 svm_has(u32 feat)
96 {
97 return svm_features & feat;
98 }
99
100 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
101 {
102 int word_index = __ffs(vcpu->irq_summary);
103 int bit_index = __ffs(vcpu->irq_pending[word_index]);
104 int irq = word_index * BITS_PER_LONG + bit_index;
105
106 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
107 if (!vcpu->irq_pending[word_index])
108 clear_bit(word_index, &vcpu->irq_summary);
109 return irq;
110 }
111
112 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
113 {
114 set_bit(irq, vcpu->irq_pending);
115 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
116 }
117
118 static inline void clgi(void)
119 {
120 asm volatile (SVM_CLGI);
121 }
122
123 static inline void stgi(void)
124 {
125 asm volatile (SVM_STGI);
126 }
127
128 static inline void invlpga(unsigned long addr, u32 asid)
129 {
130 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
131 }
132
133 static inline unsigned long kvm_read_cr2(void)
134 {
135 unsigned long cr2;
136
137 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
138 return cr2;
139 }
140
141 static inline void kvm_write_cr2(unsigned long val)
142 {
143 asm volatile ("mov %0, %%cr2" :: "r" (val));
144 }
145
146 static inline unsigned long read_dr6(void)
147 {
148 unsigned long dr6;
149
150 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
151 return dr6;
152 }
153
154 static inline void write_dr6(unsigned long val)
155 {
156 asm volatile ("mov %0, %%dr6" :: "r" (val));
157 }
158
159 static inline unsigned long read_dr7(void)
160 {
161 unsigned long dr7;
162
163 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
164 return dr7;
165 }
166
167 static inline void write_dr7(unsigned long val)
168 {
169 asm volatile ("mov %0, %%dr7" :: "r" (val));
170 }
171
172 static inline void force_new_asid(struct kvm_vcpu *vcpu)
173 {
174 to_svm(vcpu)->asid_generation--;
175 }
176
177 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
178 {
179 force_new_asid(vcpu);
180 }
181
182 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
183 {
184 if (!(efer & EFER_LMA))
185 efer &= ~EFER_LME;
186
187 to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
188 vcpu->shadow_efer = efer;
189 }
190
191 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
192 bool has_error_code, u32 error_code)
193 {
194 struct vcpu_svm *svm = to_svm(vcpu);
195
196 svm->vmcb->control.event_inj = nr
197 | SVM_EVTINJ_VALID
198 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
199 | SVM_EVTINJ_TYPE_EXEPT;
200 svm->vmcb->control.event_inj_err = error_code;
201 }
202
203 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
204 {
205 struct vcpu_svm *svm = to_svm(vcpu);
206
207 return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
208 }
209
210 static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
211 {
212 struct vcpu_svm *svm = to_svm(vcpu);
213
214 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
215 SVM_EVTINJ_VALID_ERR |
216 SVM_EVTINJ_TYPE_EXEPT |
217 GP_VECTOR;
218 svm->vmcb->control.event_inj_err = error_code;
219 }
220
221 static void inject_ud(struct kvm_vcpu *vcpu)
222 {
223 to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID |
224 SVM_EVTINJ_TYPE_EXEPT |
225 UD_VECTOR;
226 }
227
228 static int is_page_fault(uint32_t info)
229 {
230 info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
231 return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
232 }
233
234 static int is_external_interrupt(u32 info)
235 {
236 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
237 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
238 }
239
240 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
241 {
242 struct vcpu_svm *svm = to_svm(vcpu);
243
244 if (!svm->next_rip) {
245 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
246 return;
247 }
248 if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
249 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
250 __FUNCTION__,
251 svm->vmcb->save.rip,
252 svm->next_rip);
253
254 vcpu->rip = svm->vmcb->save.rip = svm->next_rip;
255 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
256
257 vcpu->interrupt_window_open = 1;
258 }
259
260 static int has_svm(void)
261 {
262 uint32_t eax, ebx, ecx, edx;
263
264 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
265 printk(KERN_INFO "has_svm: not amd\n");
266 return 0;
267 }
268
269 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
270 if (eax < SVM_CPUID_FUNC) {
271 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
272 return 0;
273 }
274
275 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
276 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
277 printk(KERN_DEBUG "has_svm: svm not available\n");
278 return 0;
279 }
280 return 1;
281 }
282
283 static void svm_hardware_disable(void *garbage)
284 {
285 struct svm_cpu_data *svm_data
286 = per_cpu(svm_data, raw_smp_processor_id());
287
288 if (svm_data) {
289 uint64_t efer;
290
291 wrmsrl(MSR_VM_HSAVE_PA, 0);
292 rdmsrl(MSR_EFER, efer);
293 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
294 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
295 __free_page(svm_data->save_area);
296 kfree(svm_data);
297 }
298 }
299
300 static void svm_hardware_enable(void *garbage)
301 {
302
303 struct svm_cpu_data *svm_data;
304 uint64_t efer;
305 #ifdef CONFIG_X86_64
306 struct desc_ptr gdt_descr;
307 #else
308 struct desc_ptr gdt_descr;
309 #endif
310 struct desc_struct *gdt;
311 int me = raw_smp_processor_id();
312
313 if (!has_svm()) {
314 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
315 return;
316 }
317 svm_data = per_cpu(svm_data, me);
318
319 if (!svm_data) {
320 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
321 me);
322 return;
323 }
324
325 svm_data->asid_generation = 1;
326 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
327 svm_data->next_asid = svm_data->max_asid + 1;
328 svm_features = cpuid_edx(SVM_CPUID_FUNC);
329
330 asm volatile ("sgdt %0" : "=m"(gdt_descr));
331 gdt = (struct desc_struct *)gdt_descr.address;
332 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
333
334 rdmsrl(MSR_EFER, efer);
335 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
336
337 wrmsrl(MSR_VM_HSAVE_PA,
338 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
339 }
340
341 static int svm_cpu_init(int cpu)
342 {
343 struct svm_cpu_data *svm_data;
344 int r;
345
346 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
347 if (!svm_data)
348 return -ENOMEM;
349 svm_data->cpu = cpu;
350 svm_data->save_area = alloc_page(GFP_KERNEL);
351 r = -ENOMEM;
352 if (!svm_data->save_area)
353 goto err_1;
354
355 per_cpu(svm_data, cpu) = svm_data;
356
357 return 0;
358
359 err_1:
360 kfree(svm_data);
361 return r;
362
363 }
364
365 static void set_msr_interception(u32 *msrpm, unsigned msr,
366 int read, int write)
367 {
368 int i;
369
370 for (i = 0; i < NUM_MSR_MAPS; i++) {
371 if (msr >= msrpm_ranges[i] &&
372 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
373 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
374 msrpm_ranges[i]) * 2;
375
376 u32 *base = msrpm + (msr_offset / 32);
377 u32 msr_shift = msr_offset % 32;
378 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
379 *base = (*base & ~(0x3 << msr_shift)) |
380 (mask << msr_shift);
381 return;
382 }
383 }
384 BUG();
385 }
386
387 static __init int svm_hardware_setup(void)
388 {
389 int cpu;
390 struct page *iopm_pages;
391 struct page *msrpm_pages;
392 void *iopm_va, *msrpm_va;
393 int r;
394
395 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
396
397 if (!iopm_pages)
398 return -ENOMEM;
399
400 iopm_va = page_address(iopm_pages);
401 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
402 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
403 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
404
405
406 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
407
408 r = -ENOMEM;
409 if (!msrpm_pages)
410 goto err_1;
411
412 msrpm_va = page_address(msrpm_pages);
413 memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
414 msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
415
416 #ifdef CONFIG_X86_64
417 set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
418 set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
419 set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
420 set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
421 set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
422 set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
423 #endif
424 set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
425 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
426 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
427 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
428
429 for_each_online_cpu(cpu) {
430 r = svm_cpu_init(cpu);
431 if (r)
432 goto err_2;
433 }
434 return 0;
435
436 err_2:
437 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
438 msrpm_base = 0;
439 err_1:
440 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
441 iopm_base = 0;
442 return r;
443 }
444
445 static __exit void svm_hardware_unsetup(void)
446 {
447 __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
448 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
449 iopm_base = msrpm_base = 0;
450 }
451
452 static void init_seg(struct vmcb_seg *seg)
453 {
454 seg->selector = 0;
455 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
456 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
457 seg->limit = 0xffff;
458 seg->base = 0;
459 }
460
461 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
462 {
463 seg->selector = 0;
464 seg->attrib = SVM_SELECTOR_P_MASK | type;
465 seg->limit = 0xffff;
466 seg->base = 0;
467 }
468
469 static void init_vmcb(struct vmcb *vmcb)
470 {
471 struct vmcb_control_area *control = &vmcb->control;
472 struct vmcb_save_area *save = &vmcb->save;
473
474 control->intercept_cr_read = INTERCEPT_CR0_MASK |
475 INTERCEPT_CR3_MASK |
476 INTERCEPT_CR4_MASK;
477
478 control->intercept_cr_write = INTERCEPT_CR0_MASK |
479 INTERCEPT_CR3_MASK |
480 INTERCEPT_CR4_MASK;
481
482 control->intercept_dr_read = INTERCEPT_DR0_MASK |
483 INTERCEPT_DR1_MASK |
484 INTERCEPT_DR2_MASK |
485 INTERCEPT_DR3_MASK;
486
487 control->intercept_dr_write = INTERCEPT_DR0_MASK |
488 INTERCEPT_DR1_MASK |
489 INTERCEPT_DR2_MASK |
490 INTERCEPT_DR3_MASK |
491 INTERCEPT_DR5_MASK |
492 INTERCEPT_DR7_MASK;
493
494 control->intercept_exceptions = (1 << PF_VECTOR) |
495 (1 << UD_VECTOR);
496
497
498 control->intercept = (1ULL << INTERCEPT_INTR) |
499 (1ULL << INTERCEPT_NMI) |
500 (1ULL << INTERCEPT_SMI) |
501 /*
502 * selective cr0 intercept bug?
503 * 0: 0f 22 d8 mov %eax,%cr3
504 * 3: 0f 20 c0 mov %cr0,%eax
505 * 6: 0d 00 00 00 80 or $0x80000000,%eax
506 * b: 0f 22 c0 mov %eax,%cr0
507 * set cr3 ->interception
508 * get cr0 ->interception
509 * set cr0 -> no interception
510 */
511 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
512 (1ULL << INTERCEPT_CPUID) |
513 (1ULL << INTERCEPT_INVD) |
514 (1ULL << INTERCEPT_HLT) |
515 (1ULL << INTERCEPT_INVLPGA) |
516 (1ULL << INTERCEPT_IOIO_PROT) |
517 (1ULL << INTERCEPT_MSR_PROT) |
518 (1ULL << INTERCEPT_TASK_SWITCH) |
519 (1ULL << INTERCEPT_SHUTDOWN) |
520 (1ULL << INTERCEPT_VMRUN) |
521 (1ULL << INTERCEPT_VMMCALL) |
522 (1ULL << INTERCEPT_VMLOAD) |
523 (1ULL << INTERCEPT_VMSAVE) |
524 (1ULL << INTERCEPT_STGI) |
525 (1ULL << INTERCEPT_CLGI) |
526 (1ULL << INTERCEPT_SKINIT) |
527 (1ULL << INTERCEPT_WBINVD) |
528 (1ULL << INTERCEPT_MONITOR) |
529 (1ULL << INTERCEPT_MWAIT);
530
531 control->iopm_base_pa = iopm_base;
532 control->msrpm_base_pa = msrpm_base;
533 control->tsc_offset = 0;
534 control->int_ctl = V_INTR_MASKING_MASK;
535
536 init_seg(&save->es);
537 init_seg(&save->ss);
538 init_seg(&save->ds);
539 init_seg(&save->fs);
540 init_seg(&save->gs);
541
542 save->cs.selector = 0xf000;
543 /* Executable/Readable Code Segment */
544 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
545 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
546 save->cs.limit = 0xffff;
547 /*
548 * cs.base should really be 0xffff0000, but vmx can't handle that, so
549 * be consistent with it.
550 *
551 * Replace when we have real mode working for vmx.
552 */
553 save->cs.base = 0xf0000;
554
555 save->gdtr.limit = 0xffff;
556 save->idtr.limit = 0xffff;
557
558 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
559 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
560
561 save->efer = MSR_EFER_SVME_MASK;
562 save->dr6 = 0xffff0ff0;
563 save->dr7 = 0x400;
564 save->rflags = 2;
565 save->rip = 0x0000fff0;
566
567 /*
568 * cr0 val on cpu init should be 0x60000010, we enable cpu
569 * cache by default. the orderly way is to enable cache in bios.
570 */
571 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
572 save->cr4 = X86_CR4_PAE;
573 /* rdx = ?? */
574 }
575
576 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
577 {
578 struct vcpu_svm *svm = to_svm(vcpu);
579
580 init_vmcb(svm->vmcb);
581
582 if (vcpu->vcpu_id != 0) {
583 svm->vmcb->save.rip = 0;
584 svm->vmcb->save.cs.base = svm->vcpu.sipi_vector << 12;
585 svm->vmcb->save.cs.selector = svm->vcpu.sipi_vector << 8;
586 }
587
588 return 0;
589 }
590
591 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
592 {
593 struct vcpu_svm *svm;
594 struct page *page;
595 int err;
596
597 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
598 if (!svm) {
599 err = -ENOMEM;
600 goto out;
601 }
602
603 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
604 if (err)
605 goto free_svm;
606
607 page = alloc_page(GFP_KERNEL);
608 if (!page) {
609 err = -ENOMEM;
610 goto uninit;
611 }
612
613 svm->vmcb = page_address(page);
614 clear_page(svm->vmcb);
615 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
616 svm->asid_generation = 0;
617 memset(svm->db_regs, 0, sizeof(svm->db_regs));
618 init_vmcb(svm->vmcb);
619
620 fx_init(&svm->vcpu);
621 svm->vcpu.fpu_active = 1;
622 svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
623 if (svm->vcpu.vcpu_id == 0)
624 svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP;
625
626 return &svm->vcpu;
627
628 uninit:
629 kvm_vcpu_uninit(&svm->vcpu);
630 free_svm:
631 kmem_cache_free(kvm_vcpu_cache, svm);
632 out:
633 return ERR_PTR(err);
634 }
635
636 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
637 {
638 struct vcpu_svm *svm = to_svm(vcpu);
639
640 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
641 kvm_vcpu_uninit(vcpu);
642 kmem_cache_free(kvm_vcpu_cache, svm);
643 }
644
645 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
646 {
647 struct vcpu_svm *svm = to_svm(vcpu);
648 int i;
649
650 if (unlikely(cpu != vcpu->cpu)) {
651 u64 tsc_this, delta;
652
653 /*
654 * Make sure that the guest sees a monotonically
655 * increasing TSC.
656 */
657 rdtscll(tsc_this);
658 delta = vcpu->host_tsc - tsc_this;
659 svm->vmcb->control.tsc_offset += delta;
660 vcpu->cpu = cpu;
661 kvm_migrate_apic_timer(vcpu);
662 }
663
664 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
665 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
666 }
667
668 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
669 {
670 struct vcpu_svm *svm = to_svm(vcpu);
671 int i;
672
673 ++vcpu->stat.host_state_reload;
674 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
675 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
676
677 rdtscll(vcpu->host_tsc);
678 }
679
680 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
681 {
682 }
683
684 static void svm_cache_regs(struct kvm_vcpu *vcpu)
685 {
686 struct vcpu_svm *svm = to_svm(vcpu);
687
688 vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
689 vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
690 vcpu->rip = svm->vmcb->save.rip;
691 }
692
693 static void svm_decache_regs(struct kvm_vcpu *vcpu)
694 {
695 struct vcpu_svm *svm = to_svm(vcpu);
696 svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
697 svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
698 svm->vmcb->save.rip = vcpu->rip;
699 }
700
701 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
702 {
703 return to_svm(vcpu)->vmcb->save.rflags;
704 }
705
706 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
707 {
708 to_svm(vcpu)->vmcb->save.rflags = rflags;
709 }
710
711 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
712 {
713 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
714
715 switch (seg) {
716 case VCPU_SREG_CS: return &save->cs;
717 case VCPU_SREG_DS: return &save->ds;
718 case VCPU_SREG_ES: return &save->es;
719 case VCPU_SREG_FS: return &save->fs;
720 case VCPU_SREG_GS: return &save->gs;
721 case VCPU_SREG_SS: return &save->ss;
722 case VCPU_SREG_TR: return &save->tr;
723 case VCPU_SREG_LDTR: return &save->ldtr;
724 }
725 BUG();
726 return NULL;
727 }
728
729 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
730 {
731 struct vmcb_seg *s = svm_seg(vcpu, seg);
732
733 return s->base;
734 }
735
736 static void svm_get_segment(struct kvm_vcpu *vcpu,
737 struct kvm_segment *var, int seg)
738 {
739 struct vmcb_seg *s = svm_seg(vcpu, seg);
740
741 var->base = s->base;
742 var->limit = s->limit;
743 var->selector = s->selector;
744 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
745 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
746 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
747 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
748 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
749 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
750 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
751 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
752 var->unusable = !var->present;
753 }
754
755 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
756 {
757 struct vcpu_svm *svm = to_svm(vcpu);
758
759 dt->limit = svm->vmcb->save.idtr.limit;
760 dt->base = svm->vmcb->save.idtr.base;
761 }
762
763 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
764 {
765 struct vcpu_svm *svm = to_svm(vcpu);
766
767 svm->vmcb->save.idtr.limit = dt->limit;
768 svm->vmcb->save.idtr.base = dt->base ;
769 }
770
771 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
772 {
773 struct vcpu_svm *svm = to_svm(vcpu);
774
775 dt->limit = svm->vmcb->save.gdtr.limit;
776 dt->base = svm->vmcb->save.gdtr.base;
777 }
778
779 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
780 {
781 struct vcpu_svm *svm = to_svm(vcpu);
782
783 svm->vmcb->save.gdtr.limit = dt->limit;
784 svm->vmcb->save.gdtr.base = dt->base ;
785 }
786
787 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
788 {
789 }
790
791 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
792 {
793 struct vcpu_svm *svm = to_svm(vcpu);
794
795 #ifdef CONFIG_X86_64
796 if (vcpu->shadow_efer & EFER_LME) {
797 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
798 vcpu->shadow_efer |= EFER_LMA;
799 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
800 }
801
802 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
803 vcpu->shadow_efer &= ~EFER_LMA;
804 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
805 }
806 }
807 #endif
808 if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
809 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
810 vcpu->fpu_active = 1;
811 }
812
813 vcpu->cr0 = cr0;
814 cr0 |= X86_CR0_PG | X86_CR0_WP;
815 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
816 svm->vmcb->save.cr0 = cr0;
817 }
818
819 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
820 {
821 vcpu->cr4 = cr4;
822 to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
823 }
824
825 static void svm_set_segment(struct kvm_vcpu *vcpu,
826 struct kvm_segment *var, int seg)
827 {
828 struct vcpu_svm *svm = to_svm(vcpu);
829 struct vmcb_seg *s = svm_seg(vcpu, seg);
830
831 s->base = var->base;
832 s->limit = var->limit;
833 s->selector = var->selector;
834 if (var->unusable)
835 s->attrib = 0;
836 else {
837 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
838 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
839 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
840 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
841 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
842 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
843 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
844 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
845 }
846 if (seg == VCPU_SREG_CS)
847 svm->vmcb->save.cpl
848 = (svm->vmcb->save.cs.attrib
849 >> SVM_SELECTOR_DPL_SHIFT) & 3;
850
851 }
852
853 /* FIXME:
854
855 svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
856 svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
857
858 */
859
860 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
861 {
862 return -EOPNOTSUPP;
863 }
864
865 static int svm_get_irq(struct kvm_vcpu *vcpu)
866 {
867 struct vcpu_svm *svm = to_svm(vcpu);
868 u32 exit_int_info = svm->vmcb->control.exit_int_info;
869
870 if (is_external_interrupt(exit_int_info))
871 return exit_int_info & SVM_EVTINJ_VEC_MASK;
872 return -1;
873 }
874
875 static void load_host_msrs(struct kvm_vcpu *vcpu)
876 {
877 #ifdef CONFIG_X86_64
878 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
879 #endif
880 }
881
882 static void save_host_msrs(struct kvm_vcpu *vcpu)
883 {
884 #ifdef CONFIG_X86_64
885 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
886 #endif
887 }
888
889 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
890 {
891 if (svm_data->next_asid > svm_data->max_asid) {
892 ++svm_data->asid_generation;
893 svm_data->next_asid = 1;
894 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
895 }
896
897 svm->vcpu.cpu = svm_data->cpu;
898 svm->asid_generation = svm_data->asid_generation;
899 svm->vmcb->control.asid = svm_data->next_asid++;
900 }
901
902 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
903 {
904 return to_svm(vcpu)->db_regs[dr];
905 }
906
907 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
908 int *exception)
909 {
910 struct vcpu_svm *svm = to_svm(vcpu);
911
912 *exception = 0;
913
914 if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
915 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
916 svm->vmcb->save.dr6 |= DR6_BD_MASK;
917 *exception = DB_VECTOR;
918 return;
919 }
920
921 switch (dr) {
922 case 0 ... 3:
923 svm->db_regs[dr] = value;
924 return;
925 case 4 ... 5:
926 if (vcpu->cr4 & X86_CR4_DE) {
927 *exception = UD_VECTOR;
928 return;
929 }
930 case 7: {
931 if (value & ~((1ULL << 32) - 1)) {
932 *exception = GP_VECTOR;
933 return;
934 }
935 svm->vmcb->save.dr7 = value;
936 return;
937 }
938 default:
939 printk(KERN_DEBUG "%s: unexpected dr %u\n",
940 __FUNCTION__, dr);
941 *exception = UD_VECTOR;
942 return;
943 }
944 }
945
946 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
947 {
948 u32 exit_int_info = svm->vmcb->control.exit_int_info;
949 struct kvm *kvm = svm->vcpu.kvm;
950 u64 fault_address;
951 u32 error_code;
952
953 if (!irqchip_in_kernel(kvm) &&
954 is_external_interrupt(exit_int_info))
955 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
956
957 fault_address = svm->vmcb->control.exit_info_2;
958 error_code = svm->vmcb->control.exit_info_1;
959 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
960 }
961
962 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
963 {
964 int er;
965
966 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0);
967 if (er != EMULATE_DONE)
968 inject_ud(&svm->vcpu);
969
970 return 1;
971 }
972
973 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
974 {
975 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
976 if (!(svm->vcpu.cr0 & X86_CR0_TS))
977 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
978 svm->vcpu.fpu_active = 1;
979
980 return 1;
981 }
982
983 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
984 {
985 /*
986 * VMCB is undefined after a SHUTDOWN intercept
987 * so reinitialize it.
988 */
989 clear_page(svm->vmcb);
990 init_vmcb(svm->vmcb);
991
992 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
993 return 0;
994 }
995
996 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
997 {
998 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
999 int size, down, in, string, rep;
1000 unsigned port;
1001
1002 ++svm->vcpu.stat.io_exits;
1003
1004 svm->next_rip = svm->vmcb->control.exit_info_2;
1005
1006 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1007
1008 if (string) {
1009 if (emulate_instruction(&svm->vcpu,
1010 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1011 return 0;
1012 return 1;
1013 }
1014
1015 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1016 port = io_info >> 16;
1017 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1018 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1019 down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1020
1021 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1022 }
1023
1024 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1025 {
1026 return 1;
1027 }
1028
1029 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1030 {
1031 svm->next_rip = svm->vmcb->save.rip + 1;
1032 skip_emulated_instruction(&svm->vcpu);
1033 return kvm_emulate_halt(&svm->vcpu);
1034 }
1035
1036 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1037 {
1038 svm->next_rip = svm->vmcb->save.rip + 3;
1039 skip_emulated_instruction(&svm->vcpu);
1040 kvm_emulate_hypercall(&svm->vcpu);
1041 return 1;
1042 }
1043
1044 static int invalid_op_interception(struct vcpu_svm *svm,
1045 struct kvm_run *kvm_run)
1046 {
1047 inject_ud(&svm->vcpu);
1048 return 1;
1049 }
1050
1051 static int task_switch_interception(struct vcpu_svm *svm,
1052 struct kvm_run *kvm_run)
1053 {
1054 pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__);
1055 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1056 return 0;
1057 }
1058
1059 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1060 {
1061 svm->next_rip = svm->vmcb->save.rip + 2;
1062 kvm_emulate_cpuid(&svm->vcpu);
1063 return 1;
1064 }
1065
1066 static int emulate_on_interception(struct vcpu_svm *svm,
1067 struct kvm_run *kvm_run)
1068 {
1069 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1070 pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__);
1071 return 1;
1072 }
1073
1074 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1075 {
1076 struct vcpu_svm *svm = to_svm(vcpu);
1077
1078 switch (ecx) {
1079 case MSR_IA32_TIME_STAMP_COUNTER: {
1080 u64 tsc;
1081
1082 rdtscll(tsc);
1083 *data = svm->vmcb->control.tsc_offset + tsc;
1084 break;
1085 }
1086 case MSR_K6_STAR:
1087 *data = svm->vmcb->save.star;
1088 break;
1089 #ifdef CONFIG_X86_64
1090 case MSR_LSTAR:
1091 *data = svm->vmcb->save.lstar;
1092 break;
1093 case MSR_CSTAR:
1094 *data = svm->vmcb->save.cstar;
1095 break;
1096 case MSR_KERNEL_GS_BASE:
1097 *data = svm->vmcb->save.kernel_gs_base;
1098 break;
1099 case MSR_SYSCALL_MASK:
1100 *data = svm->vmcb->save.sfmask;
1101 break;
1102 #endif
1103 case MSR_IA32_SYSENTER_CS:
1104 *data = svm->vmcb->save.sysenter_cs;
1105 break;
1106 case MSR_IA32_SYSENTER_EIP:
1107 *data = svm->vmcb->save.sysenter_eip;
1108 break;
1109 case MSR_IA32_SYSENTER_ESP:
1110 *data = svm->vmcb->save.sysenter_esp;
1111 break;
1112 default:
1113 return kvm_get_msr_common(vcpu, ecx, data);
1114 }
1115 return 0;
1116 }
1117
1118 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1119 {
1120 u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1121 u64 data;
1122
1123 if (svm_get_msr(&svm->vcpu, ecx, &data))
1124 svm_inject_gp(&svm->vcpu, 0);
1125 else {
1126 svm->vmcb->save.rax = data & 0xffffffff;
1127 svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32;
1128 svm->next_rip = svm->vmcb->save.rip + 2;
1129 skip_emulated_instruction(&svm->vcpu);
1130 }
1131 return 1;
1132 }
1133
1134 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1135 {
1136 struct vcpu_svm *svm = to_svm(vcpu);
1137
1138 switch (ecx) {
1139 case MSR_IA32_TIME_STAMP_COUNTER: {
1140 u64 tsc;
1141
1142 rdtscll(tsc);
1143 svm->vmcb->control.tsc_offset = data - tsc;
1144 break;
1145 }
1146 case MSR_K6_STAR:
1147 svm->vmcb->save.star = data;
1148 break;
1149 #ifdef CONFIG_X86_64
1150 case MSR_LSTAR:
1151 svm->vmcb->save.lstar = data;
1152 break;
1153 case MSR_CSTAR:
1154 svm->vmcb->save.cstar = data;
1155 break;
1156 case MSR_KERNEL_GS_BASE:
1157 svm->vmcb->save.kernel_gs_base = data;
1158 break;
1159 case MSR_SYSCALL_MASK:
1160 svm->vmcb->save.sfmask = data;
1161 break;
1162 #endif
1163 case MSR_IA32_SYSENTER_CS:
1164 svm->vmcb->save.sysenter_cs = data;
1165 break;
1166 case MSR_IA32_SYSENTER_EIP:
1167 svm->vmcb->save.sysenter_eip = data;
1168 break;
1169 case MSR_IA32_SYSENTER_ESP:
1170 svm->vmcb->save.sysenter_esp = data;
1171 break;
1172 default:
1173 return kvm_set_msr_common(vcpu, ecx, data);
1174 }
1175 return 0;
1176 }
1177
1178 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1179 {
1180 u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1181 u64 data = (svm->vmcb->save.rax & -1u)
1182 | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32);
1183 svm->next_rip = svm->vmcb->save.rip + 2;
1184 if (svm_set_msr(&svm->vcpu, ecx, data))
1185 svm_inject_gp(&svm->vcpu, 0);
1186 else
1187 skip_emulated_instruction(&svm->vcpu);
1188 return 1;
1189 }
1190
1191 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1192 {
1193 if (svm->vmcb->control.exit_info_1)
1194 return wrmsr_interception(svm, kvm_run);
1195 else
1196 return rdmsr_interception(svm, kvm_run);
1197 }
1198
1199 static int interrupt_window_interception(struct vcpu_svm *svm,
1200 struct kvm_run *kvm_run)
1201 {
1202 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1203 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1204 /*
1205 * If the user space waits to inject interrupts, exit as soon as
1206 * possible
1207 */
1208 if (kvm_run->request_interrupt_window &&
1209 !svm->vcpu.irq_summary) {
1210 ++svm->vcpu.stat.irq_window_exits;
1211 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1212 return 0;
1213 }
1214
1215 return 1;
1216 }
1217
1218 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1219 struct kvm_run *kvm_run) = {
1220 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1221 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1222 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1223 /* for now: */
1224 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1225 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1226 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1227 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1228 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1229 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1230 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1231 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1232 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1233 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1234 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1235 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1236 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1237 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
1238 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1239 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
1240 [SVM_EXIT_INTR] = nop_on_interception,
1241 [SVM_EXIT_NMI] = nop_on_interception,
1242 [SVM_EXIT_SMI] = nop_on_interception,
1243 [SVM_EXIT_INIT] = nop_on_interception,
1244 [SVM_EXIT_VINTR] = interrupt_window_interception,
1245 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1246 [SVM_EXIT_CPUID] = cpuid_interception,
1247 [SVM_EXIT_INVD] = emulate_on_interception,
1248 [SVM_EXIT_HLT] = halt_interception,
1249 [SVM_EXIT_INVLPG] = emulate_on_interception,
1250 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1251 [SVM_EXIT_IOIO] = io_interception,
1252 [SVM_EXIT_MSR] = msr_interception,
1253 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1254 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
1255 [SVM_EXIT_VMRUN] = invalid_op_interception,
1256 [SVM_EXIT_VMMCALL] = vmmcall_interception,
1257 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1258 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1259 [SVM_EXIT_STGI] = invalid_op_interception,
1260 [SVM_EXIT_CLGI] = invalid_op_interception,
1261 [SVM_EXIT_SKINIT] = invalid_op_interception,
1262 [SVM_EXIT_WBINVD] = emulate_on_interception,
1263 [SVM_EXIT_MONITOR] = invalid_op_interception,
1264 [SVM_EXIT_MWAIT] = invalid_op_interception,
1265 };
1266
1267
1268 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1269 {
1270 struct vcpu_svm *svm = to_svm(vcpu);
1271 u32 exit_code = svm->vmcb->control.exit_code;
1272
1273 kvm_reput_irq(svm);
1274
1275 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1276 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1277 kvm_run->fail_entry.hardware_entry_failure_reason
1278 = svm->vmcb->control.exit_code;
1279 return 0;
1280 }
1281
1282 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1283 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1284 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1285 "exit_code 0x%x\n",
1286 __FUNCTION__, svm->vmcb->control.exit_int_info,
1287 exit_code);
1288
1289 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1290 || !svm_exit_handlers[exit_code]) {
1291 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1292 kvm_run->hw.hardware_exit_reason = exit_code;
1293 return 0;
1294 }
1295
1296 return svm_exit_handlers[exit_code](svm, kvm_run);
1297 }
1298
1299 static void reload_tss(struct kvm_vcpu *vcpu)
1300 {
1301 int cpu = raw_smp_processor_id();
1302
1303 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1304 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1305 load_TR_desc();
1306 }
1307
1308 static void pre_svm_run(struct vcpu_svm *svm)
1309 {
1310 int cpu = raw_smp_processor_id();
1311
1312 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1313
1314 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1315 if (svm->vcpu.cpu != cpu ||
1316 svm->asid_generation != svm_data->asid_generation)
1317 new_asid(svm, svm_data);
1318 }
1319
1320
1321 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1322 {
1323 struct vmcb_control_area *control;
1324
1325 control = &svm->vmcb->control;
1326 control->int_vector = irq;
1327 control->int_ctl &= ~V_INTR_PRIO_MASK;
1328 control->int_ctl |= V_IRQ_MASK |
1329 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1330 }
1331
1332 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1333 {
1334 struct vcpu_svm *svm = to_svm(vcpu);
1335
1336 svm_inject_irq(svm, irq);
1337 }
1338
1339 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1340 {
1341 struct vcpu_svm *svm = to_svm(vcpu);
1342 struct vmcb *vmcb = svm->vmcb;
1343 int intr_vector = -1;
1344
1345 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1346 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1347 intr_vector = vmcb->control.exit_int_info &
1348 SVM_EVTINJ_VEC_MASK;
1349 vmcb->control.exit_int_info = 0;
1350 svm_inject_irq(svm, intr_vector);
1351 return;
1352 }
1353
1354 if (vmcb->control.int_ctl & V_IRQ_MASK)
1355 return;
1356
1357 if (!kvm_cpu_has_interrupt(vcpu))
1358 return;
1359
1360 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1361 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1362 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1363 /* unable to deliver irq, set pending irq */
1364 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1365 svm_inject_irq(svm, 0x0);
1366 return;
1367 }
1368 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1369 intr_vector = kvm_cpu_get_interrupt(vcpu);
1370 svm_inject_irq(svm, intr_vector);
1371 kvm_timer_intr_post(vcpu, intr_vector);
1372 }
1373
1374 static void kvm_reput_irq(struct vcpu_svm *svm)
1375 {
1376 struct vmcb_control_area *control = &svm->vmcb->control;
1377
1378 if ((control->int_ctl & V_IRQ_MASK)
1379 && !irqchip_in_kernel(svm->vcpu.kvm)) {
1380 control->int_ctl &= ~V_IRQ_MASK;
1381 push_irq(&svm->vcpu, control->int_vector);
1382 }
1383
1384 svm->vcpu.interrupt_window_open =
1385 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1386 }
1387
1388 static void svm_do_inject_vector(struct vcpu_svm *svm)
1389 {
1390 struct kvm_vcpu *vcpu = &svm->vcpu;
1391 int word_index = __ffs(vcpu->irq_summary);
1392 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1393 int irq = word_index * BITS_PER_LONG + bit_index;
1394
1395 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1396 if (!vcpu->irq_pending[word_index])
1397 clear_bit(word_index, &vcpu->irq_summary);
1398 svm_inject_irq(svm, irq);
1399 }
1400
1401 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1402 struct kvm_run *kvm_run)
1403 {
1404 struct vcpu_svm *svm = to_svm(vcpu);
1405 struct vmcb_control_area *control = &svm->vmcb->control;
1406
1407 svm->vcpu.interrupt_window_open =
1408 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1409 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1410
1411 if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary)
1412 /*
1413 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1414 */
1415 svm_do_inject_vector(svm);
1416
1417 /*
1418 * Interrupts blocked. Wait for unblock.
1419 */
1420 if (!svm->vcpu.interrupt_window_open &&
1421 (svm->vcpu.irq_summary || kvm_run->request_interrupt_window))
1422 control->intercept |= 1ULL << INTERCEPT_VINTR;
1423 else
1424 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1425 }
1426
1427 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1428 {
1429 return 0;
1430 }
1431
1432 static void save_db_regs(unsigned long *db_regs)
1433 {
1434 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1435 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1436 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1437 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1438 }
1439
1440 static void load_db_regs(unsigned long *db_regs)
1441 {
1442 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1443 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1444 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1445 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1446 }
1447
1448 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1449 {
1450 force_new_asid(vcpu);
1451 }
1452
1453 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1454 {
1455 }
1456
1457 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1458 {
1459 struct vcpu_svm *svm = to_svm(vcpu);
1460 u16 fs_selector;
1461 u16 gs_selector;
1462 u16 ldt_selector;
1463
1464 pre_svm_run(svm);
1465
1466 save_host_msrs(vcpu);
1467 fs_selector = read_fs();
1468 gs_selector = read_gs();
1469 ldt_selector = read_ldt();
1470 svm->host_cr2 = kvm_read_cr2();
1471 svm->host_dr6 = read_dr6();
1472 svm->host_dr7 = read_dr7();
1473 svm->vmcb->save.cr2 = vcpu->cr2;
1474
1475 if (svm->vmcb->save.dr7 & 0xff) {
1476 write_dr7(0);
1477 save_db_regs(svm->host_db_regs);
1478 load_db_regs(svm->db_regs);
1479 }
1480
1481 clgi();
1482
1483 local_irq_enable();
1484
1485 asm volatile (
1486 #ifdef CONFIG_X86_64
1487 "push %%rbp; \n\t"
1488 #else
1489 "push %%ebp; \n\t"
1490 #endif
1491
1492 #ifdef CONFIG_X86_64
1493 "mov %c[rbx](%[svm]), %%rbx \n\t"
1494 "mov %c[rcx](%[svm]), %%rcx \n\t"
1495 "mov %c[rdx](%[svm]), %%rdx \n\t"
1496 "mov %c[rsi](%[svm]), %%rsi \n\t"
1497 "mov %c[rdi](%[svm]), %%rdi \n\t"
1498 "mov %c[rbp](%[svm]), %%rbp \n\t"
1499 "mov %c[r8](%[svm]), %%r8 \n\t"
1500 "mov %c[r9](%[svm]), %%r9 \n\t"
1501 "mov %c[r10](%[svm]), %%r10 \n\t"
1502 "mov %c[r11](%[svm]), %%r11 \n\t"
1503 "mov %c[r12](%[svm]), %%r12 \n\t"
1504 "mov %c[r13](%[svm]), %%r13 \n\t"
1505 "mov %c[r14](%[svm]), %%r14 \n\t"
1506 "mov %c[r15](%[svm]), %%r15 \n\t"
1507 #else
1508 "mov %c[rbx](%[svm]), %%ebx \n\t"
1509 "mov %c[rcx](%[svm]), %%ecx \n\t"
1510 "mov %c[rdx](%[svm]), %%edx \n\t"
1511 "mov %c[rsi](%[svm]), %%esi \n\t"
1512 "mov %c[rdi](%[svm]), %%edi \n\t"
1513 "mov %c[rbp](%[svm]), %%ebp \n\t"
1514 #endif
1515
1516 #ifdef CONFIG_X86_64
1517 /* Enter guest mode */
1518 "push %%rax \n\t"
1519 "mov %c[vmcb](%[svm]), %%rax \n\t"
1520 SVM_VMLOAD "\n\t"
1521 SVM_VMRUN "\n\t"
1522 SVM_VMSAVE "\n\t"
1523 "pop %%rax \n\t"
1524 #else
1525 /* Enter guest mode */
1526 "push %%eax \n\t"
1527 "mov %c[vmcb](%[svm]), %%eax \n\t"
1528 SVM_VMLOAD "\n\t"
1529 SVM_VMRUN "\n\t"
1530 SVM_VMSAVE "\n\t"
1531 "pop %%eax \n\t"
1532 #endif
1533
1534 /* Save guest registers, load host registers */
1535 #ifdef CONFIG_X86_64
1536 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1537 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1538 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1539 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1540 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1541 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1542 "mov %%r8, %c[r8](%[svm]) \n\t"
1543 "mov %%r9, %c[r9](%[svm]) \n\t"
1544 "mov %%r10, %c[r10](%[svm]) \n\t"
1545 "mov %%r11, %c[r11](%[svm]) \n\t"
1546 "mov %%r12, %c[r12](%[svm]) \n\t"
1547 "mov %%r13, %c[r13](%[svm]) \n\t"
1548 "mov %%r14, %c[r14](%[svm]) \n\t"
1549 "mov %%r15, %c[r15](%[svm]) \n\t"
1550
1551 "pop %%rbp; \n\t"
1552 #else
1553 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1554 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1555 "mov %%edx, %c[rdx](%[svm]) \n\t"
1556 "mov %%esi, %c[rsi](%[svm]) \n\t"
1557 "mov %%edi, %c[rdi](%[svm]) \n\t"
1558 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1559
1560 "pop %%ebp; \n\t"
1561 #endif
1562 :
1563 : [svm]"a"(svm),
1564 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1565 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RBX])),
1566 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RCX])),
1567 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RDX])),
1568 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RSI])),
1569 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RDI])),
1570 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RBP]))
1571 #ifdef CONFIG_X86_64
1572 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R8])),
1573 [r9]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R9])),
1574 [r10]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R10])),
1575 [r11]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R11])),
1576 [r12]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R12])),
1577 [r13]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R13])),
1578 [r14]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R14])),
1579 [r15]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R15]))
1580 #endif
1581 : "cc", "memory"
1582 #ifdef CONFIG_X86_64
1583 , "rbx", "rcx", "rdx", "rsi", "rdi"
1584 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1585 #else
1586 , "ebx", "ecx", "edx" , "esi", "edi"
1587 #endif
1588 );
1589
1590 if ((svm->vmcb->save.dr7 & 0xff))
1591 load_db_regs(svm->host_db_regs);
1592
1593 vcpu->cr2 = svm->vmcb->save.cr2;
1594
1595 write_dr6(svm->host_dr6);
1596 write_dr7(svm->host_dr7);
1597 kvm_write_cr2(svm->host_cr2);
1598
1599 load_fs(fs_selector);
1600 load_gs(gs_selector);
1601 load_ldt(ldt_selector);
1602 load_host_msrs(vcpu);
1603
1604 reload_tss(vcpu);
1605
1606 local_irq_disable();
1607
1608 stgi();
1609
1610 svm->next_rip = 0;
1611 }
1612
1613 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1614 {
1615 struct vcpu_svm *svm = to_svm(vcpu);
1616
1617 svm->vmcb->save.cr3 = root;
1618 force_new_asid(vcpu);
1619
1620 if (vcpu->fpu_active) {
1621 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1622 svm->vmcb->save.cr0 |= X86_CR0_TS;
1623 vcpu->fpu_active = 0;
1624 }
1625 }
1626
1627 static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1628 unsigned long addr,
1629 uint32_t err_code)
1630 {
1631 struct vcpu_svm *svm = to_svm(vcpu);
1632 uint32_t exit_int_info = svm->vmcb->control.exit_int_info;
1633
1634 ++vcpu->stat.pf_guest;
1635
1636 if (is_page_fault(exit_int_info)) {
1637
1638 svm->vmcb->control.event_inj_err = 0;
1639 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1640 SVM_EVTINJ_VALID_ERR |
1641 SVM_EVTINJ_TYPE_EXEPT |
1642 DF_VECTOR;
1643 return;
1644 }
1645 vcpu->cr2 = addr;
1646 svm->vmcb->save.cr2 = addr;
1647 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1648 SVM_EVTINJ_VALID_ERR |
1649 SVM_EVTINJ_TYPE_EXEPT |
1650 PF_VECTOR;
1651 svm->vmcb->control.event_inj_err = err_code;
1652 }
1653
1654
1655 static int is_disabled(void)
1656 {
1657 u64 vm_cr;
1658
1659 rdmsrl(MSR_VM_CR, vm_cr);
1660 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1661 return 1;
1662
1663 return 0;
1664 }
1665
1666 static void
1667 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1668 {
1669 /*
1670 * Patch in the VMMCALL instruction:
1671 */
1672 hypercall[0] = 0x0f;
1673 hypercall[1] = 0x01;
1674 hypercall[2] = 0xd9;
1675 }
1676
1677 static void svm_check_processor_compat(void *rtn)
1678 {
1679 *(int *)rtn = 0;
1680 }
1681
1682 static struct kvm_x86_ops svm_x86_ops = {
1683 .cpu_has_kvm_support = has_svm,
1684 .disabled_by_bios = is_disabled,
1685 .hardware_setup = svm_hardware_setup,
1686 .hardware_unsetup = svm_hardware_unsetup,
1687 .check_processor_compatibility = svm_check_processor_compat,
1688 .hardware_enable = svm_hardware_enable,
1689 .hardware_disable = svm_hardware_disable,
1690
1691 .vcpu_create = svm_create_vcpu,
1692 .vcpu_free = svm_free_vcpu,
1693 .vcpu_reset = svm_vcpu_reset,
1694
1695 .prepare_guest_switch = svm_prepare_guest_switch,
1696 .vcpu_load = svm_vcpu_load,
1697 .vcpu_put = svm_vcpu_put,
1698 .vcpu_decache = svm_vcpu_decache,
1699
1700 .set_guest_debug = svm_guest_debug,
1701 .get_msr = svm_get_msr,
1702 .set_msr = svm_set_msr,
1703 .get_segment_base = svm_get_segment_base,
1704 .get_segment = svm_get_segment,
1705 .set_segment = svm_set_segment,
1706 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1707 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1708 .set_cr0 = svm_set_cr0,
1709 .set_cr3 = svm_set_cr3,
1710 .set_cr4 = svm_set_cr4,
1711 .set_efer = svm_set_efer,
1712 .get_idt = svm_get_idt,
1713 .set_idt = svm_set_idt,
1714 .get_gdt = svm_get_gdt,
1715 .set_gdt = svm_set_gdt,
1716 .get_dr = svm_get_dr,
1717 .set_dr = svm_set_dr,
1718 .cache_regs = svm_cache_regs,
1719 .decache_regs = svm_decache_regs,
1720 .get_rflags = svm_get_rflags,
1721 .set_rflags = svm_set_rflags,
1722
1723 .tlb_flush = svm_flush_tlb,
1724 .inject_page_fault = svm_inject_page_fault,
1725
1726 .inject_gp = svm_inject_gp,
1727
1728 .run = svm_vcpu_run,
1729 .handle_exit = handle_exit,
1730 .skip_emulated_instruction = skip_emulated_instruction,
1731 .patch_hypercall = svm_patch_hypercall,
1732 .get_irq = svm_get_irq,
1733 .set_irq = svm_set_irq,
1734 .queue_exception = svm_queue_exception,
1735 .exception_injected = svm_exception_injected,
1736 .inject_pending_irq = svm_intr_assist,
1737 .inject_pending_vectors = do_interrupt_requests,
1738
1739 .set_tss_addr = svm_set_tss_addr,
1740 };
1741
1742 static int __init svm_init(void)
1743 {
1744 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1745 THIS_MODULE);
1746 }
1747
1748 static void __exit svm_exit(void)
1749 {
1750 kvm_exit();
1751 }
1752
1753 module_init(svm_init)
1754 module_exit(svm_exit)
Linux kernel - Deliverables
This page took 0.079267 seconds and 6 git commands to generate.