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KVM: Rename kvm_arch_ops to kvm_x86_ops
[deliverable/linux.git] / drivers / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
17 #include "kvm_svm.h"
18 #include "x86_emulate.h"
19 #include "irq.h"
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/vmalloc.h>
24 #include <linux/highmem.h>
25 #include <linux/profile.h>
26 #include <linux/sched.h>
27
28 #include <asm/desc.h>
29
30 MODULE_AUTHOR("Qumranet");
31 MODULE_LICENSE("GPL");
32
33 #define IOPM_ALLOC_ORDER 2
34 #define MSRPM_ALLOC_ORDER 1
35
36 #define DB_VECTOR 1
37 #define UD_VECTOR 6
38 #define GP_VECTOR 13
39
40 #define DR7_GD_MASK (1 << 13)
41 #define DR6_BD_MASK (1 << 13)
42
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
45
46 #define KVM_EFER_LMA (1 << 10)
47 #define KVM_EFER_LME (1 << 8)
48
49 #define SVM_FEATURE_NPT (1 << 0)
50 #define SVM_FEATURE_LBRV (1 << 1)
51 #define SVM_DEATURE_SVML (1 << 2)
52
53 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
54 {
55 return container_of(vcpu, struct vcpu_svm, vcpu);
56 }
57
58 unsigned long iopm_base;
59 unsigned long msrpm_base;
60
61 struct kvm_ldttss_desc {
62 u16 limit0;
63 u16 base0;
64 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
65 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
66 u32 base3;
67 u32 zero1;
68 } __attribute__((packed));
69
70 struct svm_cpu_data {
71 int cpu;
72
73 u64 asid_generation;
74 u32 max_asid;
75 u32 next_asid;
76 struct kvm_ldttss_desc *tss_desc;
77
78 struct page *save_area;
79 };
80
81 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
82 static uint32_t svm_features;
83
84 struct svm_init_data {
85 int cpu;
86 int r;
87 };
88
89 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
90
91 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
92 #define MSRS_RANGE_SIZE 2048
93 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
94
95 #define MAX_INST_SIZE 15
96
97 static inline u32 svm_has(u32 feat)
98 {
99 return svm_features & feat;
100 }
101
102 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
103 {
104 int word_index = __ffs(vcpu->irq_summary);
105 int bit_index = __ffs(vcpu->irq_pending[word_index]);
106 int irq = word_index * BITS_PER_LONG + bit_index;
107
108 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
109 if (!vcpu->irq_pending[word_index])
110 clear_bit(word_index, &vcpu->irq_summary);
111 return irq;
112 }
113
114 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
115 {
116 set_bit(irq, vcpu->irq_pending);
117 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
118 }
119
120 static inline void clgi(void)
121 {
122 asm volatile (SVM_CLGI);
123 }
124
125 static inline void stgi(void)
126 {
127 asm volatile (SVM_STGI);
128 }
129
130 static inline void invlpga(unsigned long addr, u32 asid)
131 {
132 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
133 }
134
135 static inline unsigned long kvm_read_cr2(void)
136 {
137 unsigned long cr2;
138
139 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
140 return cr2;
141 }
142
143 static inline void kvm_write_cr2(unsigned long val)
144 {
145 asm volatile ("mov %0, %%cr2" :: "r" (val));
146 }
147
148 static inline unsigned long read_dr6(void)
149 {
150 unsigned long dr6;
151
152 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
153 return dr6;
154 }
155
156 static inline void write_dr6(unsigned long val)
157 {
158 asm volatile ("mov %0, %%dr6" :: "r" (val));
159 }
160
161 static inline unsigned long read_dr7(void)
162 {
163 unsigned long dr7;
164
165 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
166 return dr7;
167 }
168
169 static inline void write_dr7(unsigned long val)
170 {
171 asm volatile ("mov %0, %%dr7" :: "r" (val));
172 }
173
174 static inline void force_new_asid(struct kvm_vcpu *vcpu)
175 {
176 to_svm(vcpu)->asid_generation--;
177 }
178
179 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
180 {
181 force_new_asid(vcpu);
182 }
183
184 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
185 {
186 if (!(efer & KVM_EFER_LMA))
187 efer &= ~KVM_EFER_LME;
188
189 to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
190 vcpu->shadow_efer = efer;
191 }
192
193 static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
194 {
195 struct vcpu_svm *svm = to_svm(vcpu);
196
197 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
198 SVM_EVTINJ_VALID_ERR |
199 SVM_EVTINJ_TYPE_EXEPT |
200 GP_VECTOR;
201 svm->vmcb->control.event_inj_err = error_code;
202 }
203
204 static void inject_ud(struct kvm_vcpu *vcpu)
205 {
206 to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID |
207 SVM_EVTINJ_TYPE_EXEPT |
208 UD_VECTOR;
209 }
210
211 static int is_page_fault(uint32_t info)
212 {
213 info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
214 return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
215 }
216
217 static int is_external_interrupt(u32 info)
218 {
219 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
220 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
221 }
222
223 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
224 {
225 struct vcpu_svm *svm = to_svm(vcpu);
226
227 if (!svm->next_rip) {
228 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
229 return;
230 }
231 if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) {
232 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
233 __FUNCTION__,
234 svm->vmcb->save.rip,
235 svm->next_rip);
236 }
237
238 vcpu->rip = svm->vmcb->save.rip = svm->next_rip;
239 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
240
241 vcpu->interrupt_window_open = 1;
242 }
243
244 static int has_svm(void)
245 {
246 uint32_t eax, ebx, ecx, edx;
247
248 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
249 printk(KERN_INFO "has_svm: not amd\n");
250 return 0;
251 }
252
253 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
254 if (eax < SVM_CPUID_FUNC) {
255 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
256 return 0;
257 }
258
259 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
260 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
261 printk(KERN_DEBUG "has_svm: svm not available\n");
262 return 0;
263 }
264 return 1;
265 }
266
267 static void svm_hardware_disable(void *garbage)
268 {
269 struct svm_cpu_data *svm_data
270 = per_cpu(svm_data, raw_smp_processor_id());
271
272 if (svm_data) {
273 uint64_t efer;
274
275 wrmsrl(MSR_VM_HSAVE_PA, 0);
276 rdmsrl(MSR_EFER, efer);
277 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
278 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
279 __free_page(svm_data->save_area);
280 kfree(svm_data);
281 }
282 }
283
284 static void svm_hardware_enable(void *garbage)
285 {
286
287 struct svm_cpu_data *svm_data;
288 uint64_t efer;
289 #ifdef CONFIG_X86_64
290 struct desc_ptr gdt_descr;
291 #else
292 struct Xgt_desc_struct gdt_descr;
293 #endif
294 struct desc_struct *gdt;
295 int me = raw_smp_processor_id();
296
297 if (!has_svm()) {
298 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
299 return;
300 }
301 svm_data = per_cpu(svm_data, me);
302
303 if (!svm_data) {
304 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
305 me);
306 return;
307 }
308
309 svm_data->asid_generation = 1;
310 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
311 svm_data->next_asid = svm_data->max_asid + 1;
312 svm_features = cpuid_edx(SVM_CPUID_FUNC);
313
314 asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
315 gdt = (struct desc_struct *)gdt_descr.address;
316 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
317
318 rdmsrl(MSR_EFER, efer);
319 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
320
321 wrmsrl(MSR_VM_HSAVE_PA,
322 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
323 }
324
325 static int svm_cpu_init(int cpu)
326 {
327 struct svm_cpu_data *svm_data;
328 int r;
329
330 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
331 if (!svm_data)
332 return -ENOMEM;
333 svm_data->cpu = cpu;
334 svm_data->save_area = alloc_page(GFP_KERNEL);
335 r = -ENOMEM;
336 if (!svm_data->save_area)
337 goto err_1;
338
339 per_cpu(svm_data, cpu) = svm_data;
340
341 return 0;
342
343 err_1:
344 kfree(svm_data);
345 return r;
346
347 }
348
349 static void set_msr_interception(u32 *msrpm, unsigned msr,
350 int read, int write)
351 {
352 int i;
353
354 for (i = 0; i < NUM_MSR_MAPS; i++) {
355 if (msr >= msrpm_ranges[i] &&
356 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
357 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
358 msrpm_ranges[i]) * 2;
359
360 u32 *base = msrpm + (msr_offset / 32);
361 u32 msr_shift = msr_offset % 32;
362 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
363 *base = (*base & ~(0x3 << msr_shift)) |
364 (mask << msr_shift);
365 return;
366 }
367 }
368 BUG();
369 }
370
371 static __init int svm_hardware_setup(void)
372 {
373 int cpu;
374 struct page *iopm_pages;
375 struct page *msrpm_pages;
376 void *iopm_va, *msrpm_va;
377 int r;
378
379 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
380
381 if (!iopm_pages)
382 return -ENOMEM;
383
384 iopm_va = page_address(iopm_pages);
385 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
386 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
387 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
388
389
390 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
391
392 r = -ENOMEM;
393 if (!msrpm_pages)
394 goto err_1;
395
396 msrpm_va = page_address(msrpm_pages);
397 memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
398 msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
399
400 #ifdef CONFIG_X86_64
401 set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
402 set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
403 set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
404 set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
405 set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
406 set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
407 #endif
408 set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
409 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
410 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
411 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
412
413 for_each_online_cpu(cpu) {
414 r = svm_cpu_init(cpu);
415 if (r)
416 goto err_2;
417 }
418 return 0;
419
420 err_2:
421 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
422 msrpm_base = 0;
423 err_1:
424 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
425 iopm_base = 0;
426 return r;
427 }
428
429 static __exit void svm_hardware_unsetup(void)
430 {
431 __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
432 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
433 iopm_base = msrpm_base = 0;
434 }
435
436 static void init_seg(struct vmcb_seg *seg)
437 {
438 seg->selector = 0;
439 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
440 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
441 seg->limit = 0xffff;
442 seg->base = 0;
443 }
444
445 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
446 {
447 seg->selector = 0;
448 seg->attrib = SVM_SELECTOR_P_MASK | type;
449 seg->limit = 0xffff;
450 seg->base = 0;
451 }
452
453 static void init_vmcb(struct vmcb *vmcb)
454 {
455 struct vmcb_control_area *control = &vmcb->control;
456 struct vmcb_save_area *save = &vmcb->save;
457
458 control->intercept_cr_read = INTERCEPT_CR0_MASK |
459 INTERCEPT_CR3_MASK |
460 INTERCEPT_CR4_MASK;
461
462 control->intercept_cr_write = INTERCEPT_CR0_MASK |
463 INTERCEPT_CR3_MASK |
464 INTERCEPT_CR4_MASK;
465
466 control->intercept_dr_read = INTERCEPT_DR0_MASK |
467 INTERCEPT_DR1_MASK |
468 INTERCEPT_DR2_MASK |
469 INTERCEPT_DR3_MASK;
470
471 control->intercept_dr_write = INTERCEPT_DR0_MASK |
472 INTERCEPT_DR1_MASK |
473 INTERCEPT_DR2_MASK |
474 INTERCEPT_DR3_MASK |
475 INTERCEPT_DR5_MASK |
476 INTERCEPT_DR7_MASK;
477
478 control->intercept_exceptions = 1 << PF_VECTOR;
479
480
481 control->intercept = (1ULL << INTERCEPT_INTR) |
482 (1ULL << INTERCEPT_NMI) |
483 (1ULL << INTERCEPT_SMI) |
484 /*
485 * selective cr0 intercept bug?
486 * 0: 0f 22 d8 mov %eax,%cr3
487 * 3: 0f 20 c0 mov %cr0,%eax
488 * 6: 0d 00 00 00 80 or $0x80000000,%eax
489 * b: 0f 22 c0 mov %eax,%cr0
490 * set cr3 ->interception
491 * get cr0 ->interception
492 * set cr0 -> no interception
493 */
494 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
495 (1ULL << INTERCEPT_CPUID) |
496 (1ULL << INTERCEPT_HLT) |
497 (1ULL << INTERCEPT_INVLPGA) |
498 (1ULL << INTERCEPT_IOIO_PROT) |
499 (1ULL << INTERCEPT_MSR_PROT) |
500 (1ULL << INTERCEPT_TASK_SWITCH) |
501 (1ULL << INTERCEPT_SHUTDOWN) |
502 (1ULL << INTERCEPT_VMRUN) |
503 (1ULL << INTERCEPT_VMMCALL) |
504 (1ULL << INTERCEPT_VMLOAD) |
505 (1ULL << INTERCEPT_VMSAVE) |
506 (1ULL << INTERCEPT_STGI) |
507 (1ULL << INTERCEPT_CLGI) |
508 (1ULL << INTERCEPT_SKINIT) |
509 (1ULL << INTERCEPT_MONITOR) |
510 (1ULL << INTERCEPT_MWAIT);
511
512 control->iopm_base_pa = iopm_base;
513 control->msrpm_base_pa = msrpm_base;
514 control->tsc_offset = 0;
515 control->int_ctl = V_INTR_MASKING_MASK;
516
517 init_seg(&save->es);
518 init_seg(&save->ss);
519 init_seg(&save->ds);
520 init_seg(&save->fs);
521 init_seg(&save->gs);
522
523 save->cs.selector = 0xf000;
524 /* Executable/Readable Code Segment */
525 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
526 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
527 save->cs.limit = 0xffff;
528 /*
529 * cs.base should really be 0xffff0000, but vmx can't handle that, so
530 * be consistent with it.
531 *
532 * Replace when we have real mode working for vmx.
533 */
534 save->cs.base = 0xf0000;
535
536 save->gdtr.limit = 0xffff;
537 save->idtr.limit = 0xffff;
538
539 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
540 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
541
542 save->efer = MSR_EFER_SVME_MASK;
543
544 save->dr6 = 0xffff0ff0;
545 save->dr7 = 0x400;
546 save->rflags = 2;
547 save->rip = 0x0000fff0;
548
549 /*
550 * cr0 val on cpu init should be 0x60000010, we enable cpu
551 * cache by default. the orderly way is to enable cache in bios.
552 */
553 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
554 save->cr4 = X86_CR4_PAE;
555 /* rdx = ?? */
556 }
557
558 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
559 {
560 struct vcpu_svm *svm;
561 struct page *page;
562 int err;
563
564 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
565 if (!svm) {
566 err = -ENOMEM;
567 goto out;
568 }
569
570 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
571 if (err)
572 goto free_svm;
573
574 if (irqchip_in_kernel(kvm)) {
575 err = kvm_create_lapic(&svm->vcpu);
576 if (err < 0)
577 goto free_svm;
578 }
579
580 page = alloc_page(GFP_KERNEL);
581 if (!page) {
582 err = -ENOMEM;
583 goto uninit;
584 }
585
586 svm->vmcb = page_address(page);
587 clear_page(svm->vmcb);
588 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
589 svm->asid_generation = 0;
590 memset(svm->db_regs, 0, sizeof(svm->db_regs));
591 init_vmcb(svm->vmcb);
592
593 fx_init(&svm->vcpu);
594 svm->vcpu.fpu_active = 1;
595 svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
596 if (svm->vcpu.vcpu_id == 0)
597 svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP;
598
599 return &svm->vcpu;
600
601 uninit:
602 kvm_vcpu_uninit(&svm->vcpu);
603 free_svm:
604 kmem_cache_free(kvm_vcpu_cache, svm);
605 out:
606 return ERR_PTR(err);
607 }
608
609 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
610 {
611 struct vcpu_svm *svm = to_svm(vcpu);
612
613 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
614 kvm_vcpu_uninit(vcpu);
615 kmem_cache_free(kvm_vcpu_cache, svm);
616 }
617
618 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
619 {
620 struct vcpu_svm *svm = to_svm(vcpu);
621 int i;
622
623 if (unlikely(cpu != vcpu->cpu)) {
624 u64 tsc_this, delta;
625
626 /*
627 * Make sure that the guest sees a monotonically
628 * increasing TSC.
629 */
630 rdtscll(tsc_this);
631 delta = vcpu->host_tsc - tsc_this;
632 svm->vmcb->control.tsc_offset += delta;
633 vcpu->cpu = cpu;
634 kvm_migrate_apic_timer(vcpu);
635 }
636
637 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
638 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
639 }
640
641 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
642 {
643 struct vcpu_svm *svm = to_svm(vcpu);
644 int i;
645
646 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
647 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
648
649 rdtscll(vcpu->host_tsc);
650 }
651
652 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
653 {
654 }
655
656 static void svm_cache_regs(struct kvm_vcpu *vcpu)
657 {
658 struct vcpu_svm *svm = to_svm(vcpu);
659
660 vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
661 vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
662 vcpu->rip = svm->vmcb->save.rip;
663 }
664
665 static void svm_decache_regs(struct kvm_vcpu *vcpu)
666 {
667 struct vcpu_svm *svm = to_svm(vcpu);
668 svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
669 svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
670 svm->vmcb->save.rip = vcpu->rip;
671 }
672
673 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
674 {
675 return to_svm(vcpu)->vmcb->save.rflags;
676 }
677
678 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
679 {
680 to_svm(vcpu)->vmcb->save.rflags = rflags;
681 }
682
683 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
684 {
685 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
686
687 switch (seg) {
688 case VCPU_SREG_CS: return &save->cs;
689 case VCPU_SREG_DS: return &save->ds;
690 case VCPU_SREG_ES: return &save->es;
691 case VCPU_SREG_FS: return &save->fs;
692 case VCPU_SREG_GS: return &save->gs;
693 case VCPU_SREG_SS: return &save->ss;
694 case VCPU_SREG_TR: return &save->tr;
695 case VCPU_SREG_LDTR: return &save->ldtr;
696 }
697 BUG();
698 return NULL;
699 }
700
701 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
702 {
703 struct vmcb_seg *s = svm_seg(vcpu, seg);
704
705 return s->base;
706 }
707
708 static void svm_get_segment(struct kvm_vcpu *vcpu,
709 struct kvm_segment *var, int seg)
710 {
711 struct vmcb_seg *s = svm_seg(vcpu, seg);
712
713 var->base = s->base;
714 var->limit = s->limit;
715 var->selector = s->selector;
716 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
717 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
718 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
719 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
720 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
721 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
722 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
723 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
724 var->unusable = !var->present;
725 }
726
727 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
728 {
729 struct vcpu_svm *svm = to_svm(vcpu);
730
731 dt->limit = svm->vmcb->save.idtr.limit;
732 dt->base = svm->vmcb->save.idtr.base;
733 }
734
735 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
736 {
737 struct vcpu_svm *svm = to_svm(vcpu);
738
739 svm->vmcb->save.idtr.limit = dt->limit;
740 svm->vmcb->save.idtr.base = dt->base ;
741 }
742
743 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
744 {
745 struct vcpu_svm *svm = to_svm(vcpu);
746
747 dt->limit = svm->vmcb->save.gdtr.limit;
748 dt->base = svm->vmcb->save.gdtr.base;
749 }
750
751 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
752 {
753 struct vcpu_svm *svm = to_svm(vcpu);
754
755 svm->vmcb->save.gdtr.limit = dt->limit;
756 svm->vmcb->save.gdtr.base = dt->base ;
757 }
758
759 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
760 {
761 }
762
763 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
764 {
765 struct vcpu_svm *svm = to_svm(vcpu);
766
767 #ifdef CONFIG_X86_64
768 if (vcpu->shadow_efer & KVM_EFER_LME) {
769 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
770 vcpu->shadow_efer |= KVM_EFER_LMA;
771 svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
772 }
773
774 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG) ) {
775 vcpu->shadow_efer &= ~KVM_EFER_LMA;
776 svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
777 }
778 }
779 #endif
780 if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
781 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
782 vcpu->fpu_active = 1;
783 }
784
785 vcpu->cr0 = cr0;
786 cr0 |= X86_CR0_PG | X86_CR0_WP;
787 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
788 svm->vmcb->save.cr0 = cr0;
789 }
790
791 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
792 {
793 vcpu->cr4 = cr4;
794 to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
795 }
796
797 static void svm_set_segment(struct kvm_vcpu *vcpu,
798 struct kvm_segment *var, int seg)
799 {
800 struct vcpu_svm *svm = to_svm(vcpu);
801 struct vmcb_seg *s = svm_seg(vcpu, seg);
802
803 s->base = var->base;
804 s->limit = var->limit;
805 s->selector = var->selector;
806 if (var->unusable)
807 s->attrib = 0;
808 else {
809 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
810 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
811 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
812 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
813 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
814 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
815 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
816 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
817 }
818 if (seg == VCPU_SREG_CS)
819 svm->vmcb->save.cpl
820 = (svm->vmcb->save.cs.attrib
821 >> SVM_SELECTOR_DPL_SHIFT) & 3;
822
823 }
824
825 /* FIXME:
826
827 svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
828 svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
829
830 */
831
832 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
833 {
834 return -EOPNOTSUPP;
835 }
836
837 static int svm_get_irq(struct kvm_vcpu *vcpu)
838 {
839 struct vcpu_svm *svm = to_svm(vcpu);
840 u32 exit_int_info = svm->vmcb->control.exit_int_info;
841
842 if (is_external_interrupt(exit_int_info))
843 return exit_int_info & SVM_EVTINJ_VEC_MASK;
844 return -1;
845 }
846
847 static void load_host_msrs(struct kvm_vcpu *vcpu)
848 {
849 #ifdef CONFIG_X86_64
850 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
851 #endif
852 }
853
854 static void save_host_msrs(struct kvm_vcpu *vcpu)
855 {
856 #ifdef CONFIG_X86_64
857 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
858 #endif
859 }
860
861 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
862 {
863 if (svm_data->next_asid > svm_data->max_asid) {
864 ++svm_data->asid_generation;
865 svm_data->next_asid = 1;
866 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
867 }
868
869 svm->vcpu.cpu = svm_data->cpu;
870 svm->asid_generation = svm_data->asid_generation;
871 svm->vmcb->control.asid = svm_data->next_asid++;
872 }
873
874 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
875 {
876 return to_svm(vcpu)->db_regs[dr];
877 }
878
879 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
880 int *exception)
881 {
882 struct vcpu_svm *svm = to_svm(vcpu);
883
884 *exception = 0;
885
886 if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
887 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
888 svm->vmcb->save.dr6 |= DR6_BD_MASK;
889 *exception = DB_VECTOR;
890 return;
891 }
892
893 switch (dr) {
894 case 0 ... 3:
895 svm->db_regs[dr] = value;
896 return;
897 case 4 ... 5:
898 if (vcpu->cr4 & X86_CR4_DE) {
899 *exception = UD_VECTOR;
900 return;
901 }
902 case 7: {
903 if (value & ~((1ULL << 32) - 1)) {
904 *exception = GP_VECTOR;
905 return;
906 }
907 svm->vmcb->save.dr7 = value;
908 return;
909 }
910 default:
911 printk(KERN_DEBUG "%s: unexpected dr %u\n",
912 __FUNCTION__, dr);
913 *exception = UD_VECTOR;
914 return;
915 }
916 }
917
918 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
919 {
920 u32 exit_int_info = svm->vmcb->control.exit_int_info;
921 struct kvm *kvm = svm->vcpu.kvm;
922 u64 fault_address;
923 u32 error_code;
924 enum emulation_result er;
925 int r;
926
927 if (!irqchip_in_kernel(kvm) &&
928 is_external_interrupt(exit_int_info))
929 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
930
931 mutex_lock(&kvm->lock);
932
933 fault_address = svm->vmcb->control.exit_info_2;
934 error_code = svm->vmcb->control.exit_info_1;
935 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
936 if (r < 0) {
937 mutex_unlock(&kvm->lock);
938 return r;
939 }
940 if (!r) {
941 mutex_unlock(&kvm->lock);
942 return 1;
943 }
944 er = emulate_instruction(&svm->vcpu, kvm_run, fault_address,
945 error_code);
946 mutex_unlock(&kvm->lock);
947
948 switch (er) {
949 case EMULATE_DONE:
950 return 1;
951 case EMULATE_DO_MMIO:
952 ++svm->vcpu.stat.mmio_exits;
953 return 0;
954 case EMULATE_FAIL:
955 vcpu_printf(&svm->vcpu, "%s: emulate fail\n", __FUNCTION__);
956 break;
957 default:
958 BUG();
959 }
960
961 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
962 return 0;
963 }
964
965 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
966 {
967 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
968 if (!(svm->vcpu.cr0 & X86_CR0_TS))
969 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
970 svm->vcpu.fpu_active = 1;
971
972 return 1;
973 }
974
975 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
976 {
977 /*
978 * VMCB is undefined after a SHUTDOWN intercept
979 * so reinitialize it.
980 */
981 clear_page(svm->vmcb);
982 init_vmcb(svm->vmcb);
983
984 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
985 return 0;
986 }
987
988 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
989 {
990 u32 io_info = svm->vmcb->control.exit_info_1; //address size bug?
991 int size, down, in, string, rep;
992 unsigned port;
993
994 ++svm->vcpu.stat.io_exits;
995
996 svm->next_rip = svm->vmcb->control.exit_info_2;
997
998 string = (io_info & SVM_IOIO_STR_MASK) != 0;
999
1000 if (string) {
1001 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0) == EMULATE_DO_MMIO)
1002 return 0;
1003 return 1;
1004 }
1005
1006 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1007 port = io_info >> 16;
1008 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1009 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1010 down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1011
1012 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1013 }
1014
1015 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1016 {
1017 return 1;
1018 }
1019
1020 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1021 {
1022 svm->next_rip = svm->vmcb->save.rip + 1;
1023 skip_emulated_instruction(&svm->vcpu);
1024 return kvm_emulate_halt(&svm->vcpu);
1025 }
1026
1027 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1028 {
1029 svm->next_rip = svm->vmcb->save.rip + 3;
1030 skip_emulated_instruction(&svm->vcpu);
1031 return kvm_hypercall(&svm->vcpu, kvm_run);
1032 }
1033
1034 static int invalid_op_interception(struct vcpu_svm *svm,
1035 struct kvm_run *kvm_run)
1036 {
1037 inject_ud(&svm->vcpu);
1038 return 1;
1039 }
1040
1041 static int task_switch_interception(struct vcpu_svm *svm,
1042 struct kvm_run *kvm_run)
1043 {
1044 pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__);
1045 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1046 return 0;
1047 }
1048
1049 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1050 {
1051 svm->next_rip = svm->vmcb->save.rip + 2;
1052 kvm_emulate_cpuid(&svm->vcpu);
1053 return 1;
1054 }
1055
1056 static int emulate_on_interception(struct vcpu_svm *svm,
1057 struct kvm_run *kvm_run)
1058 {
1059 if (emulate_instruction(&svm->vcpu, NULL, 0, 0) != EMULATE_DONE)
1060 pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__);
1061 return 1;
1062 }
1063
1064 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1065 {
1066 struct vcpu_svm *svm = to_svm(vcpu);
1067
1068 switch (ecx) {
1069 case MSR_IA32_TIME_STAMP_COUNTER: {
1070 u64 tsc;
1071
1072 rdtscll(tsc);
1073 *data = svm->vmcb->control.tsc_offset + tsc;
1074 break;
1075 }
1076 case MSR_K6_STAR:
1077 *data = svm->vmcb->save.star;
1078 break;
1079 #ifdef CONFIG_X86_64
1080 case MSR_LSTAR:
1081 *data = svm->vmcb->save.lstar;
1082 break;
1083 case MSR_CSTAR:
1084 *data = svm->vmcb->save.cstar;
1085 break;
1086 case MSR_KERNEL_GS_BASE:
1087 *data = svm->vmcb->save.kernel_gs_base;
1088 break;
1089 case MSR_SYSCALL_MASK:
1090 *data = svm->vmcb->save.sfmask;
1091 break;
1092 #endif
1093 case MSR_IA32_SYSENTER_CS:
1094 *data = svm->vmcb->save.sysenter_cs;
1095 break;
1096 case MSR_IA32_SYSENTER_EIP:
1097 *data = svm->vmcb->save.sysenter_eip;
1098 break;
1099 case MSR_IA32_SYSENTER_ESP:
1100 *data = svm->vmcb->save.sysenter_esp;
1101 break;
1102 default:
1103 return kvm_get_msr_common(vcpu, ecx, data);
1104 }
1105 return 0;
1106 }
1107
1108 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1109 {
1110 u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1111 u64 data;
1112
1113 if (svm_get_msr(&svm->vcpu, ecx, &data))
1114 svm_inject_gp(&svm->vcpu, 0);
1115 else {
1116 svm->vmcb->save.rax = data & 0xffffffff;
1117 svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32;
1118 svm->next_rip = svm->vmcb->save.rip + 2;
1119 skip_emulated_instruction(&svm->vcpu);
1120 }
1121 return 1;
1122 }
1123
1124 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1125 {
1126 struct vcpu_svm *svm = to_svm(vcpu);
1127
1128 switch (ecx) {
1129 case MSR_IA32_TIME_STAMP_COUNTER: {
1130 u64 tsc;
1131
1132 rdtscll(tsc);
1133 svm->vmcb->control.tsc_offset = data - tsc;
1134 break;
1135 }
1136 case MSR_K6_STAR:
1137 svm->vmcb->save.star = data;
1138 break;
1139 #ifdef CONFIG_X86_64
1140 case MSR_LSTAR:
1141 svm->vmcb->save.lstar = data;
1142 break;
1143 case MSR_CSTAR:
1144 svm->vmcb->save.cstar = data;
1145 break;
1146 case MSR_KERNEL_GS_BASE:
1147 svm->vmcb->save.kernel_gs_base = data;
1148 break;
1149 case MSR_SYSCALL_MASK:
1150 svm->vmcb->save.sfmask = data;
1151 break;
1152 #endif
1153 case MSR_IA32_SYSENTER_CS:
1154 svm->vmcb->save.sysenter_cs = data;
1155 break;
1156 case MSR_IA32_SYSENTER_EIP:
1157 svm->vmcb->save.sysenter_eip = data;
1158 break;
1159 case MSR_IA32_SYSENTER_ESP:
1160 svm->vmcb->save.sysenter_esp = data;
1161 break;
1162 default:
1163 return kvm_set_msr_common(vcpu, ecx, data);
1164 }
1165 return 0;
1166 }
1167
1168 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1169 {
1170 u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1171 u64 data = (svm->vmcb->save.rax & -1u)
1172 | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32);
1173 svm->next_rip = svm->vmcb->save.rip + 2;
1174 if (svm_set_msr(&svm->vcpu, ecx, data))
1175 svm_inject_gp(&svm->vcpu, 0);
1176 else
1177 skip_emulated_instruction(&svm->vcpu);
1178 return 1;
1179 }
1180
1181 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1182 {
1183 if (svm->vmcb->control.exit_info_1)
1184 return wrmsr_interception(svm, kvm_run);
1185 else
1186 return rdmsr_interception(svm, kvm_run);
1187 }
1188
1189 static int interrupt_window_interception(struct vcpu_svm *svm,
1190 struct kvm_run *kvm_run)
1191 {
1192 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1193 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1194 /*
1195 * If the user space waits to inject interrupts, exit as soon as
1196 * possible
1197 */
1198 if (kvm_run->request_interrupt_window &&
1199 !svm->vcpu.irq_summary) {
1200 ++svm->vcpu.stat.irq_window_exits;
1201 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1202 return 0;
1203 }
1204
1205 return 1;
1206 }
1207
1208 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1209 struct kvm_run *kvm_run) = {
1210 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1211 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1212 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1213 /* for now: */
1214 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1215 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1216 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1217 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1218 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1219 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1220 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1221 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1222 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1223 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1224 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1225 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1226 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1227 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1228 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
1229 [SVM_EXIT_INTR] = nop_on_interception,
1230 [SVM_EXIT_NMI] = nop_on_interception,
1231 [SVM_EXIT_SMI] = nop_on_interception,
1232 [SVM_EXIT_INIT] = nop_on_interception,
1233 [SVM_EXIT_VINTR] = interrupt_window_interception,
1234 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1235 [SVM_EXIT_CPUID] = cpuid_interception,
1236 [SVM_EXIT_HLT] = halt_interception,
1237 [SVM_EXIT_INVLPG] = emulate_on_interception,
1238 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1239 [SVM_EXIT_IOIO] = io_interception,
1240 [SVM_EXIT_MSR] = msr_interception,
1241 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1242 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
1243 [SVM_EXIT_VMRUN] = invalid_op_interception,
1244 [SVM_EXIT_VMMCALL] = vmmcall_interception,
1245 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1246 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1247 [SVM_EXIT_STGI] = invalid_op_interception,
1248 [SVM_EXIT_CLGI] = invalid_op_interception,
1249 [SVM_EXIT_SKINIT] = invalid_op_interception,
1250 [SVM_EXIT_MONITOR] = invalid_op_interception,
1251 [SVM_EXIT_MWAIT] = invalid_op_interception,
1252 };
1253
1254
1255 static int handle_exit(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1256 {
1257 u32 exit_code = svm->vmcb->control.exit_code;
1258
1259 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1260 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1261 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1262 "exit_code 0x%x\n",
1263 __FUNCTION__, svm->vmcb->control.exit_int_info,
1264 exit_code);
1265
1266 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1267 || svm_exit_handlers[exit_code] == 0) {
1268 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1269 kvm_run->hw.hardware_exit_reason = exit_code;
1270 return 0;
1271 }
1272
1273 return svm_exit_handlers[exit_code](svm, kvm_run);
1274 }
1275
1276 static void reload_tss(struct kvm_vcpu *vcpu)
1277 {
1278 int cpu = raw_smp_processor_id();
1279
1280 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1281 svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1282 load_TR_desc();
1283 }
1284
1285 static void pre_svm_run(struct vcpu_svm *svm)
1286 {
1287 int cpu = raw_smp_processor_id();
1288
1289 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1290
1291 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1292 if (svm->vcpu.cpu != cpu ||
1293 svm->asid_generation != svm_data->asid_generation)
1294 new_asid(svm, svm_data);
1295 }
1296
1297
1298 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1299 {
1300 struct vmcb_control_area *control;
1301
1302 control = &svm->vmcb->control;
1303 control->int_vector = irq;
1304 control->int_ctl &= ~V_INTR_PRIO_MASK;
1305 control->int_ctl |= V_IRQ_MASK |
1306 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1307 }
1308
1309 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1310 {
1311 struct vcpu_svm *svm = to_svm(vcpu);
1312
1313 svm_inject_irq(svm, irq);
1314 }
1315
1316 static void svm_intr_assist(struct vcpu_svm *svm)
1317 {
1318 struct vmcb *vmcb = svm->vmcb;
1319 int intr_vector = -1;
1320 struct kvm_vcpu *vcpu = &svm->vcpu;
1321
1322 kvm_inject_pending_timer_irqs(vcpu);
1323 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1324 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1325 intr_vector = vmcb->control.exit_int_info &
1326 SVM_EVTINJ_VEC_MASK;
1327 vmcb->control.exit_int_info = 0;
1328 svm_inject_irq(svm, intr_vector);
1329 return;
1330 }
1331
1332 if (vmcb->control.int_ctl & V_IRQ_MASK)
1333 return;
1334
1335 if (!kvm_cpu_has_interrupt(vcpu))
1336 return;
1337
1338 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1339 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1340 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1341 /* unable to deliver irq, set pending irq */
1342 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1343 svm_inject_irq(svm, 0x0);
1344 return;
1345 }
1346 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1347 intr_vector = kvm_cpu_get_interrupt(vcpu);
1348 svm_inject_irq(svm, intr_vector);
1349 kvm_timer_intr_post(vcpu, intr_vector);
1350 }
1351
1352 static void kvm_reput_irq(struct vcpu_svm *svm)
1353 {
1354 struct vmcb_control_area *control = &svm->vmcb->control;
1355
1356 if ((control->int_ctl & V_IRQ_MASK)
1357 && !irqchip_in_kernel(svm->vcpu.kvm)) {
1358 control->int_ctl &= ~V_IRQ_MASK;
1359 push_irq(&svm->vcpu, control->int_vector);
1360 }
1361
1362 svm->vcpu.interrupt_window_open =
1363 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1364 }
1365
1366 static void svm_do_inject_vector(struct vcpu_svm *svm)
1367 {
1368 struct kvm_vcpu *vcpu = &svm->vcpu;
1369 int word_index = __ffs(vcpu->irq_summary);
1370 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1371 int irq = word_index * BITS_PER_LONG + bit_index;
1372
1373 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1374 if (!vcpu->irq_pending[word_index])
1375 clear_bit(word_index, &vcpu->irq_summary);
1376 svm_inject_irq(svm, irq);
1377 }
1378
1379 static void do_interrupt_requests(struct vcpu_svm *svm,
1380 struct kvm_run *kvm_run)
1381 {
1382 struct vmcb_control_area *control = &svm->vmcb->control;
1383
1384 svm->vcpu.interrupt_window_open =
1385 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1386 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1387
1388 if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary)
1389 /*
1390 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1391 */
1392 svm_do_inject_vector(svm);
1393
1394 /*
1395 * Interrupts blocked. Wait for unblock.
1396 */
1397 if (!svm->vcpu.interrupt_window_open &&
1398 (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) {
1399 control->intercept |= 1ULL << INTERCEPT_VINTR;
1400 } else
1401 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1402 }
1403
1404 static void post_kvm_run_save(struct vcpu_svm *svm,
1405 struct kvm_run *kvm_run)
1406 {
1407 if (irqchip_in_kernel(svm->vcpu.kvm))
1408 kvm_run->ready_for_interrupt_injection = 1;
1409 else
1410 kvm_run->ready_for_interrupt_injection =
1411 (svm->vcpu.interrupt_window_open &&
1412 svm->vcpu.irq_summary == 0);
1413 kvm_run->if_flag = (svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0;
1414 kvm_run->cr8 = get_cr8(&svm->vcpu);
1415 kvm_run->apic_base = kvm_get_apic_base(&svm->vcpu);
1416 }
1417
1418 /*
1419 * Check if userspace requested an interrupt window, and that the
1420 * interrupt window is open.
1421 *
1422 * No need to exit to userspace if we already have an interrupt queued.
1423 */
1424 static int dm_request_for_irq_injection(struct vcpu_svm *svm,
1425 struct kvm_run *kvm_run)
1426 {
1427 return (!svm->vcpu.irq_summary &&
1428 kvm_run->request_interrupt_window &&
1429 svm->vcpu.interrupt_window_open &&
1430 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1431 }
1432
1433 static void save_db_regs(unsigned long *db_regs)
1434 {
1435 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1436 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1437 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1438 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1439 }
1440
1441 static void load_db_regs(unsigned long *db_regs)
1442 {
1443 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1444 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1445 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1446 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1447 }
1448
1449 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1450 {
1451 force_new_asid(vcpu);
1452 }
1453
1454 static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1455 {
1456 struct vcpu_svm *svm = to_svm(vcpu);
1457 u16 fs_selector;
1458 u16 gs_selector;
1459 u16 ldt_selector;
1460 int r;
1461
1462 again:
1463 r = kvm_mmu_reload(vcpu);
1464 if (unlikely(r))
1465 return r;
1466
1467 clgi();
1468
1469 if (signal_pending(current)) {
1470 stgi();
1471 ++vcpu->stat.signal_exits;
1472 post_kvm_run_save(svm, kvm_run);
1473 kvm_run->exit_reason = KVM_EXIT_INTR;
1474 return -EINTR;
1475 }
1476
1477 if (irqchip_in_kernel(vcpu->kvm))
1478 svm_intr_assist(svm);
1479 else if (!vcpu->mmio_read_completed)
1480 do_interrupt_requests(svm, kvm_run);
1481
1482 vcpu->guest_mode = 1;
1483 if (vcpu->requests)
1484 if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests))
1485 svm_flush_tlb(vcpu);
1486
1487 pre_svm_run(svm);
1488
1489 save_host_msrs(vcpu);
1490 fs_selector = read_fs();
1491 gs_selector = read_gs();
1492 ldt_selector = read_ldt();
1493 svm->host_cr2 = kvm_read_cr2();
1494 svm->host_dr6 = read_dr6();
1495 svm->host_dr7 = read_dr7();
1496 svm->vmcb->save.cr2 = vcpu->cr2;
1497
1498 if (svm->vmcb->save.dr7 & 0xff) {
1499 write_dr7(0);
1500 save_db_regs(svm->host_db_regs);
1501 load_db_regs(svm->db_regs);
1502 }
1503
1504 if (vcpu->fpu_active) {
1505 fx_save(&vcpu->host_fx_image);
1506 fx_restore(&vcpu->guest_fx_image);
1507 }
1508
1509 asm volatile (
1510 #ifdef CONFIG_X86_64
1511 "push %%rbx; push %%rcx; push %%rdx;"
1512 "push %%rsi; push %%rdi; push %%rbp;"
1513 "push %%r8; push %%r9; push %%r10; push %%r11;"
1514 "push %%r12; push %%r13; push %%r14; push %%r15;"
1515 #else
1516 "push %%ebx; push %%ecx; push %%edx;"
1517 "push %%esi; push %%edi; push %%ebp;"
1518 #endif
1519
1520 #ifdef CONFIG_X86_64
1521 "mov %c[rbx](%[svm]), %%rbx \n\t"
1522 "mov %c[rcx](%[svm]), %%rcx \n\t"
1523 "mov %c[rdx](%[svm]), %%rdx \n\t"
1524 "mov %c[rsi](%[svm]), %%rsi \n\t"
1525 "mov %c[rdi](%[svm]), %%rdi \n\t"
1526 "mov %c[rbp](%[svm]), %%rbp \n\t"
1527 "mov %c[r8](%[svm]), %%r8 \n\t"
1528 "mov %c[r9](%[svm]), %%r9 \n\t"
1529 "mov %c[r10](%[svm]), %%r10 \n\t"
1530 "mov %c[r11](%[svm]), %%r11 \n\t"
1531 "mov %c[r12](%[svm]), %%r12 \n\t"
1532 "mov %c[r13](%[svm]), %%r13 \n\t"
1533 "mov %c[r14](%[svm]), %%r14 \n\t"
1534 "mov %c[r15](%[svm]), %%r15 \n\t"
1535 #else
1536 "mov %c[rbx](%[svm]), %%ebx \n\t"
1537 "mov %c[rcx](%[svm]), %%ecx \n\t"
1538 "mov %c[rdx](%[svm]), %%edx \n\t"
1539 "mov %c[rsi](%[svm]), %%esi \n\t"
1540 "mov %c[rdi](%[svm]), %%edi \n\t"
1541 "mov %c[rbp](%[svm]), %%ebp \n\t"
1542 #endif
1543
1544 #ifdef CONFIG_X86_64
1545 /* Enter guest mode */
1546 "push %%rax \n\t"
1547 "mov %c[vmcb](%[svm]), %%rax \n\t"
1548 SVM_VMLOAD "\n\t"
1549 SVM_VMRUN "\n\t"
1550 SVM_VMSAVE "\n\t"
1551 "pop %%rax \n\t"
1552 #else
1553 /* Enter guest mode */
1554 "push %%eax \n\t"
1555 "mov %c[vmcb](%[svm]), %%eax \n\t"
1556 SVM_VMLOAD "\n\t"
1557 SVM_VMRUN "\n\t"
1558 SVM_VMSAVE "\n\t"
1559 "pop %%eax \n\t"
1560 #endif
1561
1562 /* Save guest registers, load host registers */
1563 #ifdef CONFIG_X86_64
1564 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1565 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1566 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1567 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1568 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1569 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1570 "mov %%r8, %c[r8](%[svm]) \n\t"
1571 "mov %%r9, %c[r9](%[svm]) \n\t"
1572 "mov %%r10, %c[r10](%[svm]) \n\t"
1573 "mov %%r11, %c[r11](%[svm]) \n\t"
1574 "mov %%r12, %c[r12](%[svm]) \n\t"
1575 "mov %%r13, %c[r13](%[svm]) \n\t"
1576 "mov %%r14, %c[r14](%[svm]) \n\t"
1577 "mov %%r15, %c[r15](%[svm]) \n\t"
1578
1579 "pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1580 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1581 "pop %%rbp; pop %%rdi; pop %%rsi;"
1582 "pop %%rdx; pop %%rcx; pop %%rbx; \n\t"
1583 #else
1584 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1585 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1586 "mov %%edx, %c[rdx](%[svm]) \n\t"
1587 "mov %%esi, %c[rsi](%[svm]) \n\t"
1588 "mov %%edi, %c[rdi](%[svm]) \n\t"
1589 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1590
1591 "pop %%ebp; pop %%edi; pop %%esi;"
1592 "pop %%edx; pop %%ecx; pop %%ebx; \n\t"
1593 #endif
1594 :
1595 : [svm]"a"(svm),
1596 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1597 [rbx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBX])),
1598 [rcx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RCX])),
1599 [rdx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDX])),
1600 [rsi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RSI])),
1601 [rdi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDI])),
1602 [rbp]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBP]))
1603 #ifdef CONFIG_X86_64
1604 ,[r8 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R8])),
1605 [r9 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R9 ])),
1606 [r10]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R10])),
1607 [r11]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R11])),
1608 [r12]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R12])),
1609 [r13]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R13])),
1610 [r14]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R14])),
1611 [r15]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R15]))
1612 #endif
1613 : "cc", "memory" );
1614
1615 vcpu->guest_mode = 0;
1616
1617 if (vcpu->fpu_active) {
1618 fx_save(&vcpu->guest_fx_image);
1619 fx_restore(&vcpu->host_fx_image);
1620 }
1621
1622 if ((svm->vmcb->save.dr7 & 0xff))
1623 load_db_regs(svm->host_db_regs);
1624
1625 vcpu->cr2 = svm->vmcb->save.cr2;
1626
1627 write_dr6(svm->host_dr6);
1628 write_dr7(svm->host_dr7);
1629 kvm_write_cr2(svm->host_cr2);
1630
1631 load_fs(fs_selector);
1632 load_gs(gs_selector);
1633 load_ldt(ldt_selector);
1634 load_host_msrs(vcpu);
1635
1636 reload_tss(vcpu);
1637
1638 /*
1639 * Profile KVM exit RIPs:
1640 */
1641 if (unlikely(prof_on == KVM_PROFILING))
1642 profile_hit(KVM_PROFILING,
1643 (void *)(unsigned long)svm->vmcb->save.rip);
1644
1645 stgi();
1646
1647 kvm_reput_irq(svm);
1648
1649 svm->next_rip = 0;
1650
1651 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1652 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1653 kvm_run->fail_entry.hardware_entry_failure_reason
1654 = svm->vmcb->control.exit_code;
1655 post_kvm_run_save(svm, kvm_run);
1656 return 0;
1657 }
1658
1659 r = handle_exit(svm, kvm_run);
1660 if (r > 0) {
1661 if (dm_request_for_irq_injection(svm, kvm_run)) {
1662 ++vcpu->stat.request_irq_exits;
1663 post_kvm_run_save(svm, kvm_run);
1664 kvm_run->exit_reason = KVM_EXIT_INTR;
1665 return -EINTR;
1666 }
1667 kvm_resched(vcpu);
1668 goto again;
1669 }
1670 post_kvm_run_save(svm, kvm_run);
1671 return r;
1672 }
1673
1674 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1675 {
1676 struct vcpu_svm *svm = to_svm(vcpu);
1677
1678 svm->vmcb->save.cr3 = root;
1679 force_new_asid(vcpu);
1680
1681 if (vcpu->fpu_active) {
1682 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1683 svm->vmcb->save.cr0 |= X86_CR0_TS;
1684 vcpu->fpu_active = 0;
1685 }
1686 }
1687
1688 static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1689 unsigned long addr,
1690 uint32_t err_code)
1691 {
1692 struct vcpu_svm *svm = to_svm(vcpu);
1693 uint32_t exit_int_info = svm->vmcb->control.exit_int_info;
1694
1695 ++vcpu->stat.pf_guest;
1696
1697 if (is_page_fault(exit_int_info)) {
1698
1699 svm->vmcb->control.event_inj_err = 0;
1700 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1701 SVM_EVTINJ_VALID_ERR |
1702 SVM_EVTINJ_TYPE_EXEPT |
1703 DF_VECTOR;
1704 return;
1705 }
1706 vcpu->cr2 = addr;
1707 svm->vmcb->save.cr2 = addr;
1708 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1709 SVM_EVTINJ_VALID_ERR |
1710 SVM_EVTINJ_TYPE_EXEPT |
1711 PF_VECTOR;
1712 svm->vmcb->control.event_inj_err = err_code;
1713 }
1714
1715
1716 static int is_disabled(void)
1717 {
1718 u64 vm_cr;
1719
1720 rdmsrl(MSR_VM_CR, vm_cr);
1721 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1722 return 1;
1723
1724 return 0;
1725 }
1726
1727 static void
1728 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1729 {
1730 /*
1731 * Patch in the VMMCALL instruction:
1732 */
1733 hypercall[0] = 0x0f;
1734 hypercall[1] = 0x01;
1735 hypercall[2] = 0xd9;
1736 hypercall[3] = 0xc3;
1737 }
1738
1739 static void svm_check_processor_compat(void *rtn)
1740 {
1741 *(int *)rtn = 0;
1742 }
1743
1744 static struct kvm_x86_ops svm_x86_ops = {
1745 .cpu_has_kvm_support = has_svm,
1746 .disabled_by_bios = is_disabled,
1747 .hardware_setup = svm_hardware_setup,
1748 .hardware_unsetup = svm_hardware_unsetup,
1749 .check_processor_compatibility = svm_check_processor_compat,
1750 .hardware_enable = svm_hardware_enable,
1751 .hardware_disable = svm_hardware_disable,
1752
1753 .vcpu_create = svm_create_vcpu,
1754 .vcpu_free = svm_free_vcpu,
1755
1756 .vcpu_load = svm_vcpu_load,
1757 .vcpu_put = svm_vcpu_put,
1758 .vcpu_decache = svm_vcpu_decache,
1759
1760 .set_guest_debug = svm_guest_debug,
1761 .get_msr = svm_get_msr,
1762 .set_msr = svm_set_msr,
1763 .get_segment_base = svm_get_segment_base,
1764 .get_segment = svm_get_segment,
1765 .set_segment = svm_set_segment,
1766 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1767 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1768 .set_cr0 = svm_set_cr0,
1769 .set_cr3 = svm_set_cr3,
1770 .set_cr4 = svm_set_cr4,
1771 .set_efer = svm_set_efer,
1772 .get_idt = svm_get_idt,
1773 .set_idt = svm_set_idt,
1774 .get_gdt = svm_get_gdt,
1775 .set_gdt = svm_set_gdt,
1776 .get_dr = svm_get_dr,
1777 .set_dr = svm_set_dr,
1778 .cache_regs = svm_cache_regs,
1779 .decache_regs = svm_decache_regs,
1780 .get_rflags = svm_get_rflags,
1781 .set_rflags = svm_set_rflags,
1782
1783 .tlb_flush = svm_flush_tlb,
1784 .inject_page_fault = svm_inject_page_fault,
1785
1786 .inject_gp = svm_inject_gp,
1787
1788 .run = svm_vcpu_run,
1789 .skip_emulated_instruction = skip_emulated_instruction,
1790 .patch_hypercall = svm_patch_hypercall,
1791 .get_irq = svm_get_irq,
1792 .set_irq = svm_set_irq,
1793 };
1794
1795 static int __init svm_init(void)
1796 {
1797 return kvm_init_x86(&svm_x86_ops, sizeof(struct vcpu_svm),
1798 THIS_MODULE);
1799 }
1800
1801 static void __exit svm_exit(void)
1802 {
1803 kvm_exit_x86();
1804 }
1805
1806 module_init(svm_init)
1807 module_exit(svm_exit)
Linux kernel - Deliverables
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