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KVM: VMX: Only save/restore MSR_K6_STAR if necessary
[deliverable/linux.git] / drivers / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "kvm.h"
19 #include "vmx.h"
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/highmem.h>
24 #include <linux/profile.h>
25 #include <asm/io.h>
26 #include <asm/desc.h>
27
28 #include "segment_descriptor.h"
29
30 MODULE_AUTHOR("Qumranet");
31 MODULE_LICENSE("GPL");
32
33 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
34 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
35
36 #ifdef CONFIG_X86_64
37 #define HOST_IS_64 1
38 #else
39 #define HOST_IS_64 0
40 #endif
41
42 static struct vmcs_descriptor {
43 int size;
44 int order;
45 u32 revision_id;
46 } vmcs_descriptor;
47
48 #define VMX_SEGMENT_FIELD(seg) \
49 [VCPU_SREG_##seg] = { \
50 .selector = GUEST_##seg##_SELECTOR, \
51 .base = GUEST_##seg##_BASE, \
52 .limit = GUEST_##seg##_LIMIT, \
53 .ar_bytes = GUEST_##seg##_AR_BYTES, \
54 }
55
56 static struct kvm_vmx_segment_field {
57 unsigned selector;
58 unsigned base;
59 unsigned limit;
60 unsigned ar_bytes;
61 } kvm_vmx_segment_fields[] = {
62 VMX_SEGMENT_FIELD(CS),
63 VMX_SEGMENT_FIELD(DS),
64 VMX_SEGMENT_FIELD(ES),
65 VMX_SEGMENT_FIELD(FS),
66 VMX_SEGMENT_FIELD(GS),
67 VMX_SEGMENT_FIELD(SS),
68 VMX_SEGMENT_FIELD(TR),
69 VMX_SEGMENT_FIELD(LDTR),
70 };
71
72 /*
73 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
74 * away by decrementing the array size.
75 */
76 static const u32 vmx_msr_index[] = {
77 #ifdef CONFIG_X86_64
78 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
79 #endif
80 MSR_EFER, MSR_K6_STAR,
81 };
82 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
83
84 #ifdef CONFIG_X86_64
85 static unsigned msr_offset_kernel_gs_base;
86 #define NR_64BIT_MSRS 4
87 /*
88 * avoid save/load MSR_SYSCALL_MASK and MSR_LSTAR by std vt
89 * mechanism (cpu bug AA24)
90 */
91 #define NR_BAD_MSRS 2
92 #else
93 #define NR_64BIT_MSRS 0
94 #define NR_BAD_MSRS 0
95 #endif
96
97 static inline int is_page_fault(u32 intr_info)
98 {
99 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
100 INTR_INFO_VALID_MASK)) ==
101 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
102 }
103
104 static inline int is_external_interrupt(u32 intr_info)
105 {
106 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
107 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
108 }
109
110 static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
111 {
112 int i;
113
114 for (i = 0; i < vcpu->nmsrs; ++i)
115 if (vcpu->guest_msrs[i].index == msr)
116 return &vcpu->guest_msrs[i];
117 return NULL;
118 }
119
120 static void vmcs_clear(struct vmcs *vmcs)
121 {
122 u64 phys_addr = __pa(vmcs);
123 u8 error;
124
125 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
126 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
127 : "cc", "memory");
128 if (error)
129 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
130 vmcs, phys_addr);
131 }
132
133 static void __vcpu_clear(void *arg)
134 {
135 struct kvm_vcpu *vcpu = arg;
136 int cpu = raw_smp_processor_id();
137
138 if (vcpu->cpu == cpu)
139 vmcs_clear(vcpu->vmcs);
140 if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
141 per_cpu(current_vmcs, cpu) = NULL;
142 }
143
144 static void vcpu_clear(struct kvm_vcpu *vcpu)
145 {
146 if (vcpu->cpu != raw_smp_processor_id() && vcpu->cpu != -1)
147 smp_call_function_single(vcpu->cpu, __vcpu_clear, vcpu, 0, 1);
148 else
149 __vcpu_clear(vcpu);
150 vcpu->launched = 0;
151 }
152
153 static unsigned long vmcs_readl(unsigned long field)
154 {
155 unsigned long value;
156
157 asm volatile (ASM_VMX_VMREAD_RDX_RAX
158 : "=a"(value) : "d"(field) : "cc");
159 return value;
160 }
161
162 static u16 vmcs_read16(unsigned long field)
163 {
164 return vmcs_readl(field);
165 }
166
167 static u32 vmcs_read32(unsigned long field)
168 {
169 return vmcs_readl(field);
170 }
171
172 static u64 vmcs_read64(unsigned long field)
173 {
174 #ifdef CONFIG_X86_64
175 return vmcs_readl(field);
176 #else
177 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
178 #endif
179 }
180
181 static noinline void vmwrite_error(unsigned long field, unsigned long value)
182 {
183 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
184 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
185 dump_stack();
186 }
187
188 static void vmcs_writel(unsigned long field, unsigned long value)
189 {
190 u8 error;
191
192 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
193 : "=q"(error) : "a"(value), "d"(field) : "cc" );
194 if (unlikely(error))
195 vmwrite_error(field, value);
196 }
197
198 static void vmcs_write16(unsigned long field, u16 value)
199 {
200 vmcs_writel(field, value);
201 }
202
203 static void vmcs_write32(unsigned long field, u32 value)
204 {
205 vmcs_writel(field, value);
206 }
207
208 static void vmcs_write64(unsigned long field, u64 value)
209 {
210 #ifdef CONFIG_X86_64
211 vmcs_writel(field, value);
212 #else
213 vmcs_writel(field, value);
214 asm volatile ("");
215 vmcs_writel(field+1, value >> 32);
216 #endif
217 }
218
219 /*
220 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
221 * vcpu mutex is already taken.
222 */
223 static void vmx_vcpu_load(struct kvm_vcpu *vcpu)
224 {
225 u64 phys_addr = __pa(vcpu->vmcs);
226 int cpu;
227
228 cpu = get_cpu();
229
230 if (vcpu->cpu != cpu)
231 vcpu_clear(vcpu);
232
233 if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
234 u8 error;
235
236 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
237 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
238 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
239 : "cc");
240 if (error)
241 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
242 vcpu->vmcs, phys_addr);
243 }
244
245 if (vcpu->cpu != cpu) {
246 struct descriptor_table dt;
247 unsigned long sysenter_esp;
248
249 vcpu->cpu = cpu;
250 /*
251 * Linux uses per-cpu TSS and GDT, so set these when switching
252 * processors.
253 */
254 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
255 get_gdt(&dt);
256 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
257
258 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
259 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
260 }
261 }
262
263 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
264 {
265 put_cpu();
266 }
267
268 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
269 {
270 vcpu_clear(vcpu);
271 }
272
273 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
274 {
275 return vmcs_readl(GUEST_RFLAGS);
276 }
277
278 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
279 {
280 vmcs_writel(GUEST_RFLAGS, rflags);
281 }
282
283 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
284 {
285 unsigned long rip;
286 u32 interruptibility;
287
288 rip = vmcs_readl(GUEST_RIP);
289 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
290 vmcs_writel(GUEST_RIP, rip);
291
292 /*
293 * We emulated an instruction, so temporary interrupt blocking
294 * should be removed, if set.
295 */
296 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
297 if (interruptibility & 3)
298 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
299 interruptibility & ~3);
300 vcpu->interrupt_window_open = 1;
301 }
302
303 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
304 {
305 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
306 vmcs_readl(GUEST_RIP));
307 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
308 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
309 GP_VECTOR |
310 INTR_TYPE_EXCEPTION |
311 INTR_INFO_DELIEVER_CODE_MASK |
312 INTR_INFO_VALID_MASK);
313 }
314
315 /*
316 * Set up the vmcs to automatically save and restore system
317 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
318 * mode, as fiddling with msrs is very expensive.
319 */
320 static void setup_msrs(struct kvm_vcpu *vcpu)
321 {
322 int nr_skip, nr_good_msrs;
323
324 if (is_long_mode(vcpu))
325 nr_skip = NR_BAD_MSRS;
326 else
327 nr_skip = NR_64BIT_MSRS;
328 nr_good_msrs = vcpu->nmsrs - nr_skip;
329
330 /*
331 * MSR_K6_STAR is only needed on long mode guests, and only
332 * if efer.sce is enabled.
333 */
334 if (find_msr_entry(vcpu, MSR_K6_STAR)) {
335 --nr_good_msrs;
336 #ifdef CONFIG_X86_64
337 if (is_long_mode(vcpu) && (vcpu->shadow_efer & EFER_SCE))
338 ++nr_good_msrs;
339 #endif
340 }
341
342 vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR,
343 virt_to_phys(vcpu->guest_msrs + nr_skip));
344 vmcs_writel(VM_EXIT_MSR_STORE_ADDR,
345 virt_to_phys(vcpu->guest_msrs + nr_skip));
346 vmcs_writel(VM_EXIT_MSR_LOAD_ADDR,
347 virt_to_phys(vcpu->host_msrs + nr_skip));
348 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */
349 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
350 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
351 }
352
353 /*
354 * reads and returns guest's timestamp counter "register"
355 * guest_tsc = host_tsc + tsc_offset -- 21.3
356 */
357 static u64 guest_read_tsc(void)
358 {
359 u64 host_tsc, tsc_offset;
360
361 rdtscll(host_tsc);
362 tsc_offset = vmcs_read64(TSC_OFFSET);
363 return host_tsc + tsc_offset;
364 }
365
366 /*
367 * writes 'guest_tsc' into guest's timestamp counter "register"
368 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
369 */
370 static void guest_write_tsc(u64 guest_tsc)
371 {
372 u64 host_tsc;
373
374 rdtscll(host_tsc);
375 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
376 }
377
378 static void reload_tss(void)
379 {
380 #ifndef CONFIG_X86_64
381
382 /*
383 * VT restores TR but not its size. Useless.
384 */
385 struct descriptor_table gdt;
386 struct segment_descriptor *descs;
387
388 get_gdt(&gdt);
389 descs = (void *)gdt.base;
390 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
391 load_TR_desc();
392 #endif
393 }
394
395 /*
396 * Reads an msr value (of 'msr_index') into 'pdata'.
397 * Returns 0 on success, non-0 otherwise.
398 * Assumes vcpu_load() was already called.
399 */
400 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
401 {
402 u64 data;
403 struct vmx_msr_entry *msr;
404
405 if (!pdata) {
406 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
407 return -EINVAL;
408 }
409
410 switch (msr_index) {
411 #ifdef CONFIG_X86_64
412 case MSR_FS_BASE:
413 data = vmcs_readl(GUEST_FS_BASE);
414 break;
415 case MSR_GS_BASE:
416 data = vmcs_readl(GUEST_GS_BASE);
417 break;
418 case MSR_EFER:
419 return kvm_get_msr_common(vcpu, msr_index, pdata);
420 #endif
421 case MSR_IA32_TIME_STAMP_COUNTER:
422 data = guest_read_tsc();
423 break;
424 case MSR_IA32_SYSENTER_CS:
425 data = vmcs_read32(GUEST_SYSENTER_CS);
426 break;
427 case MSR_IA32_SYSENTER_EIP:
428 data = vmcs_readl(GUEST_SYSENTER_EIP);
429 break;
430 case MSR_IA32_SYSENTER_ESP:
431 data = vmcs_readl(GUEST_SYSENTER_ESP);
432 break;
433 default:
434 msr = find_msr_entry(vcpu, msr_index);
435 if (msr) {
436 data = msr->data;
437 break;
438 }
439 return kvm_get_msr_common(vcpu, msr_index, pdata);
440 }
441
442 *pdata = data;
443 return 0;
444 }
445
446 /*
447 * Writes msr value into into the appropriate "register".
448 * Returns 0 on success, non-0 otherwise.
449 * Assumes vcpu_load() was already called.
450 */
451 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
452 {
453 struct vmx_msr_entry *msr;
454 switch (msr_index) {
455 #ifdef CONFIG_X86_64
456 case MSR_EFER:
457 return kvm_set_msr_common(vcpu, msr_index, data);
458 case MSR_FS_BASE:
459 vmcs_writel(GUEST_FS_BASE, data);
460 break;
461 case MSR_GS_BASE:
462 vmcs_writel(GUEST_GS_BASE, data);
463 break;
464 #endif
465 case MSR_IA32_SYSENTER_CS:
466 vmcs_write32(GUEST_SYSENTER_CS, data);
467 break;
468 case MSR_IA32_SYSENTER_EIP:
469 vmcs_writel(GUEST_SYSENTER_EIP, data);
470 break;
471 case MSR_IA32_SYSENTER_ESP:
472 vmcs_writel(GUEST_SYSENTER_ESP, data);
473 break;
474 case MSR_IA32_TIME_STAMP_COUNTER:
475 guest_write_tsc(data);
476 break;
477 default:
478 msr = find_msr_entry(vcpu, msr_index);
479 if (msr) {
480 msr->data = data;
481 break;
482 }
483 return kvm_set_msr_common(vcpu, msr_index, data);
484 msr->data = data;
485 break;
486 }
487
488 return 0;
489 }
490
491 /*
492 * Sync the rsp and rip registers into the vcpu structure. This allows
493 * registers to be accessed by indexing vcpu->regs.
494 */
495 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
496 {
497 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
498 vcpu->rip = vmcs_readl(GUEST_RIP);
499 }
500
501 /*
502 * Syncs rsp and rip back into the vmcs. Should be called after possible
503 * modification.
504 */
505 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
506 {
507 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
508 vmcs_writel(GUEST_RIP, vcpu->rip);
509 }
510
511 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
512 {
513 unsigned long dr7 = 0x400;
514 u32 exception_bitmap;
515 int old_singlestep;
516
517 exception_bitmap = vmcs_read32(EXCEPTION_BITMAP);
518 old_singlestep = vcpu->guest_debug.singlestep;
519
520 vcpu->guest_debug.enabled = dbg->enabled;
521 if (vcpu->guest_debug.enabled) {
522 int i;
523
524 dr7 |= 0x200; /* exact */
525 for (i = 0; i < 4; ++i) {
526 if (!dbg->breakpoints[i].enabled)
527 continue;
528 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
529 dr7 |= 2 << (i*2); /* global enable */
530 dr7 |= 0 << (i*4+16); /* execution breakpoint */
531 }
532
533 exception_bitmap |= (1u << 1); /* Trap debug exceptions */
534
535 vcpu->guest_debug.singlestep = dbg->singlestep;
536 } else {
537 exception_bitmap &= ~(1u << 1); /* Ignore debug exceptions */
538 vcpu->guest_debug.singlestep = 0;
539 }
540
541 if (old_singlestep && !vcpu->guest_debug.singlestep) {
542 unsigned long flags;
543
544 flags = vmcs_readl(GUEST_RFLAGS);
545 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
546 vmcs_writel(GUEST_RFLAGS, flags);
547 }
548
549 vmcs_write32(EXCEPTION_BITMAP, exception_bitmap);
550 vmcs_writel(GUEST_DR7, dr7);
551
552 return 0;
553 }
554
555 static __init int cpu_has_kvm_support(void)
556 {
557 unsigned long ecx = cpuid_ecx(1);
558 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
559 }
560
561 static __init int vmx_disabled_by_bios(void)
562 {
563 u64 msr;
564
565 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
566 return (msr & 5) == 1; /* locked but not enabled */
567 }
568
569 static void hardware_enable(void *garbage)
570 {
571 int cpu = raw_smp_processor_id();
572 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
573 u64 old;
574
575 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
576 if ((old & 5) != 5)
577 /* enable and lock */
578 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
579 write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
580 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
581 : "memory", "cc");
582 }
583
584 static void hardware_disable(void *garbage)
585 {
586 asm volatile (ASM_VMX_VMXOFF : : : "cc");
587 }
588
589 static __init void setup_vmcs_descriptor(void)
590 {
591 u32 vmx_msr_low, vmx_msr_high;
592
593 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
594 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
595 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
596 vmcs_descriptor.revision_id = vmx_msr_low;
597 }
598
599 static struct vmcs *alloc_vmcs_cpu(int cpu)
600 {
601 int node = cpu_to_node(cpu);
602 struct page *pages;
603 struct vmcs *vmcs;
604
605 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
606 if (!pages)
607 return NULL;
608 vmcs = page_address(pages);
609 memset(vmcs, 0, vmcs_descriptor.size);
610 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
611 return vmcs;
612 }
613
614 static struct vmcs *alloc_vmcs(void)
615 {
616 return alloc_vmcs_cpu(raw_smp_processor_id());
617 }
618
619 static void free_vmcs(struct vmcs *vmcs)
620 {
621 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
622 }
623
624 static __exit void free_kvm_area(void)
625 {
626 int cpu;
627
628 for_each_online_cpu(cpu)
629 free_vmcs(per_cpu(vmxarea, cpu));
630 }
631
632 extern struct vmcs *alloc_vmcs_cpu(int cpu);
633
634 static __init int alloc_kvm_area(void)
635 {
636 int cpu;
637
638 for_each_online_cpu(cpu) {
639 struct vmcs *vmcs;
640
641 vmcs = alloc_vmcs_cpu(cpu);
642 if (!vmcs) {
643 free_kvm_area();
644 return -ENOMEM;
645 }
646
647 per_cpu(vmxarea, cpu) = vmcs;
648 }
649 return 0;
650 }
651
652 static __init int hardware_setup(void)
653 {
654 setup_vmcs_descriptor();
655 return alloc_kvm_area();
656 }
657
658 static __exit void hardware_unsetup(void)
659 {
660 free_kvm_area();
661 }
662
663 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
664 {
665 if (vcpu->rmode.active)
666 vmcs_write32(EXCEPTION_BITMAP, ~0);
667 else
668 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
669 }
670
671 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
672 {
673 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
674
675 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
676 vmcs_write16(sf->selector, save->selector);
677 vmcs_writel(sf->base, save->base);
678 vmcs_write32(sf->limit, save->limit);
679 vmcs_write32(sf->ar_bytes, save->ar);
680 } else {
681 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
682 << AR_DPL_SHIFT;
683 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
684 }
685 }
686
687 static void enter_pmode(struct kvm_vcpu *vcpu)
688 {
689 unsigned long flags;
690
691 vcpu->rmode.active = 0;
692
693 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
694 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
695 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
696
697 flags = vmcs_readl(GUEST_RFLAGS);
698 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
699 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
700 vmcs_writel(GUEST_RFLAGS, flags);
701
702 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
703 (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
704
705 update_exception_bitmap(vcpu);
706
707 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
708 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
709 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
710 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
711
712 vmcs_write16(GUEST_SS_SELECTOR, 0);
713 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
714
715 vmcs_write16(GUEST_CS_SELECTOR,
716 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
717 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
718 }
719
720 static int rmode_tss_base(struct kvm* kvm)
721 {
722 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
723 return base_gfn << PAGE_SHIFT;
724 }
725
726 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
727 {
728 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
729
730 save->selector = vmcs_read16(sf->selector);
731 save->base = vmcs_readl(sf->base);
732 save->limit = vmcs_read32(sf->limit);
733 save->ar = vmcs_read32(sf->ar_bytes);
734 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
735 vmcs_write32(sf->limit, 0xffff);
736 vmcs_write32(sf->ar_bytes, 0xf3);
737 }
738
739 static void enter_rmode(struct kvm_vcpu *vcpu)
740 {
741 unsigned long flags;
742
743 vcpu->rmode.active = 1;
744
745 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
746 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
747
748 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
749 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
750
751 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
752 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
753
754 flags = vmcs_readl(GUEST_RFLAGS);
755 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
756
757 flags |= IOPL_MASK | X86_EFLAGS_VM;
758
759 vmcs_writel(GUEST_RFLAGS, flags);
760 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
761 update_exception_bitmap(vcpu);
762
763 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
764 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
765 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
766
767 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
768 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
769 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
770 vmcs_writel(GUEST_CS_BASE, 0xf0000);
771 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
772
773 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
774 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
775 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
776 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
777 }
778
779 #ifdef CONFIG_X86_64
780
781 static void enter_lmode(struct kvm_vcpu *vcpu)
782 {
783 u32 guest_tr_ar;
784
785 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
786 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
787 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
788 __FUNCTION__);
789 vmcs_write32(GUEST_TR_AR_BYTES,
790 (guest_tr_ar & ~AR_TYPE_MASK)
791 | AR_TYPE_BUSY_64_TSS);
792 }
793
794 vcpu->shadow_efer |= EFER_LMA;
795
796 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
797 vmcs_write32(VM_ENTRY_CONTROLS,
798 vmcs_read32(VM_ENTRY_CONTROLS)
799 | VM_ENTRY_CONTROLS_IA32E_MASK);
800 }
801
802 static void exit_lmode(struct kvm_vcpu *vcpu)
803 {
804 vcpu->shadow_efer &= ~EFER_LMA;
805
806 vmcs_write32(VM_ENTRY_CONTROLS,
807 vmcs_read32(VM_ENTRY_CONTROLS)
808 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
809 }
810
811 #endif
812
813 static void vmx_decache_cr0_cr4_guest_bits(struct kvm_vcpu *vcpu)
814 {
815 vcpu->cr0 &= KVM_GUEST_CR0_MASK;
816 vcpu->cr0 |= vmcs_readl(GUEST_CR0) & ~KVM_GUEST_CR0_MASK;
817
818 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
819 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
820 }
821
822 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
823 {
824 if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
825 enter_pmode(vcpu);
826
827 if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
828 enter_rmode(vcpu);
829
830 #ifdef CONFIG_X86_64
831 if (vcpu->shadow_efer & EFER_LME) {
832 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
833 enter_lmode(vcpu);
834 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
835 exit_lmode(vcpu);
836 }
837 #endif
838
839 vmcs_writel(CR0_READ_SHADOW, cr0);
840 vmcs_writel(GUEST_CR0,
841 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
842 vcpu->cr0 = cr0;
843 }
844
845 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
846 {
847 vmcs_writel(GUEST_CR3, cr3);
848 }
849
850 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
851 {
852 vmcs_writel(CR4_READ_SHADOW, cr4);
853 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
854 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
855 vcpu->cr4 = cr4;
856 }
857
858 #ifdef CONFIG_X86_64
859
860 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
861 {
862 struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
863
864 vcpu->shadow_efer = efer;
865 if (efer & EFER_LMA) {
866 vmcs_write32(VM_ENTRY_CONTROLS,
867 vmcs_read32(VM_ENTRY_CONTROLS) |
868 VM_ENTRY_CONTROLS_IA32E_MASK);
869 msr->data = efer;
870
871 } else {
872 vmcs_write32(VM_ENTRY_CONTROLS,
873 vmcs_read32(VM_ENTRY_CONTROLS) &
874 ~VM_ENTRY_CONTROLS_IA32E_MASK);
875
876 msr->data = efer & ~EFER_LME;
877 }
878 setup_msrs(vcpu);
879 }
880
881 #endif
882
883 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
884 {
885 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
886
887 return vmcs_readl(sf->base);
888 }
889
890 static void vmx_get_segment(struct kvm_vcpu *vcpu,
891 struct kvm_segment *var, int seg)
892 {
893 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
894 u32 ar;
895
896 var->base = vmcs_readl(sf->base);
897 var->limit = vmcs_read32(sf->limit);
898 var->selector = vmcs_read16(sf->selector);
899 ar = vmcs_read32(sf->ar_bytes);
900 if (ar & AR_UNUSABLE_MASK)
901 ar = 0;
902 var->type = ar & 15;
903 var->s = (ar >> 4) & 1;
904 var->dpl = (ar >> 5) & 3;
905 var->present = (ar >> 7) & 1;
906 var->avl = (ar >> 12) & 1;
907 var->l = (ar >> 13) & 1;
908 var->db = (ar >> 14) & 1;
909 var->g = (ar >> 15) & 1;
910 var->unusable = (ar >> 16) & 1;
911 }
912
913 static void vmx_set_segment(struct kvm_vcpu *vcpu,
914 struct kvm_segment *var, int seg)
915 {
916 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
917 u32 ar;
918
919 vmcs_writel(sf->base, var->base);
920 vmcs_write32(sf->limit, var->limit);
921 vmcs_write16(sf->selector, var->selector);
922 if (vcpu->rmode.active && var->s) {
923 /*
924 * Hack real-mode segments into vm86 compatibility.
925 */
926 if (var->base == 0xffff0000 && var->selector == 0xf000)
927 vmcs_writel(sf->base, 0xf0000);
928 ar = 0xf3;
929 } else if (var->unusable)
930 ar = 1 << 16;
931 else {
932 ar = var->type & 15;
933 ar |= (var->s & 1) << 4;
934 ar |= (var->dpl & 3) << 5;
935 ar |= (var->present & 1) << 7;
936 ar |= (var->avl & 1) << 12;
937 ar |= (var->l & 1) << 13;
938 ar |= (var->db & 1) << 14;
939 ar |= (var->g & 1) << 15;
940 }
941 if (ar == 0) /* a 0 value means unusable */
942 ar = AR_UNUSABLE_MASK;
943 vmcs_write32(sf->ar_bytes, ar);
944 }
945
946 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
947 {
948 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
949
950 *db = (ar >> 14) & 1;
951 *l = (ar >> 13) & 1;
952 }
953
954 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
955 {
956 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
957 dt->base = vmcs_readl(GUEST_IDTR_BASE);
958 }
959
960 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
961 {
962 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
963 vmcs_writel(GUEST_IDTR_BASE, dt->base);
964 }
965
966 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
967 {
968 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
969 dt->base = vmcs_readl(GUEST_GDTR_BASE);
970 }
971
972 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
973 {
974 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
975 vmcs_writel(GUEST_GDTR_BASE, dt->base);
976 }
977
978 static int init_rmode_tss(struct kvm* kvm)
979 {
980 struct page *p1, *p2, *p3;
981 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
982 char *page;
983
984 p1 = gfn_to_page(kvm, fn++);
985 p2 = gfn_to_page(kvm, fn++);
986 p3 = gfn_to_page(kvm, fn);
987
988 if (!p1 || !p2 || !p3) {
989 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
990 return 0;
991 }
992
993 page = kmap_atomic(p1, KM_USER0);
994 memset(page, 0, PAGE_SIZE);
995 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
996 kunmap_atomic(page, KM_USER0);
997
998 page = kmap_atomic(p2, KM_USER0);
999 memset(page, 0, PAGE_SIZE);
1000 kunmap_atomic(page, KM_USER0);
1001
1002 page = kmap_atomic(p3, KM_USER0);
1003 memset(page, 0, PAGE_SIZE);
1004 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1005 kunmap_atomic(page, KM_USER0);
1006
1007 return 1;
1008 }
1009
1010 static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
1011 {
1012 u32 msr_high, msr_low;
1013
1014 rdmsr(msr, msr_low, msr_high);
1015
1016 val &= msr_high;
1017 val |= msr_low;
1018 vmcs_write32(vmcs_field, val);
1019 }
1020
1021 static void seg_setup(int seg)
1022 {
1023 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1024
1025 vmcs_write16(sf->selector, 0);
1026 vmcs_writel(sf->base, 0);
1027 vmcs_write32(sf->limit, 0xffff);
1028 vmcs_write32(sf->ar_bytes, 0x93);
1029 }
1030
1031 /*
1032 * Sets up the vmcs for emulated real mode.
1033 */
1034 static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
1035 {
1036 u32 host_sysenter_cs;
1037 u32 junk;
1038 unsigned long a;
1039 struct descriptor_table dt;
1040 int i;
1041 int ret = 0;
1042 extern asmlinkage void kvm_vmx_return(void);
1043
1044 if (!init_rmode_tss(vcpu->kvm)) {
1045 ret = -ENOMEM;
1046 goto out;
1047 }
1048
1049 memset(vcpu->regs, 0, sizeof(vcpu->regs));
1050 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
1051 vcpu->cr8 = 0;
1052 vcpu->apic_base = 0xfee00000 |
1053 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
1054 MSR_IA32_APICBASE_ENABLE;
1055
1056 fx_init(vcpu);
1057
1058 /*
1059 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1060 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1061 */
1062 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1063 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1064 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1065 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1066
1067 seg_setup(VCPU_SREG_DS);
1068 seg_setup(VCPU_SREG_ES);
1069 seg_setup(VCPU_SREG_FS);
1070 seg_setup(VCPU_SREG_GS);
1071 seg_setup(VCPU_SREG_SS);
1072
1073 vmcs_write16(GUEST_TR_SELECTOR, 0);
1074 vmcs_writel(GUEST_TR_BASE, 0);
1075 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1076 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1077
1078 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1079 vmcs_writel(GUEST_LDTR_BASE, 0);
1080 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1081 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1082
1083 vmcs_write32(GUEST_SYSENTER_CS, 0);
1084 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1085 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1086
1087 vmcs_writel(GUEST_RFLAGS, 0x02);
1088 vmcs_writel(GUEST_RIP, 0xfff0);
1089 vmcs_writel(GUEST_RSP, 0);
1090
1091 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1092 vmcs_writel(GUEST_DR7, 0x400);
1093
1094 vmcs_writel(GUEST_GDTR_BASE, 0);
1095 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1096
1097 vmcs_writel(GUEST_IDTR_BASE, 0);
1098 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1099
1100 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1101 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1102 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1103
1104 /* I/O */
1105 vmcs_write64(IO_BITMAP_A, 0);
1106 vmcs_write64(IO_BITMAP_B, 0);
1107
1108 guest_write_tsc(0);
1109
1110 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1111
1112 /* Special registers */
1113 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1114
1115 /* Control */
1116 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS,
1117 PIN_BASED_VM_EXEC_CONTROL,
1118 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1119 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1120 );
1121 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS,
1122 CPU_BASED_VM_EXEC_CONTROL,
1123 CPU_BASED_HLT_EXITING /* 20.6.2 */
1124 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1125 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
1126 | CPU_BASED_UNCOND_IO_EXITING /* 20.6.2 */
1127 | CPU_BASED_MOV_DR_EXITING
1128 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1129 );
1130
1131 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
1132 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1133 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1134 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1135
1136 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1137 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1138 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1139
1140 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1141 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1142 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1143 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1144 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1145 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1146 #ifdef CONFIG_X86_64
1147 rdmsrl(MSR_FS_BASE, a);
1148 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1149 rdmsrl(MSR_GS_BASE, a);
1150 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1151 #else
1152 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1153 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1154 #endif
1155
1156 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1157
1158 get_idt(&dt);
1159 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1160
1161
1162 vmcs_writel(HOST_RIP, (unsigned long)kvm_vmx_return); /* 22.2.5 */
1163
1164 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1165 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1166 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1167 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1168 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1169 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1170
1171 for (i = 0; i < NR_VMX_MSR; ++i) {
1172 u32 index = vmx_msr_index[i];
1173 u32 data_low, data_high;
1174 u64 data;
1175 int j = vcpu->nmsrs;
1176
1177 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1178 continue;
1179 if (wrmsr_safe(index, data_low, data_high) < 0)
1180 continue;
1181 data = data_low | ((u64)data_high << 32);
1182 vcpu->host_msrs[j].index = index;
1183 vcpu->host_msrs[j].reserved = 0;
1184 vcpu->host_msrs[j].data = data;
1185 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
1186 #ifdef CONFIG_X86_64
1187 if (index == MSR_KERNEL_GS_BASE)
1188 msr_offset_kernel_gs_base = j;
1189 #endif
1190 ++vcpu->nmsrs;
1191 }
1192
1193 setup_msrs(vcpu);
1194
1195 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS, VM_EXIT_CONTROLS,
1196 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
1197
1198 /* 22.2.1, 20.8.1 */
1199 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS,
1200 VM_ENTRY_CONTROLS, 0);
1201 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1202
1203 #ifdef CONFIG_X86_64
1204 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1205 vmcs_writel(TPR_THRESHOLD, 0);
1206 #endif
1207
1208 vmcs_writel(CR0_GUEST_HOST_MASK, KVM_GUEST_CR0_MASK);
1209 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1210
1211 vcpu->cr0 = 0x60000010;
1212 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1213 vmx_set_cr4(vcpu, 0);
1214 #ifdef CONFIG_X86_64
1215 vmx_set_efer(vcpu, 0);
1216 #endif
1217
1218 return 0;
1219
1220 out:
1221 return ret;
1222 }
1223
1224 static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1225 {
1226 u16 ent[2];
1227 u16 cs;
1228 u16 ip;
1229 unsigned long flags;
1230 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1231 u16 sp = vmcs_readl(GUEST_RSP);
1232 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1233
1234 if (sp > ss_limit || sp < 6 ) {
1235 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1236 __FUNCTION__,
1237 vmcs_readl(GUEST_RSP),
1238 vmcs_readl(GUEST_SS_BASE),
1239 vmcs_read32(GUEST_SS_LIMIT));
1240 return;
1241 }
1242
1243 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1244 sizeof(ent)) {
1245 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1246 return;
1247 }
1248
1249 flags = vmcs_readl(GUEST_RFLAGS);
1250 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1251 ip = vmcs_readl(GUEST_RIP);
1252
1253
1254 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1255 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1256 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1257 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1258 return;
1259 }
1260
1261 vmcs_writel(GUEST_RFLAGS, flags &
1262 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1263 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1264 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1265 vmcs_writel(GUEST_RIP, ent[0]);
1266 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1267 }
1268
1269 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1270 {
1271 int word_index = __ffs(vcpu->irq_summary);
1272 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1273 int irq = word_index * BITS_PER_LONG + bit_index;
1274
1275 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1276 if (!vcpu->irq_pending[word_index])
1277 clear_bit(word_index, &vcpu->irq_summary);
1278
1279 if (vcpu->rmode.active) {
1280 inject_rmode_irq(vcpu, irq);
1281 return;
1282 }
1283 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1284 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1285 }
1286
1287
1288 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1289 struct kvm_run *kvm_run)
1290 {
1291 u32 cpu_based_vm_exec_control;
1292
1293 vcpu->interrupt_window_open =
1294 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1295 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1296
1297 if (vcpu->interrupt_window_open &&
1298 vcpu->irq_summary &&
1299 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1300 /*
1301 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1302 */
1303 kvm_do_inject_irq(vcpu);
1304
1305 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1306 if (!vcpu->interrupt_window_open &&
1307 (vcpu->irq_summary || kvm_run->request_interrupt_window))
1308 /*
1309 * Interrupts blocked. Wait for unblock.
1310 */
1311 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1312 else
1313 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1314 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1315 }
1316
1317 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1318 {
1319 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1320
1321 set_debugreg(dbg->bp[0], 0);
1322 set_debugreg(dbg->bp[1], 1);
1323 set_debugreg(dbg->bp[2], 2);
1324 set_debugreg(dbg->bp[3], 3);
1325
1326 if (dbg->singlestep) {
1327 unsigned long flags;
1328
1329 flags = vmcs_readl(GUEST_RFLAGS);
1330 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1331 vmcs_writel(GUEST_RFLAGS, flags);
1332 }
1333 }
1334
1335 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1336 int vec, u32 err_code)
1337 {
1338 if (!vcpu->rmode.active)
1339 return 0;
1340
1341 if (vec == GP_VECTOR && err_code == 0)
1342 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1343 return 1;
1344 return 0;
1345 }
1346
1347 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1348 {
1349 u32 intr_info, error_code;
1350 unsigned long cr2, rip;
1351 u32 vect_info;
1352 enum emulation_result er;
1353 int r;
1354
1355 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1356 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1357
1358 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1359 !is_page_fault(intr_info)) {
1360 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1361 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1362 }
1363
1364 if (is_external_interrupt(vect_info)) {
1365 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1366 set_bit(irq, vcpu->irq_pending);
1367 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1368 }
1369
1370 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1371 asm ("int $2");
1372 return 1;
1373 }
1374 error_code = 0;
1375 rip = vmcs_readl(GUEST_RIP);
1376 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1377 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1378 if (is_page_fault(intr_info)) {
1379 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1380
1381 spin_lock(&vcpu->kvm->lock);
1382 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1383 if (r < 0) {
1384 spin_unlock(&vcpu->kvm->lock);
1385 return r;
1386 }
1387 if (!r) {
1388 spin_unlock(&vcpu->kvm->lock);
1389 return 1;
1390 }
1391
1392 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1393 spin_unlock(&vcpu->kvm->lock);
1394
1395 switch (er) {
1396 case EMULATE_DONE:
1397 return 1;
1398 case EMULATE_DO_MMIO:
1399 ++kvm_stat.mmio_exits;
1400 kvm_run->exit_reason = KVM_EXIT_MMIO;
1401 return 0;
1402 case EMULATE_FAIL:
1403 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1404 break;
1405 default:
1406 BUG();
1407 }
1408 }
1409
1410 if (vcpu->rmode.active &&
1411 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1412 error_code))
1413 return 1;
1414
1415 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1416 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1417 return 0;
1418 }
1419 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1420 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1421 kvm_run->ex.error_code = error_code;
1422 return 0;
1423 }
1424
1425 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1426 struct kvm_run *kvm_run)
1427 {
1428 ++kvm_stat.irq_exits;
1429 return 1;
1430 }
1431
1432 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1433 {
1434 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1435 return 0;
1436 }
1437
1438 static int get_io_count(struct kvm_vcpu *vcpu, unsigned long *count)
1439 {
1440 u64 inst;
1441 gva_t rip;
1442 int countr_size;
1443 int i, n;
1444
1445 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1446 countr_size = 2;
1447 } else {
1448 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1449
1450 countr_size = (cs_ar & AR_L_MASK) ? 8:
1451 (cs_ar & AR_DB_MASK) ? 4: 2;
1452 }
1453
1454 rip = vmcs_readl(GUEST_RIP);
1455 if (countr_size != 8)
1456 rip += vmcs_readl(GUEST_CS_BASE);
1457
1458 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1459
1460 for (i = 0; i < n; i++) {
1461 switch (((u8*)&inst)[i]) {
1462 case 0xf0:
1463 case 0xf2:
1464 case 0xf3:
1465 case 0x2e:
1466 case 0x36:
1467 case 0x3e:
1468 case 0x26:
1469 case 0x64:
1470 case 0x65:
1471 case 0x66:
1472 break;
1473 case 0x67:
1474 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1475 default:
1476 goto done;
1477 }
1478 }
1479 return 0;
1480 done:
1481 countr_size *= 8;
1482 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
1483 //printk("cx: %lx\n", vcpu->regs[VCPU_REGS_RCX]);
1484 return 1;
1485 }
1486
1487 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1488 {
1489 u64 exit_qualification;
1490 int size, down, in, string, rep;
1491 unsigned port;
1492 unsigned long count;
1493 gva_t address;
1494
1495 ++kvm_stat.io_exits;
1496 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1497 in = (exit_qualification & 8) != 0;
1498 size = (exit_qualification & 7) + 1;
1499 string = (exit_qualification & 16) != 0;
1500 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1501 count = 1;
1502 rep = (exit_qualification & 32) != 0;
1503 port = exit_qualification >> 16;
1504 address = 0;
1505 if (string) {
1506 if (rep && !get_io_count(vcpu, &count))
1507 return 1;
1508 address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1509 }
1510 return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down,
1511 address, rep, port);
1512 }
1513
1514 static void
1515 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1516 {
1517 /*
1518 * Patch in the VMCALL instruction:
1519 */
1520 hypercall[0] = 0x0f;
1521 hypercall[1] = 0x01;
1522 hypercall[2] = 0xc1;
1523 hypercall[3] = 0xc3;
1524 }
1525
1526 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1527 {
1528 u64 exit_qualification;
1529 int cr;
1530 int reg;
1531
1532 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1533 cr = exit_qualification & 15;
1534 reg = (exit_qualification >> 8) & 15;
1535 switch ((exit_qualification >> 4) & 3) {
1536 case 0: /* mov to cr */
1537 switch (cr) {
1538 case 0:
1539 vcpu_load_rsp_rip(vcpu);
1540 set_cr0(vcpu, vcpu->regs[reg]);
1541 skip_emulated_instruction(vcpu);
1542 return 1;
1543 case 3:
1544 vcpu_load_rsp_rip(vcpu);
1545 set_cr3(vcpu, vcpu->regs[reg]);
1546 skip_emulated_instruction(vcpu);
1547 return 1;
1548 case 4:
1549 vcpu_load_rsp_rip(vcpu);
1550 set_cr4(vcpu, vcpu->regs[reg]);
1551 skip_emulated_instruction(vcpu);
1552 return 1;
1553 case 8:
1554 vcpu_load_rsp_rip(vcpu);
1555 set_cr8(vcpu, vcpu->regs[reg]);
1556 skip_emulated_instruction(vcpu);
1557 return 1;
1558 };
1559 break;
1560 case 1: /*mov from cr*/
1561 switch (cr) {
1562 case 3:
1563 vcpu_load_rsp_rip(vcpu);
1564 vcpu->regs[reg] = vcpu->cr3;
1565 vcpu_put_rsp_rip(vcpu);
1566 skip_emulated_instruction(vcpu);
1567 return 1;
1568 case 8:
1569 printk(KERN_DEBUG "handle_cr: read CR8 "
1570 "cpu erratum AA15\n");
1571 vcpu_load_rsp_rip(vcpu);
1572 vcpu->regs[reg] = vcpu->cr8;
1573 vcpu_put_rsp_rip(vcpu);
1574 skip_emulated_instruction(vcpu);
1575 return 1;
1576 }
1577 break;
1578 case 3: /* lmsw */
1579 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1580
1581 skip_emulated_instruction(vcpu);
1582 return 1;
1583 default:
1584 break;
1585 }
1586 kvm_run->exit_reason = 0;
1587 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1588 (int)(exit_qualification >> 4) & 3, cr);
1589 return 0;
1590 }
1591
1592 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1593 {
1594 u64 exit_qualification;
1595 unsigned long val;
1596 int dr, reg;
1597
1598 /*
1599 * FIXME: this code assumes the host is debugging the guest.
1600 * need to deal with guest debugging itself too.
1601 */
1602 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1603 dr = exit_qualification & 7;
1604 reg = (exit_qualification >> 8) & 15;
1605 vcpu_load_rsp_rip(vcpu);
1606 if (exit_qualification & 16) {
1607 /* mov from dr */
1608 switch (dr) {
1609 case 6:
1610 val = 0xffff0ff0;
1611 break;
1612 case 7:
1613 val = 0x400;
1614 break;
1615 default:
1616 val = 0;
1617 }
1618 vcpu->regs[reg] = val;
1619 } else {
1620 /* mov to dr */
1621 }
1622 vcpu_put_rsp_rip(vcpu);
1623 skip_emulated_instruction(vcpu);
1624 return 1;
1625 }
1626
1627 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1628 {
1629 kvm_emulate_cpuid(vcpu);
1630 return 1;
1631 }
1632
1633 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1634 {
1635 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1636 u64 data;
1637
1638 if (vmx_get_msr(vcpu, ecx, &data)) {
1639 vmx_inject_gp(vcpu, 0);
1640 return 1;
1641 }
1642
1643 /* FIXME: handling of bits 32:63 of rax, rdx */
1644 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1645 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1646 skip_emulated_instruction(vcpu);
1647 return 1;
1648 }
1649
1650 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1651 {
1652 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1653 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1654 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1655
1656 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1657 vmx_inject_gp(vcpu, 0);
1658 return 1;
1659 }
1660
1661 skip_emulated_instruction(vcpu);
1662 return 1;
1663 }
1664
1665 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1666 struct kvm_run *kvm_run)
1667 {
1668 kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0;
1669 kvm_run->cr8 = vcpu->cr8;
1670 kvm_run->apic_base = vcpu->apic_base;
1671 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1672 vcpu->irq_summary == 0);
1673 }
1674
1675 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1676 struct kvm_run *kvm_run)
1677 {
1678 /*
1679 * If the user space waits to inject interrupts, exit as soon as
1680 * possible
1681 */
1682 if (kvm_run->request_interrupt_window &&
1683 !vcpu->irq_summary) {
1684 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1685 ++kvm_stat.irq_window_exits;
1686 return 0;
1687 }
1688 return 1;
1689 }
1690
1691 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1692 {
1693 skip_emulated_instruction(vcpu);
1694 if (vcpu->irq_summary)
1695 return 1;
1696
1697 kvm_run->exit_reason = KVM_EXIT_HLT;
1698 ++kvm_stat.halt_exits;
1699 return 0;
1700 }
1701
1702 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1703 {
1704 skip_emulated_instruction(vcpu);
1705 return kvm_hypercall(vcpu, kvm_run);
1706 }
1707
1708 /*
1709 * The exit handlers return 1 if the exit was handled fully and guest execution
1710 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1711 * to be done to userspace and return 0.
1712 */
1713 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1714 struct kvm_run *kvm_run) = {
1715 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1716 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
1717 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
1718 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
1719 [EXIT_REASON_CR_ACCESS] = handle_cr,
1720 [EXIT_REASON_DR_ACCESS] = handle_dr,
1721 [EXIT_REASON_CPUID] = handle_cpuid,
1722 [EXIT_REASON_MSR_READ] = handle_rdmsr,
1723 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
1724 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
1725 [EXIT_REASON_HLT] = handle_halt,
1726 [EXIT_REASON_VMCALL] = handle_vmcall,
1727 };
1728
1729 static const int kvm_vmx_max_exit_handlers =
1730 sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers);
1731
1732 /*
1733 * The guest has exited. See if we can fix it or if we need userspace
1734 * assistance.
1735 */
1736 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1737 {
1738 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1739 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1740
1741 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1742 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1743 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1744 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
1745 kvm_run->instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1746 if (exit_reason < kvm_vmx_max_exit_handlers
1747 && kvm_vmx_exit_handlers[exit_reason])
1748 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1749 else {
1750 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1751 kvm_run->hw.hardware_exit_reason = exit_reason;
1752 }
1753 return 0;
1754 }
1755
1756 /*
1757 * Check if userspace requested an interrupt window, and that the
1758 * interrupt window is open.
1759 *
1760 * No need to exit to userspace if we already have an interrupt queued.
1761 */
1762 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1763 struct kvm_run *kvm_run)
1764 {
1765 return (!vcpu->irq_summary &&
1766 kvm_run->request_interrupt_window &&
1767 vcpu->interrupt_window_open &&
1768 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
1769 }
1770
1771 static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1772 {
1773 u8 fail;
1774 u16 fs_sel, gs_sel, ldt_sel;
1775 int fs_gs_ldt_reload_needed;
1776 int r;
1777
1778 again:
1779 /*
1780 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1781 * allow segment selectors with cpl > 0 or ti == 1.
1782 */
1783 fs_sel = read_fs();
1784 gs_sel = read_gs();
1785 ldt_sel = read_ldt();
1786 fs_gs_ldt_reload_needed = (fs_sel & 7) | (gs_sel & 7) | ldt_sel;
1787 if (!fs_gs_ldt_reload_needed) {
1788 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1789 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1790 } else {
1791 vmcs_write16(HOST_FS_SELECTOR, 0);
1792 vmcs_write16(HOST_GS_SELECTOR, 0);
1793 }
1794
1795 #ifdef CONFIG_X86_64
1796 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1797 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1798 #else
1799 vmcs_writel(HOST_FS_BASE, segment_base(fs_sel));
1800 vmcs_writel(HOST_GS_BASE, segment_base(gs_sel));
1801 #endif
1802
1803 if (!vcpu->mmio_read_completed)
1804 do_interrupt_requests(vcpu, kvm_run);
1805
1806 if (vcpu->guest_debug.enabled)
1807 kvm_guest_debug_pre(vcpu);
1808
1809 fx_save(vcpu->host_fx_image);
1810 fx_restore(vcpu->guest_fx_image);
1811
1812 #ifdef CONFIG_X86_64
1813 if (is_long_mode(vcpu)) {
1814 save_msrs(vcpu->host_msrs + msr_offset_kernel_gs_base, 1);
1815 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1816 }
1817 #endif
1818
1819 asm (
1820 /* Store host registers */
1821 "pushf \n\t"
1822 #ifdef CONFIG_X86_64
1823 "push %%rax; push %%rbx; push %%rdx;"
1824 "push %%rsi; push %%rdi; push %%rbp;"
1825 "push %%r8; push %%r9; push %%r10; push %%r11;"
1826 "push %%r12; push %%r13; push %%r14; push %%r15;"
1827 "push %%rcx \n\t"
1828 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1829 #else
1830 "pusha; push %%ecx \n\t"
1831 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1832 #endif
1833 /* Check if vmlaunch of vmresume is needed */
1834 "cmp $0, %1 \n\t"
1835 /* Load guest registers. Don't clobber flags. */
1836 #ifdef CONFIG_X86_64
1837 "mov %c[cr2](%3), %%rax \n\t"
1838 "mov %%rax, %%cr2 \n\t"
1839 "mov %c[rax](%3), %%rax \n\t"
1840 "mov %c[rbx](%3), %%rbx \n\t"
1841 "mov %c[rdx](%3), %%rdx \n\t"
1842 "mov %c[rsi](%3), %%rsi \n\t"
1843 "mov %c[rdi](%3), %%rdi \n\t"
1844 "mov %c[rbp](%3), %%rbp \n\t"
1845 "mov %c[r8](%3), %%r8 \n\t"
1846 "mov %c[r9](%3), %%r9 \n\t"
1847 "mov %c[r10](%3), %%r10 \n\t"
1848 "mov %c[r11](%3), %%r11 \n\t"
1849 "mov %c[r12](%3), %%r12 \n\t"
1850 "mov %c[r13](%3), %%r13 \n\t"
1851 "mov %c[r14](%3), %%r14 \n\t"
1852 "mov %c[r15](%3), %%r15 \n\t"
1853 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
1854 #else
1855 "mov %c[cr2](%3), %%eax \n\t"
1856 "mov %%eax, %%cr2 \n\t"
1857 "mov %c[rax](%3), %%eax \n\t"
1858 "mov %c[rbx](%3), %%ebx \n\t"
1859 "mov %c[rdx](%3), %%edx \n\t"
1860 "mov %c[rsi](%3), %%esi \n\t"
1861 "mov %c[rdi](%3), %%edi \n\t"
1862 "mov %c[rbp](%3), %%ebp \n\t"
1863 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
1864 #endif
1865 /* Enter guest mode */
1866 "jne launched \n\t"
1867 ASM_VMX_VMLAUNCH "\n\t"
1868 "jmp kvm_vmx_return \n\t"
1869 "launched: " ASM_VMX_VMRESUME "\n\t"
1870 ".globl kvm_vmx_return \n\t"
1871 "kvm_vmx_return: "
1872 /* Save guest registers, load host registers, keep flags */
1873 #ifdef CONFIG_X86_64
1874 "xchg %3, (%%rsp) \n\t"
1875 "mov %%rax, %c[rax](%3) \n\t"
1876 "mov %%rbx, %c[rbx](%3) \n\t"
1877 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
1878 "mov %%rdx, %c[rdx](%3) \n\t"
1879 "mov %%rsi, %c[rsi](%3) \n\t"
1880 "mov %%rdi, %c[rdi](%3) \n\t"
1881 "mov %%rbp, %c[rbp](%3) \n\t"
1882 "mov %%r8, %c[r8](%3) \n\t"
1883 "mov %%r9, %c[r9](%3) \n\t"
1884 "mov %%r10, %c[r10](%3) \n\t"
1885 "mov %%r11, %c[r11](%3) \n\t"
1886 "mov %%r12, %c[r12](%3) \n\t"
1887 "mov %%r13, %c[r13](%3) \n\t"
1888 "mov %%r14, %c[r14](%3) \n\t"
1889 "mov %%r15, %c[r15](%3) \n\t"
1890 "mov %%cr2, %%rax \n\t"
1891 "mov %%rax, %c[cr2](%3) \n\t"
1892 "mov (%%rsp), %3 \n\t"
1893
1894 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1895 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1896 "pop %%rbp; pop %%rdi; pop %%rsi;"
1897 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
1898 #else
1899 "xchg %3, (%%esp) \n\t"
1900 "mov %%eax, %c[rax](%3) \n\t"
1901 "mov %%ebx, %c[rbx](%3) \n\t"
1902 "pushl (%%esp); popl %c[rcx](%3) \n\t"
1903 "mov %%edx, %c[rdx](%3) \n\t"
1904 "mov %%esi, %c[rsi](%3) \n\t"
1905 "mov %%edi, %c[rdi](%3) \n\t"
1906 "mov %%ebp, %c[rbp](%3) \n\t"
1907 "mov %%cr2, %%eax \n\t"
1908 "mov %%eax, %c[cr2](%3) \n\t"
1909 "mov (%%esp), %3 \n\t"
1910
1911 "pop %%ecx; popa \n\t"
1912 #endif
1913 "setbe %0 \n\t"
1914 "popf \n\t"
1915 : "=q" (fail)
1916 : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
1917 "c"(vcpu),
1918 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
1919 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1920 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1921 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1922 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1923 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1924 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
1925 #ifdef CONFIG_X86_64
1926 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1927 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1928 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1929 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1930 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1931 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1932 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1933 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
1934 #endif
1935 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
1936 : "cc", "memory" );
1937
1938 /*
1939 * Reload segment selectors ASAP. (it's needed for a functional
1940 * kernel: x86 relies on having __KERNEL_PDA in %fs and x86_64
1941 * relies on having 0 in %gs for the CPU PDA to work.)
1942 */
1943 if (fs_gs_ldt_reload_needed) {
1944 load_ldt(ldt_sel);
1945 load_fs(fs_sel);
1946 /*
1947 * If we have to reload gs, we must take care to
1948 * preserve our gs base.
1949 */
1950 local_irq_disable();
1951 load_gs(gs_sel);
1952 #ifdef CONFIG_X86_64
1953 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
1954 #endif
1955 local_irq_enable();
1956
1957 reload_tss();
1958 }
1959 ++kvm_stat.exits;
1960
1961 #ifdef CONFIG_X86_64
1962 if (is_long_mode(vcpu)) {
1963 save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1964 load_msrs(vcpu->host_msrs, NR_BAD_MSRS);
1965 }
1966 #endif
1967
1968 fx_save(vcpu->guest_fx_image);
1969 fx_restore(vcpu->host_fx_image);
1970 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
1971
1972 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
1973
1974 if (fail) {
1975 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1976 kvm_run->fail_entry.hardware_entry_failure_reason
1977 = vmcs_read32(VM_INSTRUCTION_ERROR);
1978 r = 0;
1979 } else {
1980 /*
1981 * Profile KVM exit RIPs:
1982 */
1983 if (unlikely(prof_on == KVM_PROFILING))
1984 profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP));
1985
1986 vcpu->launched = 1;
1987 r = kvm_handle_exit(kvm_run, vcpu);
1988 if (r > 0) {
1989 /* Give scheduler a change to reschedule. */
1990 if (signal_pending(current)) {
1991 ++kvm_stat.signal_exits;
1992 post_kvm_run_save(vcpu, kvm_run);
1993 kvm_run->exit_reason = KVM_EXIT_INTR;
1994 return -EINTR;
1995 }
1996
1997 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
1998 ++kvm_stat.request_irq_exits;
1999 post_kvm_run_save(vcpu, kvm_run);
2000 kvm_run->exit_reason = KVM_EXIT_INTR;
2001 return -EINTR;
2002 }
2003
2004 kvm_resched(vcpu);
2005 goto again;
2006 }
2007 }
2008
2009 post_kvm_run_save(vcpu, kvm_run);
2010 return r;
2011 }
2012
2013 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2014 {
2015 vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3));
2016 }
2017
2018 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2019 unsigned long addr,
2020 u32 err_code)
2021 {
2022 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2023
2024 ++kvm_stat.pf_guest;
2025
2026 if (is_page_fault(vect_info)) {
2027 printk(KERN_DEBUG "inject_page_fault: "
2028 "double fault 0x%lx @ 0x%lx\n",
2029 addr, vmcs_readl(GUEST_RIP));
2030 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2031 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2032 DF_VECTOR |
2033 INTR_TYPE_EXCEPTION |
2034 INTR_INFO_DELIEVER_CODE_MASK |
2035 INTR_INFO_VALID_MASK);
2036 return;
2037 }
2038 vcpu->cr2 = addr;
2039 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2040 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2041 PF_VECTOR |
2042 INTR_TYPE_EXCEPTION |
2043 INTR_INFO_DELIEVER_CODE_MASK |
2044 INTR_INFO_VALID_MASK);
2045
2046 }
2047
2048 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2049 {
2050 if (vcpu->vmcs) {
2051 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
2052 free_vmcs(vcpu->vmcs);
2053 vcpu->vmcs = NULL;
2054 }
2055 }
2056
2057 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2058 {
2059 vmx_free_vmcs(vcpu);
2060 }
2061
2062 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
2063 {
2064 struct vmcs *vmcs;
2065
2066 vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2067 if (!vcpu->guest_msrs)
2068 return -ENOMEM;
2069
2070 vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2071 if (!vcpu->host_msrs)
2072 goto out_free_guest_msrs;
2073
2074 vmcs = alloc_vmcs();
2075 if (!vmcs)
2076 goto out_free_msrs;
2077
2078 vmcs_clear(vmcs);
2079 vcpu->vmcs = vmcs;
2080 vcpu->launched = 0;
2081
2082 return 0;
2083
2084 out_free_msrs:
2085 kfree(vcpu->host_msrs);
2086 vcpu->host_msrs = NULL;
2087
2088 out_free_guest_msrs:
2089 kfree(vcpu->guest_msrs);
2090 vcpu->guest_msrs = NULL;
2091
2092 return -ENOMEM;
2093 }
2094
2095 static struct kvm_arch_ops vmx_arch_ops = {
2096 .cpu_has_kvm_support = cpu_has_kvm_support,
2097 .disabled_by_bios = vmx_disabled_by_bios,
2098 .hardware_setup = hardware_setup,
2099 .hardware_unsetup = hardware_unsetup,
2100 .hardware_enable = hardware_enable,
2101 .hardware_disable = hardware_disable,
2102
2103 .vcpu_create = vmx_create_vcpu,
2104 .vcpu_free = vmx_free_vcpu,
2105
2106 .vcpu_load = vmx_vcpu_load,
2107 .vcpu_put = vmx_vcpu_put,
2108 .vcpu_decache = vmx_vcpu_decache,
2109
2110 .set_guest_debug = set_guest_debug,
2111 .get_msr = vmx_get_msr,
2112 .set_msr = vmx_set_msr,
2113 .get_segment_base = vmx_get_segment_base,
2114 .get_segment = vmx_get_segment,
2115 .set_segment = vmx_set_segment,
2116 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2117 .decache_cr0_cr4_guest_bits = vmx_decache_cr0_cr4_guest_bits,
2118 .set_cr0 = vmx_set_cr0,
2119 .set_cr3 = vmx_set_cr3,
2120 .set_cr4 = vmx_set_cr4,
2121 #ifdef CONFIG_X86_64
2122 .set_efer = vmx_set_efer,
2123 #endif
2124 .get_idt = vmx_get_idt,
2125 .set_idt = vmx_set_idt,
2126 .get_gdt = vmx_get_gdt,
2127 .set_gdt = vmx_set_gdt,
2128 .cache_regs = vcpu_load_rsp_rip,
2129 .decache_regs = vcpu_put_rsp_rip,
2130 .get_rflags = vmx_get_rflags,
2131 .set_rflags = vmx_set_rflags,
2132
2133 .tlb_flush = vmx_flush_tlb,
2134 .inject_page_fault = vmx_inject_page_fault,
2135
2136 .inject_gp = vmx_inject_gp,
2137
2138 .run = vmx_vcpu_run,
2139 .skip_emulated_instruction = skip_emulated_instruction,
2140 .vcpu_setup = vmx_vcpu_setup,
2141 .patch_hypercall = vmx_patch_hypercall,
2142 };
2143
2144 static int __init vmx_init(void)
2145 {
2146 return kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
2147 }
2148
2149 static void __exit vmx_exit(void)
2150 {
2151 kvm_exit_arch();
2152 }
2153
2154 module_init(vmx_init)
2155 module_exit(vmx_exit)
Linux kernel - Deliverables
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