2 * Sony CXD2820R demodulator driver
4 * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "cxd2820r_priv.h"
25 module_param_named(debug
, cxd2820r_debug
, int, 0644);
26 MODULE_PARM_DESC(debug
, "Turn on/off frontend debugging (default:off).");
28 /* write multiple registers */
29 static int cxd2820r_wr_regs_i2c(struct cxd2820r_priv
*priv
, u8 i2c
, u8 reg
,
34 struct i2c_msg msg
[1] = {
44 memcpy(&buf
[1], val
, len
);
46 ret
= i2c_transfer(priv
->i2c
, msg
, 1);
50 warn("i2c wr failed ret:%d reg:%02x len:%d", ret
, reg
, len
);
56 /* read multiple registers */
57 static int cxd2820r_rd_regs_i2c(struct cxd2820r_priv
*priv
, u8 i2c
, u8 reg
,
62 struct i2c_msg msg
[2] = {
76 ret
= i2c_transfer(priv
->i2c
, msg
, 2);
78 memcpy(val
, buf
, len
);
81 warn("i2c rd failed ret:%d reg:%02x len:%d", ret
, reg
, len
);
88 /* write multiple registers */
89 int cxd2820r_wr_regs(struct cxd2820r_priv
*priv
, u32 reginfo
, u8
*val
,
94 u8 reg
= (reginfo
>> 0) & 0xff;
95 u8 bank
= (reginfo
>> 8) & 0xff;
96 u8 i2c
= (reginfo
>> 16) & 0x01;
100 i2c_addr
= priv
->cfg
.i2c_address
| (1 << 1); /* DVB-C */
102 i2c_addr
= priv
->cfg
.i2c_address
; /* DVB-T/T2 */
104 /* switch bank if needed */
105 if (bank
!= priv
->bank
[i2c
]) {
106 ret
= cxd2820r_wr_regs_i2c(priv
, i2c_addr
, 0x00, &bank
, 1);
109 priv
->bank
[i2c
] = bank
;
111 return cxd2820r_wr_regs_i2c(priv
, i2c_addr
, reg
, val
, len
);
114 /* read multiple registers */
115 int cxd2820r_rd_regs(struct cxd2820r_priv
*priv
, u32 reginfo
, u8
*val
,
120 u8 reg
= (reginfo
>> 0) & 0xff;
121 u8 bank
= (reginfo
>> 8) & 0xff;
122 u8 i2c
= (reginfo
>> 16) & 0x01;
126 i2c_addr
= priv
->cfg
.i2c_address
| (1 << 1); /* DVB-C */
128 i2c_addr
= priv
->cfg
.i2c_address
; /* DVB-T/T2 */
130 /* switch bank if needed */
131 if (bank
!= priv
->bank
[i2c
]) {
132 ret
= cxd2820r_wr_regs_i2c(priv
, i2c_addr
, 0x00, &bank
, 1);
135 priv
->bank
[i2c
] = bank
;
137 return cxd2820r_rd_regs_i2c(priv
, i2c_addr
, reg
, val
, len
);
140 /* write single register */
141 int cxd2820r_wr_reg(struct cxd2820r_priv
*priv
, u32 reg
, u8 val
)
143 return cxd2820r_wr_regs(priv
, reg
, &val
, 1);
146 /* read single register */
147 int cxd2820r_rd_reg(struct cxd2820r_priv
*priv
, u32 reg
, u8
*val
)
149 return cxd2820r_rd_regs(priv
, reg
, val
, 1);
152 /* write single register with mask */
153 int cxd2820r_wr_reg_mask(struct cxd2820r_priv
*priv
, u32 reg
, u8 val
,
159 /* no need for read if whole reg is written */
161 ret
= cxd2820r_rd_reg(priv
, reg
, &tmp
);
170 return cxd2820r_wr_reg(priv
, reg
, val
);
173 int cxd2820r_gpio(struct dvb_frontend
*fe
)
175 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
177 u8
*gpio
, tmp0
, tmp1
;
178 dbg("%s: delsys=%d", __func__
, fe
->dtv_property_cache
.delivery_system
);
180 switch (fe
->dtv_property_cache
.delivery_system
) {
182 gpio
= priv
->cfg
.gpio_dvbt
;
185 gpio
= priv
->cfg
.gpio_dvbt2
;
187 case SYS_DVBC_ANNEX_AC
:
188 gpio
= priv
->cfg
.gpio_dvbc
;
195 /* update GPIOs only when needed */
196 if (!memcmp(gpio
, priv
->gpio
, sizeof(priv
->gpio
)))
201 for (i
= 0; i
< sizeof(priv
->gpio
); i
++) {
202 /* enable / disable */
203 if (gpio
[i
] & CXD2820R_GPIO_E
)
204 tmp0
|= (2 << 6) >> (2 * i
);
206 tmp0
|= (1 << 6) >> (2 * i
);
209 if (gpio
[i
] & CXD2820R_GPIO_I
)
210 tmp1
|= (1 << (3 + i
));
212 tmp1
|= (0 << (3 + i
));
215 if (gpio
[i
] & CXD2820R_GPIO_H
)
216 tmp1
|= (1 << (0 + i
));
218 tmp1
|= (0 << (0 + i
));
220 dbg("%s: GPIO i=%d %02x %02x", __func__
, i
, tmp0
, tmp1
);
223 dbg("%s: wr gpio=%02x %02x", __func__
, tmp0
, tmp1
);
225 /* write bits [7:2] */
226 ret
= cxd2820r_wr_reg_mask(priv
, 0x00089, tmp0
, 0xfc);
230 /* write bits [5:0] */
231 ret
= cxd2820r_wr_reg_mask(priv
, 0x0008e, tmp1
, 0x3f);
235 memcpy(priv
->gpio
, gpio
, sizeof(priv
->gpio
));
239 dbg("%s: failed:%d", __func__
, ret
);
243 /* 64 bit div with round closest, like DIV_ROUND_CLOSEST but 64 bit */
244 u32
cxd2820r_div_u64_round_closest(u64 dividend
, u32 divisor
)
246 return div_u64(dividend
+ (divisor
/ 2), divisor
);
249 static int cxd2820r_set_frontend(struct dvb_frontend
*fe
)
251 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
254 dbg("%s: delsys=%d", __func__
, fe
->dtv_property_cache
.delivery_system
);
255 switch (c
->delivery_system
) {
257 ret
= cxd2820r_init_t(fe
);
260 ret
= cxd2820r_set_frontend_t(fe
);
265 ret
= cxd2820r_init_t(fe
);
268 ret
= cxd2820r_set_frontend_t2(fe
);
272 case SYS_DVBC_ANNEX_A
:
273 ret
= cxd2820r_init_c(fe
);
276 ret
= cxd2820r_set_frontend_c(fe
);
281 dbg("%s: error state=%d", __func__
, fe
->dtv_property_cache
.delivery_system
);
288 static int cxd2820r_read_status(struct dvb_frontend
*fe
, fe_status_t
*status
)
292 dbg("%s: delsys=%d", __func__
, fe
->dtv_property_cache
.delivery_system
);
293 switch (fe
->dtv_property_cache
.delivery_system
) {
295 ret
= cxd2820r_read_status_t(fe
, status
);
298 ret
= cxd2820r_read_status_t2(fe
, status
);
300 case SYS_DVBC_ANNEX_A
:
301 ret
= cxd2820r_read_status_c(fe
, status
);
310 static int cxd2820r_get_frontend(struct dvb_frontend
*fe
)
314 dbg("%s: delsys=%d", __func__
, fe
->dtv_property_cache
.delivery_system
);
315 switch (fe
->dtv_property_cache
.delivery_system
) {
317 ret
= cxd2820r_get_frontend_t(fe
);
320 ret
= cxd2820r_get_frontend_t2(fe
);
322 case SYS_DVBC_ANNEX_A
:
323 ret
= cxd2820r_get_frontend_c(fe
);
332 static int cxd2820r_read_ber(struct dvb_frontend
*fe
, u32
*ber
)
336 dbg("%s: delsys=%d", __func__
, fe
->dtv_property_cache
.delivery_system
);
337 switch (fe
->dtv_property_cache
.delivery_system
) {
339 ret
= cxd2820r_read_ber_t(fe
, ber
);
342 ret
= cxd2820r_read_ber_t2(fe
, ber
);
344 case SYS_DVBC_ANNEX_A
:
345 ret
= cxd2820r_read_ber_c(fe
, ber
);
354 static int cxd2820r_read_signal_strength(struct dvb_frontend
*fe
, u16
*strength
)
358 dbg("%s: delsys=%d", __func__
, fe
->dtv_property_cache
.delivery_system
);
359 switch (fe
->dtv_property_cache
.delivery_system
) {
361 ret
= cxd2820r_read_signal_strength_t(fe
, strength
);
364 ret
= cxd2820r_read_signal_strength_t2(fe
, strength
);
366 case SYS_DVBC_ANNEX_A
:
367 ret
= cxd2820r_read_signal_strength_c(fe
, strength
);
376 static int cxd2820r_read_snr(struct dvb_frontend
*fe
, u16
*snr
)
380 dbg("%s: delsys=%d", __func__
, fe
->dtv_property_cache
.delivery_system
);
381 switch (fe
->dtv_property_cache
.delivery_system
) {
383 ret
= cxd2820r_read_snr_t(fe
, snr
);
386 ret
= cxd2820r_read_snr_t2(fe
, snr
);
388 case SYS_DVBC_ANNEX_A
:
389 ret
= cxd2820r_read_snr_c(fe
, snr
);
398 static int cxd2820r_read_ucblocks(struct dvb_frontend
*fe
, u32
*ucblocks
)
402 dbg("%s: delsys=%d", __func__
, fe
->dtv_property_cache
.delivery_system
);
403 switch (fe
->dtv_property_cache
.delivery_system
) {
405 ret
= cxd2820r_read_ucblocks_t(fe
, ucblocks
);
408 ret
= cxd2820r_read_ucblocks_t2(fe
, ucblocks
);
410 case SYS_DVBC_ANNEX_A
:
411 ret
= cxd2820r_read_ucblocks_c(fe
, ucblocks
);
420 static int cxd2820r_init(struct dvb_frontend
*fe
)
425 static int cxd2820r_sleep(struct dvb_frontend
*fe
)
429 dbg("%s: delsys=%d", __func__
, fe
->dtv_property_cache
.delivery_system
);
430 switch (fe
->dtv_property_cache
.delivery_system
) {
432 ret
= cxd2820r_sleep_t(fe
);
435 ret
= cxd2820r_sleep_t2(fe
);
437 case SYS_DVBC_ANNEX_A
:
438 ret
= cxd2820r_sleep_c(fe
);
447 static int cxd2820r_get_tune_settings(struct dvb_frontend
*fe
,
448 struct dvb_frontend_tune_settings
*s
)
452 dbg("%s: delsys=%d", __func__
, fe
->dtv_property_cache
.delivery_system
);
453 switch (fe
->dtv_property_cache
.delivery_system
) {
455 ret
= cxd2820r_get_tune_settings_t(fe
, s
);
458 ret
= cxd2820r_get_tune_settings_t2(fe
, s
);
460 case SYS_DVBC_ANNEX_A
:
461 ret
= cxd2820r_get_tune_settings_c(fe
, s
);
470 static enum dvbfe_search
cxd2820r_search(struct dvb_frontend
*fe
)
472 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
473 struct dtv_frontend_properties
*c
= &fe
->dtv_property_cache
;
475 fe_status_t status
= 0;
476 dbg("%s: delsys=%d", __func__
, fe
->dtv_property_cache
.delivery_system
);
478 /* switch between DVB-T and DVB-T2 when tune fails */
479 if (priv
->last_tune_failed
&& (priv
->delivery_system
!= SYS_DVBC_ANNEX_A
)) {
480 if (priv
->delivery_system
== SYS_DVBT
)
481 c
->delivery_system
= SYS_DVBT2
;
483 c
->delivery_system
= SYS_DVBT
;
487 ret
= cxd2820r_set_frontend(fe
);
492 /* frontend lock wait loop count */
493 switch (priv
->delivery_system
) {
506 /* wait frontend lock */
508 dbg("%s: LOOP=%d", __func__
, i
);
510 ret
= cxd2820r_read_status(fe
, &status
);
514 if (status
& FE_HAS_SIGNAL
)
518 /* check if we have a valid signal */
520 priv
->last_tune_failed
= 0;
521 return DVBFE_ALGO_SEARCH_SUCCESS
;
523 priv
->last_tune_failed
= 1;
524 return DVBFE_ALGO_SEARCH_AGAIN
;
528 dbg("%s: failed:%d", __func__
, ret
);
529 return DVBFE_ALGO_SEARCH_ERROR
;
532 static int cxd2820r_get_frontend_algo(struct dvb_frontend
*fe
)
534 return DVBFE_ALGO_CUSTOM
;
537 static void cxd2820r_release(struct dvb_frontend
*fe
)
539 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
546 static int cxd2820r_i2c_gate_ctrl(struct dvb_frontend
*fe
, int enable
)
548 struct cxd2820r_priv
*priv
= fe
->demodulator_priv
;
549 dbg("%s: %d", __func__
, enable
);
551 /* Bit 0 of reg 0xdb in bank 0x00 controls I2C repeater */
552 return cxd2820r_wr_reg_mask(priv
, 0xdb, enable
? 1 : 0, 0x1);
555 static const struct dvb_frontend_ops cxd2820r_ops
= {
556 .delsys
= { SYS_DVBT
, SYS_DVBT2
, SYS_DVBC_ANNEX_A
},
558 /* default: DVB-T/T2 */
560 .name
= "Sony CXD2820R (DVB-T/T2)",
563 .caps
= FE_CAN_FEC_1_2
|
574 FE_CAN_TRANSMISSION_MODE_AUTO
|
575 FE_CAN_GUARD_INTERVAL_AUTO
|
576 FE_CAN_HIERARCHY_AUTO
|
581 .release
= cxd2820r_release
,
582 .init
= cxd2820r_init
,
583 .sleep
= cxd2820r_sleep
,
585 .get_tune_settings
= cxd2820r_get_tune_settings
,
586 .i2c_gate_ctrl
= cxd2820r_i2c_gate_ctrl
,
588 .get_frontend
= cxd2820r_get_frontend
,
590 .get_frontend_algo
= cxd2820r_get_frontend_algo
,
591 .search
= cxd2820r_search
,
593 .read_status
= cxd2820r_read_status
,
594 .read_snr
= cxd2820r_read_snr
,
595 .read_ber
= cxd2820r_read_ber
,
596 .read_ucblocks
= cxd2820r_read_ucblocks
,
597 .read_signal_strength
= cxd2820r_read_signal_strength
,
600 struct dvb_frontend
*cxd2820r_attach(const struct cxd2820r_config
*cfg
,
601 struct i2c_adapter
*i2c
,
602 struct dvb_frontend
*fe
)
604 struct cxd2820r_priv
*priv
= NULL
;
608 priv
= kzalloc(sizeof (struct cxd2820r_priv
), GFP_KERNEL
);
613 memcpy(&priv
->cfg
, cfg
, sizeof (struct cxd2820r_config
));
615 priv
->bank
[0] = priv
->bank
[1] = 0xff;
616 ret
= cxd2820r_rd_reg(priv
, 0x000fd, &tmp
);
617 dbg("%s: chip id=%02x", __func__
, tmp
);
618 if (ret
|| tmp
!= 0xe1)
621 memcpy(&priv
->fe
.ops
, &cxd2820r_ops
, sizeof (struct dvb_frontend_ops
));
622 priv
->fe
.demodulator_priv
= priv
;
628 EXPORT_SYMBOL(cxd2820r_attach
);
630 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
631 MODULE_DESCRIPTION("Sony CXD2820R demodulator driver");
632 MODULE_LICENSE("GPL");