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[deliverable/linux.git] / drivers / media / dvb / frontends / ds3000.c
1 /*
2 Montage Technology DS3000/TS2020 - DVBS/S2 Demodulator/Tuner driver
3 Copyright (C) 2009 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
4
5 Copyright (C) 2009 TurboSight.com
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/slab.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/firmware.h>
28
29 #include "dvb_frontend.h"
30 #include "ds3000.h"
31
32 static int debug;
33
34 #define dprintk(args...) \
35 do { \
36 if (debug) \
37 printk(args); \
38 } while (0)
39
40 /* as of March 2009 current DS3000 firmware version is 1.78 */
41 /* DS3000 FW v1.78 MD5: a32d17910c4f370073f9346e71d34b80 */
42 #define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds3000.fw"
43
44 #define DS3000_SAMPLE_RATE 96000 /* in kHz */
45 #define DS3000_XTAL_FREQ 27000 /* in kHz */
46
47 /* Register values to initialise the demod in DVB-S mode */
48 static u8 ds3000_dvbs_init_tab[] = {
49 0x23, 0x05,
50 0x08, 0x03,
51 0x0c, 0x00,
52 0x21, 0x54,
53 0x25, 0x82,
54 0x27, 0x31,
55 0x30, 0x08,
56 0x31, 0x40,
57 0x32, 0x32,
58 0x33, 0x35,
59 0x35, 0xff,
60 0x3a, 0x00,
61 0x37, 0x10,
62 0x38, 0x10,
63 0x39, 0x02,
64 0x42, 0x60,
65 0x4a, 0x40,
66 0x4b, 0x04,
67 0x4d, 0x91,
68 0x5d, 0xc8,
69 0x50, 0x77,
70 0x51, 0x77,
71 0x52, 0x36,
72 0x53, 0x36,
73 0x56, 0x01,
74 0x63, 0x43,
75 0x64, 0x30,
76 0x65, 0x40,
77 0x68, 0x26,
78 0x69, 0x4c,
79 0x70, 0x20,
80 0x71, 0x70,
81 0x72, 0x04,
82 0x73, 0x00,
83 0x70, 0x40,
84 0x71, 0x70,
85 0x72, 0x04,
86 0x73, 0x00,
87 0x70, 0x60,
88 0x71, 0x70,
89 0x72, 0x04,
90 0x73, 0x00,
91 0x70, 0x80,
92 0x71, 0x70,
93 0x72, 0x04,
94 0x73, 0x00,
95 0x70, 0xa0,
96 0x71, 0x70,
97 0x72, 0x04,
98 0x73, 0x00,
99 0x70, 0x1f,
100 0x76, 0x00,
101 0x77, 0xd1,
102 0x78, 0x0c,
103 0x79, 0x80,
104 0x7f, 0x04,
105 0x7c, 0x00,
106 0x80, 0x86,
107 0x81, 0xa6,
108 0x85, 0x04,
109 0xcd, 0xf4,
110 0x90, 0x33,
111 0xa0, 0x44,
112 0xc0, 0x18,
113 0xc3, 0x10,
114 0xc4, 0x08,
115 0xc5, 0x80,
116 0xc6, 0x80,
117 0xc7, 0x0a,
118 0xc8, 0x1a,
119 0xc9, 0x80,
120 0xfe, 0x92,
121 0xe0, 0xf8,
122 0xe6, 0x8b,
123 0xd0, 0x40,
124 0xf8, 0x20,
125 0xfa, 0x0f,
126 0xfd, 0x20,
127 0xad, 0x20,
128 0xae, 0x07,
129 0xb8, 0x00,
130 };
131
132 /* Register values to initialise the demod in DVB-S2 mode */
133 static u8 ds3000_dvbs2_init_tab[] = {
134 0x23, 0x0f,
135 0x08, 0x07,
136 0x0c, 0x00,
137 0x21, 0x54,
138 0x25, 0x82,
139 0x27, 0x31,
140 0x30, 0x08,
141 0x31, 0x32,
142 0x32, 0x32,
143 0x33, 0x35,
144 0x35, 0xff,
145 0x3a, 0x00,
146 0x37, 0x10,
147 0x38, 0x10,
148 0x39, 0x02,
149 0x42, 0x60,
150 0x4a, 0x80,
151 0x4b, 0x04,
152 0x4d, 0x81,
153 0x5d, 0x88,
154 0x50, 0x36,
155 0x51, 0x36,
156 0x52, 0x36,
157 0x53, 0x36,
158 0x63, 0x60,
159 0x64, 0x10,
160 0x65, 0x10,
161 0x68, 0x04,
162 0x69, 0x29,
163 0x70, 0x20,
164 0x71, 0x70,
165 0x72, 0x04,
166 0x73, 0x00,
167 0x70, 0x40,
168 0x71, 0x70,
169 0x72, 0x04,
170 0x73, 0x00,
171 0x70, 0x60,
172 0x71, 0x70,
173 0x72, 0x04,
174 0x73, 0x00,
175 0x70, 0x80,
176 0x71, 0x70,
177 0x72, 0x04,
178 0x73, 0x00,
179 0x70, 0xa0,
180 0x71, 0x70,
181 0x72, 0x04,
182 0x73, 0x00,
183 0x70, 0x1f,
184 0xa0, 0x44,
185 0xc0, 0x08,
186 0xc1, 0x10,
187 0xc2, 0x08,
188 0xc3, 0x10,
189 0xc4, 0x08,
190 0xc5, 0xf0,
191 0xc6, 0xf0,
192 0xc7, 0x0a,
193 0xc8, 0x1a,
194 0xc9, 0x80,
195 0xca, 0x23,
196 0xcb, 0x24,
197 0xce, 0x74,
198 0x90, 0x03,
199 0x76, 0x80,
200 0x77, 0x42,
201 0x78, 0x0a,
202 0x79, 0x80,
203 0xad, 0x40,
204 0xae, 0x07,
205 0x7f, 0xd4,
206 0x7c, 0x00,
207 0x80, 0xa8,
208 0x81, 0xda,
209 0x7c, 0x01,
210 0x80, 0xda,
211 0x81, 0xec,
212 0x7c, 0x02,
213 0x80, 0xca,
214 0x81, 0xeb,
215 0x7c, 0x03,
216 0x80, 0xba,
217 0x81, 0xdb,
218 0x85, 0x08,
219 0x86, 0x00,
220 0x87, 0x02,
221 0x89, 0x80,
222 0x8b, 0x44,
223 0x8c, 0xaa,
224 0x8a, 0x10,
225 0xba, 0x00,
226 0xf5, 0x04,
227 0xfe, 0x44,
228 0xd2, 0x32,
229 0xb8, 0x00,
230 };
231
232 struct ds3000_state {
233 struct i2c_adapter *i2c;
234 const struct ds3000_config *config;
235 struct dvb_frontend frontend;
236 u8 skip_fw_load;
237 /* previous uncorrected block counter for DVB-S2 */
238 u16 prevUCBS2;
239 };
240
241 static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
242 {
243 u8 buf[] = { reg, data };
244 struct i2c_msg msg = { .addr = state->config->demod_address,
245 .flags = 0, .buf = buf, .len = 2 };
246 int err;
247
248 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
249
250 err = i2c_transfer(state->i2c, &msg, 1);
251 if (err != 1) {
252 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x,"
253 " value == 0x%02x)\n", __func__, err, reg, data);
254 return -EREMOTEIO;
255 }
256
257 return 0;
258 }
259
260 static int ds3000_tuner_writereg(struct ds3000_state *state, int reg, int data)
261 {
262 u8 buf[] = { reg, data };
263 struct i2c_msg msg = { .addr = 0x60,
264 .flags = 0, .buf = buf, .len = 2 };
265 int err;
266
267 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
268
269 ds3000_writereg(state, 0x03, 0x11);
270 err = i2c_transfer(state->i2c, &msg, 1);
271 if (err != 1) {
272 printk("%s: writereg error(err == %i, reg == 0x%02x,"
273 " value == 0x%02x)\n", __func__, err, reg, data);
274 return -EREMOTEIO;
275 }
276
277 return 0;
278 }
279
280 /* I2C write for 8k firmware load */
281 static int ds3000_writeFW(struct ds3000_state *state, int reg,
282 const u8 *data, u16 len)
283 {
284 int i, ret = -EREMOTEIO;
285 struct i2c_msg msg;
286 u8 *buf;
287
288 buf = kmalloc(33, GFP_KERNEL);
289 if (buf == NULL) {
290 printk(KERN_ERR "Unable to kmalloc\n");
291 ret = -ENOMEM;
292 goto error;
293 }
294
295 *(buf) = reg;
296
297 msg.addr = state->config->demod_address;
298 msg.flags = 0;
299 msg.buf = buf;
300 msg.len = 33;
301
302 for (i = 0; i < len; i += 32) {
303 memcpy(buf + 1, data + i, 32);
304
305 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
306
307 ret = i2c_transfer(state->i2c, &msg, 1);
308 if (ret != 1) {
309 printk(KERN_ERR "%s: write error(err == %i, "
310 "reg == 0x%02x\n", __func__, ret, reg);
311 ret = -EREMOTEIO;
312 }
313 }
314
315 error:
316 kfree(buf);
317
318 return ret;
319 }
320
321 static int ds3000_readreg(struct ds3000_state *state, u8 reg)
322 {
323 int ret;
324 u8 b0[] = { reg };
325 u8 b1[] = { 0 };
326 struct i2c_msg msg[] = {
327 {
328 .addr = state->config->demod_address,
329 .flags = 0,
330 .buf = b0,
331 .len = 1
332 }, {
333 .addr = state->config->demod_address,
334 .flags = I2C_M_RD,
335 .buf = b1,
336 .len = 1
337 }
338 };
339
340 ret = i2c_transfer(state->i2c, msg, 2);
341
342 if (ret != 2) {
343 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
344 return ret;
345 }
346
347 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
348
349 return b1[0];
350 }
351
352 static int ds3000_tuner_readreg(struct ds3000_state *state, u8 reg)
353 {
354 int ret;
355 u8 b0[] = { reg };
356 u8 b1[] = { 0 };
357 struct i2c_msg msg[] = {
358 {
359 .addr = 0x60,
360 .flags = 0,
361 .buf = b0,
362 .len = 1
363 }, {
364 .addr = 0x60,
365 .flags = I2C_M_RD,
366 .buf = b1,
367 .len = 1
368 }
369 };
370
371 ds3000_writereg(state, 0x03, 0x12);
372 ret = i2c_transfer(state->i2c, msg, 2);
373
374 if (ret != 2) {
375 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
376 return ret;
377 }
378
379 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
380
381 return b1[0];
382 }
383
384 static int ds3000_load_firmware(struct dvb_frontend *fe,
385 const struct firmware *fw);
386
387 static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
388 {
389 struct ds3000_state *state = fe->demodulator_priv;
390 const struct firmware *fw;
391 int ret = 0;
392
393 dprintk("%s()\n", __func__);
394
395 if (ds3000_readreg(state, 0xb2) <= 0)
396 return ret;
397
398 if (state->skip_fw_load)
399 return 0;
400 /* Load firmware */
401 /* request the firmware, this will block until someone uploads it */
402 printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
403 DS3000_DEFAULT_FIRMWARE);
404 ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE,
405 state->i2c->dev.parent);
406 printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
407 if (ret) {
408 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not "
409 "found?)\n", __func__);
410 return ret;
411 }
412
413 /* Make sure we don't recurse back through here during loading */
414 state->skip_fw_load = 1;
415
416 ret = ds3000_load_firmware(fe, fw);
417 if (ret)
418 printk("%s: Writing firmware to device failed\n", __func__);
419
420 release_firmware(fw);
421
422 dprintk("%s: Firmware upload %s\n", __func__,
423 ret == 0 ? "complete" : "failed");
424
425 /* Ensure firmware is always loaded if required */
426 state->skip_fw_load = 0;
427
428 return ret;
429 }
430
431 static int ds3000_load_firmware(struct dvb_frontend *fe,
432 const struct firmware *fw)
433 {
434 struct ds3000_state *state = fe->demodulator_priv;
435
436 dprintk("%s\n", __func__);
437 dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
438 fw->size,
439 fw->data[0],
440 fw->data[1],
441 fw->data[fw->size - 2],
442 fw->data[fw->size - 1]);
443
444 /* Begin the firmware load process */
445 ds3000_writereg(state, 0xb2, 0x01);
446 /* write the entire firmware */
447 ds3000_writeFW(state, 0xb0, fw->data, fw->size);
448 ds3000_writereg(state, 0xb2, 0x00);
449
450 return 0;
451 }
452
453 static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
454 {
455 struct ds3000_state *state = fe->demodulator_priv;
456 u8 data;
457
458 dprintk("%s(%d)\n", __func__, voltage);
459
460 data = ds3000_readreg(state, 0xa2);
461 data |= 0x03; /* bit0 V/H, bit1 off/on */
462
463 switch (voltage) {
464 case SEC_VOLTAGE_18:
465 data &= ~0x03;
466 break;
467 case SEC_VOLTAGE_13:
468 data &= ~0x03;
469 data |= 0x01;
470 break;
471 case SEC_VOLTAGE_OFF:
472 break;
473 }
474
475 ds3000_writereg(state, 0xa2, data);
476
477 return 0;
478 }
479
480 static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
481 {
482 struct ds3000_state *state = fe->demodulator_priv;
483 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
484 int lock;
485
486 *status = 0;
487
488 switch (c->delivery_system) {
489 case SYS_DVBS:
490 lock = ds3000_readreg(state, 0xd1);
491 if ((lock & 0x07) == 0x07)
492 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
493 FE_HAS_VITERBI | FE_HAS_SYNC |
494 FE_HAS_LOCK;
495
496 break;
497 case SYS_DVBS2:
498 lock = ds3000_readreg(state, 0x0d);
499 if ((lock & 0x8f) == 0x8f)
500 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
501 FE_HAS_VITERBI | FE_HAS_SYNC |
502 FE_HAS_LOCK;
503
504 break;
505 default:
506 return 1;
507 }
508
509 dprintk("%s: status = 0x%02x\n", __func__, lock);
510
511 return 0;
512 }
513
514 /* read DS3000 BER value */
515 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
516 {
517 struct ds3000_state *state = fe->demodulator_priv;
518 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
519 u8 data;
520 u32 ber_reading, lpdc_frames;
521
522 dprintk("%s()\n", __func__);
523
524 switch (c->delivery_system) {
525 case SYS_DVBS:
526 /* set the number of bytes checked during
527 BER estimation */
528 ds3000_writereg(state, 0xf9, 0x04);
529 /* read BER estimation status */
530 data = ds3000_readreg(state, 0xf8);
531 /* check if BER estimation is ready */
532 if ((data & 0x10) == 0) {
533 /* this is the number of error bits,
534 to calculate the bit error rate
535 divide to 8388608 */
536 *ber = (ds3000_readreg(state, 0xf7) << 8) |
537 ds3000_readreg(state, 0xf6);
538 /* start counting error bits */
539 /* need to be set twice
540 otherwise it fails sometimes */
541 data |= 0x10;
542 ds3000_writereg(state, 0xf8, data);
543 ds3000_writereg(state, 0xf8, data);
544 } else
545 /* used to indicate that BER estimation
546 is not ready, i.e. BER is unknown */
547 *ber = 0xffffffff;
548 break;
549 case SYS_DVBS2:
550 /* read the number of LPDC decoded frames */
551 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
552 (ds3000_readreg(state, 0xd6) << 8) |
553 ds3000_readreg(state, 0xd5);
554 /* read the number of packets with bad CRC */
555 ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
556 ds3000_readreg(state, 0xf7);
557 if (lpdc_frames > 750) {
558 /* clear LPDC frame counters */
559 ds3000_writereg(state, 0xd1, 0x01);
560 /* clear bad packets counter */
561 ds3000_writereg(state, 0xf9, 0x01);
562 /* enable bad packets counter */
563 ds3000_writereg(state, 0xf9, 0x00);
564 /* enable LPDC frame counters */
565 ds3000_writereg(state, 0xd1, 0x00);
566 *ber = ber_reading;
567 } else
568 /* used to indicate that BER estimation is not ready,
569 i.e. BER is unknown */
570 *ber = 0xffffffff;
571 break;
572 default:
573 return 1;
574 }
575
576 return 0;
577 }
578
579 /* read TS2020 signal strength */
580 static int ds3000_read_signal_strength(struct dvb_frontend *fe,
581 u16 *signal_strength)
582 {
583 struct ds3000_state *state = fe->demodulator_priv;
584 u16 sig_reading, sig_strength;
585 u8 rfgain, bbgain;
586
587 dprintk("%s()\n", __func__);
588
589 rfgain = ds3000_tuner_readreg(state, 0x3d) & 0x1f;
590 bbgain = ds3000_tuner_readreg(state, 0x21) & 0x1f;
591
592 if (rfgain > 15)
593 rfgain = 15;
594 if (bbgain > 13)
595 bbgain = 13;
596
597 sig_reading = rfgain * 2 + bbgain * 3;
598
599 sig_strength = 40 + (64 - sig_reading) * 50 / 64 ;
600
601 /* cook the value to be suitable for szap-s2 human readable output */
602 *signal_strength = sig_strength * 1000;
603
604 dprintk("%s: raw / cooked = 0x%04x / 0x%04x\n", __func__,
605 sig_reading, *signal_strength);
606
607 return 0;
608 }
609
610 /* calculate DS3000 snr value in dB */
611 static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
612 {
613 struct ds3000_state *state = fe->demodulator_priv;
614 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
615 u8 snr_reading, snr_value;
616 u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
617 static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
618 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
619 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
620 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
621 };
622 static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
623 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
624 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
625 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
626 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
627 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
628 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
629 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
630 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
631 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
632 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
633 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
634 0x49e9, 0x4a20, 0x4a57
635 };
636
637 dprintk("%s()\n", __func__);
638
639 switch (c->delivery_system) {
640 case SYS_DVBS:
641 snr_reading = ds3000_readreg(state, 0xff);
642 snr_reading /= 8;
643 if (snr_reading == 0)
644 *snr = 0x0000;
645 else {
646 if (snr_reading > 20)
647 snr_reading = 20;
648 snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
649 /* cook the value to be suitable for szap-s2
650 human readable output */
651 *snr = snr_value * 8 * 655;
652 }
653 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
654 snr_reading, *snr);
655 break;
656 case SYS_DVBS2:
657 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
658 (ds3000_readreg(state, 0x8d) << 4);
659 dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
660 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
661 if (tmp == 0) {
662 *snr = 0x0000;
663 return 0;
664 }
665 if (dvbs2_noise_reading == 0) {
666 snr_value = 0x0013;
667 /* cook the value to be suitable for szap-s2
668 human readable output */
669 *snr = 0xffff;
670 return 0;
671 }
672 if (tmp > dvbs2_noise_reading) {
673 snr_reading = tmp / dvbs2_noise_reading;
674 if (snr_reading > 80)
675 snr_reading = 80;
676 snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
677 /* cook the value to be suitable for szap-s2
678 human readable output */
679 *snr = snr_value * 5 * 655;
680 } else {
681 snr_reading = dvbs2_noise_reading / tmp;
682 if (snr_reading > 80)
683 snr_reading = 80;
684 *snr = -(dvbs2_snr_tab[snr_reading] / 1000);
685 }
686 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
687 snr_reading, *snr);
688 break;
689 default:
690 return 1;
691 }
692
693 return 0;
694 }
695
696 /* read DS3000 uncorrected blocks */
697 static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
698 {
699 struct ds3000_state *state = fe->demodulator_priv;
700 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
701 u8 data;
702 u16 _ucblocks;
703
704 dprintk("%s()\n", __func__);
705
706 switch (c->delivery_system) {
707 case SYS_DVBS:
708 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
709 ds3000_readreg(state, 0xf4);
710 data = ds3000_readreg(state, 0xf8);
711 /* clear packet counters */
712 data &= ~0x20;
713 ds3000_writereg(state, 0xf8, data);
714 /* enable packet counters */
715 data |= 0x20;
716 ds3000_writereg(state, 0xf8, data);
717 break;
718 case SYS_DVBS2:
719 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
720 ds3000_readreg(state, 0xe1);
721 if (_ucblocks > state->prevUCBS2)
722 *ucblocks = _ucblocks - state->prevUCBS2;
723 else
724 *ucblocks = state->prevUCBS2 - _ucblocks;
725 state->prevUCBS2 = _ucblocks;
726 break;
727 default:
728 return 1;
729 }
730
731 return 0;
732 }
733
734 static int ds3000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
735 {
736 struct ds3000_state *state = fe->demodulator_priv;
737 u8 data;
738
739 dprintk("%s(%d)\n", __func__, tone);
740 if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
741 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
742 return -EINVAL;
743 }
744
745 data = ds3000_readreg(state, 0xa2);
746 data &= ~0xc0;
747 ds3000_writereg(state, 0xa2, data);
748
749 switch (tone) {
750 case SEC_TONE_ON:
751 dprintk("%s: setting tone on\n", __func__);
752 data = ds3000_readreg(state, 0xa1);
753 data &= ~0x43;
754 data |= 0x04;
755 ds3000_writereg(state, 0xa1, data);
756 break;
757 case SEC_TONE_OFF:
758 dprintk("%s: setting tone off\n", __func__);
759 data = ds3000_readreg(state, 0xa2);
760 data |= 0x80;
761 ds3000_writereg(state, 0xa2, data);
762 break;
763 }
764
765 return 0;
766 }
767
768 static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
769 struct dvb_diseqc_master_cmd *d)
770 {
771 struct ds3000_state *state = fe->demodulator_priv;
772 int i;
773 u8 data;
774
775 /* Dump DiSEqC message */
776 dprintk("%s(", __func__);
777 for (i = 0 ; i < d->msg_len;) {
778 dprintk("0x%02x", d->msg[i]);
779 if (++i < d->msg_len)
780 dprintk(", ");
781 }
782
783 /* enable DiSEqC message send pin */
784 data = ds3000_readreg(state, 0xa2);
785 data &= ~0xc0;
786 ds3000_writereg(state, 0xa2, data);
787
788 /* DiSEqC message */
789 for (i = 0; i < d->msg_len; i++)
790 ds3000_writereg(state, 0xa3 + i, d->msg[i]);
791
792 data = ds3000_readreg(state, 0xa1);
793 /* clear DiSEqC message length and status,
794 enable DiSEqC message send */
795 data &= ~0xf8;
796 /* set DiSEqC mode, modulation active during 33 pulses,
797 set DiSEqC message length */
798 data |= ((d->msg_len - 1) << 3) | 0x07;
799 ds3000_writereg(state, 0xa1, data);
800
801 /* wait up to 150ms for DiSEqC transmission to complete */
802 for (i = 0; i < 15; i++) {
803 data = ds3000_readreg(state, 0xa1);
804 if ((data & 0x40) == 0)
805 break;
806 msleep(10);
807 }
808
809 /* DiSEqC timeout after 150ms */
810 if (i == 15) {
811 data = ds3000_readreg(state, 0xa1);
812 data &= ~0x80;
813 data |= 0x40;
814 ds3000_writereg(state, 0xa1, data);
815
816 data = ds3000_readreg(state, 0xa2);
817 data &= ~0xc0;
818 data |= 0x80;
819 ds3000_writereg(state, 0xa2, data);
820
821 return 1;
822 }
823
824 data = ds3000_readreg(state, 0xa2);
825 data &= ~0xc0;
826 data |= 0x80;
827 ds3000_writereg(state, 0xa2, data);
828
829 return 0;
830 }
831
832 /* Send DiSEqC burst */
833 static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
834 fe_sec_mini_cmd_t burst)
835 {
836 struct ds3000_state *state = fe->demodulator_priv;
837 int i;
838 u8 data;
839
840 dprintk("%s()\n", __func__);
841
842 data = ds3000_readreg(state, 0xa2);
843 data &= ~0xc0;
844 ds3000_writereg(state, 0xa2, data);
845
846 /* DiSEqC burst */
847 if (burst == SEC_MINI_A)
848 /* Unmodulated tone burst */
849 ds3000_writereg(state, 0xa1, 0x02);
850 else if (burst == SEC_MINI_B)
851 /* Modulated tone burst */
852 ds3000_writereg(state, 0xa1, 0x01);
853 else
854 return -EINVAL;
855
856 msleep(13);
857 for (i = 0; i < 5; i++) {
858 data = ds3000_readreg(state, 0xa1);
859 if ((data & 0x40) == 0)
860 break;
861 msleep(1);
862 }
863
864 if (i == 5) {
865 data = ds3000_readreg(state, 0xa1);
866 data &= ~0x80;
867 data |= 0x40;
868 ds3000_writereg(state, 0xa1, data);
869
870 data = ds3000_readreg(state, 0xa2);
871 data &= ~0xc0;
872 data |= 0x80;
873 ds3000_writereg(state, 0xa2, data);
874
875 return 1;
876 }
877
878 data = ds3000_readreg(state, 0xa2);
879 data &= ~0xc0;
880 data |= 0x80;
881 ds3000_writereg(state, 0xa2, data);
882
883 return 0;
884 }
885
886 static void ds3000_release(struct dvb_frontend *fe)
887 {
888 struct ds3000_state *state = fe->demodulator_priv;
889 dprintk("%s\n", __func__);
890 kfree(state);
891 }
892
893 static struct dvb_frontend_ops ds3000_ops;
894
895 struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
896 struct i2c_adapter *i2c)
897 {
898 struct ds3000_state *state = NULL;
899 int ret;
900
901 dprintk("%s\n", __func__);
902
903 /* allocate memory for the internal state */
904 state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL);
905 if (state == NULL) {
906 printk(KERN_ERR "Unable to kmalloc\n");
907 goto error2;
908 }
909
910 state->config = config;
911 state->i2c = i2c;
912 state->prevUCBS2 = 0;
913
914 /* check if the demod is present */
915 ret = ds3000_readreg(state, 0x00) & 0xfe;
916 if (ret != 0xe0) {
917 printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
918 goto error3;
919 }
920
921 printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
922 ds3000_readreg(state, 0x02),
923 ds3000_readreg(state, 0x01));
924
925 memcpy(&state->frontend.ops, &ds3000_ops,
926 sizeof(struct dvb_frontend_ops));
927 state->frontend.demodulator_priv = state;
928 return &state->frontend;
929
930 error3:
931 kfree(state);
932 error2:
933 return NULL;
934 }
935 EXPORT_SYMBOL(ds3000_attach);
936
937 static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
938 s32 carrier_offset_khz)
939 {
940 struct ds3000_state *state = fe->demodulator_priv;
941 s32 tmp;
942
943 tmp = carrier_offset_khz;
944 tmp *= 65536;
945 tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
946
947 if (tmp < 0)
948 tmp += 65536;
949
950 ds3000_writereg(state, 0x5f, tmp >> 8);
951 ds3000_writereg(state, 0x5e, tmp & 0xff);
952
953 return 0;
954 }
955
956 static int ds3000_set_frontend(struct dvb_frontend *fe)
957 {
958 struct ds3000_state *state = fe->demodulator_priv;
959 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
960
961 int i;
962 fe_status_t status;
963 u8 mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf, div4;
964 s32 offset_khz;
965 u16 value, ndiv;
966 u32 f3db;
967
968 dprintk("%s() ", __func__);
969
970 if (state->config->set_ts_params)
971 state->config->set_ts_params(fe, 0);
972 /* Tune */
973 /* unknown */
974 ds3000_tuner_writereg(state, 0x07, 0x02);
975 ds3000_tuner_writereg(state, 0x10, 0x00);
976 ds3000_tuner_writereg(state, 0x60, 0x79);
977 ds3000_tuner_writereg(state, 0x08, 0x01);
978 ds3000_tuner_writereg(state, 0x00, 0x01);
979 div4 = 0;
980
981 /* calculate and set freq divider */
982 if (c->frequency < 1146000) {
983 ds3000_tuner_writereg(state, 0x10, 0x11);
984 div4 = 1;
985 ndiv = ((c->frequency * (6 + 8) * 4) +
986 (DS3000_XTAL_FREQ / 2)) /
987 DS3000_XTAL_FREQ - 1024;
988 } else {
989 ds3000_tuner_writereg(state, 0x10, 0x01);
990 ndiv = ((c->frequency * (6 + 8) * 2) +
991 (DS3000_XTAL_FREQ / 2)) /
992 DS3000_XTAL_FREQ - 1024;
993 }
994
995 ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
996 ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
997
998 /* set pll */
999 ds3000_tuner_writereg(state, 0x03, 0x06);
1000 ds3000_tuner_writereg(state, 0x51, 0x0f);
1001 ds3000_tuner_writereg(state, 0x51, 0x1f);
1002 ds3000_tuner_writereg(state, 0x50, 0x10);
1003 ds3000_tuner_writereg(state, 0x50, 0x00);
1004 msleep(5);
1005
1006 /* unknown */
1007 ds3000_tuner_writereg(state, 0x51, 0x17);
1008 ds3000_tuner_writereg(state, 0x51, 0x1f);
1009 ds3000_tuner_writereg(state, 0x50, 0x08);
1010 ds3000_tuner_writereg(state, 0x50, 0x00);
1011 msleep(5);
1012
1013 value = ds3000_tuner_readreg(state, 0x3d);
1014 value &= 0x0f;
1015 if ((value > 4) && (value < 15)) {
1016 value -= 3;
1017 if (value < 4)
1018 value = 4;
1019 value = ((value << 3) | 0x01) & 0x79;
1020 }
1021
1022 ds3000_tuner_writereg(state, 0x60, value);
1023 ds3000_tuner_writereg(state, 0x51, 0x17);
1024 ds3000_tuner_writereg(state, 0x51, 0x1f);
1025 ds3000_tuner_writereg(state, 0x50, 0x08);
1026 ds3000_tuner_writereg(state, 0x50, 0x00);
1027
1028 /* set low-pass filter period */
1029 ds3000_tuner_writereg(state, 0x04, 0x2e);
1030 ds3000_tuner_writereg(state, 0x51, 0x1b);
1031 ds3000_tuner_writereg(state, 0x51, 0x1f);
1032 ds3000_tuner_writereg(state, 0x50, 0x04);
1033 ds3000_tuner_writereg(state, 0x50, 0x00);
1034 msleep(5);
1035
1036 f3db = ((c->symbol_rate / 1000) << 2) / 5 + 2000;
1037 if ((c->symbol_rate / 1000) < 5000)
1038 f3db += 3000;
1039 if (f3db < 7000)
1040 f3db = 7000;
1041 if (f3db > 40000)
1042 f3db = 40000;
1043
1044 /* set low-pass filter baseband */
1045 value = ds3000_tuner_readreg(state, 0x26);
1046 mlpf = 0x2e * 207 / ((value << 1) + 151);
1047 mlpf_max = mlpf * 135 / 100;
1048 mlpf_min = mlpf * 78 / 100;
1049 if (mlpf_max > 63)
1050 mlpf_max = 63;
1051
1052 /* rounded to the closest integer */
1053 nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
1054 / (2766 * DS3000_XTAL_FREQ);
1055 if (nlpf > 23)
1056 nlpf = 23;
1057 if (nlpf < 1)
1058 nlpf = 1;
1059
1060 /* rounded to the closest integer */
1061 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1062 (1000 * f3db / 2)) / (1000 * f3db);
1063
1064 if (mlpf_new < mlpf_min) {
1065 nlpf++;
1066 mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1067 (1000 * f3db / 2)) / (1000 * f3db);
1068 }
1069
1070 if (mlpf_new > mlpf_max)
1071 mlpf_new = mlpf_max;
1072
1073 ds3000_tuner_writereg(state, 0x04, mlpf_new);
1074 ds3000_tuner_writereg(state, 0x06, nlpf);
1075 ds3000_tuner_writereg(state, 0x51, 0x1b);
1076 ds3000_tuner_writereg(state, 0x51, 0x1f);
1077 ds3000_tuner_writereg(state, 0x50, 0x04);
1078 ds3000_tuner_writereg(state, 0x50, 0x00);
1079 msleep(5);
1080
1081 /* unknown */
1082 ds3000_tuner_writereg(state, 0x51, 0x1e);
1083 ds3000_tuner_writereg(state, 0x51, 0x1f);
1084 ds3000_tuner_writereg(state, 0x50, 0x01);
1085 ds3000_tuner_writereg(state, 0x50, 0x00);
1086 msleep(60);
1087
1088 offset_khz = (ndiv - ndiv % 2 + 1024) * DS3000_XTAL_FREQ
1089 / (6 + 8) / (div4 + 1) / 2 - c->frequency;
1090
1091 /* ds3000 global reset */
1092 ds3000_writereg(state, 0x07, 0x80);
1093 ds3000_writereg(state, 0x07, 0x00);
1094 /* ds3000 build-in uC reset */
1095 ds3000_writereg(state, 0xb2, 0x01);
1096 /* ds3000 software reset */
1097 ds3000_writereg(state, 0x00, 0x01);
1098
1099 switch (c->delivery_system) {
1100 case SYS_DVBS:
1101 /* initialise the demod in DVB-S mode */
1102 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
1103 ds3000_writereg(state,
1104 ds3000_dvbs_init_tab[i],
1105 ds3000_dvbs_init_tab[i + 1]);
1106 value = ds3000_readreg(state, 0xfe);
1107 value &= 0xc0;
1108 value |= 0x1b;
1109 ds3000_writereg(state, 0xfe, value);
1110 break;
1111 case SYS_DVBS2:
1112 /* initialise the demod in DVB-S2 mode */
1113 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
1114 ds3000_writereg(state,
1115 ds3000_dvbs2_init_tab[i],
1116 ds3000_dvbs2_init_tab[i + 1]);
1117 ds3000_writereg(state, 0xfe, 0x98);
1118 break;
1119 default:
1120 return 1;
1121 }
1122
1123 /* enable 27MHz clock output */
1124 ds3000_writereg(state, 0x29, 0x80);
1125 /* enable ac coupling */
1126 ds3000_writereg(state, 0x25, 0x8a);
1127
1128 /* enhance symbol rate performance */
1129 if ((c->symbol_rate / 1000) <= 5000) {
1130 value = 29777 / (c->symbol_rate / 1000) + 1;
1131 if (value % 2 != 0)
1132 value++;
1133 ds3000_writereg(state, 0xc3, 0x0d);
1134 ds3000_writereg(state, 0xc8, value);
1135 ds3000_writereg(state, 0xc4, 0x10);
1136 ds3000_writereg(state, 0xc7, 0x0e);
1137 } else if ((c->symbol_rate / 1000) <= 10000) {
1138 value = 92166 / (c->symbol_rate / 1000) + 1;
1139 if (value % 2 != 0)
1140 value++;
1141 ds3000_writereg(state, 0xc3, 0x07);
1142 ds3000_writereg(state, 0xc8, value);
1143 ds3000_writereg(state, 0xc4, 0x09);
1144 ds3000_writereg(state, 0xc7, 0x12);
1145 } else if ((c->symbol_rate / 1000) <= 20000) {
1146 value = 64516 / (c->symbol_rate / 1000) + 1;
1147 ds3000_writereg(state, 0xc3, value);
1148 ds3000_writereg(state, 0xc8, 0x0e);
1149 ds3000_writereg(state, 0xc4, 0x07);
1150 ds3000_writereg(state, 0xc7, 0x18);
1151 } else {
1152 value = 129032 / (c->symbol_rate / 1000) + 1;
1153 ds3000_writereg(state, 0xc3, value);
1154 ds3000_writereg(state, 0xc8, 0x0a);
1155 ds3000_writereg(state, 0xc4, 0x05);
1156 ds3000_writereg(state, 0xc7, 0x24);
1157 }
1158
1159 /* normalized symbol rate rounded to the closest integer */
1160 value = (((c->symbol_rate / 1000) << 16) +
1161 (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
1162 ds3000_writereg(state, 0x61, value & 0x00ff);
1163 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
1164
1165 /* co-channel interference cancellation disabled */
1166 ds3000_writereg(state, 0x56, 0x00);
1167
1168 /* equalizer disabled */
1169 ds3000_writereg(state, 0x76, 0x00);
1170
1171 /*ds3000_writereg(state, 0x08, 0x03);
1172 ds3000_writereg(state, 0xfd, 0x22);
1173 ds3000_writereg(state, 0x08, 0x07);
1174 ds3000_writereg(state, 0xfd, 0x42);
1175 ds3000_writereg(state, 0x08, 0x07);*/
1176
1177 if (state->config->ci_mode) {
1178 switch (c->delivery_system) {
1179 case SYS_DVBS:
1180 default:
1181 ds3000_writereg(state, 0xfd, 0x80);
1182 break;
1183 case SYS_DVBS2:
1184 ds3000_writereg(state, 0xfd, 0x01);
1185 break;
1186 }
1187 }
1188
1189 /* ds3000 out of software reset */
1190 ds3000_writereg(state, 0x00, 0x00);
1191 /* start ds3000 build-in uC */
1192 ds3000_writereg(state, 0xb2, 0x00);
1193
1194 ds3000_set_carrier_offset(fe, offset_khz);
1195
1196 for (i = 0; i < 30 ; i++) {
1197 ds3000_read_status(fe, &status);
1198 if (status & FE_HAS_LOCK)
1199 break;
1200
1201 msleep(10);
1202 }
1203
1204 return 0;
1205 }
1206
1207 static int ds3000_tune(struct dvb_frontend *fe,
1208 bool re_tune,
1209 unsigned int mode_flags,
1210 unsigned int *delay,
1211 fe_status_t *status)
1212 {
1213 if (re_tune) {
1214 int ret = ds3000_set_frontend(fe);
1215 if (ret)
1216 return ret;
1217 }
1218
1219 *delay = HZ / 5;
1220
1221 return ds3000_read_status(fe, status);
1222 }
1223
1224 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1225 {
1226 dprintk("%s()\n", __func__);
1227 return DVBFE_ALGO_HW;
1228 }
1229
1230 /*
1231 * Initialise or wake up device
1232 *
1233 * Power config will reset and load initial firmware if required
1234 */
1235 static int ds3000_initfe(struct dvb_frontend *fe)
1236 {
1237 struct ds3000_state *state = fe->demodulator_priv;
1238 int ret;
1239
1240 dprintk("%s()\n", __func__);
1241 /* hard reset */
1242 ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
1243 msleep(1);
1244
1245 /* TS2020 init */
1246 ds3000_tuner_writereg(state, 0x42, 0x73);
1247 ds3000_tuner_writereg(state, 0x05, 0x01);
1248 ds3000_tuner_writereg(state, 0x62, 0xf5);
1249 /* Load the firmware if required */
1250 ret = ds3000_firmware_ondemand(fe);
1251 if (ret != 0) {
1252 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
1253 return ret;
1254 }
1255
1256 return 0;
1257 }
1258
1259 /* Put device to sleep */
1260 static int ds3000_sleep(struct dvb_frontend *fe)
1261 {
1262 dprintk("%s()\n", __func__);
1263 return 0;
1264 }
1265
1266 static struct dvb_frontend_ops ds3000_ops = {
1267 .delsys = { SYS_DVBS, SYS_DVBS2},
1268 .info = {
1269 .name = "Montage Technology DS3000/TS2020",
1270 .frequency_min = 950000,
1271 .frequency_max = 2150000,
1272 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
1273 .frequency_tolerance = 5000,
1274 .symbol_rate_min = 1000000,
1275 .symbol_rate_max = 45000000,
1276 .caps = FE_CAN_INVERSION_AUTO |
1277 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1278 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1279 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1280 FE_CAN_2G_MODULATION |
1281 FE_CAN_QPSK | FE_CAN_RECOVER
1282 },
1283
1284 .release = ds3000_release,
1285
1286 .init = ds3000_initfe,
1287 .sleep = ds3000_sleep,
1288 .read_status = ds3000_read_status,
1289 .read_ber = ds3000_read_ber,
1290 .read_signal_strength = ds3000_read_signal_strength,
1291 .read_snr = ds3000_read_snr,
1292 .read_ucblocks = ds3000_read_ucblocks,
1293 .set_voltage = ds3000_set_voltage,
1294 .set_tone = ds3000_set_tone,
1295 .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
1296 .diseqc_send_burst = ds3000_diseqc_send_burst,
1297 .get_frontend_algo = ds3000_get_algo,
1298
1299 .set_frontend = ds3000_set_frontend,
1300 .tune = ds3000_tune,
1301 };
1302
1303 module_param(debug, int, 0644);
1304 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1305
1306 MODULE_DESCRIPTION("DVB Frontend module for Montage Technology "
1307 "DS3000/TS2020 hardware");
1308 MODULE_AUTHOR("Konstantin Dimitrov");
1309 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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