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[deliverable/linux.git] / drivers / media / dvb / frontends / nxt200x.c
1 /*
2 * Support for NXT2002 and NXT2004 - VSB/QAM
3 *
4 * Copyright (C) 2005 Kirk Lapray <kirk.lapray@gmail.com>
5 * Copyright (C) 2006 Michael Krufky <mkrufky@m1k.net>
6 * based on nxt2002 by Taylor Jacob <rtjacob@earthlink.net>
7 * and nxt2004 by Jean-Francois Thibert <jeanfrancois@sagetv.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25 /*
26 * NOTES ABOUT THIS DRIVER
27 *
28 * This Linux driver supports:
29 * B2C2/BBTI Technisat Air2PC - ATSC (NXT2002)
30 * AverTVHD MCE A180 (NXT2004)
31 * ATI HDTV Wonder (NXT2004)
32 *
33 * This driver needs external firmware. Please use the command
34 * "<kerneldir>/Documentation/dvb/get_dvb_firmware nxt2002" or
35 * "<kerneldir>/Documentation/dvb/get_dvb_firmware nxt2004" to
36 * download/extract the appropriate firmware, and then copy it to
37 * /usr/lib/hotplug/firmware/ or /lib/firmware/
38 * (depending on configuration of firmware hotplug).
39 */
40 #define NXT2002_DEFAULT_FIRMWARE "dvb-fe-nxt2002.fw"
41 #define NXT2004_DEFAULT_FIRMWARE "dvb-fe-nxt2004.fw"
42 #define CRC_CCIT_MASK 0x1021
43
44 #include <linux/kernel.h>
45 #include <linux/init.h>
46 #include <linux/module.h>
47 #include <linux/moduleparam.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50
51 #include "dvb_frontend.h"
52 #include "dvb-pll.h"
53 #include "nxt200x.h"
54
55 struct nxt200x_state {
56
57 struct i2c_adapter* i2c;
58 struct dvb_frontend_ops ops;
59 const struct nxt200x_config* config;
60 struct dvb_frontend frontend;
61
62 /* demodulator private data */
63 nxt_chip_type demod_chip;
64 u8 initialised:1;
65 };
66
67 static int debug;
68 #define dprintk(args...) \
69 do { \
70 if (debug) printk(KERN_DEBUG "nxt200x: " args); \
71 } while (0)
72
73 static int i2c_writebytes (struct nxt200x_state* state, u8 addr, u8 *buf, u8 len)
74 {
75 int err;
76 struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = len };
77
78 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
79 printk (KERN_WARNING "nxt200x: %s: i2c write error (addr 0x%02x, err == %i)\n",
80 __FUNCTION__, addr, err);
81 return -EREMOTEIO;
82 }
83 return 0;
84 }
85
86 static u8 i2c_readbytes (struct nxt200x_state* state, u8 addr, u8* buf, u8 len)
87 {
88 int err;
89 struct i2c_msg msg = { .addr = addr, .flags = I2C_M_RD, .buf = buf, .len = len };
90
91 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
92 printk (KERN_WARNING "nxt200x: %s: i2c read error (addr 0x%02x, err == %i)\n",
93 __FUNCTION__, addr, err);
94 return -EREMOTEIO;
95 }
96 return 0;
97 }
98
99 static int nxt200x_writebytes (struct nxt200x_state* state, u8 reg, u8 *buf, u8 len)
100 {
101 u8 buf2 [len+1];
102 int err;
103 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len + 1 };
104
105 buf2[0] = reg;
106 memcpy(&buf2[1], buf, len);
107
108 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
109 printk (KERN_WARNING "nxt200x: %s: i2c write error (addr 0x%02x, err == %i)\n",
110 __FUNCTION__, state->config->demod_address, err);
111 return -EREMOTEIO;
112 }
113 return 0;
114 }
115
116 static u8 nxt200x_readbytes (struct nxt200x_state* state, u8 reg, u8* buf, u8 len)
117 {
118 u8 reg2 [] = { reg };
119
120 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = reg2, .len = 1 },
121 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len } };
122
123 int err;
124
125 if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) {
126 printk (KERN_WARNING "nxt200x: %s: i2c read error (addr 0x%02x, err == %i)\n",
127 __FUNCTION__, state->config->demod_address, err);
128 return -EREMOTEIO;
129 }
130 return 0;
131 }
132
133 static u16 nxt200x_crc(u16 crc, u8 c)
134 {
135 u8 i;
136 u16 input = (u16) c & 0xFF;
137
138 input<<=8;
139 for(i=0; i<8; i++) {
140 if((crc^input) & 0x8000)
141 crc=(crc<<1)^CRC_CCIT_MASK;
142 else
143 crc<<=1;
144 input<<=1;
145 }
146 return crc;
147 }
148
149 static int nxt200x_writereg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len)
150 {
151 u8 attr, len2, buf;
152 dprintk("%s\n", __FUNCTION__);
153
154 /* set mutli register register */
155 nxt200x_writebytes(state, 0x35, &reg, 1);
156
157 /* send the actual data */
158 nxt200x_writebytes(state, 0x36, data, len);
159
160 switch (state->demod_chip) {
161 case NXT2002:
162 len2 = len;
163 buf = 0x02;
164 break;
165 case NXT2004:
166 /* probably not right, but gives correct values */
167 attr = 0x02;
168 if (reg & 0x80) {
169 attr = attr << 1;
170 if (reg & 0x04)
171 attr = attr >> 1;
172 }
173 /* set write bit */
174 len2 = ((attr << 4) | 0x10) | len;
175 buf = 0x80;
176 break;
177 default:
178 return -EINVAL;
179 break;
180 }
181
182 /* set multi register length */
183 nxt200x_writebytes(state, 0x34, &len2, 1);
184
185 /* toggle the multireg write bit */
186 nxt200x_writebytes(state, 0x21, &buf, 1);
187
188 nxt200x_readbytes(state, 0x21, &buf, 1);
189
190 switch (state->demod_chip) {
191 case NXT2002:
192 if ((buf & 0x02) == 0)
193 return 0;
194 break;
195 case NXT2004:
196 if (buf == 0)
197 return 0;
198 break;
199 default:
200 return -EINVAL;
201 break;
202 }
203
204 printk(KERN_WARNING "nxt200x: Error writing multireg register 0x%02X\n",reg);
205
206 return 0;
207 }
208
209 static int nxt200x_readreg_multibyte (struct nxt200x_state* state, u8 reg, u8* data, u8 len)
210 {
211 int i;
212 u8 buf, len2, attr;
213 dprintk("%s\n", __FUNCTION__);
214
215 /* set mutli register register */
216 nxt200x_writebytes(state, 0x35, &reg, 1);
217
218 switch (state->demod_chip) {
219 case NXT2002:
220 /* set multi register length */
221 len2 = len & 0x80;
222 nxt200x_writebytes(state, 0x34, &len2, 1);
223
224 /* read the actual data */
225 nxt200x_readbytes(state, reg, data, len);
226 return 0;
227 break;
228 case NXT2004:
229 /* probably not right, but gives correct values */
230 attr = 0x02;
231 if (reg & 0x80) {
232 attr = attr << 1;
233 if (reg & 0x04)
234 attr = attr >> 1;
235 }
236
237 /* set multi register length */
238 len2 = (attr << 4) | len;
239 nxt200x_writebytes(state, 0x34, &len2, 1);
240
241 /* toggle the multireg bit*/
242 buf = 0x80;
243 nxt200x_writebytes(state, 0x21, &buf, 1);
244
245 /* read the actual data */
246 for(i = 0; i < len; i++) {
247 nxt200x_readbytes(state, 0x36 + i, &data[i], 1);
248 }
249 return 0;
250 break;
251 default:
252 return -EINVAL;
253 break;
254 }
255 }
256
257 static void nxt200x_microcontroller_stop (struct nxt200x_state* state)
258 {
259 u8 buf, stopval, counter = 0;
260 dprintk("%s\n", __FUNCTION__);
261
262 /* set correct stop value */
263 switch (state->demod_chip) {
264 case NXT2002:
265 stopval = 0x40;
266 break;
267 case NXT2004:
268 stopval = 0x10;
269 break;
270 default:
271 stopval = 0;
272 break;
273 }
274
275 buf = 0x80;
276 nxt200x_writebytes(state, 0x22, &buf, 1);
277
278 while (counter < 20) {
279 nxt200x_readbytes(state, 0x31, &buf, 1);
280 if (buf & stopval)
281 return;
282 msleep(10);
283 counter++;
284 }
285
286 printk(KERN_WARNING "nxt200x: Timeout waiting for nxt200x to stop. This is ok after firmware upload.\n");
287 return;
288 }
289
290 static void nxt200x_microcontroller_start (struct nxt200x_state* state)
291 {
292 u8 buf;
293 dprintk("%s\n", __FUNCTION__);
294
295 buf = 0x00;
296 nxt200x_writebytes(state, 0x22, &buf, 1);
297 }
298
299 static void nxt2004_microcontroller_init (struct nxt200x_state* state)
300 {
301 u8 buf[9];
302 u8 counter = 0;
303 dprintk("%s\n", __FUNCTION__);
304
305 buf[0] = 0x00;
306 nxt200x_writebytes(state, 0x2b, buf, 1);
307 buf[0] = 0x70;
308 nxt200x_writebytes(state, 0x34, buf, 1);
309 buf[0] = 0x04;
310 nxt200x_writebytes(state, 0x35, buf, 1);
311 buf[0] = 0x01; buf[1] = 0x23; buf[2] = 0x45; buf[3] = 0x67; buf[4] = 0x89;
312 buf[5] = 0xAB; buf[6] = 0xCD; buf[7] = 0xEF; buf[8] = 0xC0;
313 nxt200x_writebytes(state, 0x36, buf, 9);
314 buf[0] = 0x80;
315 nxt200x_writebytes(state, 0x21, buf, 1);
316
317 while (counter < 20) {
318 nxt200x_readbytes(state, 0x21, buf, 1);
319 if (buf[0] == 0)
320 return;
321 msleep(10);
322 counter++;
323 }
324
325 printk(KERN_WARNING "nxt200x: Timeout waiting for nxt2004 to init.\n");
326
327 return;
328 }
329
330 static int nxt200x_writetuner (struct nxt200x_state* state, u8* data)
331 {
332 u8 buf, count = 0;
333
334 dprintk("%s\n", __FUNCTION__);
335
336 dprintk("Tuner Bytes: %02X %02X %02X %02X\n", data[1], data[2], data[3], data[4]);
337
338 /* if NXT2004, write directly to tuner. if NXT2002, write through NXT chip.
339 * direct write is required for Philips TUV1236D and ALPS TDHU2 */
340 switch (state->demod_chip) {
341 case NXT2004:
342 if (i2c_writebytes(state, data[0], data+1, 4))
343 printk(KERN_WARNING "nxt200x: error writing to tuner\n");
344 /* wait until we have a lock */
345 while (count < 20) {
346 i2c_readbytes(state, data[0], &buf, 1);
347 if (buf & 0x40)
348 return 0;
349 msleep(100);
350 count++;
351 }
352 printk("nxt2004: timeout waiting for tuner lock\n");
353 break;
354 case NXT2002:
355 /* set the i2c transfer speed to the tuner */
356 buf = 0x03;
357 nxt200x_writebytes(state, 0x20, &buf, 1);
358
359 /* setup to transfer 4 bytes via i2c */
360 buf = 0x04;
361 nxt200x_writebytes(state, 0x34, &buf, 1);
362
363 /* write actual tuner bytes */
364 nxt200x_writebytes(state, 0x36, data+1, 4);
365
366 /* set tuner i2c address */
367 buf = data[0] << 1;
368 nxt200x_writebytes(state, 0x35, &buf, 1);
369
370 /* write UC Opmode to begin transfer */
371 buf = 0x80;
372 nxt200x_writebytes(state, 0x21, &buf, 1);
373
374 while (count < 20) {
375 nxt200x_readbytes(state, 0x21, &buf, 1);
376 if ((buf & 0x80)== 0x00)
377 return 0;
378 msleep(100);
379 count++;
380 }
381 printk("nxt2002: timeout error writing tuner\n");
382 break;
383 default:
384 return -EINVAL;
385 break;
386 }
387 return 0;
388 }
389
390 static void nxt200x_agc_reset(struct nxt200x_state* state)
391 {
392 u8 buf;
393 dprintk("%s\n", __FUNCTION__);
394
395 switch (state->demod_chip) {
396 case NXT2002:
397 buf = 0x08;
398 nxt200x_writebytes(state, 0x08, &buf, 1);
399 buf = 0x00;
400 nxt200x_writebytes(state, 0x08, &buf, 1);
401 break;
402 case NXT2004:
403 nxt200x_readreg_multibyte(state, 0x08, &buf, 1);
404 buf = 0x08;
405 nxt200x_writereg_multibyte(state, 0x08, &buf, 1);
406 buf = 0x00;
407 nxt200x_writereg_multibyte(state, 0x08, &buf, 1);
408 break;
409 default:
410 break;
411 }
412 return;
413 }
414
415 static int nxt2002_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
416 {
417
418 struct nxt200x_state* state = fe->demodulator_priv;
419 u8 buf[3], written = 0, chunkpos = 0;
420 u16 rambase, position, crc = 0;
421
422 dprintk("%s\n", __FUNCTION__);
423 dprintk("Firmware is %zu bytes\n", fw->size);
424
425 /* Get the RAM base for this nxt2002 */
426 nxt200x_readbytes(state, 0x10, buf, 1);
427
428 if (buf[0] & 0x10)
429 rambase = 0x1000;
430 else
431 rambase = 0x0000;
432
433 dprintk("rambase on this nxt2002 is %04X\n", rambase);
434
435 /* Hold the micro in reset while loading firmware */
436 buf[0] = 0x80;
437 nxt200x_writebytes(state, 0x2B, buf, 1);
438
439 for (position = 0; position < fw->size; position++) {
440 if (written == 0) {
441 crc = 0;
442 chunkpos = 0x28;
443 buf[0] = ((rambase + position) >> 8);
444 buf[1] = (rambase + position) & 0xFF;
445 buf[2] = 0x81;
446 /* write starting address */
447 nxt200x_writebytes(state, 0x29, buf, 3);
448 }
449 written++;
450 chunkpos++;
451
452 if ((written % 4) == 0)
453 nxt200x_writebytes(state, chunkpos, &fw->data[position-3], 4);
454
455 crc = nxt200x_crc(crc, fw->data[position]);
456
457 if ((written == 255) || (position+1 == fw->size)) {
458 /* write remaining bytes of firmware */
459 nxt200x_writebytes(state, chunkpos+4-(written %4),
460 &fw->data[position-(written %4) + 1],
461 written %4);
462 buf[0] = crc << 8;
463 buf[1] = crc & 0xFF;
464
465 /* write crc */
466 nxt200x_writebytes(state, 0x2C, buf, 2);
467
468 /* do a read to stop things */
469 nxt200x_readbytes(state, 0x2A, buf, 1);
470
471 /* set transfer mode to complete */
472 buf[0] = 0x80;
473 nxt200x_writebytes(state, 0x2B, buf, 1);
474
475 written = 0;
476 }
477 }
478
479 return 0;
480 };
481
482 static int nxt2004_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
483 {
484
485 struct nxt200x_state* state = fe->demodulator_priv;
486 u8 buf[3];
487 u16 rambase, position, crc=0;
488
489 dprintk("%s\n", __FUNCTION__);
490 dprintk("Firmware is %zu bytes\n", fw->size);
491
492 /* set rambase */
493 rambase = 0x1000;
494
495 /* hold the micro in reset while loading firmware */
496 buf[0] = 0x80;
497 nxt200x_writebytes(state, 0x2B, buf,1);
498
499 /* calculate firmware CRC */
500 for (position = 0; position < fw->size; position++) {
501 crc = nxt200x_crc(crc, fw->data[position]);
502 }
503
504 buf[0] = rambase >> 8;
505 buf[1] = rambase & 0xFF;
506 buf[2] = 0x81;
507 /* write starting address */
508 nxt200x_writebytes(state,0x29,buf,3);
509
510 for (position = 0; position < fw->size;) {
511 nxt200x_writebytes(state, 0x2C, &fw->data[position],
512 fw->size-position > 255 ? 255 : fw->size-position);
513 position += (fw->size-position > 255 ? 255 : fw->size-position);
514 }
515 buf[0] = crc >> 8;
516 buf[1] = crc & 0xFF;
517
518 dprintk("firmware crc is 0x%02X 0x%02X\n", buf[0], buf[1]);
519
520 /* write crc */
521 nxt200x_writebytes(state, 0x2C, buf,2);
522
523 /* do a read to stop things */
524 nxt200x_readbytes(state, 0x2C, buf, 1);
525
526 /* set transfer mode to complete */
527 buf[0] = 0x80;
528 nxt200x_writebytes(state, 0x2B, buf,1);
529
530 return 0;
531 };
532
533 static int nxt200x_setup_frontend_parameters (struct dvb_frontend* fe,
534 struct dvb_frontend_parameters *p)
535 {
536 struct nxt200x_state* state = fe->demodulator_priv;
537 u8 buf[5];
538
539 /* stop the micro first */
540 nxt200x_microcontroller_stop(state);
541
542 if (state->demod_chip == NXT2004) {
543 /* make sure demod is set to digital */
544 buf[0] = 0x04;
545 nxt200x_writebytes(state, 0x14, buf, 1);
546 buf[0] = 0x00;
547 nxt200x_writebytes(state, 0x17, buf, 1);
548 }
549
550 /* get tuning information */
551 if (fe->ops->tuner_ops.calc_regs) {
552 fe->ops->tuner_ops.calc_regs(fe, p, buf, 5);
553 }
554
555 /* set additional params */
556 switch (p->u.vsb.modulation) {
557 case QAM_64:
558 case QAM_256:
559 /* Set punctured clock for QAM */
560 /* This is just a guess since I am unable to test it */
561 if (state->config->set_ts_params)
562 state->config->set_ts_params(fe, 1);
563
564 /* set input */
565 if (state->config->set_pll_input)
566 state->config->set_pll_input(buf, 1);
567 break;
568 case VSB_8:
569 /* Set non-punctured clock for VSB */
570 if (state->config->set_ts_params)
571 state->config->set_ts_params(fe, 0);
572
573 /* set input */
574 if (state->config->set_pll_input)
575 state->config->set_pll_input(buf, 0);
576 break;
577 default:
578 return -EINVAL;
579 break;
580 }
581
582 /* write frequency information */
583 nxt200x_writetuner(state, buf);
584
585 /* reset the agc now that tuning has been completed */
586 nxt200x_agc_reset(state);
587
588 /* set target power level */
589 switch (p->u.vsb.modulation) {
590 case QAM_64:
591 case QAM_256:
592 buf[0] = 0x74;
593 break;
594 case VSB_8:
595 buf[0] = 0x70;
596 break;
597 default:
598 return -EINVAL;
599 break;
600 }
601 nxt200x_writebytes(state, 0x42, buf, 1);
602
603 /* configure sdm */
604 switch (state->demod_chip) {
605 case NXT2002:
606 buf[0] = 0x87;
607 break;
608 case NXT2004:
609 buf[0] = 0x07;
610 break;
611 default:
612 return -EINVAL;
613 break;
614 }
615 nxt200x_writebytes(state, 0x57, buf, 1);
616
617 /* write sdm1 input */
618 buf[0] = 0x10;
619 buf[1] = 0x00;
620 switch (state->demod_chip) {
621 case NXT2002:
622 nxt200x_writereg_multibyte(state, 0x58, buf, 2);
623 break;
624 case NXT2004:
625 nxt200x_writebytes(state, 0x58, buf, 2);
626 break;
627 default:
628 return -EINVAL;
629 break;
630 }
631
632 /* write sdmx input */
633 switch (p->u.vsb.modulation) {
634 case QAM_64:
635 buf[0] = 0x68;
636 break;
637 case QAM_256:
638 buf[0] = 0x64;
639 break;
640 case VSB_8:
641 buf[0] = 0x60;
642 break;
643 default:
644 return -EINVAL;
645 break;
646 }
647 buf[1] = 0x00;
648 switch (state->demod_chip) {
649 case NXT2002:
650 nxt200x_writereg_multibyte(state, 0x5C, buf, 2);
651 break;
652 case NXT2004:
653 nxt200x_writebytes(state, 0x5C, buf, 2);
654 break;
655 default:
656 return -EINVAL;
657 break;
658 }
659
660 /* write adc power lpf fc */
661 buf[0] = 0x05;
662 nxt200x_writebytes(state, 0x43, buf, 1);
663
664 if (state->demod_chip == NXT2004) {
665 /* write ??? */
666 buf[0] = 0x00;
667 buf[1] = 0x00;
668 nxt200x_writebytes(state, 0x46, buf, 2);
669 }
670
671 /* write accumulator2 input */
672 buf[0] = 0x80;
673 buf[1] = 0x00;
674 switch (state->demod_chip) {
675 case NXT2002:
676 nxt200x_writereg_multibyte(state, 0x4B, buf, 2);
677 break;
678 case NXT2004:
679 nxt200x_writebytes(state, 0x4B, buf, 2);
680 break;
681 default:
682 return -EINVAL;
683 break;
684 }
685
686 /* write kg1 */
687 buf[0] = 0x00;
688 nxt200x_writebytes(state, 0x4D, buf, 1);
689
690 /* write sdm12 lpf fc */
691 buf[0] = 0x44;
692 nxt200x_writebytes(state, 0x55, buf, 1);
693
694 /* write agc control reg */
695 buf[0] = 0x04;
696 nxt200x_writebytes(state, 0x41, buf, 1);
697
698 if (state->demod_chip == NXT2004) {
699 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
700 buf[0] = 0x24;
701 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
702
703 /* soft reset? */
704 nxt200x_readreg_multibyte(state, 0x08, buf, 1);
705 buf[0] = 0x10;
706 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
707 nxt200x_readreg_multibyte(state, 0x08, buf, 1);
708 buf[0] = 0x00;
709 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
710
711 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
712 buf[0] = 0x04;
713 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
714 buf[0] = 0x00;
715 nxt200x_writereg_multibyte(state, 0x81, buf, 1);
716 buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00;
717 nxt200x_writereg_multibyte(state, 0x82, buf, 3);
718 nxt200x_readreg_multibyte(state, 0x88, buf, 1);
719 buf[0] = 0x11;
720 nxt200x_writereg_multibyte(state, 0x88, buf, 1);
721 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
722 buf[0] = 0x44;
723 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
724 }
725
726 /* write agc ucgp0 */
727 switch (p->u.vsb.modulation) {
728 case QAM_64:
729 buf[0] = 0x02;
730 break;
731 case QAM_256:
732 buf[0] = 0x03;
733 break;
734 case VSB_8:
735 buf[0] = 0x00;
736 break;
737 default:
738 return -EINVAL;
739 break;
740 }
741 nxt200x_writebytes(state, 0x30, buf, 1);
742
743 /* write agc control reg */
744 buf[0] = 0x00;
745 nxt200x_writebytes(state, 0x41, buf, 1);
746
747 /* write accumulator2 input */
748 buf[0] = 0x80;
749 buf[1] = 0x00;
750 switch (state->demod_chip) {
751 case NXT2002:
752 nxt200x_writereg_multibyte(state, 0x49, buf, 2);
753 nxt200x_writereg_multibyte(state, 0x4B, buf, 2);
754 break;
755 case NXT2004:
756 nxt200x_writebytes(state, 0x49, buf, 2);
757 nxt200x_writebytes(state, 0x4B, buf, 2);
758 break;
759 default:
760 return -EINVAL;
761 break;
762 }
763
764 /* write agc control reg */
765 buf[0] = 0x04;
766 nxt200x_writebytes(state, 0x41, buf, 1);
767
768 nxt200x_microcontroller_start(state);
769
770 if (state->demod_chip == NXT2004) {
771 nxt2004_microcontroller_init(state);
772
773 /* ???? */
774 buf[0] = 0xF0;
775 buf[1] = 0x00;
776 nxt200x_writebytes(state, 0x5C, buf, 2);
777 }
778
779 /* adjacent channel detection should be done here, but I don't
780 have any stations with this need so I cannot test it */
781
782 return 0;
783 }
784
785 static int nxt200x_read_status(struct dvb_frontend* fe, fe_status_t* status)
786 {
787 struct nxt200x_state* state = fe->demodulator_priv;
788 u8 lock;
789 nxt200x_readbytes(state, 0x31, &lock, 1);
790
791 *status = 0;
792 if (lock & 0x20) {
793 *status |= FE_HAS_SIGNAL;
794 *status |= FE_HAS_CARRIER;
795 *status |= FE_HAS_VITERBI;
796 *status |= FE_HAS_SYNC;
797 *status |= FE_HAS_LOCK;
798 }
799 return 0;
800 }
801
802 static int nxt200x_read_ber(struct dvb_frontend* fe, u32* ber)
803 {
804 struct nxt200x_state* state = fe->demodulator_priv;
805 u8 b[3];
806
807 nxt200x_readreg_multibyte(state, 0xE6, b, 3);
808
809 *ber = ((b[0] << 8) + b[1]) * 8;
810
811 return 0;
812 }
813
814 static int nxt200x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
815 {
816 struct nxt200x_state* state = fe->demodulator_priv;
817 u8 b[2];
818 u16 temp = 0;
819
820 /* setup to read cluster variance */
821 b[0] = 0x00;
822 nxt200x_writebytes(state, 0xA1, b, 1);
823
824 /* get multreg val */
825 nxt200x_readreg_multibyte(state, 0xA6, b, 2);
826
827 temp = (b[0] << 8) | b[1];
828 *strength = ((0x7FFF - temp) & 0x0FFF) * 16;
829
830 return 0;
831 }
832
833 static int nxt200x_read_snr(struct dvb_frontend* fe, u16* snr)
834 {
835
836 struct nxt200x_state* state = fe->demodulator_priv;
837 u8 b[2];
838 u16 temp = 0, temp2;
839 u32 snrdb = 0;
840
841 /* setup to read cluster variance */
842 b[0] = 0x00;
843 nxt200x_writebytes(state, 0xA1, b, 1);
844
845 /* get multreg val from 0xA6 */
846 nxt200x_readreg_multibyte(state, 0xA6, b, 2);
847
848 temp = (b[0] << 8) | b[1];
849 temp2 = 0x7FFF - temp;
850
851 /* snr will be in db */
852 if (temp2 > 0x7F00)
853 snrdb = 1000*24 + ( 1000*(30-24) * ( temp2 - 0x7F00 ) / ( 0x7FFF - 0x7F00 ) );
854 else if (temp2 > 0x7EC0)
855 snrdb = 1000*18 + ( 1000*(24-18) * ( temp2 - 0x7EC0 ) / ( 0x7F00 - 0x7EC0 ) );
856 else if (temp2 > 0x7C00)
857 snrdb = 1000*12 + ( 1000*(18-12) * ( temp2 - 0x7C00 ) / ( 0x7EC0 - 0x7C00 ) );
858 else
859 snrdb = 1000*0 + ( 1000*(12-0) * ( temp2 - 0 ) / ( 0x7C00 - 0 ) );
860
861 /* the value reported back from the frontend will be FFFF=32db 0000=0db */
862 *snr = snrdb * (0xFFFF/32000);
863
864 return 0;
865 }
866
867 static int nxt200x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
868 {
869 struct nxt200x_state* state = fe->demodulator_priv;
870 u8 b[3];
871
872 nxt200x_readreg_multibyte(state, 0xE6, b, 3);
873 *ucblocks = b[2];
874
875 return 0;
876 }
877
878 static int nxt200x_sleep(struct dvb_frontend* fe)
879 {
880 return 0;
881 }
882
883 static int nxt2002_init(struct dvb_frontend* fe)
884 {
885 struct nxt200x_state* state = fe->demodulator_priv;
886 const struct firmware *fw;
887 int ret;
888 u8 buf[2];
889
890 /* request the firmware, this will block until someone uploads it */
891 printk("nxt2002: Waiting for firmware upload (%s)...\n", NXT2002_DEFAULT_FIRMWARE);
892 ret = request_firmware(&fw, NXT2002_DEFAULT_FIRMWARE, &state->i2c->dev);
893 printk("nxt2002: Waiting for firmware upload(2)...\n");
894 if (ret) {
895 printk("nxt2002: No firmware uploaded (timeout or file not found?)\n");
896 return ret;
897 }
898
899 ret = nxt2002_load_firmware(fe, fw);
900 if (ret) {
901 printk("nxt2002: Writing firmware to device failed\n");
902 release_firmware(fw);
903 return ret;
904 }
905 printk("nxt2002: Firmware upload complete\n");
906
907 /* Put the micro into reset */
908 nxt200x_microcontroller_stop(state);
909
910 /* ensure transfer is complete */
911 buf[0]=0x00;
912 nxt200x_writebytes(state, 0x2B, buf, 1);
913
914 /* Put the micro into reset for real this time */
915 nxt200x_microcontroller_stop(state);
916
917 /* soft reset everything (agc,frontend,eq,fec)*/
918 buf[0] = 0x0F;
919 nxt200x_writebytes(state, 0x08, buf, 1);
920 buf[0] = 0x00;
921 nxt200x_writebytes(state, 0x08, buf, 1);
922
923 /* write agc sdm configure */
924 buf[0] = 0xF1;
925 nxt200x_writebytes(state, 0x57, buf, 1);
926
927 /* write mod output format */
928 buf[0] = 0x20;
929 nxt200x_writebytes(state, 0x09, buf, 1);
930
931 /* write fec mpeg mode */
932 buf[0] = 0x7E;
933 buf[1] = 0x00;
934 nxt200x_writebytes(state, 0xE9, buf, 2);
935
936 /* write mux selection */
937 buf[0] = 0x00;
938 nxt200x_writebytes(state, 0xCC, buf, 1);
939
940 return 0;
941 }
942
943 static int nxt2004_init(struct dvb_frontend* fe)
944 {
945 struct nxt200x_state* state = fe->demodulator_priv;
946 const struct firmware *fw;
947 int ret;
948 u8 buf[3];
949
950 /* ??? */
951 buf[0]=0x00;
952 nxt200x_writebytes(state, 0x1E, buf, 1);
953
954 /* request the firmware, this will block until someone uploads it */
955 printk("nxt2004: Waiting for firmware upload (%s)...\n", NXT2004_DEFAULT_FIRMWARE);
956 ret = request_firmware(&fw, NXT2004_DEFAULT_FIRMWARE, &state->i2c->dev);
957 printk("nxt2004: Waiting for firmware upload(2)...\n");
958 if (ret) {
959 printk("nxt2004: No firmware uploaded (timeout or file not found?)\n");
960 return ret;
961 }
962
963 ret = nxt2004_load_firmware(fe, fw);
964 if (ret) {
965 printk("nxt2004: Writing firmware to device failed\n");
966 release_firmware(fw);
967 return ret;
968 }
969 printk("nxt2004: Firmware upload complete\n");
970
971 /* ensure transfer is complete */
972 buf[0] = 0x01;
973 nxt200x_writebytes(state, 0x19, buf, 1);
974
975 nxt2004_microcontroller_init(state);
976 nxt200x_microcontroller_stop(state);
977 nxt200x_microcontroller_stop(state);
978 nxt2004_microcontroller_init(state);
979 nxt200x_microcontroller_stop(state);
980
981 /* soft reset everything (agc,frontend,eq,fec)*/
982 buf[0] = 0xFF;
983 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
984 buf[0] = 0x00;
985 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
986
987 /* write agc sdm configure */
988 buf[0] = 0xD7;
989 nxt200x_writebytes(state, 0x57, buf, 1);
990
991 /* ???*/
992 buf[0] = 0x07;
993 buf[1] = 0xfe;
994 nxt200x_writebytes(state, 0x35, buf, 2);
995 buf[0] = 0x12;
996 nxt200x_writebytes(state, 0x34, buf, 1);
997 buf[0] = 0x80;
998 nxt200x_writebytes(state, 0x21, buf, 1);
999
1000 /* ???*/
1001 buf[0] = 0x21;
1002 nxt200x_writebytes(state, 0x0A, buf, 1);
1003
1004 /* ???*/
1005 buf[0] = 0x01;
1006 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1007
1008 /* write fec mpeg mode */
1009 buf[0] = 0x7E;
1010 buf[1] = 0x00;
1011 nxt200x_writebytes(state, 0xE9, buf, 2);
1012
1013 /* write mux selection */
1014 buf[0] = 0x00;
1015 nxt200x_writebytes(state, 0xCC, buf, 1);
1016
1017 /* ???*/
1018 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1019 buf[0] = 0x00;
1020 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1021
1022 /* soft reset? */
1023 nxt200x_readreg_multibyte(state, 0x08, buf, 1);
1024 buf[0] = 0x10;
1025 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
1026 nxt200x_readreg_multibyte(state, 0x08, buf, 1);
1027 buf[0] = 0x00;
1028 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
1029
1030 /* ???*/
1031 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1032 buf[0] = 0x01;
1033 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1034 buf[0] = 0x70;
1035 nxt200x_writereg_multibyte(state, 0x81, buf, 1);
1036 buf[0] = 0x31; buf[1] = 0x5E; buf[2] = 0x66;
1037 nxt200x_writereg_multibyte(state, 0x82, buf, 3);
1038
1039 nxt200x_readreg_multibyte(state, 0x88, buf, 1);
1040 buf[0] = 0x11;
1041 nxt200x_writereg_multibyte(state, 0x88, buf, 1);
1042 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1043 buf[0] = 0x40;
1044 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1045
1046 nxt200x_readbytes(state, 0x10, buf, 1);
1047 buf[0] = 0x10;
1048 nxt200x_writebytes(state, 0x10, buf, 1);
1049 nxt200x_readbytes(state, 0x0A, buf, 1);
1050 buf[0] = 0x21;
1051 nxt200x_writebytes(state, 0x0A, buf, 1);
1052
1053 nxt2004_microcontroller_init(state);
1054
1055 buf[0] = 0x21;
1056 nxt200x_writebytes(state, 0x0A, buf, 1);
1057 buf[0] = 0x7E;
1058 nxt200x_writebytes(state, 0xE9, buf, 1);
1059 buf[0] = 0x00;
1060 nxt200x_writebytes(state, 0xEA, buf, 1);
1061
1062 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1063 buf[0] = 0x00;
1064 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1065 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1066 buf[0] = 0x00;
1067 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1068
1069 /* soft reset? */
1070 nxt200x_readreg_multibyte(state, 0x08, buf, 1);
1071 buf[0] = 0x10;
1072 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
1073 nxt200x_readreg_multibyte(state, 0x08, buf, 1);
1074 buf[0] = 0x00;
1075 nxt200x_writereg_multibyte(state, 0x08, buf, 1);
1076
1077 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1078 buf[0] = 0x04;
1079 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1080 buf[0] = 0x00;
1081 nxt200x_writereg_multibyte(state, 0x81, buf, 1);
1082 buf[0] = 0x80; buf[1] = 0x00; buf[2] = 0x00;
1083 nxt200x_writereg_multibyte(state, 0x82, buf, 3);
1084
1085 nxt200x_readreg_multibyte(state, 0x88, buf, 1);
1086 buf[0] = 0x11;
1087 nxt200x_writereg_multibyte(state, 0x88, buf, 1);
1088
1089 nxt200x_readreg_multibyte(state, 0x80, buf, 1);
1090 buf[0] = 0x44;
1091 nxt200x_writereg_multibyte(state, 0x80, buf, 1);
1092
1093 /* initialize tuner */
1094 nxt200x_readbytes(state, 0x10, buf, 1);
1095 buf[0] = 0x12;
1096 nxt200x_writebytes(state, 0x10, buf, 1);
1097 buf[0] = 0x04;
1098 nxt200x_writebytes(state, 0x13, buf, 1);
1099 buf[0] = 0x00;
1100 nxt200x_writebytes(state, 0x16, buf, 1);
1101 buf[0] = 0x04;
1102 nxt200x_writebytes(state, 0x14, buf, 1);
1103 buf[0] = 0x00;
1104 nxt200x_writebytes(state, 0x14, buf, 1);
1105 nxt200x_writebytes(state, 0x17, buf, 1);
1106 nxt200x_writebytes(state, 0x14, buf, 1);
1107 nxt200x_writebytes(state, 0x17, buf, 1);
1108
1109 return 0;
1110 }
1111
1112 static int nxt200x_init(struct dvb_frontend* fe)
1113 {
1114 struct nxt200x_state* state = fe->demodulator_priv;
1115 int ret = 0;
1116
1117 if (!state->initialised) {
1118 switch (state->demod_chip) {
1119 case NXT2002:
1120 ret = nxt2002_init(fe);
1121 break;
1122 case NXT2004:
1123 ret = nxt2004_init(fe);
1124 break;
1125 default:
1126 return -EINVAL;
1127 break;
1128 }
1129 state->initialised = 1;
1130 }
1131 return ret;
1132 }
1133
1134 static int nxt200x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1135 {
1136 fesettings->min_delay_ms = 500;
1137 fesettings->step_size = 0;
1138 fesettings->max_drift = 0;
1139 return 0;
1140 }
1141
1142 static void nxt200x_release(struct dvb_frontend* fe)
1143 {
1144 struct nxt200x_state* state = fe->demodulator_priv;
1145 kfree(state);
1146 }
1147
1148 static struct dvb_frontend_ops nxt200x_ops;
1149
1150 struct dvb_frontend* nxt200x_attach(const struct nxt200x_config* config,
1151 struct i2c_adapter* i2c)
1152 {
1153 struct nxt200x_state* state = NULL;
1154 u8 buf [] = {0,0,0,0,0};
1155
1156 /* allocate memory for the internal state */
1157 state = kzalloc(sizeof(struct nxt200x_state), GFP_KERNEL);
1158 if (state == NULL)
1159 goto error;
1160
1161 /* setup the state */
1162 state->config = config;
1163 state->i2c = i2c;
1164 memcpy(&state->ops, &nxt200x_ops, sizeof(struct dvb_frontend_ops));
1165 state->initialised = 0;
1166
1167 /* read card id */
1168 nxt200x_readbytes(state, 0x00, buf, 5);
1169 dprintk("NXT info: %02X %02X %02X %02X %02X\n",
1170 buf[0], buf[1], buf[2], buf[3], buf[4]);
1171
1172 /* set demod chip */
1173 switch (buf[0]) {
1174 case 0x04:
1175 state->demod_chip = NXT2002;
1176 printk("nxt200x: NXT2002 Detected\n");
1177 break;
1178 case 0x05:
1179 state->demod_chip = NXT2004;
1180 printk("nxt200x: NXT2004 Detected\n");
1181 break;
1182 default:
1183 goto error;
1184 }
1185
1186 /* make sure demod chip is supported */
1187 switch (state->demod_chip) {
1188 case NXT2002:
1189 if (buf[0] != 0x04) goto error; /* device id */
1190 if (buf[1] != 0x02) goto error; /* fab id */
1191 if (buf[2] != 0x11) goto error; /* month */
1192 if (buf[3] != 0x20) goto error; /* year msb */
1193 if (buf[4] != 0x00) goto error; /* year lsb */
1194 break;
1195 case NXT2004:
1196 if (buf[0] != 0x05) goto error; /* device id */
1197 break;
1198 default:
1199 goto error;
1200 }
1201
1202 /* create dvb_frontend */
1203 state->frontend.ops = &state->ops;
1204 state->frontend.demodulator_priv = state;
1205 return &state->frontend;
1206
1207 error:
1208 kfree(state);
1209 printk("Unknown/Unsupported NXT chip: %02X %02X %02X %02X %02X\n",
1210 buf[0], buf[1], buf[2], buf[3], buf[4]);
1211 return NULL;
1212 }
1213
1214 static struct dvb_frontend_ops nxt200x_ops = {
1215
1216 .info = {
1217 .name = "Nextwave NXT200X VSB/QAM frontend",
1218 .type = FE_ATSC,
1219 .frequency_min = 54000000,
1220 .frequency_max = 860000000,
1221 .frequency_stepsize = 166666, /* stepsize is just a guess */
1222 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1223 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1224 FE_CAN_8VSB | FE_CAN_QAM_64 | FE_CAN_QAM_256
1225 },
1226
1227 .release = nxt200x_release,
1228
1229 .init = nxt200x_init,
1230 .sleep = nxt200x_sleep,
1231
1232 .set_frontend = nxt200x_setup_frontend_parameters,
1233 .get_tune_settings = nxt200x_get_tune_settings,
1234
1235 .read_status = nxt200x_read_status,
1236 .read_ber = nxt200x_read_ber,
1237 .read_signal_strength = nxt200x_read_signal_strength,
1238 .read_snr = nxt200x_read_snr,
1239 .read_ucblocks = nxt200x_read_ucblocks,
1240 };
1241
1242 module_param(debug, int, 0644);
1243 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1244
1245 MODULE_DESCRIPTION("NXT200X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver");
1246 MODULE_AUTHOR("Kirk Lapray, Michael Krufky, Jean-Francois Thibert, and Taylor Jacob");
1247 MODULE_LICENSE("GPL");
1248
1249 EXPORT_SYMBOL(nxt200x_attach);
1250
Linux kernel - Deliverables
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