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[media] cxd2841er: fix signal strength scale for ISDB-T
[deliverable/linux.git] / drivers / media / dvb-frontends / cxd2841er.c
1 /*
2 * cxd2841er.c
3 *
4 * Sony digital demodulator driver for
5 * CXD2841ER - DVB-S/S2/T/T2/C/C2
6 * CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
7 *
8 * Copyright 2012 Sony Corporation
9 * Copyright (C) 2014 NetUP Inc.
10 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
11 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 */
23
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/string.h>
27 #include <linux/slab.h>
28 #include <linux/bitops.h>
29 #include <linux/math64.h>
30 #include <linux/log2.h>
31 #include <linux/dynamic_debug.h>
32
33 #include "dvb_math.h"
34 #include "dvb_frontend.h"
35 #include "cxd2841er.h"
36 #include "cxd2841er_priv.h"
37
38 #define MAX_WRITE_REGSIZE 16
39
40 enum cxd2841er_state {
41 STATE_SHUTDOWN = 0,
42 STATE_SLEEP_S,
43 STATE_ACTIVE_S,
44 STATE_SLEEP_TC,
45 STATE_ACTIVE_TC
46 };
47
48 struct cxd2841er_priv {
49 struct dvb_frontend frontend;
50 struct i2c_adapter *i2c;
51 u8 i2c_addr_slvx;
52 u8 i2c_addr_slvt;
53 const struct cxd2841er_config *config;
54 enum cxd2841er_state state;
55 u8 system;
56 enum cxd2841er_xtal xtal;
57 enum fe_caps caps;
58 };
59
60 static const struct cxd2841er_cnr_data s_cn_data[] = {
61 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
62 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
63 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
64 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
65 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
66 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
67 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
68 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
69 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
70 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
71 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
72 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
73 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
74 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
75 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
76 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
77 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
78 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
79 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
80 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
81 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
82 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
83 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
84 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
85 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
86 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
87 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
88 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
89 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
90 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
91 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
92 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
93 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
94 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
95 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
96 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
97 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
98 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
99 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
100 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
101 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
102 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
103 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
104 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
105 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
106 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
107 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
108 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
109 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
110 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
111 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
112 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
113 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
114 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
115 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
116 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
117 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
118 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
119 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
120 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
121 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
122 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
123 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
124 { 0x0015, 19900 }, { 0x0014, 20000 },
125 };
126
127 static const struct cxd2841er_cnr_data s2_cn_data[] = {
128 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
129 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
130 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
131 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
132 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
133 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
134 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
135 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
136 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
137 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
138 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
139 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
140 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
141 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
142 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
143 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
144 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
145 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
146 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
147 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
148 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
149 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
150 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
151 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
152 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
153 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
154 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
155 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
156 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
157 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
158 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
159 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
160 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
161 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
162 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
163 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
164 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
165 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
166 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
167 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
168 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
169 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
170 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
171 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
172 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
173 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
174 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
175 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
176 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
177 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
178 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
179 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
180 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
181 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
182 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
183 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
184 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
185 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
186 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
187 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
188 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
189 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
190 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
191 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
192 };
193
194 #define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
195 #define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
196 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
197 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
198
199 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
200 u8 addr, u8 reg, u8 write,
201 const u8 *data, u32 len)
202 {
203 dev_dbg(&priv->i2c->dev,
204 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
205 (write == 0 ? "read" : "write"), addr, reg, len);
206 print_hex_dump_bytes("cxd2841er: I2C data: ",
207 DUMP_PREFIX_OFFSET, data, len);
208 }
209
210 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
211 u8 addr, u8 reg, const u8 *data, u32 len)
212 {
213 int ret;
214 u8 buf[MAX_WRITE_REGSIZE + 1];
215 u8 i2c_addr = (addr == I2C_SLVX ?
216 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
217 struct i2c_msg msg[1] = {
218 {
219 .addr = i2c_addr,
220 .flags = 0,
221 .len = len + 1,
222 .buf = buf,
223 }
224 };
225
226 if (len + 1 >= sizeof(buf)) {
227 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
228 reg, len + 1);
229 return -E2BIG;
230 }
231
232 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
233 buf[0] = reg;
234 memcpy(&buf[1], data, len);
235
236 ret = i2c_transfer(priv->i2c, msg, 1);
237 if (ret >= 0 && ret != 1)
238 ret = -EIO;
239 if (ret < 0) {
240 dev_warn(&priv->i2c->dev,
241 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
242 KBUILD_MODNAME, ret, i2c_addr, reg, len);
243 return ret;
244 }
245 return 0;
246 }
247
248 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
249 u8 addr, u8 reg, u8 val)
250 {
251 return cxd2841er_write_regs(priv, addr, reg, &val, 1);
252 }
253
254 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
255 u8 addr, u8 reg, u8 *val, u32 len)
256 {
257 int ret;
258 u8 i2c_addr = (addr == I2C_SLVX ?
259 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
260 struct i2c_msg msg[2] = {
261 {
262 .addr = i2c_addr,
263 .flags = 0,
264 .len = 1,
265 .buf = &reg,
266 }, {
267 .addr = i2c_addr,
268 .flags = I2C_M_RD,
269 .len = len,
270 .buf = val,
271 }
272 };
273
274 ret = i2c_transfer(priv->i2c, &msg[0], 1);
275 if (ret >= 0 && ret != 1)
276 ret = -EIO;
277 if (ret < 0) {
278 dev_warn(&priv->i2c->dev,
279 "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
280 KBUILD_MODNAME, ret, i2c_addr, reg);
281 return ret;
282 }
283 ret = i2c_transfer(priv->i2c, &msg[1], 1);
284 if (ret >= 0 && ret != 1)
285 ret = -EIO;
286 if (ret < 0) {
287 dev_warn(&priv->i2c->dev,
288 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
289 KBUILD_MODNAME, ret, i2c_addr, reg);
290 return ret;
291 }
292 cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
293 return 0;
294 }
295
296 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
297 u8 addr, u8 reg, u8 *val)
298 {
299 return cxd2841er_read_regs(priv, addr, reg, val, 1);
300 }
301
302 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
303 u8 addr, u8 reg, u8 data, u8 mask)
304 {
305 int res;
306 u8 rdata;
307
308 if (mask != 0xff) {
309 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
310 if (res)
311 return res;
312 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
313 }
314 return cxd2841er_write_reg(priv, addr, reg, data);
315 }
316
317 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
318 u32 symbol_rate)
319 {
320 u32 reg_value = 0;
321 u8 data[3] = {0, 0, 0};
322
323 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
324 /*
325 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
326 * = ((symbolRateKSps * 2^14) + 500) / 1000
327 * = ((symbolRateKSps * 16384) + 500) / 1000
328 */
329 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
330 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
331 dev_err(&priv->i2c->dev,
332 "%s(): reg_value is out of range\n", __func__);
333 return -EINVAL;
334 }
335 data[0] = (u8)((reg_value >> 16) & 0x0F);
336 data[1] = (u8)((reg_value >> 8) & 0xFF);
337 data[2] = (u8)(reg_value & 0xFF);
338 /* Set SLV-T Bank : 0xAE */
339 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
340 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
341 return 0;
342 }
343
344 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
345 u8 system);
346
347 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
348 u8 system, u32 symbol_rate)
349 {
350 int ret;
351 u8 data[4] = { 0, 0, 0, 0 };
352
353 if (priv->state != STATE_SLEEP_S) {
354 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
355 __func__, (int)priv->state);
356 return -EINVAL;
357 }
358 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
359 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
360 /* Set demod mode */
361 if (system == SYS_DVBS) {
362 data[0] = 0x0A;
363 } else if (system == SYS_DVBS2) {
364 data[0] = 0x0B;
365 } else {
366 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
367 __func__, system);
368 return -EINVAL;
369 }
370 /* Set SLV-X Bank : 0x00 */
371 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
372 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
373 /* DVB-S/S2 */
374 data[0] = 0x00;
375 /* Set SLV-T Bank : 0x00 */
376 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
377 /* Enable S/S2 auto detection 1 */
378 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
379 /* Set SLV-T Bank : 0xAE */
380 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
381 /* Enable S/S2 auto detection 2 */
382 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
383 /* Set SLV-T Bank : 0x00 */
384 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
385 /* Enable demod clock */
386 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
387 /* Enable ADC clock */
388 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
389 /* Enable ADC 1 */
390 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
391 /* Enable ADC 2 */
392 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
393 /* Set SLV-X Bank : 0x00 */
394 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
395 /* Enable ADC 3 */
396 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
397 /* Set SLV-T Bank : 0xA3 */
398 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
399 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
400 data[0] = 0x07;
401 data[1] = 0x3B;
402 data[2] = 0x08;
403 data[3] = 0xC5;
404 /* Set SLV-T Bank : 0xAB */
405 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
406 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
407 data[0] = 0x05;
408 data[1] = 0x80;
409 data[2] = 0x0A;
410 data[3] = 0x80;
411 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
412 data[0] = 0x0C;
413 data[1] = 0xCC;
414 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
415 /* Set demod parameter */
416 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
417 if (ret != 0)
418 return ret;
419 /* Set SLV-T Bank : 0x00 */
420 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
421 /* disable Hi-Z setting 1 */
422 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
423 /* disable Hi-Z setting 2 */
424 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
425 priv->state = STATE_ACTIVE_S;
426 return 0;
427 }
428
429 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
430 u32 bandwidth);
431
432 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
433 u32 bandwidth);
434
435 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
436 u32 bandwidth);
437
438 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
439 u32 bandwidth);
440
441 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
442
443 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
444
445 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
446
447 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
448 struct dtv_frontend_properties *p)
449 {
450 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
451 if (priv->state != STATE_ACTIVE_S &&
452 priv->state != STATE_ACTIVE_TC) {
453 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
454 __func__, priv->state);
455 return -EINVAL;
456 }
457 /* Set SLV-T Bank : 0x00 */
458 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
459 /* disable TS output */
460 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
461 if (priv->state == STATE_ACTIVE_S)
462 return cxd2841er_dvbs2_set_symbol_rate(
463 priv, p->symbol_rate / 1000);
464 else if (priv->state == STATE_ACTIVE_TC) {
465 switch (priv->system) {
466 case SYS_DVBT:
467 return cxd2841er_sleep_tc_to_active_t_band(
468 priv, p->bandwidth_hz);
469 case SYS_DVBT2:
470 return cxd2841er_sleep_tc_to_active_t2_band(
471 priv, p->bandwidth_hz);
472 case SYS_DVBC_ANNEX_A:
473 return cxd2841er_sleep_tc_to_active_c_band(
474 priv, p->bandwidth_hz);
475 case SYS_ISDBT:
476 cxd2841er_active_i_to_sleep_tc(priv);
477 cxd2841er_sleep_tc_to_shutdown(priv);
478 cxd2841er_shutdown_to_sleep_tc(priv);
479 return cxd2841er_sleep_tc_to_active_i(
480 priv, p->bandwidth_hz);
481 }
482 }
483 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
484 __func__, priv->system);
485 return -EINVAL;
486 }
487
488 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
489 {
490 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
491 if (priv->state != STATE_ACTIVE_S) {
492 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
493 __func__, priv->state);
494 return -EINVAL;
495 }
496 /* Set SLV-T Bank : 0x00 */
497 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
498 /* disable TS output */
499 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
500 /* enable Hi-Z setting 1 */
501 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
502 /* enable Hi-Z setting 2 */
503 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
504 /* Set SLV-X Bank : 0x00 */
505 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
506 /* disable ADC 1 */
507 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
508 /* Set SLV-T Bank : 0x00 */
509 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
510 /* disable ADC clock */
511 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
512 /* disable ADC 2 */
513 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
514 /* disable ADC 3 */
515 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
516 /* SADC Bias ON */
517 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
518 /* disable demod clock */
519 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
520 /* Set SLV-T Bank : 0xAE */
521 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
522 /* disable S/S2 auto detection1 */
523 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
524 /* Set SLV-T Bank : 0x00 */
525 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
526 /* disable S/S2 auto detection2 */
527 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
528 priv->state = STATE_SLEEP_S;
529 return 0;
530 }
531
532 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
533 {
534 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
535 if (priv->state != STATE_SLEEP_S) {
536 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
537 __func__, priv->state);
538 return -EINVAL;
539 }
540 /* Set SLV-T Bank : 0x00 */
541 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
542 /* Disable DSQOUT */
543 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
544 /* Disable DSQIN */
545 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
546 /* Set SLV-X Bank : 0x00 */
547 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
548 /* Disable oscillator */
549 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
550 /* Set demod mode */
551 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
552 priv->state = STATE_SHUTDOWN;
553 return 0;
554 }
555
556 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
557 {
558 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
559 if (priv->state != STATE_SLEEP_TC) {
560 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
561 __func__, priv->state);
562 return -EINVAL;
563 }
564 /* Set SLV-X Bank : 0x00 */
565 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
566 /* Disable oscillator */
567 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
568 /* Set demod mode */
569 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
570 priv->state = STATE_SHUTDOWN;
571 return 0;
572 }
573
574 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
575 {
576 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
577 if (priv->state != STATE_ACTIVE_TC) {
578 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
579 __func__, priv->state);
580 return -EINVAL;
581 }
582 /* Set SLV-T Bank : 0x00 */
583 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
584 /* disable TS output */
585 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
586 /* enable Hi-Z setting 1 */
587 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
588 /* enable Hi-Z setting 2 */
589 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
590 /* Set SLV-X Bank : 0x00 */
591 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
592 /* disable ADC 1 */
593 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
594 /* Set SLV-T Bank : 0x00 */
595 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
596 /* Disable ADC 2 */
597 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
598 /* Disable ADC 3 */
599 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
600 /* Disable ADC clock */
601 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
602 /* Disable RF level monitor */
603 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
604 /* Disable demod clock */
605 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
606 priv->state = STATE_SLEEP_TC;
607 return 0;
608 }
609
610 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
611 {
612 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
613 if (priv->state != STATE_ACTIVE_TC) {
614 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
615 __func__, priv->state);
616 return -EINVAL;
617 }
618 /* Set SLV-T Bank : 0x00 */
619 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
620 /* disable TS output */
621 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
622 /* enable Hi-Z setting 1 */
623 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
624 /* enable Hi-Z setting 2 */
625 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
626 /* Cancel DVB-T2 setting */
627 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
628 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
629 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
630 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
631 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
632 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
633 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
634 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
635 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
636 /* Set SLV-X Bank : 0x00 */
637 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
638 /* disable ADC 1 */
639 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
640 /* Set SLV-T Bank : 0x00 */
641 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
642 /* Disable ADC 2 */
643 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
644 /* Disable ADC 3 */
645 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
646 /* Disable ADC clock */
647 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
648 /* Disable RF level monitor */
649 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
650 /* Disable demod clock */
651 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
652 priv->state = STATE_SLEEP_TC;
653 return 0;
654 }
655
656 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
657 {
658 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
659 if (priv->state != STATE_ACTIVE_TC) {
660 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
661 __func__, priv->state);
662 return -EINVAL;
663 }
664 /* Set SLV-T Bank : 0x00 */
665 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
666 /* disable TS output */
667 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
668 /* enable Hi-Z setting 1 */
669 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
670 /* enable Hi-Z setting 2 */
671 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
672 /* Cancel DVB-C setting */
673 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
674 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
675 /* Set SLV-X Bank : 0x00 */
676 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
677 /* disable ADC 1 */
678 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
679 /* Set SLV-T Bank : 0x00 */
680 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
681 /* Disable ADC 2 */
682 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
683 /* Disable ADC 3 */
684 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
685 /* Disable ADC clock */
686 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
687 /* Disable RF level monitor */
688 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
689 /* Disable demod clock */
690 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
691 priv->state = STATE_SLEEP_TC;
692 return 0;
693 }
694
695 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
696 {
697 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
698 if (priv->state != STATE_ACTIVE_TC) {
699 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
700 __func__, priv->state);
701 return -EINVAL;
702 }
703 /* Set SLV-T Bank : 0x00 */
704 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
705 /* disable TS output */
706 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
707 /* enable Hi-Z setting 1 */
708 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
709 /* enable Hi-Z setting 2 */
710 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
711
712 /* TODO: Cancel demod parameter */
713
714 /* Set SLV-X Bank : 0x00 */
715 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
716 /* disable ADC 1 */
717 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
718 /* Set SLV-T Bank : 0x00 */
719 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
720 /* Disable ADC 2 */
721 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
722 /* Disable ADC 3 */
723 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
724 /* Disable ADC clock */
725 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
726 /* Disable RF level monitor */
727 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
728 /* Disable demod clock */
729 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
730 priv->state = STATE_SLEEP_TC;
731 return 0;
732 }
733
734 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
735 {
736 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
737 if (priv->state != STATE_SHUTDOWN) {
738 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
739 __func__, priv->state);
740 return -EINVAL;
741 }
742 /* Set SLV-X Bank : 0x00 */
743 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
744 /* Clear all demodulator registers */
745 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
746 usleep_range(3000, 5000);
747 /* Set SLV-X Bank : 0x00 */
748 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
749 /* Set demod SW reset */
750 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
751
752 switch (priv->xtal) {
753 case SONY_XTAL_20500:
754 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
755 break;
756 case SONY_XTAL_24000:
757 /* Select demod frequency */
758 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
759 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
760 break;
761 case SONY_XTAL_41000:
762 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
763 break;
764 default:
765 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
766 __func__, priv->xtal);
767 return -EINVAL;
768 }
769
770 /* Set demod mode */
771 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
772 /* Clear demod SW reset */
773 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
774 usleep_range(1000, 2000);
775 /* Set SLV-T Bank : 0x00 */
776 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
777 /* enable DSQOUT */
778 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
779 /* enable DSQIN */
780 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
781 /* TADC Bias On */
782 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
783 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
784 /* SADC Bias On */
785 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
786 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
787 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
788 priv->state = STATE_SLEEP_S;
789 return 0;
790 }
791
792 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
793 {
794 u8 data = 0;
795
796 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
797 if (priv->state != STATE_SHUTDOWN) {
798 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
799 __func__, priv->state);
800 return -EINVAL;
801 }
802 /* Set SLV-X Bank : 0x00 */
803 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
804 /* Clear all demodulator registers */
805 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
806 usleep_range(3000, 5000);
807 /* Set SLV-X Bank : 0x00 */
808 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
809 /* Set demod SW reset */
810 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
811 /* Select ADC clock mode */
812 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
813
814 switch (priv->xtal) {
815 case SONY_XTAL_20500:
816 data = 0x0;
817 break;
818 case SONY_XTAL_24000:
819 /* Select demod frequency */
820 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
821 data = 0x3;
822 break;
823 case SONY_XTAL_41000:
824 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
825 data = 0x1;
826 break;
827 }
828 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
829 /* Clear demod SW reset */
830 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
831 usleep_range(1000, 2000);
832 /* Set SLV-T Bank : 0x00 */
833 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
834 /* TADC Bias On */
835 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
836 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
837 /* SADC Bias On */
838 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
839 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
840 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
841 priv->state = STATE_SLEEP_TC;
842 return 0;
843 }
844
845 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
846 {
847 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
848 /* Set SLV-T Bank : 0x00 */
849 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
850 /* SW Reset */
851 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
852 /* Enable TS output */
853 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
854 return 0;
855 }
856
857 /* Set TS parallel mode */
858 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
859 u8 system)
860 {
861 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
862
863 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
864 /* Set SLV-T Bank : 0x00 */
865 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
866 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
867 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
868 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
869 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
870 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
871
872 /*
873 * slave Bank Addr Bit default Name
874 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
875 */
876 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
877 /*
878 * Disable TS IF Clock
879 * slave Bank Addr Bit default Name
880 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
881 */
882 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
883 /*
884 * slave Bank Addr Bit default Name
885 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
886 */
887 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
888 /*
889 * Enable TS IF Clock
890 * slave Bank Addr Bit default Name
891 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
892 */
893 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
894
895 if (system == SYS_DVBT) {
896 /* Enable parity period for DVB-T */
897 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
898 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
899 } else if (system == SYS_DVBC_ANNEX_A) {
900 /* Enable parity period for DVB-C */
901 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
902 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
903 }
904 }
905
906 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
907 {
908 u8 chip_id = 0;
909
910 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
911 if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
912 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
913 else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
914 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
915
916 return chip_id;
917 }
918
919 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
920 enum fe_status *status)
921 {
922 u8 reg = 0;
923 struct cxd2841er_priv *priv = fe->demodulator_priv;
924
925 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
926 *status = 0;
927 if (priv->state != STATE_ACTIVE_S) {
928 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
929 __func__, priv->state);
930 return -EINVAL;
931 }
932 /* Set SLV-T Bank : 0xA0 */
933 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
934 /*
935 * slave Bank Addr Bit Signal name
936 * <SLV-T> A0h 11h [2] ITSLOCK
937 */
938 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
939 if (reg & 0x04) {
940 *status = FE_HAS_SIGNAL
941 | FE_HAS_CARRIER
942 | FE_HAS_VITERBI
943 | FE_HAS_SYNC
944 | FE_HAS_LOCK;
945 }
946 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
947 return 0;
948 }
949
950 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
951 u8 *sync, u8 *tslock, u8 *unlock)
952 {
953 u8 data = 0;
954
955 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
956 if (priv->state != STATE_ACTIVE_TC)
957 return -EINVAL;
958 if (priv->system == SYS_DVBT) {
959 /* Set SLV-T Bank : 0x10 */
960 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
961 } else {
962 /* Set SLV-T Bank : 0x20 */
963 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
964 }
965 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
966 if ((data & 0x07) == 0x07) {
967 dev_dbg(&priv->i2c->dev,
968 "%s(): invalid hardware state detected\n", __func__);
969 *sync = 0;
970 *tslock = 0;
971 *unlock = 0;
972 } else {
973 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
974 *tslock = ((data & 0x20) ? 1 : 0);
975 *unlock = ((data & 0x10) ? 1 : 0);
976 }
977 return 0;
978 }
979
980 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
981 {
982 u8 data;
983
984 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
985 if (priv->state != STATE_ACTIVE_TC)
986 return -EINVAL;
987 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
988 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
989 if ((data & 0x01) == 0) {
990 *tslock = 0;
991 } else {
992 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
993 *tslock = ((data & 0x20) ? 1 : 0);
994 }
995 return 0;
996 }
997
998 static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
999 u8 *sync, u8 *tslock, u8 *unlock)
1000 {
1001 u8 data = 0;
1002
1003 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1004 if (priv->state != STATE_ACTIVE_TC)
1005 return -EINVAL;
1006 /* Set SLV-T Bank : 0x60 */
1007 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1008 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1009 dev_dbg(&priv->i2c->dev,
1010 "%s(): lock=0x%x\n", __func__, data);
1011 *sync = ((data & 0x02) ? 1 : 0);
1012 *tslock = ((data & 0x01) ? 1 : 0);
1013 *unlock = ((data & 0x10) ? 1 : 0);
1014 return 0;
1015 }
1016
1017 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1018 enum fe_status *status)
1019 {
1020 int ret = 0;
1021 u8 sync = 0;
1022 u8 tslock = 0;
1023 u8 unlock = 0;
1024 struct cxd2841er_priv *priv = fe->demodulator_priv;
1025
1026 *status = 0;
1027 if (priv->state == STATE_ACTIVE_TC) {
1028 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1029 ret = cxd2841er_read_status_t_t2(
1030 priv, &sync, &tslock, &unlock);
1031 if (ret)
1032 goto done;
1033 if (unlock)
1034 goto done;
1035 if (sync)
1036 *status = FE_HAS_SIGNAL |
1037 FE_HAS_CARRIER |
1038 FE_HAS_VITERBI |
1039 FE_HAS_SYNC;
1040 if (tslock)
1041 *status |= FE_HAS_LOCK;
1042 } else if (priv->system == SYS_ISDBT) {
1043 ret = cxd2841er_read_status_i(
1044 priv, &sync, &tslock, &unlock);
1045 if (ret)
1046 goto done;
1047 if (unlock)
1048 goto done;
1049 if (sync)
1050 *status = FE_HAS_SIGNAL |
1051 FE_HAS_CARRIER |
1052 FE_HAS_VITERBI |
1053 FE_HAS_SYNC;
1054 if (tslock)
1055 *status |= FE_HAS_LOCK;
1056 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1057 ret = cxd2841er_read_status_c(priv, &tslock);
1058 if (ret)
1059 goto done;
1060 if (tslock)
1061 *status = FE_HAS_SIGNAL |
1062 FE_HAS_CARRIER |
1063 FE_HAS_VITERBI |
1064 FE_HAS_SYNC |
1065 FE_HAS_LOCK;
1066 }
1067 }
1068 done:
1069 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1070 return ret;
1071 }
1072
1073 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1074 int *offset)
1075 {
1076 u8 data[3];
1077 u8 is_hs_mode;
1078 s32 cfrl_ctrlval;
1079 s32 temp_div, temp_q, temp_r;
1080
1081 if (priv->state != STATE_ACTIVE_S) {
1082 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1083 __func__, priv->state);
1084 return -EINVAL;
1085 }
1086 /*
1087 * Get High Sampling Rate mode
1088 * slave Bank Addr Bit Signal name
1089 * <SLV-T> A0h 10h [0] ITRL_LOCK
1090 */
1091 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1092 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1093 if (data[0] & 0x01) {
1094 /*
1095 * slave Bank Addr Bit Signal name
1096 * <SLV-T> A0h 50h [4] IHSMODE
1097 */
1098 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1099 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1100 } else {
1101 dev_dbg(&priv->i2c->dev,
1102 "%s(): unable to detect sampling rate mode\n",
1103 __func__);
1104 return -EINVAL;
1105 }
1106 /*
1107 * slave Bank Addr Bit Signal name
1108 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
1109 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
1110 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
1111 */
1112 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1113 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1114 (((u32)data[1] & 0xFF) << 8) |
1115 ((u32)data[2] & 0xFF), 20);
1116 temp_div = (is_hs_mode ? 1048576 : 1572864);
1117 if (cfrl_ctrlval > 0) {
1118 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1119 temp_div, &temp_r);
1120 } else {
1121 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1122 temp_div, &temp_r);
1123 }
1124 if (temp_r >= temp_div / 2)
1125 temp_q++;
1126 if (cfrl_ctrlval > 0)
1127 temp_q *= -1;
1128 *offset = temp_q;
1129 return 0;
1130 }
1131
1132 static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1133 u32 bandwidth, int *offset)
1134 {
1135 u8 data[4];
1136
1137 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1138 if (priv->state != STATE_ACTIVE_TC) {
1139 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1140 __func__, priv->state);
1141 return -EINVAL;
1142 }
1143 if (priv->system != SYS_ISDBT) {
1144 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1145 __func__, priv->system);
1146 return -EINVAL;
1147 }
1148 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1149 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1150 *offset = -1 * sign_extend32(
1151 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1152 ((u32)data[2] << 8) | (u32)data[3], 29);
1153
1154 switch (bandwidth) {
1155 case 6000000:
1156 *offset = -1 * ((*offset) * 8/264);
1157 break;
1158 case 7000000:
1159 *offset = -1 * ((*offset) * 8/231);
1160 break;
1161 case 8000000:
1162 *offset = -1 * ((*offset) * 8/198);
1163 break;
1164 default:
1165 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1166 __func__, bandwidth);
1167 return -EINVAL;
1168 }
1169
1170 dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1171 __func__, bandwidth, *offset);
1172
1173 return 0;
1174 }
1175
1176 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1177 u32 bandwidth, int *offset)
1178 {
1179 u8 data[4];
1180
1181 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1182 if (priv->state != STATE_ACTIVE_TC) {
1183 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1184 __func__, priv->state);
1185 return -EINVAL;
1186 }
1187 if (priv->system != SYS_DVBT) {
1188 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1189 __func__, priv->system);
1190 return -EINVAL;
1191 }
1192 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1193 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1194 *offset = -1 * sign_extend32(
1195 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1196 ((u32)data[2] << 8) | (u32)data[3], 29);
1197 *offset *= (bandwidth / 1000000);
1198 *offset /= 235;
1199 return 0;
1200 }
1201
1202 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1203 u32 bandwidth, int *offset)
1204 {
1205 u8 data[4];
1206
1207 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1208 if (priv->state != STATE_ACTIVE_TC) {
1209 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1210 __func__, priv->state);
1211 return -EINVAL;
1212 }
1213 if (priv->system != SYS_DVBT2) {
1214 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1215 __func__, priv->system);
1216 return -EINVAL;
1217 }
1218 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1219 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1220 *offset = -1 * sign_extend32(
1221 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1222 ((u32)data[2] << 8) | (u32)data[3], 27);
1223 switch (bandwidth) {
1224 case 1712000:
1225 *offset /= 582;
1226 break;
1227 case 5000000:
1228 case 6000000:
1229 case 7000000:
1230 case 8000000:
1231 *offset *= (bandwidth / 1000000);
1232 *offset /= 940;
1233 break;
1234 default:
1235 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1236 __func__, bandwidth);
1237 return -EINVAL;
1238 }
1239 return 0;
1240 }
1241
1242 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1243 int *offset)
1244 {
1245 u8 data[2];
1246
1247 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1248 if (priv->state != STATE_ACTIVE_TC) {
1249 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1250 __func__, priv->state);
1251 return -EINVAL;
1252 }
1253 if (priv->system != SYS_DVBC_ANNEX_A) {
1254 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1255 __func__, priv->system);
1256 return -EINVAL;
1257 }
1258 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1259 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1260 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1261 | (u32)data[1], 13), 16384);
1262 return 0;
1263 }
1264
1265 static int cxd2841er_read_packet_errors_t(
1266 struct cxd2841er_priv *priv, u32 *penum)
1267 {
1268 u8 data[3];
1269
1270 *penum = 0;
1271 if (priv->state != STATE_ACTIVE_TC) {
1272 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1273 __func__, priv->state);
1274 return -EINVAL;
1275 }
1276 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1277 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1278 if (data[2] & 0x01)
1279 *penum = ((u32)data[0] << 8) | (u32)data[1];
1280 return 0;
1281 }
1282
1283 static int cxd2841er_read_packet_errors_t2(
1284 struct cxd2841er_priv *priv, u32 *penum)
1285 {
1286 u8 data[3];
1287
1288 *penum = 0;
1289 if (priv->state != STATE_ACTIVE_TC) {
1290 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1291 __func__, priv->state);
1292 return -EINVAL;
1293 }
1294 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1295 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1296 if (data[0] & 0x01)
1297 *penum = ((u32)data[1] << 8) | (u32)data[2];
1298 return 0;
1299 }
1300
1301 static int cxd2841er_read_packet_errors_i(
1302 struct cxd2841er_priv *priv, u32 *penum)
1303 {
1304 u8 data[2];
1305
1306 *penum = 0;
1307 if (priv->state != STATE_ACTIVE_TC) {
1308 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1309 __func__, priv->state);
1310 return -EINVAL;
1311 }
1312 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1313 cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1314
1315 if (!(data[0] & 0x01))
1316 return 0;
1317
1318 /* Layer A */
1319 cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1320 *penum = ((u32)data[0] << 8) | (u32)data[1];
1321
1322 /* Layer B */
1323 cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1324 *penum += ((u32)data[0] << 8) | (u32)data[1];
1325
1326 /* Layer C */
1327 cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1328 *penum += ((u32)data[0] << 8) | (u32)data[1];
1329
1330 return 0;
1331 }
1332
1333 static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
1334 u32 *bit_error, u32 *bit_count)
1335 {
1336 u8 data[11];
1337
1338 /* Set SLV-T Bank : 0xA0 */
1339 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1340 /*
1341 * slave Bank Addr Bit Signal name
1342 * <SLV-T> A0h 35h [0] IFVBER_VALID
1343 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1344 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1345 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1346 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1347 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1348 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1349 */
1350 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1351 if (data[0] & 0x01) {
1352 *bit_error = ((u32)(data[1] & 0x3F) << 16) |
1353 ((u32)(data[2] & 0xFF) << 8) |
1354 (u32)(data[3] & 0xFF);
1355 *bit_count = ((u32)(data[8] & 0x3F) << 16) |
1356 ((u32)(data[9] & 0xFF) << 8) |
1357 (u32)(data[10] & 0xFF);
1358 if ((*bit_count == 0) || (*bit_error > *bit_count)) {
1359 dev_dbg(&priv->i2c->dev,
1360 "%s(): invalid bit_error %d, bit_count %d\n",
1361 __func__, *bit_error, *bit_count);
1362 return -EINVAL;
1363 }
1364 return 0;
1365 }
1366 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1367 return -EINVAL;
1368 }
1369
1370
1371 static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
1372 u32 *bit_error, u32 *bit_count)
1373 {
1374 u8 data[5];
1375 u32 period;
1376
1377 /* Set SLV-T Bank : 0xB2 */
1378 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1379 /*
1380 * slave Bank Addr Bit Signal name
1381 * <SLV-T> B2h 30h [0] IFLBER_VALID
1382 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1383 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1384 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1385 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1386 */
1387 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1388 if (data[0] & 0x01) {
1389 /* Bit error count */
1390 *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1391 ((u32)(data[2] & 0xFF) << 16) |
1392 ((u32)(data[3] & 0xFF) << 8) |
1393 (u32)(data[4] & 0xFF);
1394
1395 /* Set SLV-T Bank : 0xA0 */
1396 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1397 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1398 /* Measurement period */
1399 period = (u32)(1 << (data[0] & 0x0F));
1400 if (period == 0) {
1401 dev_dbg(&priv->i2c->dev,
1402 "%s(): period is 0\n", __func__);
1403 return -EINVAL;
1404 }
1405 if (*bit_error > (period * 64800)) {
1406 dev_dbg(&priv->i2c->dev,
1407 "%s(): invalid bit_err 0x%x period 0x%x\n",
1408 __func__, *bit_error, period);
1409 return -EINVAL;
1410 }
1411 *bit_count = period * 64800;
1412
1413 return 0;
1414 } else {
1415 dev_dbg(&priv->i2c->dev,
1416 "%s(): no data available\n", __func__);
1417 }
1418 return -EINVAL;
1419 }
1420
1421 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
1422 u32 *bit_error, u32 *bit_count)
1423 {
1424 u8 data[4];
1425 u32 period_exp, n_ldpc;
1426
1427 if (priv->state != STATE_ACTIVE_TC) {
1428 dev_dbg(&priv->i2c->dev,
1429 "%s(): invalid state %d\n", __func__, priv->state);
1430 return -EINVAL;
1431 }
1432 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1433 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1434 if (!(data[0] & 0x10)) {
1435 dev_dbg(&priv->i2c->dev,
1436 "%s(): no valid BER data\n", __func__);
1437 return -EINVAL;
1438 }
1439 *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1440 ((u32)data[1] << 16) |
1441 ((u32)data[2] << 8) |
1442 (u32)data[3];
1443 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1444 period_exp = data[0] & 0x0f;
1445 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1446 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1447 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1448 if (*bit_error > ((1U << period_exp) * n_ldpc)) {
1449 dev_dbg(&priv->i2c->dev,
1450 "%s(): invalid BER value\n", __func__);
1451 return -EINVAL;
1452 }
1453
1454 /*
1455 * FIXME: the right thing would be to return bit_error untouched,
1456 * but, as we don't know the scale returned by the counters, let's
1457 * at least preserver BER = bit_error/bit_count.
1458 */
1459 if (period_exp >= 4) {
1460 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
1461 *bit_error *= 3125ULL;
1462 } else {
1463 *bit_count = (1U << period_exp) * (n_ldpc / 200);
1464 *bit_error *= 50000ULL;;
1465 }
1466 return 0;
1467 }
1468
1469 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
1470 u32 *bit_error, u32 *bit_count)
1471 {
1472 u8 data[2];
1473 u32 period;
1474
1475 if (priv->state != STATE_ACTIVE_TC) {
1476 dev_dbg(&priv->i2c->dev,
1477 "%s(): invalid state %d\n", __func__, priv->state);
1478 return -EINVAL;
1479 }
1480 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1481 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1482 if (!(data[0] & 0x01)) {
1483 dev_dbg(&priv->i2c->dev,
1484 "%s(): no valid BER data\n", __func__);
1485 return 0;
1486 }
1487 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1488 *bit_error = ((u32)data[0] << 8) | (u32)data[1];
1489 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1490 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1491
1492 /*
1493 * FIXME: the right thing would be to return bit_error untouched,
1494 * but, as we don't know the scale returned by the counters, let's
1495 * at least preserver BER = bit_error/bit_count.
1496 */
1497 *bit_count = period / 128;
1498 *bit_error *= 78125ULL;
1499 return 0;
1500 }
1501
1502 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys)
1503 {
1504 u8 data[3];
1505 u32 res = 0, value;
1506 int min_index, max_index, index;
1507 static const struct cxd2841er_cnr_data *cn_data;
1508
1509 /* Set SLV-T Bank : 0xA1 */
1510 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1511 /*
1512 * slave Bank Addr Bit Signal name
1513 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1514 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1515 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1516 */
1517 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1518 if (data[0] & 0x01) {
1519 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1520 min_index = 0;
1521 if (delsys == SYS_DVBS) {
1522 cn_data = s_cn_data;
1523 max_index = sizeof(s_cn_data) /
1524 sizeof(s_cn_data[0]) - 1;
1525 } else {
1526 cn_data = s2_cn_data;
1527 max_index = sizeof(s2_cn_data) /
1528 sizeof(s2_cn_data[0]) - 1;
1529 }
1530 if (value >= cn_data[min_index].value) {
1531 res = cn_data[min_index].cnr_x1000;
1532 goto done;
1533 }
1534 if (value <= cn_data[max_index].value) {
1535 res = cn_data[max_index].cnr_x1000;
1536 goto done;
1537 }
1538 while ((max_index - min_index) > 1) {
1539 index = (max_index + min_index) / 2;
1540 if (value == cn_data[index].value) {
1541 res = cn_data[index].cnr_x1000;
1542 goto done;
1543 } else if (value > cn_data[index].value)
1544 max_index = index;
1545 else
1546 min_index = index;
1547 if ((max_index - min_index) <= 1) {
1548 if (value == cn_data[max_index].value) {
1549 res = cn_data[max_index].cnr_x1000;
1550 goto done;
1551 } else {
1552 res = cn_data[min_index].cnr_x1000;
1553 goto done;
1554 }
1555 }
1556 }
1557 } else {
1558 dev_dbg(&priv->i2c->dev,
1559 "%s(): no data available\n", __func__);
1560 }
1561 done:
1562 return res;
1563 }
1564
1565 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1566 {
1567 u32 reg;
1568 u8 data[2];
1569
1570 *snr = 0;
1571 if (priv->state != STATE_ACTIVE_TC) {
1572 dev_dbg(&priv->i2c->dev,
1573 "%s(): invalid state %d\n", __func__, priv->state);
1574 return -EINVAL;
1575 }
1576 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1577 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1578 reg = ((u32)data[0] << 8) | (u32)data[1];
1579 if (reg == 0) {
1580 dev_dbg(&priv->i2c->dev,
1581 "%s(): reg value out of range\n", __func__);
1582 return 0;
1583 }
1584 if (reg > 4996)
1585 reg = 4996;
1586 *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1587 return 0;
1588 }
1589
1590 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1591 {
1592 u32 reg;
1593 u8 data[2];
1594
1595 *snr = 0;
1596 if (priv->state != STATE_ACTIVE_TC) {
1597 dev_dbg(&priv->i2c->dev,
1598 "%s(): invalid state %d\n", __func__, priv->state);
1599 return -EINVAL;
1600 }
1601 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1602 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1603 reg = ((u32)data[0] << 8) | (u32)data[1];
1604 if (reg == 0) {
1605 dev_dbg(&priv->i2c->dev,
1606 "%s(): reg value out of range\n", __func__);
1607 return 0;
1608 }
1609 if (reg > 10876)
1610 reg = 10876;
1611 *snr = 10000 * ((intlog10(reg) -
1612 intlog10(12600 - reg)) >> 24) + 32000;
1613 return 0;
1614 }
1615
1616 static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1617 {
1618 u32 reg;
1619 u8 data[2];
1620
1621 *snr = 0;
1622 if (priv->state != STATE_ACTIVE_TC) {
1623 dev_dbg(&priv->i2c->dev,
1624 "%s(): invalid state %d\n", __func__,
1625 priv->state);
1626 return -EINVAL;
1627 }
1628
1629 /* Freeze all registers */
1630 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1631
1632
1633 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1634 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1635 reg = ((u32)data[0] << 8) | (u32)data[1];
1636 if (reg == 0) {
1637 dev_dbg(&priv->i2c->dev,
1638 "%s(): reg value out of range\n", __func__);
1639 return 0;
1640 }
1641 if (reg > 4996)
1642 reg = 4996;
1643 *snr = 100 * intlog10(reg) - 9031;
1644 return 0;
1645 }
1646
1647 static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1648 u8 delsys)
1649 {
1650 u8 data[2];
1651
1652 cxd2841er_write_reg(
1653 priv, I2C_SLVT, 0x00, 0x40);
1654 cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1655 dev_dbg(&priv->i2c->dev,
1656 "%s(): AGC value=%u\n",
1657 __func__, (((u16)data[0] & 0x0F) << 8) |
1658 (u16)(data[1] & 0xFF));
1659 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1660 }
1661
1662 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1663 u8 delsys)
1664 {
1665 u8 data[2];
1666
1667 cxd2841er_write_reg(
1668 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1669 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1670 dev_dbg(&priv->i2c->dev,
1671 "%s(): AGC value=%u\n",
1672 __func__, (((u16)data[0] & 0x0F) << 8) |
1673 (u16)(data[1] & 0xFF));
1674 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1675 }
1676
1677 static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1678 u8 delsys)
1679 {
1680 u8 data[2];
1681
1682 cxd2841er_write_reg(
1683 priv, I2C_SLVT, 0x00, 0x60);
1684 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1685
1686 dev_dbg(&priv->i2c->dev,
1687 "%s(): AGC value=%u\n",
1688 __func__, (((u16)data[0] & 0x0F) << 8) |
1689 (u16)(data[1] & 0xFF));
1690 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1691 }
1692
1693 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1694 {
1695 u8 data[2];
1696
1697 /* Set SLV-T Bank : 0xA0 */
1698 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1699 /*
1700 * slave Bank Addr Bit Signal name
1701 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1702 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1703 */
1704 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1705 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1706 }
1707
1708 static void cxd2841er_read_ber(struct dvb_frontend *fe)
1709 {
1710 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1711 struct cxd2841er_priv *priv = fe->demodulator_priv;
1712 u32 ret, bit_error = 0, bit_count = 0;
1713
1714 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1715 switch (p->delivery_system) {
1716 case SYS_DVBS:
1717 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
1718 break;
1719 case SYS_DVBS2:
1720 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
1721 break;
1722 case SYS_DVBT:
1723 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
1724 break;
1725 case SYS_DVBT2:
1726 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
1727 break;
1728 default:
1729 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1730 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1731 return;
1732 }
1733
1734 if (!ret) {
1735 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1736 p->post_bit_error.stat[0].uvalue = bit_error;
1737 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1738 p->post_bit_count.stat[0].uvalue = bit_count;
1739 } else {
1740 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1741 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1742 }
1743 }
1744
1745 static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
1746 {
1747 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1748 struct cxd2841er_priv *priv = fe->demodulator_priv;
1749 s32 strength;
1750
1751 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1752 switch (p->delivery_system) {
1753 case SYS_DVBC_ANNEX_B:
1754 case SYS_DVBC_ANNEX_C:
1755 strength = 65535 - cxd2841er_read_agc_gain_c(
1756 priv, p->delivery_system);
1757 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1758 p->strength.stat[0].uvalue = strength;
1759 break;
1760 case SYS_DVBT:
1761 case SYS_DVBT2:
1762 strength = cxd2841er_read_agc_gain_t_t2(priv,
1763 p->delivery_system);
1764 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1765 /* Formula was empirically determinated @ 410 MHz */
1766 p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
1767 break; /* Code moved out of the function */
1768 case SYS_DVBC_ANNEX_A:
1769 strength = cxd2841er_read_agc_gain_t_t2(priv,
1770 p->delivery_system);
1771 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1772 /*
1773 * Formula was empirically determinated via linear regression,
1774 * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
1775 * stream modulated with QAM64
1776 */
1777 p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
1778 break;
1779 case SYS_ISDBT:
1780 strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
1781 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1782 /*
1783 * Formula was empirically determinated via linear regression,
1784 * using frequencies: 175 MHz, 410 MHz and 800 MHz.
1785 */
1786 p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
1787 break;
1788 case SYS_DVBS:
1789 case SYS_DVBS2:
1790 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1791 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1792 p->strength.stat[0].uvalue = strength;
1793 break;
1794 default:
1795 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1796 break;
1797 }
1798 }
1799
1800 static void cxd2841er_read_snr(struct dvb_frontend *fe)
1801 {
1802 u32 tmp = 0;
1803 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1804 struct cxd2841er_priv *priv = fe->demodulator_priv;
1805
1806 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1807 switch (p->delivery_system) {
1808 case SYS_DVBT:
1809 cxd2841er_read_snr_t(priv, &tmp);
1810 break;
1811 case SYS_DVBT2:
1812 cxd2841er_read_snr_t2(priv, &tmp);
1813 break;
1814 case SYS_ISDBT:
1815 cxd2841er_read_snr_i(priv, &tmp);
1816 break;
1817 case SYS_DVBS:
1818 case SYS_DVBS2:
1819 tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system);
1820 break;
1821 default:
1822 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1823 __func__, p->delivery_system);
1824 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1825 return;
1826 }
1827
1828 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1829 p->cnr.stat[0].svalue = tmp;
1830 }
1831
1832 static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
1833 {
1834 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1835 struct cxd2841er_priv *priv = fe->demodulator_priv;
1836 u32 ucblocks;
1837
1838 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1839 switch (p->delivery_system) {
1840 case SYS_DVBT:
1841 cxd2841er_read_packet_errors_t(priv, &ucblocks);
1842 break;
1843 case SYS_DVBT2:
1844 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
1845 break;
1846 case SYS_ISDBT:
1847 cxd2841er_read_packet_errors_i(priv, &ucblocks);
1848 break;
1849 default:
1850 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1851 return;
1852 }
1853 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1854
1855 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
1856 p->block_error.stat[0].uvalue = ucblocks;
1857 }
1858
1859 static int cxd2841er_dvbt2_set_profile(
1860 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
1861 {
1862 u8 tune_mode;
1863 u8 seq_not2d_time;
1864
1865 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1866 switch (profile) {
1867 case DVBT2_PROFILE_BASE:
1868 tune_mode = 0x01;
1869 /* Set early unlock time */
1870 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
1871 break;
1872 case DVBT2_PROFILE_LITE:
1873 tune_mode = 0x05;
1874 /* Set early unlock time */
1875 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
1876 break;
1877 case DVBT2_PROFILE_ANY:
1878 tune_mode = 0x00;
1879 /* Set early unlock time */
1880 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
1881 break;
1882 default:
1883 return -EINVAL;
1884 }
1885 /* Set SLV-T Bank : 0x2E */
1886 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
1887 /* Set profile and tune mode */
1888 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
1889 /* Set SLV-T Bank : 0x2B */
1890 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1891 /* Set early unlock detection time */
1892 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
1893 return 0;
1894 }
1895
1896 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
1897 u8 is_auto, u8 plp_id)
1898 {
1899 if (is_auto) {
1900 dev_dbg(&priv->i2c->dev,
1901 "%s() using auto PLP selection\n", __func__);
1902 } else {
1903 dev_dbg(&priv->i2c->dev,
1904 "%s() using manual PLP selection, ID %d\n",
1905 __func__, plp_id);
1906 }
1907 /* Set SLV-T Bank : 0x23 */
1908 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
1909 if (!is_auto) {
1910 /* Manual PLP selection mode. Set the data PLP Id. */
1911 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
1912 }
1913 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1914 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
1915 return 0;
1916 }
1917
1918 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
1919 u32 bandwidth)
1920 {
1921 u32 iffreq;
1922 u8 data[MAX_WRITE_REGSIZE];
1923
1924 const uint8_t nominalRate8bw[3][5] = {
1925 /* TRCG Nominal Rate [37:0] */
1926 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1927 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1928 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
1929 };
1930
1931 const uint8_t nominalRate7bw[3][5] = {
1932 /* TRCG Nominal Rate [37:0] */
1933 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1934 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1935 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
1936 };
1937
1938 const uint8_t nominalRate6bw[3][5] = {
1939 /* TRCG Nominal Rate [37:0] */
1940 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
1941 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1942 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
1943 };
1944
1945 const uint8_t nominalRate5bw[3][5] = {
1946 /* TRCG Nominal Rate [37:0] */
1947 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
1948 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
1949 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
1950 };
1951
1952 const uint8_t nominalRate17bw[3][5] = {
1953 /* TRCG Nominal Rate [37:0] */
1954 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
1955 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
1956 {0x58, 0xE2, 0xAF, 0xE0, 0xBC} /* 41MHz XTal */
1957 };
1958
1959 const uint8_t itbCoef8bw[3][14] = {
1960 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
1961 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
1962 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
1963 0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
1964 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
1965 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
1966 };
1967
1968 const uint8_t itbCoef7bw[3][14] = {
1969 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
1970 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
1971 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
1972 0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
1973 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
1974 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
1975 };
1976
1977 const uint8_t itbCoef6bw[3][14] = {
1978 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1979 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1980 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
1981 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
1982 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1983 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
1984 };
1985
1986 const uint8_t itbCoef5bw[3][14] = {
1987 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1988 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1989 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
1990 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
1991 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1992 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
1993 };
1994
1995 const uint8_t itbCoef17bw[3][14] = {
1996 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
1997 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
1998 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
1999 0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal */
2000 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2001 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99} /* 41MHz XTal */
2002 };
2003
2004 /* Set SLV-T Bank : 0x20 */
2005 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2006
2007 switch (bandwidth) {
2008 case 8000000:
2009 /* <Timing Recovery setting> */
2010 cxd2841er_write_regs(priv, I2C_SLVT,
2011 0x9F, nominalRate8bw[priv->xtal], 5);
2012
2013 /* Set SLV-T Bank : 0x27 */
2014 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2015 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2016 0x7a, 0x00, 0x0f);
2017
2018 /* Set SLV-T Bank : 0x10 */
2019 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2020
2021 /* Group delay equaliser settings for
2022 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2023 */
2024 cxd2841er_write_regs(priv, I2C_SLVT,
2025 0xA6, itbCoef8bw[priv->xtal], 14);
2026 /* <IF freq setting> */
2027 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2028 data[0] = (u8) ((iffreq >> 16) & 0xff);
2029 data[1] = (u8)((iffreq >> 8) & 0xff);
2030 data[2] = (u8)(iffreq & 0xff);
2031 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2032 /* System bandwidth setting */
2033 cxd2841er_set_reg_bits(
2034 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2035 break;
2036 case 7000000:
2037 /* <Timing Recovery setting> */
2038 cxd2841er_write_regs(priv, I2C_SLVT,
2039 0x9F, nominalRate7bw[priv->xtal], 5);
2040
2041 /* Set SLV-T Bank : 0x27 */
2042 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2043 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2044 0x7a, 0x00, 0x0f);
2045
2046 /* Set SLV-T Bank : 0x10 */
2047 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2048
2049 /* Group delay equaliser settings for
2050 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2051 */
2052 cxd2841er_write_regs(priv, I2C_SLVT,
2053 0xA6, itbCoef7bw[priv->xtal], 14);
2054 /* <IF freq setting> */
2055 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2056 data[0] = (u8) ((iffreq >> 16) & 0xff);
2057 data[1] = (u8)((iffreq >> 8) & 0xff);
2058 data[2] = (u8)(iffreq & 0xff);
2059 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2060 /* System bandwidth setting */
2061 cxd2841er_set_reg_bits(
2062 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2063 break;
2064 case 6000000:
2065 /* <Timing Recovery setting> */
2066 cxd2841er_write_regs(priv, I2C_SLVT,
2067 0x9F, nominalRate6bw[priv->xtal], 5);
2068
2069 /* Set SLV-T Bank : 0x27 */
2070 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2071 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2072 0x7a, 0x00, 0x0f);
2073
2074 /* Set SLV-T Bank : 0x10 */
2075 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2076
2077 /* Group delay equaliser settings for
2078 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2079 */
2080 cxd2841er_write_regs(priv, I2C_SLVT,
2081 0xA6, itbCoef6bw[priv->xtal], 14);
2082 /* <IF freq setting> */
2083 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2084 data[0] = (u8) ((iffreq >> 16) & 0xff);
2085 data[1] = (u8)((iffreq >> 8) & 0xff);
2086 data[2] = (u8)(iffreq & 0xff);
2087 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2088 /* System bandwidth setting */
2089 cxd2841er_set_reg_bits(
2090 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2091 break;
2092 case 5000000:
2093 /* <Timing Recovery setting> */
2094 cxd2841er_write_regs(priv, I2C_SLVT,
2095 0x9F, nominalRate5bw[priv->xtal], 5);
2096
2097 /* Set SLV-T Bank : 0x27 */
2098 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2099 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2100 0x7a, 0x00, 0x0f);
2101
2102 /* Set SLV-T Bank : 0x10 */
2103 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2104
2105 /* Group delay equaliser settings for
2106 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2107 */
2108 cxd2841er_write_regs(priv, I2C_SLVT,
2109 0xA6, itbCoef5bw[priv->xtal], 14);
2110 /* <IF freq setting> */
2111 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2112 data[0] = (u8) ((iffreq >> 16) & 0xff);
2113 data[1] = (u8)((iffreq >> 8) & 0xff);
2114 data[2] = (u8)(iffreq & 0xff);
2115 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2116 /* System bandwidth setting */
2117 cxd2841er_set_reg_bits(
2118 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2119 break;
2120 case 1712000:
2121 /* <Timing Recovery setting> */
2122 cxd2841er_write_regs(priv, I2C_SLVT,
2123 0x9F, nominalRate17bw[priv->xtal], 5);
2124
2125 /* Set SLV-T Bank : 0x27 */
2126 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2127 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2128 0x7a, 0x03, 0x0f);
2129
2130 /* Set SLV-T Bank : 0x10 */
2131 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2132
2133 /* Group delay equaliser settings for
2134 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2135 */
2136 cxd2841er_write_regs(priv, I2C_SLVT,
2137 0xA6, itbCoef17bw[priv->xtal], 14);
2138 /* <IF freq setting> */
2139 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.50);
2140 data[0] = (u8) ((iffreq >> 16) & 0xff);
2141 data[1] = (u8)((iffreq >> 8) & 0xff);
2142 data[2] = (u8)(iffreq & 0xff);
2143 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2144 /* System bandwidth setting */
2145 cxd2841er_set_reg_bits(
2146 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
2147 break;
2148 default:
2149 return -EINVAL;
2150 }
2151 return 0;
2152 }
2153
2154 static int cxd2841er_sleep_tc_to_active_t_band(
2155 struct cxd2841er_priv *priv, u32 bandwidth)
2156 {
2157 u8 data[MAX_WRITE_REGSIZE];
2158 u32 iffreq;
2159 u8 nominalRate8bw[3][5] = {
2160 /* TRCG Nominal Rate [37:0] */
2161 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2162 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2163 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
2164 };
2165 u8 nominalRate7bw[3][5] = {
2166 /* TRCG Nominal Rate [37:0] */
2167 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2168 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2169 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
2170 };
2171 u8 nominalRate6bw[3][5] = {
2172 /* TRCG Nominal Rate [37:0] */
2173 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2174 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2175 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
2176 };
2177 u8 nominalRate5bw[3][5] = {
2178 /* TRCG Nominal Rate [37:0] */
2179 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2180 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2181 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
2182 };
2183
2184 u8 itbCoef8bw[3][14] = {
2185 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2186 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2187 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2188 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
2189 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2190 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
2191 };
2192 u8 itbCoef7bw[3][14] = {
2193 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2194 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2195 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2196 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
2197 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2198 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
2199 };
2200 u8 itbCoef6bw[3][14] = {
2201 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2202 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2203 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2204 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2205 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2206 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2207 };
2208 u8 itbCoef5bw[3][14] = {
2209 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2210 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2211 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2212 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2213 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2214 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2215 };
2216
2217 /* Set SLV-T Bank : 0x13 */
2218 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2219 /* Echo performance optimization setting */
2220 data[0] = 0x01;
2221 data[1] = 0x14;
2222 cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2223
2224 /* Set SLV-T Bank : 0x10 */
2225 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2226
2227 switch (bandwidth) {
2228 case 8000000:
2229 /* <Timing Recovery setting> */
2230 cxd2841er_write_regs(priv, I2C_SLVT,
2231 0x9F, nominalRate8bw[priv->xtal], 5);
2232 /* Group delay equaliser settings for
2233 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2234 */
2235 cxd2841er_write_regs(priv, I2C_SLVT,
2236 0xA6, itbCoef8bw[priv->xtal], 14);
2237 /* <IF freq setting> */
2238 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2239 data[0] = (u8) ((iffreq >> 16) & 0xff);
2240 data[1] = (u8)((iffreq >> 8) & 0xff);
2241 data[2] = (u8)(iffreq & 0xff);
2242 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2243 /* System bandwidth setting */
2244 cxd2841er_set_reg_bits(
2245 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2246
2247 /* Demod core latency setting */
2248 if (priv->xtal == SONY_XTAL_24000) {
2249 data[0] = 0x15;
2250 data[1] = 0x28;
2251 } else {
2252 data[0] = 0x01;
2253 data[1] = 0xE0;
2254 }
2255 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2256
2257 /* Notch filter setting */
2258 data[0] = 0x01;
2259 data[1] = 0x02;
2260 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2261 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2262 break;
2263 case 7000000:
2264 /* <Timing Recovery setting> */
2265 cxd2841er_write_regs(priv, I2C_SLVT,
2266 0x9F, nominalRate7bw[priv->xtal], 5);
2267 /* Group delay equaliser settings for
2268 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2269 */
2270 cxd2841er_write_regs(priv, I2C_SLVT,
2271 0xA6, itbCoef7bw[priv->xtal], 14);
2272 /* <IF freq setting> */
2273 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2274 data[0] = (u8) ((iffreq >> 16) & 0xff);
2275 data[1] = (u8)((iffreq >> 8) & 0xff);
2276 data[2] = (u8)(iffreq & 0xff);
2277 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2278 /* System bandwidth setting */
2279 cxd2841er_set_reg_bits(
2280 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2281
2282 /* Demod core latency setting */
2283 if (priv->xtal == SONY_XTAL_24000) {
2284 data[0] = 0x1F;
2285 data[1] = 0xF8;
2286 } else {
2287 data[0] = 0x12;
2288 data[1] = 0xF8;
2289 }
2290 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2291
2292 /* Notch filter setting */
2293 data[0] = 0x00;
2294 data[1] = 0x03;
2295 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2296 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2297 break;
2298 case 6000000:
2299 /* <Timing Recovery setting> */
2300 cxd2841er_write_regs(priv, I2C_SLVT,
2301 0x9F, nominalRate6bw[priv->xtal], 5);
2302 /* Group delay equaliser settings for
2303 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2304 */
2305 cxd2841er_write_regs(priv, I2C_SLVT,
2306 0xA6, itbCoef6bw[priv->xtal], 14);
2307 /* <IF freq setting> */
2308 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2309 data[0] = (u8) ((iffreq >> 16) & 0xff);
2310 data[1] = (u8)((iffreq >> 8) & 0xff);
2311 data[2] = (u8)(iffreq & 0xff);
2312 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2313 /* System bandwidth setting */
2314 cxd2841er_set_reg_bits(
2315 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2316
2317 /* Demod core latency setting */
2318 if (priv->xtal == SONY_XTAL_24000) {
2319 data[0] = 0x25;
2320 data[1] = 0x4C;
2321 } else {
2322 data[0] = 0x1F;
2323 data[1] = 0xDC;
2324 }
2325 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2326
2327 /* Notch filter setting */
2328 data[0] = 0x00;
2329 data[1] = 0x03;
2330 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2331 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2332 break;
2333 case 5000000:
2334 /* <Timing Recovery setting> */
2335 cxd2841er_write_regs(priv, I2C_SLVT,
2336 0x9F, nominalRate5bw[priv->xtal], 5);
2337 /* Group delay equaliser settings for
2338 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2339 */
2340 cxd2841er_write_regs(priv, I2C_SLVT,
2341 0xA6, itbCoef5bw[priv->xtal], 14);
2342 /* <IF freq setting> */
2343 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2344 data[0] = (u8) ((iffreq >> 16) & 0xff);
2345 data[1] = (u8)((iffreq >> 8) & 0xff);
2346 data[2] = (u8)(iffreq & 0xff);
2347 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2348 /* System bandwidth setting */
2349 cxd2841er_set_reg_bits(
2350 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2351
2352 /* Demod core latency setting */
2353 if (priv->xtal == SONY_XTAL_24000) {
2354 data[0] = 0x2C;
2355 data[1] = 0xC2;
2356 } else {
2357 data[0] = 0x26;
2358 data[1] = 0x3C;
2359 }
2360 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2361
2362 /* Notch filter setting */
2363 data[0] = 0x00;
2364 data[1] = 0x03;
2365 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2366 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2367 break;
2368 }
2369
2370 return 0;
2371 }
2372
2373 static int cxd2841er_sleep_tc_to_active_i_band(
2374 struct cxd2841er_priv *priv, u32 bandwidth)
2375 {
2376 u32 iffreq;
2377 u8 data[3];
2378
2379 /* TRCG Nominal Rate */
2380 u8 nominalRate8bw[3][5] = {
2381 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2382 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2383 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2384 };
2385
2386 u8 nominalRate7bw[3][5] = {
2387 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2388 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2389 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2390 };
2391
2392 u8 nominalRate6bw[3][5] = {
2393 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2394 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2395 {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
2396 };
2397
2398 u8 itbCoef8bw[3][14] = {
2399 {0x00}, /* 20.5MHz XTal */
2400 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2401 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2402 {0x0}, /* 41MHz XTal */
2403 };
2404
2405 u8 itbCoef7bw[3][14] = {
2406 {0x00}, /* 20.5MHz XTal */
2407 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2408 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2409 {0x00}, /* 41MHz XTal */
2410 };
2411
2412 u8 itbCoef6bw[3][14] = {
2413 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2414 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2415 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2416 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
2417 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2418 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
2419 };
2420
2421 dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2422 /* Set SLV-T Bank : 0x10 */
2423 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2424
2425 /* 20.5/41MHz Xtal support is not available
2426 * on ISDB-T 7MHzBW and 8MHzBW
2427 */
2428 if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2429 dev_err(&priv->i2c->dev,
2430 "%s(): bandwidth %d supported only for 24MHz xtal\n",
2431 __func__, bandwidth);
2432 return -EINVAL;
2433 }
2434
2435 switch (bandwidth) {
2436 case 8000000:
2437 /* TRCG Nominal Rate */
2438 cxd2841er_write_regs(priv, I2C_SLVT,
2439 0x9F, nominalRate8bw[priv->xtal], 5);
2440 /* Group delay equaliser settings for ASCOT tuners optimized */
2441 cxd2841er_write_regs(priv, I2C_SLVT,
2442 0xA6, itbCoef8bw[priv->xtal], 14);
2443
2444 /* IF freq setting */
2445 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75);
2446 data[0] = (u8) ((iffreq >> 16) & 0xff);
2447 data[1] = (u8)((iffreq >> 8) & 0xff);
2448 data[2] = (u8)(iffreq & 0xff);
2449 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2450
2451 /* System bandwidth setting */
2452 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2453
2454 /* Demod core latency setting */
2455 data[0] = 0x13;
2456 data[1] = 0xFC;
2457 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2458
2459 /* Acquisition optimization setting */
2460 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2461 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2462 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2463 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2464 break;
2465 case 7000000:
2466 /* TRCG Nominal Rate */
2467 cxd2841er_write_regs(priv, I2C_SLVT,
2468 0x9F, nominalRate7bw[priv->xtal], 5);
2469 /* Group delay equaliser settings for ASCOT tuners optimized */
2470 cxd2841er_write_regs(priv, I2C_SLVT,
2471 0xA6, itbCoef7bw[priv->xtal], 14);
2472
2473 /* IF freq setting */
2474 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15);
2475 data[0] = (u8) ((iffreq >> 16) & 0xff);
2476 data[1] = (u8)((iffreq >> 8) & 0xff);
2477 data[2] = (u8)(iffreq & 0xff);
2478 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2479
2480 /* System bandwidth setting */
2481 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2482
2483 /* Demod core latency setting */
2484 data[0] = 0x1A;
2485 data[1] = 0xFA;
2486 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2487
2488 /* Acquisition optimization setting */
2489 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2490 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2491 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2492 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2493 break;
2494 case 6000000:
2495 /* TRCG Nominal Rate */
2496 cxd2841er_write_regs(priv, I2C_SLVT,
2497 0x9F, nominalRate6bw[priv->xtal], 5);
2498 /* Group delay equaliser settings for ASCOT tuners optimized */
2499 cxd2841er_write_regs(priv, I2C_SLVT,
2500 0xA6, itbCoef6bw[priv->xtal], 14);
2501
2502 /* IF freq setting */
2503 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55);
2504 data[0] = (u8) ((iffreq >> 16) & 0xff);
2505 data[1] = (u8)((iffreq >> 8) & 0xff);
2506 data[2] = (u8)(iffreq & 0xff);
2507 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2508
2509 /* System bandwidth setting */
2510 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2511
2512 /* Demod core latency setting */
2513 if (priv->xtal == SONY_XTAL_24000) {
2514 data[0] = 0x1F;
2515 data[1] = 0x79;
2516 } else {
2517 data[0] = 0x1A;
2518 data[1] = 0xE2;
2519 }
2520 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2521
2522 /* Acquisition optimization setting */
2523 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2524 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2525 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2526 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2527 break;
2528 default:
2529 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2530 __func__, bandwidth);
2531 return -EINVAL;
2532 }
2533 return 0;
2534 }
2535
2536 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2537 u32 bandwidth)
2538 {
2539 u8 bw7_8mhz_b10_a6[] = {
2540 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2541 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2542 u8 bw6mhz_b10_a6[] = {
2543 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2544 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2545 u8 b10_b6[3];
2546 u32 iffreq;
2547
2548 dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
2549 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2550 switch (bandwidth) {
2551 case 8000000:
2552 case 7000000:
2553 cxd2841er_write_regs(
2554 priv, I2C_SLVT, 0xa6,
2555 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2556 iffreq = MAKE_IFFREQ_CONFIG(4.9);
2557 break;
2558 case 6000000:
2559 cxd2841er_write_regs(
2560 priv, I2C_SLVT, 0xa6,
2561 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2562 iffreq = MAKE_IFFREQ_CONFIG(3.7);
2563 break;
2564 default:
2565 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2566 __func__, bandwidth);
2567 return -EINVAL;
2568 }
2569 /* <IF freq setting> */
2570 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2571 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2572 b10_b6[2] = (u8)(iffreq & 0xff);
2573 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2574 /* Set SLV-T Bank : 0x11 */
2575 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2576 switch (bandwidth) {
2577 case 8000000:
2578 case 7000000:
2579 cxd2841er_set_reg_bits(
2580 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2581 break;
2582 case 6000000:
2583 cxd2841er_set_reg_bits(
2584 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2585 break;
2586 }
2587 /* Set SLV-T Bank : 0x40 */
2588 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2589 switch (bandwidth) {
2590 case 8000000:
2591 cxd2841er_set_reg_bits(
2592 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2593 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
2594 break;
2595 case 7000000:
2596 cxd2841er_set_reg_bits(
2597 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2598 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
2599 break;
2600 case 6000000:
2601 cxd2841er_set_reg_bits(
2602 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2603 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
2604 break;
2605 }
2606 return 0;
2607 }
2608
2609 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2610 u32 bandwidth)
2611 {
2612 u8 data[2] = { 0x09, 0x54 };
2613 u8 data24m[3] = {0xDC, 0x6C, 0x00};
2614
2615 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2616 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2617 /* Set SLV-X Bank : 0x00 */
2618 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2619 /* Set demod mode */
2620 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2621 /* Set SLV-T Bank : 0x00 */
2622 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2623 /* Enable demod clock */
2624 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2625 /* Disable RF level monitor */
2626 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2627 /* Enable ADC clock */
2628 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2629 /* Enable ADC 1 */
2630 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2631 /* Enable ADC 2 & 3 */
2632 if (priv->xtal == SONY_XTAL_41000) {
2633 data[0] = 0x0A;
2634 data[1] = 0xD4;
2635 }
2636 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2637 /* Enable ADC 4 */
2638 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2639 /* Set SLV-T Bank : 0x10 */
2640 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2641 /* IFAGC gain settings */
2642 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2643 /* Set SLV-T Bank : 0x11 */
2644 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2645 /* BBAGC TARGET level setting */
2646 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2647 /* Set SLV-T Bank : 0x10 */
2648 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2649 /* ASCOT setting ON */
2650 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2651 /* Set SLV-T Bank : 0x18 */
2652 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2653 /* Pre-RS BER moniter setting */
2654 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2655 /* FEC Auto Recovery setting */
2656 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2657 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2658 /* Set SLV-T Bank : 0x00 */
2659 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2660 /* TSIF setting */
2661 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2662 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2663
2664 if (priv->xtal == SONY_XTAL_24000) {
2665 /* Set SLV-T Bank : 0x10 */
2666 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2667 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2668 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2669 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2670 }
2671
2672 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2673 /* Set SLV-T Bank : 0x00 */
2674 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2675 /* Disable HiZ Setting 1 */
2676 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2677 /* Disable HiZ Setting 2 */
2678 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2679 priv->state = STATE_ACTIVE_TC;
2680 return 0;
2681 }
2682
2683 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2684 u32 bandwidth)
2685 {
2686 u8 data[MAX_WRITE_REGSIZE];
2687
2688 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2689 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2690 /* Set SLV-X Bank : 0x00 */
2691 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2692 /* Set demod mode */
2693 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2694 /* Set SLV-T Bank : 0x00 */
2695 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2696 /* Enable demod clock */
2697 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2698 /* Disable RF level monitor */
2699 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
2700 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2701 /* Enable ADC clock */
2702 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2703 /* Enable ADC 1 */
2704 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2705
2706 if (priv->xtal == SONY_XTAL_41000) {
2707 data[0] = 0x0A;
2708 data[1] = 0xD4;
2709 } else {
2710 data[0] = 0x09;
2711 data[1] = 0x54;
2712 }
2713
2714 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2715 /* Enable ADC 4 */
2716 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2717 /* Set SLV-T Bank : 0x10 */
2718 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2719 /* IFAGC gain settings */
2720 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2721 /* Set SLV-T Bank : 0x11 */
2722 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2723 /* BBAGC TARGET level setting */
2724 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2725 /* Set SLV-T Bank : 0x10 */
2726 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2727 /* ASCOT setting ON */
2728 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2729 /* Set SLV-T Bank : 0x20 */
2730 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2731 /* Acquisition optimization setting */
2732 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2733 /* Set SLV-T Bank : 0x2b */
2734 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2735 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
2736 /* Set SLV-T Bank : 0x23 */
2737 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2738 /* L1 Control setting */
2739 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
2740 /* Set SLV-T Bank : 0x00 */
2741 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2742 /* TSIF setting */
2743 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2744 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2745 /* DVB-T2 initial setting */
2746 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2747 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2748 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2749 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2750 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2751 /* Set SLV-T Bank : 0x2a */
2752 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2753 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2754 /* Set SLV-T Bank : 0x2b */
2755 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2756 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2757
2758 /* 24MHz Xtal setting */
2759 if (priv->xtal == SONY_XTAL_24000) {
2760 /* Set SLV-T Bank : 0x11 */
2761 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2762 data[0] = 0xEB;
2763 data[1] = 0x03;
2764 data[2] = 0x3B;
2765 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
2766
2767 /* Set SLV-T Bank : 0x20 */
2768 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2769 data[0] = 0x5E;
2770 data[1] = 0x5E;
2771 data[2] = 0x47;
2772 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
2773
2774 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
2775
2776 data[0] = 0x3F;
2777 data[1] = 0xFF;
2778 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2779
2780 /* Set SLV-T Bank : 0x24 */
2781 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
2782 data[0] = 0x0B;
2783 data[1] = 0x72;
2784 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
2785
2786 data[0] = 0x93;
2787 data[1] = 0xF3;
2788 data[2] = 0x00;
2789 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
2790
2791 data[0] = 0x05;
2792 data[1] = 0xB8;
2793 data[2] = 0xD8;
2794 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
2795
2796 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
2797
2798 /* Set SLV-T Bank : 0x25 */
2799 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
2800 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
2801
2802 /* Set SLV-T Bank : 0x27 */
2803 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2804 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
2805
2806 /* Set SLV-T Bank : 0x2B */
2807 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
2808 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
2809 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
2810
2811 /* Set SLV-T Bank : 0x2D */
2812 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
2813 data[0] = 0x89;
2814 data[1] = 0x89;
2815 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
2816
2817 /* Set SLV-T Bank : 0x5E */
2818 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
2819 data[0] = 0x24;
2820 data[1] = 0x95;
2821 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
2822 }
2823
2824 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2825
2826 /* Set SLV-T Bank : 0x00 */
2827 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2828 /* Disable HiZ Setting 1 */
2829 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2830 /* Disable HiZ Setting 2 */
2831 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2832 priv->state = STATE_ACTIVE_TC;
2833 return 0;
2834 }
2835
2836 /* ISDB-Tb part */
2837 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
2838 u32 bandwidth)
2839 {
2840 u8 data[2] = { 0x09, 0x54 };
2841 u8 data24m[2] = {0x60, 0x00};
2842 u8 data24m2[3] = {0xB7, 0x1B, 0x00};
2843
2844 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2845 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2846 /* Set SLV-X Bank : 0x00 */
2847 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2848 /* Set demod mode */
2849 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
2850 /* Set SLV-T Bank : 0x00 */
2851 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2852 /* Enable demod clock */
2853 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2854 /* Enable RF level monitor */
2855 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
2856 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
2857 /* Enable ADC clock */
2858 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2859 /* Enable ADC 1 */
2860 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2861 /* xtal freq 20.5MHz or 24M */
2862 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2863 /* Enable ADC 4 */
2864 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2865 /* ASCOT setting ON */
2866 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2867 /* FEC Auto Recovery setting */
2868 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2869 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
2870 /* ISDB-T initial setting */
2871 /* Set SLV-T Bank : 0x00 */
2872 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2873 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
2874 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
2875 /* Set SLV-T Bank : 0x10 */
2876 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2877 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
2878 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
2879 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
2880 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
2881 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
2882 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
2883 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
2884 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
2885 /* Set SLV-T Bank : 0x15 */
2886 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2887 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
2888 /* Set SLV-T Bank : 0x1E */
2889 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
2890 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
2891 /* Set SLV-T Bank : 0x63 */
2892 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
2893 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
2894
2895 /* for xtal 24MHz */
2896 /* Set SLV-T Bank : 0x10 */
2897 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2898 cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
2899 /* Set SLV-T Bank : 0x60 */
2900 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
2901 cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
2902
2903 cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
2904 /* Set SLV-T Bank : 0x00 */
2905 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2906 /* Disable HiZ Setting 1 */
2907 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2908 /* Disable HiZ Setting 2 */
2909 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2910 priv->state = STATE_ACTIVE_TC;
2911 return 0;
2912 }
2913
2914 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
2915 u32 bandwidth)
2916 {
2917 u8 data[2] = { 0x09, 0x54 };
2918
2919 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2920 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
2921 /* Set SLV-X Bank : 0x00 */
2922 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2923 /* Set demod mode */
2924 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
2925 /* Set SLV-T Bank : 0x00 */
2926 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2927 /* Enable demod clock */
2928 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2929 /* Disable RF level monitor */
2930 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2931 /* Enable ADC clock */
2932 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2933 /* Enable ADC 1 */
2934 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2935 /* xtal freq 20.5MHz */
2936 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2937 /* Enable ADC 4 */
2938 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2939 /* Set SLV-T Bank : 0x10 */
2940 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2941 /* IFAGC gain settings */
2942 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
2943 /* Set SLV-T Bank : 0x11 */
2944 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2945 /* BBAGC TARGET level setting */
2946 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
2947 /* Set SLV-T Bank : 0x10 */
2948 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2949 /* ASCOT setting ON */
2950 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2951 /* Set SLV-T Bank : 0x40 */
2952 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2953 /* Demod setting */
2954 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
2955 /* Set SLV-T Bank : 0x00 */
2956 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2957 /* TSIF setting */
2958 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2959 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2960
2961 cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
2962 /* Set SLV-T Bank : 0x00 */
2963 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2964 /* Disable HiZ Setting 1 */
2965 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2966 /* Disable HiZ Setting 2 */
2967 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2968 priv->state = STATE_ACTIVE_TC;
2969 return 0;
2970 }
2971
2972 static int cxd2841er_get_frontend(struct dvb_frontend *fe,
2973 struct dtv_frontend_properties *p)
2974 {
2975 enum fe_status status = 0;
2976 struct cxd2841er_priv *priv = fe->demodulator_priv;
2977
2978 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2979 if (priv->state == STATE_ACTIVE_S)
2980 cxd2841er_read_status_s(fe, &status);
2981 else if (priv->state == STATE_ACTIVE_TC)
2982 cxd2841er_read_status_tc(fe, &status);
2983
2984 cxd2841er_read_signal_strength(fe);
2985
2986 if (status & FE_HAS_LOCK) {
2987 cxd2841er_read_snr(fe);
2988 cxd2841er_read_ucblocks(fe);
2989
2990 cxd2841er_read_ber(fe);
2991 } else {
2992 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2993 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2994 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2995 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2996 }
2997 return 0;
2998 }
2999
3000 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
3001 {
3002 int ret = 0, i, timeout, carr_offset;
3003 enum fe_status status;
3004 struct cxd2841er_priv *priv = fe->demodulator_priv;
3005 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3006 u32 symbol_rate = p->symbol_rate/1000;
3007
3008 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
3009 __func__,
3010 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
3011 p->frequency, symbol_rate, priv->xtal);
3012 switch (priv->state) {
3013 case STATE_SLEEP_S:
3014 ret = cxd2841er_sleep_s_to_active_s(
3015 priv, p->delivery_system, symbol_rate);
3016 break;
3017 case STATE_ACTIVE_S:
3018 ret = cxd2841er_retune_active(priv, p);
3019 break;
3020 default:
3021 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3022 __func__, priv->state);
3023 ret = -EINVAL;
3024 goto done;
3025 }
3026 if (ret) {
3027 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3028 goto done;
3029 }
3030 if (fe->ops.i2c_gate_ctrl)
3031 fe->ops.i2c_gate_ctrl(fe, 1);
3032 if (fe->ops.tuner_ops.set_params)
3033 fe->ops.tuner_ops.set_params(fe);
3034 if (fe->ops.i2c_gate_ctrl)
3035 fe->ops.i2c_gate_ctrl(fe, 0);
3036 cxd2841er_tune_done(priv);
3037 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3038 for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
3039 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3040 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3041 cxd2841er_read_status_s(fe, &status);
3042 if (status & FE_HAS_LOCK)
3043 break;
3044 }
3045 if (status & FE_HAS_LOCK) {
3046 if (cxd2841er_get_carrier_offset_s_s2(
3047 priv, &carr_offset)) {
3048 ret = -EINVAL;
3049 goto done;
3050 }
3051 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3052 __func__, carr_offset);
3053 }
3054 done:
3055 /* Reset stats */
3056 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3057 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3058 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3059 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3060 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3061
3062 return ret;
3063 }
3064
3065 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3066 {
3067 int ret = 0, timeout;
3068 enum fe_status status;
3069 struct cxd2841er_priv *priv = fe->demodulator_priv;
3070 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3071
3072 dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3073 __func__, p->delivery_system, p->bandwidth_hz);
3074 if (p->delivery_system == SYS_DVBT) {
3075 priv->system = SYS_DVBT;
3076 switch (priv->state) {
3077 case STATE_SLEEP_TC:
3078 ret = cxd2841er_sleep_tc_to_active_t(
3079 priv, p->bandwidth_hz);
3080 break;
3081 case STATE_ACTIVE_TC:
3082 ret = cxd2841er_retune_active(priv, p);
3083 break;
3084 default:
3085 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3086 __func__, priv->state);
3087 ret = -EINVAL;
3088 }
3089 } else if (p->delivery_system == SYS_DVBT2) {
3090 priv->system = SYS_DVBT2;
3091 cxd2841er_dvbt2_set_plp_config(priv,
3092 (int)(p->stream_id > 255), p->stream_id);
3093 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3094 switch (priv->state) {
3095 case STATE_SLEEP_TC:
3096 ret = cxd2841er_sleep_tc_to_active_t2(priv,
3097 p->bandwidth_hz);
3098 break;
3099 case STATE_ACTIVE_TC:
3100 ret = cxd2841er_retune_active(priv, p);
3101 break;
3102 default:
3103 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3104 __func__, priv->state);
3105 ret = -EINVAL;
3106 }
3107 } else if (p->delivery_system == SYS_ISDBT) {
3108 priv->system = SYS_ISDBT;
3109 switch (priv->state) {
3110 case STATE_SLEEP_TC:
3111 ret = cxd2841er_sleep_tc_to_active_i(
3112 priv, p->bandwidth_hz);
3113 break;
3114 case STATE_ACTIVE_TC:
3115 ret = cxd2841er_retune_active(priv, p);
3116 break;
3117 default:
3118 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3119 __func__, priv->state);
3120 ret = -EINVAL;
3121 }
3122 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3123 p->delivery_system == SYS_DVBC_ANNEX_C) {
3124 priv->system = SYS_DVBC_ANNEX_A;
3125 /* correct bandwidth */
3126 if (p->bandwidth_hz != 6000000 &&
3127 p->bandwidth_hz != 7000000 &&
3128 p->bandwidth_hz != 8000000) {
3129 p->bandwidth_hz = 8000000;
3130 dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3131 __func__, p->bandwidth_hz);
3132 }
3133
3134 switch (priv->state) {
3135 case STATE_SLEEP_TC:
3136 ret = cxd2841er_sleep_tc_to_active_c(
3137 priv, p->bandwidth_hz);
3138 break;
3139 case STATE_ACTIVE_TC:
3140 ret = cxd2841er_retune_active(priv, p);
3141 break;
3142 default:
3143 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3144 __func__, priv->state);
3145 ret = -EINVAL;
3146 }
3147 } else {
3148 dev_dbg(&priv->i2c->dev,
3149 "%s(): invalid delivery system %d\n",
3150 __func__, p->delivery_system);
3151 ret = -EINVAL;
3152 }
3153 if (ret)
3154 goto done;
3155 if (fe->ops.i2c_gate_ctrl)
3156 fe->ops.i2c_gate_ctrl(fe, 1);
3157 if (fe->ops.tuner_ops.set_params)
3158 fe->ops.tuner_ops.set_params(fe);
3159 if (fe->ops.i2c_gate_ctrl)
3160 fe->ops.i2c_gate_ctrl(fe, 0);
3161 cxd2841er_tune_done(priv);
3162 timeout = 2500;
3163 while (timeout > 0) {
3164 ret = cxd2841er_read_status_tc(fe, &status);
3165 if (ret)
3166 goto done;
3167 if (status & FE_HAS_LOCK)
3168 break;
3169 msleep(20);
3170 timeout -= 20;
3171 }
3172 if (timeout < 0)
3173 dev_dbg(&priv->i2c->dev,
3174 "%s(): LOCK wait timeout\n", __func__);
3175 done:
3176 return ret;
3177 }
3178
3179 static int cxd2841er_tune_s(struct dvb_frontend *fe,
3180 bool re_tune,
3181 unsigned int mode_flags,
3182 unsigned int *delay,
3183 enum fe_status *status)
3184 {
3185 int ret, carrier_offset;
3186 struct cxd2841er_priv *priv = fe->demodulator_priv;
3187 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3188
3189 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3190 if (re_tune) {
3191 ret = cxd2841er_set_frontend_s(fe);
3192 if (ret)
3193 return ret;
3194 cxd2841er_read_status_s(fe, status);
3195 if (*status & FE_HAS_LOCK) {
3196 if (cxd2841er_get_carrier_offset_s_s2(
3197 priv, &carrier_offset))
3198 return -EINVAL;
3199 p->frequency += carrier_offset;
3200 ret = cxd2841er_set_frontend_s(fe);
3201 if (ret)
3202 return ret;
3203 }
3204 }
3205 *delay = HZ / 5;
3206 return cxd2841er_read_status_s(fe, status);
3207 }
3208
3209 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3210 bool re_tune,
3211 unsigned int mode_flags,
3212 unsigned int *delay,
3213 enum fe_status *status)
3214 {
3215 int ret, carrier_offset;
3216 struct cxd2841er_priv *priv = fe->demodulator_priv;
3217 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3218
3219 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3220 re_tune, p->bandwidth_hz);
3221 if (re_tune) {
3222 ret = cxd2841er_set_frontend_tc(fe);
3223 if (ret)
3224 return ret;
3225 cxd2841er_read_status_tc(fe, status);
3226 if (*status & FE_HAS_LOCK) {
3227 switch (priv->system) {
3228 case SYS_ISDBT:
3229 ret = cxd2841er_get_carrier_offset_i(
3230 priv, p->bandwidth_hz,
3231 &carrier_offset);
3232 break;
3233 case SYS_DVBT:
3234 ret = cxd2841er_get_carrier_offset_t(
3235 priv, p->bandwidth_hz,
3236 &carrier_offset);
3237 break;
3238 case SYS_DVBT2:
3239 ret = cxd2841er_get_carrier_offset_t2(
3240 priv, p->bandwidth_hz,
3241 &carrier_offset);
3242 break;
3243 case SYS_DVBC_ANNEX_A:
3244 ret = cxd2841er_get_carrier_offset_c(
3245 priv, &carrier_offset);
3246 break;
3247 default:
3248 dev_dbg(&priv->i2c->dev,
3249 "%s(): invalid delivery system %d\n",
3250 __func__, priv->system);
3251 return -EINVAL;
3252 }
3253 if (ret)
3254 return ret;
3255 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3256 __func__, carrier_offset);
3257 p->frequency += carrier_offset;
3258 ret = cxd2841er_set_frontend_tc(fe);
3259 if (ret)
3260 return ret;
3261 }
3262 }
3263 *delay = HZ / 5;
3264 return cxd2841er_read_status_tc(fe, status);
3265 }
3266
3267 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3268 {
3269 struct cxd2841er_priv *priv = fe->demodulator_priv;
3270
3271 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3272 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3273 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3274 return 0;
3275 }
3276
3277 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3278 {
3279 struct cxd2841er_priv *priv = fe->demodulator_priv;
3280
3281 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3282 if (priv->state == STATE_ACTIVE_TC) {
3283 switch (priv->system) {
3284 case SYS_DVBT:
3285 cxd2841er_active_t_to_sleep_tc(priv);
3286 break;
3287 case SYS_DVBT2:
3288 cxd2841er_active_t2_to_sleep_tc(priv);
3289 break;
3290 case SYS_ISDBT:
3291 cxd2841er_active_i_to_sleep_tc(priv);
3292 break;
3293 case SYS_DVBC_ANNEX_A:
3294 cxd2841er_active_c_to_sleep_tc(priv);
3295 break;
3296 default:
3297 dev_warn(&priv->i2c->dev,
3298 "%s(): unknown delivery system %d\n",
3299 __func__, priv->system);
3300 }
3301 }
3302 if (priv->state != STATE_SLEEP_TC) {
3303 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3304 __func__, priv->state);
3305 return -EINVAL;
3306 }
3307 cxd2841er_sleep_tc_to_shutdown(priv);
3308 return 0;
3309 }
3310
3311 static int cxd2841er_send_burst(struct dvb_frontend *fe,
3312 enum fe_sec_mini_cmd burst)
3313 {
3314 u8 data;
3315 struct cxd2841er_priv *priv = fe->demodulator_priv;
3316
3317 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3318 (burst == SEC_MINI_A ? "A" : "B"));
3319 if (priv->state != STATE_SLEEP_S &&
3320 priv->state != STATE_ACTIVE_S) {
3321 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3322 __func__, priv->state);
3323 return -EINVAL;
3324 }
3325 data = (burst == SEC_MINI_A ? 0 : 1);
3326 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3327 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3328 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3329 return 0;
3330 }
3331
3332 static int cxd2841er_set_tone(struct dvb_frontend *fe,
3333 enum fe_sec_tone_mode tone)
3334 {
3335 u8 data;
3336 struct cxd2841er_priv *priv = fe->demodulator_priv;
3337
3338 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3339 (tone == SEC_TONE_ON ? "On" : "Off"));
3340 if (priv->state != STATE_SLEEP_S &&
3341 priv->state != STATE_ACTIVE_S) {
3342 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3343 __func__, priv->state);
3344 return -EINVAL;
3345 }
3346 data = (tone == SEC_TONE_ON ? 1 : 0);
3347 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3348 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3349 return 0;
3350 }
3351
3352 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3353 struct dvb_diseqc_master_cmd *cmd)
3354 {
3355 int i;
3356 u8 data[12];
3357 struct cxd2841er_priv *priv = fe->demodulator_priv;
3358
3359 if (priv->state != STATE_SLEEP_S &&
3360 priv->state != STATE_ACTIVE_S) {
3361 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3362 __func__, priv->state);
3363 return -EINVAL;
3364 }
3365 dev_dbg(&priv->i2c->dev,
3366 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3367 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3368 /* DiDEqC enable */
3369 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3370 /* cmd1 length & data */
3371 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3372 memset(data, 0, sizeof(data));
3373 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3374 data[i] = cmd->msg[i];
3375 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3376 /* repeat count for cmd1 */
3377 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3378 /* repeat count for cmd2: always 0 */
3379 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3380 /* start transmit */
3381 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3382 /* wait for 1 sec timeout */
3383 for (i = 0; i < 50; i++) {
3384 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3385 if (!data[0]) {
3386 dev_dbg(&priv->i2c->dev,
3387 "%s(): DiSEqC cmd has been sent\n", __func__);
3388 return 0;
3389 }
3390 msleep(20);
3391 }
3392 dev_dbg(&priv->i2c->dev,
3393 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3394 return -ETIMEDOUT;
3395 }
3396
3397 static void cxd2841er_release(struct dvb_frontend *fe)
3398 {
3399 struct cxd2841er_priv *priv = fe->demodulator_priv;
3400
3401 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3402 kfree(priv);
3403 }
3404
3405 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3406 {
3407 struct cxd2841er_priv *priv = fe->demodulator_priv;
3408
3409 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3410 cxd2841er_set_reg_bits(
3411 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3412 return 0;
3413 }
3414
3415 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3416 {
3417 struct cxd2841er_priv *priv = fe->demodulator_priv;
3418
3419 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3420 return DVBFE_ALGO_HW;
3421 }
3422
3423 static void cxd2841er_init_stats(struct dvb_frontend *fe)
3424 {
3425 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3426
3427 p->strength.len = 1;
3428 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3429 p->cnr.len = 1;
3430 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3431 p->block_error.len = 1;
3432 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3433 p->post_bit_error.len = 1;
3434 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3435 p->post_bit_count.len = 1;
3436 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3437 }
3438
3439
3440 static int cxd2841er_init_s(struct dvb_frontend *fe)
3441 {
3442 struct cxd2841er_priv *priv = fe->demodulator_priv;
3443
3444 /* sanity. force demod to SHUTDOWN state */
3445 if (priv->state == STATE_SLEEP_S) {
3446 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3447 __func__);
3448 cxd2841er_sleep_s_to_shutdown(priv);
3449 } else if (priv->state == STATE_ACTIVE_S) {
3450 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3451 __func__);
3452 cxd2841er_active_s_to_sleep_s(priv);
3453 cxd2841er_sleep_s_to_shutdown(priv);
3454 }
3455
3456 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3457 cxd2841er_shutdown_to_sleep_s(priv);
3458 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3459 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3460 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3461
3462 cxd2841er_init_stats(fe);
3463
3464 return 0;
3465 }
3466
3467 static int cxd2841er_init_tc(struct dvb_frontend *fe)
3468 {
3469 struct cxd2841er_priv *priv = fe->demodulator_priv;
3470 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3471
3472 dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3473 __func__, p->bandwidth_hz);
3474 cxd2841er_shutdown_to_sleep_tc(priv);
3475 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3476 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3477 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3478 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3479 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3480 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3481 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3482 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
3483
3484 cxd2841er_init_stats(fe);
3485
3486 return 0;
3487 }
3488
3489 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3490 static struct dvb_frontend_ops cxd2841er_t_c_ops;
3491
3492 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3493 struct i2c_adapter *i2c,
3494 u8 system)
3495 {
3496 u8 chip_id = 0;
3497 const char *type;
3498 const char *name;
3499 struct cxd2841er_priv *priv = NULL;
3500
3501 /* allocate memory for the internal state */
3502 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3503 if (!priv)
3504 return NULL;
3505 priv->i2c = i2c;
3506 priv->config = cfg;
3507 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3508 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
3509 priv->xtal = cfg->xtal;
3510 priv->frontend.demodulator_priv = priv;
3511 dev_info(&priv->i2c->dev,
3512 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3513 __func__, priv->i2c,
3514 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3515 chip_id = cxd2841er_chip_id(priv);
3516 switch (chip_id) {
3517 case CXD2841ER_CHIP_ID:
3518 snprintf(cxd2841er_t_c_ops.info.name, 128,
3519 "Sony CXD2841ER DVB-T/T2/C demodulator");
3520 name = "CXD2841ER";
3521 break;
3522 case CXD2854ER_CHIP_ID:
3523 snprintf(cxd2841er_t_c_ops.info.name, 128,
3524 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3525 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3526 name = "CXD2854ER";
3527 break;
3528 default:
3529 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3530 __func__, chip_id);
3531 priv->frontend.demodulator_priv = NULL;
3532 kfree(priv);
3533 return NULL;
3534 }
3535
3536 /* create dvb_frontend */
3537 if (system == SYS_DVBS) {
3538 memcpy(&priv->frontend.ops,
3539 &cxd2841er_dvbs_s2_ops,
3540 sizeof(struct dvb_frontend_ops));
3541 type = "S/S2";
3542 } else {
3543 memcpy(&priv->frontend.ops,
3544 &cxd2841er_t_c_ops,
3545 sizeof(struct dvb_frontend_ops));
3546 type = "T/T2/C/ISDB-T";
3547 }
3548
3549 dev_info(&priv->i2c->dev,
3550 "%s(): attaching %s DVB-%s frontend\n",
3551 __func__, name, type);
3552 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3553 __func__, chip_id);
3554 return &priv->frontend;
3555 }
3556
3557 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3558 struct i2c_adapter *i2c)
3559 {
3560 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3561 }
3562 EXPORT_SYMBOL(cxd2841er_attach_s);
3563
3564 struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
3565 struct i2c_adapter *i2c)
3566 {
3567 return cxd2841er_attach(cfg, i2c, 0);
3568 }
3569 EXPORT_SYMBOL(cxd2841er_attach_t_c);
3570
3571 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3572 .delsys = { SYS_DVBS, SYS_DVBS2 },
3573 .info = {
3574 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
3575 .frequency_min = 500000,
3576 .frequency_max = 2500000,
3577 .frequency_stepsize = 0,
3578 .symbol_rate_min = 1000000,
3579 .symbol_rate_max = 45000000,
3580 .symbol_rate_tolerance = 500,
3581 .caps = FE_CAN_INVERSION_AUTO |
3582 FE_CAN_FEC_AUTO |
3583 FE_CAN_QPSK,
3584 },
3585 .init = cxd2841er_init_s,
3586 .sleep = cxd2841er_sleep_s,
3587 .release = cxd2841er_release,
3588 .set_frontend = cxd2841er_set_frontend_s,
3589 .get_frontend = cxd2841er_get_frontend,
3590 .read_status = cxd2841er_read_status_s,
3591 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3592 .get_frontend_algo = cxd2841er_get_algo,
3593 .set_tone = cxd2841er_set_tone,
3594 .diseqc_send_burst = cxd2841er_send_burst,
3595 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3596 .tune = cxd2841er_tune_s
3597 };
3598
3599 static struct dvb_frontend_ops cxd2841er_t_c_ops = {
3600 .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
3601 .info = {
3602 .name = "", /* will set in attach function */
3603 .caps = FE_CAN_FEC_1_2 |
3604 FE_CAN_FEC_2_3 |
3605 FE_CAN_FEC_3_4 |
3606 FE_CAN_FEC_5_6 |
3607 FE_CAN_FEC_7_8 |
3608 FE_CAN_FEC_AUTO |
3609 FE_CAN_QPSK |
3610 FE_CAN_QAM_16 |
3611 FE_CAN_QAM_32 |
3612 FE_CAN_QAM_64 |
3613 FE_CAN_QAM_128 |
3614 FE_CAN_QAM_256 |
3615 FE_CAN_QAM_AUTO |
3616 FE_CAN_TRANSMISSION_MODE_AUTO |
3617 FE_CAN_GUARD_INTERVAL_AUTO |
3618 FE_CAN_HIERARCHY_AUTO |
3619 FE_CAN_MUTE_TS |
3620 FE_CAN_2G_MODULATION,
3621 .frequency_min = 42000000,
3622 .frequency_max = 1002000000
3623 },
3624 .init = cxd2841er_init_tc,
3625 .sleep = cxd2841er_sleep_tc,
3626 .release = cxd2841er_release,
3627 .set_frontend = cxd2841er_set_frontend_tc,
3628 .get_frontend = cxd2841er_get_frontend,
3629 .read_status = cxd2841er_read_status_tc,
3630 .tune = cxd2841er_tune_tc,
3631 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3632 .get_frontend_algo = cxd2841er_get_algo
3633 };
3634
3635 MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3636 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
3637 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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