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[deliverable/linux.git] / drivers / media / dvb-frontends / drx39xyj / drx_dap_fasi.c
1 /*
2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright notice,
9 this list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice,
11 this list of conditions and the following disclaimer in the documentation
12 and/or other materials provided with the distribution.
13 * Neither the name of Trident Microsystems nor Hauppauge Computer Works
14 nor the names of its contributors may be used to endorse or promote
15 products derived from this software without specific prior written
16 permission.
17
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 /*******************************************************************************
32 * FILENAME: $Id: drx_dap_fasi.c,v 1.7 2009/12/28 14:36:21 carlo Exp $
33 *
34 * DESCRIPTION:
35 * Part of DRX driver.
36 * Data access protocol: Fast Access Sequential Interface (fasi)
37 * Fast access, because of short addressing format (16 instead of 32 bits addr)
38 * Sequential, because of I2C.
39 * These functions know how the chip's memory and registers are to be accessed,
40 * but nothing more.
41 *
42 * These functions should not need adapting to a new platform.
43 *
44 * USAGE:
45 * -
46 *
47 * NOTES:
48 *
49 *
50 *******************************************************************************/
51
52 #include "drx_dap_fasi.h"
53 #include "bsp_host.h" /* for DRXBSP_HST_Memcpy() */
54
55 /*============================================================================*/
56
57 /* Function prototypes */
58 static DRXStatus_t DRXDAP_FASI_WriteBlock (
59 pI2CDeviceAddr_t devAddr, /* address of I2C device */
60 DRXaddr_t addr, /* address of register/memory */
61 u16_t datasize, /* size of data */
62 pu8_t data, /* data to send */
63 DRXflags_t flags); /* special device flags */
64
65 static DRXStatus_t DRXDAP_FASI_ReadBlock (
66 pI2CDeviceAddr_t devAddr, /* address of I2C device */
67 DRXaddr_t addr, /* address of register/memory */
68 u16_t datasize, /* size of data */
69 pu8_t data, /* data to send */
70 DRXflags_t flags); /* special device flags */
71
72 static DRXStatus_t DRXDAP_FASI_WriteReg8 (
73 pI2CDeviceAddr_t devAddr, /* address of I2C device */
74 DRXaddr_t addr, /* address of register */
75 u8_t data, /* data to write */
76 DRXflags_t flags); /* special device flags */
77
78 static DRXStatus_t DRXDAP_FASI_ReadReg8 (
79 pI2CDeviceAddr_t devAddr, /* address of I2C device */
80 DRXaddr_t addr, /* address of register */
81 pu8_t data, /* buffer to receive data */
82 DRXflags_t flags); /* special device flags */
83
84 static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 (
85 pI2CDeviceAddr_t devAddr, /* address of I2C device */
86 DRXaddr_t waddr, /* address of register */
87 DRXaddr_t raddr, /* address to read back from */
88 u8_t datain, /* data to send */
89 pu8_t dataout); /* data to receive back */
90
91 static DRXStatus_t DRXDAP_FASI_WriteReg16 (
92 pI2CDeviceAddr_t devAddr, /* address of I2C device */
93 DRXaddr_t addr, /* address of register */
94 u16_t data, /* data to write */
95 DRXflags_t flags); /* special device flags */
96
97 static DRXStatus_t DRXDAP_FASI_ReadReg16 (
98 pI2CDeviceAddr_t devAddr, /* address of I2C device */
99 DRXaddr_t addr, /* address of register */
100 pu16_t data, /* buffer to receive data */
101 DRXflags_t flags); /* special device flags */
102
103 static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 (
104 pI2CDeviceAddr_t devAddr, /* address of I2C device */
105 DRXaddr_t waddr, /* address of register */
106 DRXaddr_t raddr, /* address to read back from */
107 u16_t datain, /* data to send */
108 pu16_t dataout); /* data to receive back */
109
110 static DRXStatus_t DRXDAP_FASI_WriteReg32 (
111 pI2CDeviceAddr_t devAddr, /* address of I2C device */
112 DRXaddr_t addr, /* address of register */
113 u32_t data, /* data to write */
114 DRXflags_t flags); /* special device flags */
115
116 static DRXStatus_t DRXDAP_FASI_ReadReg32 (
117 pI2CDeviceAddr_t devAddr, /* address of I2C device */
118 DRXaddr_t addr, /* address of register */
119 pu32_t data, /* buffer to receive data */
120 DRXflags_t flags); /* special device flags */
121
122 static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 (
123 pI2CDeviceAddr_t devAddr, /* address of I2C device */
124 DRXaddr_t waddr, /* address of register */
125 DRXaddr_t raddr, /* address to read back from */
126 u32_t datain, /* data to send */
127 pu32_t dataout); /* data to receive back */
128
129 /* The version structure of this protocol implementation */
130 char drxDapFASIModuleName[] = "FASI Data Access Protocol";
131 char drxDapFASIVersionText[] = "";
132
133 DRXVersion_t drxDapFASIVersion =
134 {
135 DRX_MODULE_DAP, /**< type identifier of the module */
136 drxDapFASIModuleName, /**< name or description of module */
137
138 0, /**< major version number */
139 0, /**< minor version number */
140 0, /**< patch version number */
141 drxDapFASIVersionText /**< version as text string */
142 };
143
144 /* The structure containing the protocol interface */
145 DRXAccessFunc_t drxDapFASIFunct_g =
146 {
147 &drxDapFASIVersion,
148 DRXDAP_FASI_WriteBlock, /* Supported */
149 DRXDAP_FASI_ReadBlock, /* Supported */
150 DRXDAP_FASI_WriteReg8, /* Not supported */
151 DRXDAP_FASI_ReadReg8, /* Not supported */
152 DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */
153 DRXDAP_FASI_WriteReg16, /* Supported */
154 DRXDAP_FASI_ReadReg16, /* Supported */
155 DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */
156 DRXDAP_FASI_WriteReg32, /* Supported */
157 DRXDAP_FASI_ReadReg32, /* Supported */
158 DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */
159 };
160
161 /*============================================================================*/
162
163 /* Functions not supported by protocol*/
164
165 static DRXStatus_t DRXDAP_FASI_WriteReg8 (
166 pI2CDeviceAddr_t devAddr, /* address of I2C device */
167 DRXaddr_t addr, /* address of register */
168 u8_t data, /* data to write */
169 DRXflags_t flags) /* special device flags */
170 {
171 return DRX_STS_ERROR;
172 }
173
174 static DRXStatus_t DRXDAP_FASI_ReadReg8 (
175 pI2CDeviceAddr_t devAddr, /* address of I2C device */
176 DRXaddr_t addr, /* address of register */
177 pu8_t data, /* buffer to receive data */
178 DRXflags_t flags) /* special device flags */
179 {
180 return DRX_STS_ERROR;
181 }
182
183 static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 (
184 pI2CDeviceAddr_t devAddr, /* address of I2C device */
185 DRXaddr_t waddr, /* address of register */
186 DRXaddr_t raddr, /* address to read back from */
187 u8_t datain, /* data to send */
188 pu8_t dataout) /* data to receive back */
189 {
190 return DRX_STS_ERROR;
191 }
192
193 static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 (
194 pI2CDeviceAddr_t devAddr, /* address of I2C device */
195 DRXaddr_t waddr, /* address of register */
196 DRXaddr_t raddr, /* address to read back from */
197 u32_t datain, /* data to send */
198 pu32_t dataout) /* data to receive back */
199 {
200 return DRX_STS_ERROR;
201 }
202
203 /*============================================================================*/
204
205 /******************************
206 *
207 * DRXStatus_t DRXDAP_FASI_ReadBlock (
208 * pI2CDeviceAddr_t devAddr, -- address of I2C device
209 * DRXaddr_t addr, -- address of chip register/memory
210 * u16_t datasize, -- number of bytes to read
211 * pu8_t data, -- data to receive
212 * DRXflags_t flags) -- special device flags
213 *
214 * Read block data from chip address. Because the chip is word oriented,
215 * the number of bytes to read must be even.
216 *
217 * Make sure that the buffer to receive the data is large enough.
218 *
219 * Although this function expects an even number of bytes, it is still byte
220 * oriented, and the data read back is NOT translated to the endianness of
221 * the target platform.
222 *
223 * Output:
224 * - DRX_STS_OK if reading was successful
225 * in that case: data read is in *data.
226 * - DRX_STS_ERROR if anything went wrong
227 *
228 ******************************/
229
230 static DRXStatus_t DRXDAP_FASI_ReadBlock ( pI2CDeviceAddr_t devAddr,
231 DRXaddr_t addr,
232 u16_t datasize,
233 pu8_t data,
234 DRXflags_t flags )
235 {
236 u8_t buf[4];
237 u16_t bufx;
238 DRXStatus_t rc;
239 u16_t overheadSize = 0;
240
241 /* Check parameters ********************************************************/
242 if ( devAddr == NULL )
243 {
244 return DRX_STS_INVALID_ARG;
245 }
246
247 overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) +
248 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 );
249
250 if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) ||
251 ( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) &&
252 DRXDAP_FASI_LONG_FORMAT( addr ) ) ||
253 (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
254 ((datasize!=0) && (data==NULL)) ||
255 ((datasize & 1)==1 ) )
256 {
257 return DRX_STS_INVALID_ARG;
258 }
259
260 /* ReadModifyWrite & mode flag bits are not allowed */
261 flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
262 #if DRXDAP_SINGLE_MASTER
263 flags |= DRXDAP_FASI_SINGLE_MASTER;
264 #endif
265
266 /* Read block from I2C *****************************************************/
267 do {
268 u16_t todo = ( datasize < DRXDAP_MAX_RCHUNKSIZE ?
269 datasize : DRXDAP_MAX_RCHUNKSIZE);
270
271 bufx = 0;
272
273 addr &= ~DRXDAP_FASI_FLAGS;
274 addr |= flags;
275
276 #if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
277 ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
278 /* short format address preferred but long format otherwise */
279 if ( DRXDAP_FASI_LONG_FORMAT(addr) )
280 {
281 #endif
282 #if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 )
283 buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01);
284 buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
285 buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
286 buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
287 #endif
288 #if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
289 ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
290 } else {
291 #endif
292 #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
293 buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
294 buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) );
295 #endif
296 #if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
297 ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
298 }
299 #endif
300
301
302
303
304 #if DRXDAP_SINGLE_MASTER
305 /*
306 * In single master mode, split the read and write actions.
307 * No special action is needed for write chunks here.
308 */
309 rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, 0, 0, 0);
310 if (rc == DRX_STS_OK)
311 {
312 rc = DRXBSP_I2C_WriteRead (0, 0, 0, devAddr, todo, data);
313 }
314 #else
315 /* In multi master mode, do everything in one RW action */
316 rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, devAddr, todo, data);
317 #endif
318 data += todo;
319 addr += (todo >> 1);
320 datasize -= todo;
321 } while (datasize && rc == DRX_STS_OK);
322
323 return rc;
324 }
325
326
327
328
329 /******************************
330 *
331 * DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 (
332 * pI2CDeviceAddr_t devAddr, -- address of I2C device
333 * DRXaddr_t waddr, -- address of chip register/memory
334 * DRXaddr_t raddr, -- chip address to read back from
335 * u16_t wdata, -- data to send
336 * pu16_t rdata) -- data to receive back
337 *
338 * Write 16-bit data, then read back the original contents of that location.
339 * Requires long addressing format to be allowed.
340 *
341 * Before sending data, the data is converted to little endian. The
342 * data received back is converted back to the target platform's endianness.
343 *
344 * WARNING: This function is only guaranteed to work if there is one
345 * master on the I2C bus.
346 *
347 * Output:
348 * - DRX_STS_OK if reading was successful
349 * in that case: read back data is at *rdata
350 * - DRX_STS_ERROR if anything went wrong
351 *
352 ******************************/
353
354 static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( pI2CDeviceAddr_t devAddr,
355 DRXaddr_t waddr,
356 DRXaddr_t raddr,
357 u16_t wdata,
358 pu16_t rdata )
359 {
360 DRXStatus_t rc=DRX_STS_ERROR;
361
362 #if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 )
363 if (rdata == NULL)
364 {
365 return DRX_STS_INVALID_ARG;
366 }
367
368 rc = DRXDAP_FASI_WriteReg16 (devAddr, waddr, wdata, DRXDAP_FASI_RMW);
369 if (rc == DRX_STS_OK)
370 {
371 rc = DRXDAP_FASI_ReadReg16 (devAddr, raddr, rdata, 0);
372 }
373 #endif
374
375 return rc;
376 }
377
378
379
380
381 /******************************
382 *
383 * DRXStatus_t DRXDAP_FASI_ReadReg16 (
384 * pI2CDeviceAddr_t devAddr, -- address of I2C device
385 * DRXaddr_t addr, -- address of chip register/memory
386 * pu16_t data, -- data to receive
387 * DRXflags_t flags) -- special device flags
388 *
389 * Read one 16-bit register or memory location. The data received back is
390 * converted back to the target platform's endianness.
391 *
392 * Output:
393 * - DRX_STS_OK if reading was successful
394 * in that case: read data is at *data
395 * - DRX_STS_ERROR if anything went wrong
396 *
397 ******************************/
398
399 static DRXStatus_t DRXDAP_FASI_ReadReg16 ( pI2CDeviceAddr_t devAddr,
400 DRXaddr_t addr,
401 pu16_t data,
402 DRXflags_t flags )
403 {
404 u8_t buf[sizeof (*data)];
405 DRXStatus_t rc;
406
407 if (!data)
408 {
409 return DRX_STS_INVALID_ARG;
410 }
411 rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags);
412 *data = buf[0] + (((u16_t) buf[1]) << 8);
413 return rc;
414 }
415
416
417
418
419 /******************************
420 *
421 * DRXStatus_t DRXDAP_FASI_ReadReg32 (
422 * pI2CDeviceAddr_t devAddr, -- address of I2C device
423 * DRXaddr_t addr, -- address of chip register/memory
424 * pu32_t data, -- data to receive
425 * DRXflags_t flags) -- special device flags
426 *
427 * Read one 32-bit register or memory location. The data received back is
428 * converted back to the target platform's endianness.
429 *
430 * Output:
431 * - DRX_STS_OK if reading was successful
432 * in that case: read data is at *data
433 * - DRX_STS_ERROR if anything went wrong
434 *
435 ******************************/
436
437 static DRXStatus_t DRXDAP_FASI_ReadReg32 ( pI2CDeviceAddr_t devAddr,
438 DRXaddr_t addr,
439 pu32_t data,
440 DRXflags_t flags )
441 {
442 u8_t buf[sizeof (*data)];
443 DRXStatus_t rc;
444
445 if (!data)
446 {
447 return DRX_STS_INVALID_ARG;
448 }
449 rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags);
450 *data = (((u32_t) buf[0]) << 0) +
451 (((u32_t) buf[1]) << 8) +
452 (((u32_t) buf[2]) << 16) +
453 (((u32_t) buf[3]) << 24);
454 return rc;
455 }
456
457
458
459
460 /******************************
461 *
462 * DRXStatus_t DRXDAP_FASI_WriteBlock (
463 * pI2CDeviceAddr_t devAddr, -- address of I2C device
464 * DRXaddr_t addr, -- address of chip register/memory
465 * u16_t datasize, -- number of bytes to read
466 * pu8_t data, -- data to receive
467 * DRXflags_t flags) -- special device flags
468 *
469 * Write block data to chip address. Because the chip is word oriented,
470 * the number of bytes to write must be even.
471 *
472 * Although this function expects an even number of bytes, it is still byte
473 * oriented, and the data being written is NOT translated from the endianness of
474 * the target platform.
475 *
476 * Output:
477 * - DRX_STS_OK if writing was successful
478 * - DRX_STS_ERROR if anything went wrong
479 *
480 ******************************/
481
482 static DRXStatus_t DRXDAP_FASI_WriteBlock ( pI2CDeviceAddr_t devAddr,
483 DRXaddr_t addr,
484 u16_t datasize,
485 pu8_t data,
486 DRXflags_t flags )
487 {
488 u8_t buf[ DRXDAP_MAX_WCHUNKSIZE ];
489 DRXStatus_t st = DRX_STS_ERROR;
490 DRXStatus_t firstErr = DRX_STS_OK;
491 u16_t overheadSize = 0;
492 u16_t blockSize = 0;
493
494 /* Check parameters ********************************************************/
495 if ( devAddr == NULL )
496 {
497 return DRX_STS_INVALID_ARG;
498 }
499
500 overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) +
501 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 );
502
503 if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) ||
504 ( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) &&
505 DRXDAP_FASI_LONG_FORMAT( addr ) ) ||
506 (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
507 ((datasize!=0) && (data==NULL)) ||
508 ((datasize & 1)==1 ) )
509 {
510 return DRX_STS_INVALID_ARG;
511 }
512
513 flags &= DRXDAP_FASI_FLAGS;
514 flags &= ~DRXDAP_FASI_MODEFLAGS;
515 #if DRXDAP_SINGLE_MASTER
516 flags |= DRXDAP_FASI_SINGLE_MASTER;
517 #endif
518
519 /* Write block to I2C ******************************************************/
520 blockSize = ( (DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1;
521 do
522 {
523 u16_t todo = 0;
524 u16_t bufx = 0;
525
526 /* Buffer device address */
527 addr &= ~DRXDAP_FASI_FLAGS;
528 addr |= flags;
529 #if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
530 ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
531 /* short format address preferred but long format otherwise */
532 if ( DRXDAP_FASI_LONG_FORMAT(addr) )
533 {
534 #endif
535 #if ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 )
536 buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01);
537 buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
538 buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
539 buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
540 #endif
541 #if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
542 ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
543 } else {
544 #endif
545 #if ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 )
546 buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
547 buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) );
548 #endif
549 #if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
550 ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
551 }
552 #endif
553
554 /*
555 In single master mode blockSize can be 0. In such a case this I2C
556 sequense will be visible: (1) write address {i2c addr,
557 4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
558 (3) write address (4) write data etc...
559 Addres must be rewriten because HI is reset after data transport and
560 expects an address.
561 */
562 todo = (blockSize < datasize ? blockSize : datasize);
563 if (todo==0)
564 {
565 u16_t overheadSizeI2cAddr = 0;
566 u16_t dataBlockSize = 0;
567
568 overheadSizeI2cAddr = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1);
569 dataBlockSize = ( DRXDAP_MAX_WCHUNKSIZE - overheadSizeI2cAddr) & ~1;
570
571 /* write device address */
572 st = DRXBSP_I2C_WriteRead( devAddr,
573 (u16_t) (bufx),
574 buf,
575 (pI2CDeviceAddr_t)(NULL),
576 0,
577 (pu8_t)(NULL) );
578
579 if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) )
580 {
581 /* at the end, return the first error encountered */
582 firstErr = st;
583 }
584 bufx = 0;
585 todo = (dataBlockSize < datasize ? dataBlockSize : datasize);
586 }
587 DRXBSP_HST_Memcpy (&buf[bufx], data, todo);
588 /* write (address if can do and) data */
589 st = DRXBSP_I2C_WriteRead( devAddr,
590 (u16_t)(bufx + todo),
591 buf,
592 (pI2CDeviceAddr_t)(NULL),
593 0,
594 (pu8_t)(NULL) );
595
596 if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) )
597 {
598 /* at the end, return the first error encountered */
599 firstErr = st;
600 }
601 datasize -= todo;
602 data += todo;
603 addr += (todo >> 1);
604 } while (datasize);
605
606 return firstErr;
607 }
608
609
610
611
612 /******************************
613 *
614 * DRXStatus_t DRXDAP_FASI_WriteReg16 (
615 * pI2CDeviceAddr_t devAddr, -- address of I2C device
616 * DRXaddr_t addr, -- address of chip register/memory
617 * u16_t data, -- data to send
618 * DRXflags_t flags) -- special device flags
619 *
620 * Write one 16-bit register or memory location. The data being written is
621 * converted from the target platform's endianness to little endian.
622 *
623 * Output:
624 * - DRX_STS_OK if writing was successful
625 * - DRX_STS_ERROR if anything went wrong
626 *
627 ******************************/
628
629 static DRXStatus_t DRXDAP_FASI_WriteReg16 ( pI2CDeviceAddr_t devAddr,
630 DRXaddr_t addr,
631 u16_t data,
632 DRXflags_t flags )
633 {
634 u8_t buf[sizeof (data)];
635
636 buf[0] = (u8_t) ( (data >> 0 ) & 0xFF );
637 buf[1] = (u8_t) ( (data >> 8 ) & 0xFF );
638
639 return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags);
640 }
641
642
643
644
645 /******************************
646 *
647 * DRXStatus_t DRXDAP_FASI_WriteReg32 (
648 * pI2CDeviceAddr_t devAddr, -- address of I2C device
649 * DRXaddr_t addr, -- address of chip register/memory
650 * u32_t data, -- data to send
651 * DRXflags_t flags) -- special device flags
652 *
653 * Write one 32-bit register or memory location. The data being written is
654 * converted from the target platform's endianness to little endian.
655 *
656 * Output:
657 * - DRX_STS_OK if writing was successful
658 * - DRX_STS_ERROR if anything went wrong
659 *
660 ******************************/
661
662 static DRXStatus_t DRXDAP_FASI_WriteReg32 ( pI2CDeviceAddr_t devAddr,
663 DRXaddr_t addr,
664 u32_t data,
665 DRXflags_t flags )
666 {
667 u8_t buf[sizeof (data)];
668
669 buf[0] = (u8_t) ( (data >> 0 ) & 0xFF );
670 buf[1] = (u8_t) ( (data >> 8 ) & 0xFF );
671 buf[2] = (u8_t) ( (data >> 16) & 0xFF );
672 buf[3] = (u8_t) ( (data >> 24) & 0xFF );
673
674 return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags);
675 }
Linux kernel - Deliverables
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