drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c

   1 /*
   2   Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
   3   All rights reserved.
   4
   5   Redistribution and use in source and binary forms, with or without
   6   modification, are permitted provided that the following conditions are met:
   7
   8   * Redistributions of source code must retain the above copyright notice,
   9     this list of conditions and the following disclaimer.
  10   * Redistributions in binary form must reproduce the above copyright notice,
  11     this list of conditions and the following disclaimer in the documentation
  12         and/or other materials provided with the distribution.
  13   * Neither the name of Trident Microsystems nor Hauppauge Computer Works
  14     nor the names of its contributors may be used to endorse or promote
  15         products derived from this software without specific prior written
  16         permission.
  17
  18   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  22   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  28   POSSIBILITY OF SUCH DAMAGE.
  29 */
  30
  31 /*******************************************************************************
  32 * FILENAME: $Id: drx_dap_fasi.c,v 1.7 2009/12/28 14:36:21 carlo Exp $
  33 *
  34 * DESCRIPTION:
  35 * Part of DRX driver.
  36 * Data access protocol: Fast Access Sequential Interface (fasi)
  37 * Fast access, because of short addressing format (16 instead of 32 bits addr)
  38 * Sequential, because of I2C.
  39 * These functions know how the chip's memory and registers are to be accessed,
  40 * but nothing more.
  41 *
  42 * These functions should not need adapting to a new platform.
  43 *
  44 * USAGE:
  45 * -
  46 *
  47 * NOTES:
  48 *
  49 *
  50 *******************************************************************************/
  51
  52 #include "drx_dap_fasi.h"
  53 #include "drx_driver.h"         /* for drxbsp_hst_memcpy() */
  54
  55 /*============================================================================*/
  56
  57 /* Function prototypes */
  58 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,    /* address of I2C device        */
  59                                           dr_xaddr_t addr,      /* address of register/memory   */
  60                                           u16 datasize, /* size of data                 */
  61                                           u8 *data,     /* data to send                 */
  62                                           dr_xflags_t flags);   /* special device flags         */
  63
  64 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,     /* address of I2C device        */
  65                                          dr_xaddr_t addr,       /* address of register/memory   */
  66                                          u16 datasize,  /* size of data                 */
  67                                          u8 *data,      /* data to send                 */
  68                                          dr_xflags_t flags);    /* special device flags         */
  69
  70 static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr,     /* address of I2C device        */
  71                                          dr_xaddr_t addr,       /* address of register          */
  72                                          u8 data,       /* data to write                */
  73                                          dr_xflags_t flags);    /* special device flags         */
  74
  75 static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr,      /* address of I2C device        */
  76                                         dr_xaddr_t addr,        /* address of register          */
  77                                         u8 *data,       /* buffer to receive data       */
  78                                         dr_xflags_t flags);     /* special device flags         */
  79
  80 static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device        */
  81                                                    dr_xaddr_t waddr,    /* address of register          */
  82                                                    dr_xaddr_t raddr,    /* address to read back from    */
  83                                                    u8 datain,   /* data to send                 */
  84                                                    u8 *dataout);        /* data to receive back         */
  85
  86 static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr,    /* address of I2C device        */
  87                                           dr_xaddr_t addr,      /* address of register          */
  88                                           u16 data,     /* data to write                */
  89                                           dr_xflags_t flags);   /* special device flags         */
  90
  91 static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr,     /* address of I2C device        */
  92                                          dr_xaddr_t addr,       /* address of register          */
  93                                          u16 *data,     /* buffer to receive data       */
  94                                          dr_xflags_t flags);    /* special device flags         */
  95
  96 static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr,        /* address of I2C device        */
  97                                                     dr_xaddr_t waddr,   /* address of register          */
  98                                                     dr_xaddr_t raddr,   /* address to read back from    */
  99                                                     u16 datain, /* data to send                 */
 100                                                     u16 *dataout);      /* data to receive back         */
 101
 102 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,    /* address of I2C device        */
 103                                           dr_xaddr_t addr,      /* address of register          */
 104                                           u32 data,     /* data to write                */
 105                                           dr_xflags_t flags);   /* special device flags         */
 106
 107 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,     /* address of I2C device        */
 108                                          dr_xaddr_t addr,       /* address of register          */
 109                                          u32 *data,     /* buffer to receive data       */
 110                                          dr_xflags_t flags);    /* special device flags         */
 111
 112 static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr,        /* address of I2C device        */
 113                                                     dr_xaddr_t waddr,   /* address of register          */
 114                                                     dr_xaddr_t raddr,   /* address to read back from    */
 115                                                     u32 datain, /* data to send                 */
 116                                                     u32 *dataout);      /* data to receive back         */
 117
 118 /* The version structure of this protocol implementation */
 119 char drx_dap_fasi_module_name[] = "FASI Data Access Protocol";
 120 char drx_dap_fasi_version_text[] = "";
 121
 122 drx_version_t drx_dap_fasi_version = {
 123         DRX_MODULE_DAP,       /**< type identifier of the module */
 124         drx_dap_fasi_module_name, /**< name or description of module */
 125
 126         0,                    /**< major version number */
 127         0,                    /**< minor version number */
 128         0,                    /**< patch version number */
 129         drx_dap_fasi_version_text /**< version as text string */
 130 };
 131
 132 /* The structure containing the protocol interface */
 133 drx_access_func_t drx_dap_fasi_funct_g = {
 134         &drx_dap_fasi_version,
 135         drxdap_fasi_write_block,        /* Supported */
 136         drxdap_fasi_read_block, /* Supported */
 137         drxdap_fasi_write_reg8, /* Not supported */
 138         drxdap_fasi_read_reg8,  /* Not supported */
 139         drxdap_fasi_read_modify_write_reg8,     /* Not supported */
 140         drxdap_fasi_write_reg16,        /* Supported */
 141         drxdap_fasi_read_reg16, /* Supported */
 142         drxdap_fasi_read_modify_write_reg16,    /* Supported */
 143         drxdap_fasi_write_reg32,        /* Supported */
 144         drxdap_fasi_read_reg32, /* Supported */
 145         drxdap_fasi_read_modify_write_reg32     /* Not supported */
 146 };
 147
 148 /*============================================================================*/
 149
 150 /* Functions not supported by protocol*/
 151
 152 static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr,     /* address of I2C device        */
 153                                          dr_xaddr_t addr,       /* address of register          */
 154                                          u8 data,       /* data to write                */
 155                                          dr_xflags_t flags)
 156 {                               /* special device flags         */
 157         return DRX_STS_ERROR;
 158 }
 159
 160 static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr,      /* address of I2C device        */
 161                                         dr_xaddr_t addr,        /* address of register          */
 162                                         u8 *data,       /* buffer to receive data       */
 163                                         dr_xflags_t flags)
 164 {                               /* special device flags         */
 165         return DRX_STS_ERROR;
 166 }
 167
 168 static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device        */
 169                                                    dr_xaddr_t waddr,    /* address of register          */
 170                                                    dr_xaddr_t raddr,    /* address to read back from    */
 171                                                    u8 datain,   /* data to send                 */
 172                                                    u8 *dataout)
 173 {                               /* data to receive back         */
 174         return DRX_STS_ERROR;
 175 }
 176
 177 static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr,        /* address of I2C device        */
 178                                                     dr_xaddr_t waddr,   /* address of register          */
 179                                                     dr_xaddr_t raddr,   /* address to read back from    */
 180                                                     u32 datain, /* data to send                 */
 181                                                     u32 *dataout)
 182 {                               /* data to receive back         */
 183         return DRX_STS_ERROR;
 184 }
 185
 186 /*============================================================================*/
 187
 188 /******************************
 189 *
 190 * int drxdap_fasi_read_block (
 191 *      struct i2c_device_addr *dev_addr,      -- address of I2C device
 192 *      dr_xaddr_t        addr,         -- address of chip register/memory
 193 *      u16            datasize,     -- number of bytes to read
 194 *      u8 *data,         -- data to receive
 195 *      dr_xflags_t       flags)        -- special device flags
 196 *
 197 * Read block data from chip address. Because the chip is word oriented,
 198 * the number of bytes to read must be even.
 199 *
 200 * Make sure that the buffer to receive the data is large enough.
 201 *
 202 * Although this function expects an even number of bytes, it is still byte
 203 * oriented, and the data read back is NOT translated to the endianness of
 204 * the target platform.
 205 *
 206 * Output:
 207 * - DRX_STS_OK     if reading was successful
 208 *                  in that case: data read is in *data.
 209 * - DRX_STS_ERROR  if anything went wrong
 210 *
 211 ******************************/
 212
 213 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
 214                                          dr_xaddr_t addr,
 215                                          u16 datasize,
 216                                          u8 *data, dr_xflags_t flags)
 217 {
 218         u8 buf[4];
 219         u16 bufx;
 220         int rc;
 221         u16 overhead_size = 0;
 222
 223         /* Check parameters ******************************************************* */
 224         if (dev_addr == NULL) {
 225                 return DRX_STS_INVALID_ARG;
 226         }
 227
 228         overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
 229             (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
 230
 231         if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
 232             ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
 233              DRXDAP_FASI_LONG_FORMAT(addr)) ||
 234             (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
 235             ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
 236                 return DRX_STS_INVALID_ARG;
 237         }
 238
 239         /* ReadModifyWrite & mode flag bits are not allowed */
 240         flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
 241 #if DRXDAP_SINGLE_MASTER
 242         flags |= DRXDAP_FASI_SINGLE_MASTER;
 243 #endif
 244
 245         /* Read block from I2C **************************************************** */
 246         do {
 247                 u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ?
 248                               datasize : DRXDAP_MAX_RCHUNKSIZE);
 249
 250                 bufx = 0;
 251
 252                 addr &= ~DRXDAP_FASI_FLAGS;
 253                 addr |= flags;
 254
 255 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \
 256       (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
 257                 /* short format address preferred but long format otherwise */
 258                 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
 259 #endif
 260 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
 261                         buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
 262                         buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
 263                         buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
 264                         buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
 265 #endif
 266 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \
 267       (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
 268                 } else {
 269 #endif
 270 #if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)
 271                         buf[bufx++] = (u8) ((addr << 1) & 0xFF);
 272                         buf[bufx++] =
 273                             (u8) (((addr >> 16) & 0x0F) |
 274                                     ((addr >> 18) & 0xF0));
 275 #endif
 276 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && \
 277       (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
 278                 }
 279 #endif
 280
 281 #if DRXDAP_SINGLE_MASTER
 282                 /*
 283                  * In single master mode, split the read and write actions.
 284                  * No special action is needed for write chunks here.
 285                  */
 286                 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, 0, 0, 0);
 287                 if (rc == DRX_STS_OK) {
 288                         rc = drxbsp_i2c_write_read(0, 0, 0, dev_addr, todo, data);
 289                 }
 290 #else
 291                 /* In multi master mode, do everything in one RW action */
 292                 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,
 293                                           data);
 294 #endif
 295                 data += todo;
 296                 addr += (todo >> 1);
 297                 datasize -= todo;
 298         } while (datasize && rc == DRX_STS_OK);
 299
 300         return rc;
 301 }
 302
 303 /******************************
 304 *
 305 * int drxdap_fasi_read_modify_write_reg16 (
 306 *      struct i2c_device_addr *dev_addr,   -- address of I2C device
 307 *      dr_xaddr_t        waddr,     -- address of chip register/memory
 308 *      dr_xaddr_t        raddr,     -- chip address to read back from
 309 *      u16            wdata,     -- data to send
 310 *      u16 *rdata)     -- data to receive back
 311 *
 312 * Write 16-bit data, then read back the original contents of that location.
 313 * Requires long addressing format to be allowed.
 314 *
 315 * Before sending data, the data is converted to little endian. The
 316 * data received back is converted back to the target platform's endianness.
 317 *
 318 * WARNING: This function is only guaranteed to work if there is one
 319 * master on the I2C bus.
 320 *
 321 * Output:
 322 * - DRX_STS_OK     if reading was successful
 323 *                  in that case: read back data is at *rdata
 324 * - DRX_STS_ERROR  if anything went wrong
 325 *
 326 ******************************/
 327
 328 static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
 329                                                     dr_xaddr_t waddr,
 330                                                     dr_xaddr_t raddr,
 331                                                     u16 wdata, u16 *rdata)
 332 {
 333         int rc = DRX_STS_ERROR;
 334
 335 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
 336         if (rdata == NULL) {
 337                 return DRX_STS_INVALID_ARG;
 338         }
 339
 340         rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);
 341         if (rc == DRX_STS_OK) {
 342                 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);
 343         }
 344 #endif
 345
 346         return rc;
 347 }
 348
 349 /******************************
 350 *
 351 * int drxdap_fasi_read_reg16 (
 352 *     struct i2c_device_addr *dev_addr, -- address of I2C device
 353 *     dr_xaddr_t        addr,    -- address of chip register/memory
 354 *     u16 *data,    -- data to receive
 355 *     dr_xflags_t       flags)   -- special device flags
 356 *
 357 * Read one 16-bit register or memory location. The data received back is
 358 * converted back to the target platform's endianness.
 359 *
 360 * Output:
 361 * - DRX_STS_OK     if reading was successful
 362 *                  in that case: read data is at *data
 363 * - DRX_STS_ERROR  if anything went wrong
 364 *
 365 ******************************/
 366
 367 static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr,
 368                                          dr_xaddr_t addr,
 369                                          u16 *data, dr_xflags_t flags)
 370 {
 371         u8 buf[sizeof(*data)];
 372         int rc;
 373
 374         if (!data) {
 375                 return DRX_STS_INVALID_ARG;
 376         }
 377         rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
 378         *data = buf[0] + (((u16) buf[1]) << 8);
 379         return rc;
 380 }
 381
 382 /******************************
 383 *
 384 * int drxdap_fasi_read_reg32 (
 385 *     struct i2c_device_addr *dev_addr, -- address of I2C device
 386 *     dr_xaddr_t        addr,    -- address of chip register/memory
 387 *     u32 *data,    -- data to receive
 388 *     dr_xflags_t       flags)   -- special device flags
 389 *
 390 * Read one 32-bit register or memory location. The data received back is
 391 * converted back to the target platform's endianness.
 392 *
 393 * Output:
 394 * - DRX_STS_OK     if reading was successful
 395 *                  in that case: read data is at *data
 396 * - DRX_STS_ERROR  if anything went wrong
 397 *
 398 ******************************/
 399
 400 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
 401                                          dr_xaddr_t addr,
 402                                          u32 *data, dr_xflags_t flags)
 403 {
 404         u8 buf[sizeof(*data)];
 405         int rc;
 406
 407         if (!data) {
 408                 return DRX_STS_INVALID_ARG;
 409         }
 410         rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
 411         *data = (((u32) buf[0]) << 0) +
 412             (((u32) buf[1]) << 8) +
 413             (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
 414         return rc;
 415 }
 416
 417 /******************************
 418 *
 419 * int drxdap_fasi_write_block (
 420 *      struct i2c_device_addr *dev_addr,    -- address of I2C device
 421 *      dr_xaddr_t        addr,       -- address of chip register/memory
 422 *      u16            datasize,   -- number of bytes to read
 423 *      u8 *data,       -- data to receive
 424 *      dr_xflags_t       flags)      -- special device flags
 425 *
 426 * Write block data to chip address. Because the chip is word oriented,
 427 * the number of bytes to write must be even.
 428 *
 429 * Although this function expects an even number of bytes, it is still byte
 430 * oriented, and the data being written is NOT translated from the endianness of
 431 * the target platform.
 432 *
 433 * Output:
 434 * - DRX_STS_OK     if writing was successful
 435 * - DRX_STS_ERROR  if anything went wrong
 436 *
 437 ******************************/
 438
 439 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
 440                                           dr_xaddr_t addr,
 441                                           u16 datasize,
 442                                           u8 *data, dr_xflags_t flags)
 443 {
 444         u8 buf[DRXDAP_MAX_WCHUNKSIZE];
 445         int st = DRX_STS_ERROR;
 446         int first_err = DRX_STS_OK;
 447         u16 overhead_size = 0;
 448         u16 block_size = 0;
 449
 450         /* Check parameters ******************************************************* */
 451         if (dev_addr == NULL) {
 452                 return DRX_STS_INVALID_ARG;
 453         }
 454
 455         overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
 456             (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
 457
 458         if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
 459             ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
 460              DRXDAP_FASI_LONG_FORMAT(addr)) ||
 461             (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
 462             ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
 463                 return DRX_STS_INVALID_ARG;
 464         }
 465
 466         flags &= DRXDAP_FASI_FLAGS;
 467         flags &= ~DRXDAP_FASI_MODEFLAGS;
 468 #if DRXDAP_SINGLE_MASTER
 469         flags |= DRXDAP_FASI_SINGLE_MASTER;
 470 #endif
 471
 472         /* Write block to I2C ***************************************************** */
 473         block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1;
 474         do {
 475                 u16 todo = 0;
 476                 u16 bufx = 0;
 477
 478                 /* Buffer device address */
 479                 addr &= ~DRXDAP_FASI_FLAGS;
 480                 addr |= flags;
 481 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \
 482       ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
 483                 /* short format address preferred but long format otherwise */
 484                 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
 485 #endif
 486 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1)
 487                         buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
 488                         buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
 489                         buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
 490                         buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
 491 #endif
 492 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \
 493       ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
 494                 } else {
 495 #endif
 496 #if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)
 497                         buf[bufx++] = (u8) ((addr << 1) & 0xFF);
 498                         buf[bufx++] =
 499                             (u8) (((addr >> 16) & 0x0F) |
 500                                     ((addr >> 18) & 0xF0));
 501 #endif
 502 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && \
 503       ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
 504                 }
 505 #endif
 506
 507                 /*
 508                    In single master mode block_size can be 0. In such a case this I2C
 509                    sequense will be visible: (1) write address {i2c addr,
 510                    4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
 511                    (3) write address (4) write data etc...
 512                    Addres must be rewriten because HI is reset after data transport and
 513                    expects an address.
 514                  */
 515                 todo = (block_size < datasize ? block_size : datasize);
 516                 if (todo == 0) {
 517                         u16 overhead_sizeI2cAddr = 0;
 518                         u16 data_block_size = 0;
 519
 520                         overhead_sizeI2cAddr =
 521                             (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1);
 522                         data_block_size =
 523                             (DRXDAP_MAX_WCHUNKSIZE - overhead_sizeI2cAddr) & ~1;
 524
 525                         /* write device address */
 526                         st = drxbsp_i2c_write_read(dev_addr,
 527                                                   (u16) (bufx),
 528                                                   buf,
 529                                                   (struct i2c_device_addr *)(NULL),
 530                                                   0, (u8 *)(NULL));
 531
 532                         if ((st != DRX_STS_OK) && (first_err == DRX_STS_OK)) {
 533                                 /* at the end, return the first error encountered */
 534                                 first_err = st;
 535                         }
 536                         bufx = 0;
 537                         todo =
 538                             (data_block_size <
 539                              datasize ? data_block_size : datasize);
 540                 }
 541                 drxbsp_hst_memcpy(&buf[bufx], data, todo);
 542                 /* write (address if can do and) data */
 543                 st = drxbsp_i2c_write_read(dev_addr,
 544                                           (u16) (bufx + todo),
 545                                           buf,
 546                                           (struct i2c_device_addr *)(NULL),
 547                                           0, (u8 *)(NULL));
 548
 549                 if ((st != DRX_STS_OK) && (first_err == DRX_STS_OK)) {
 550                         /* at the end, return the first error encountered */
 551                         first_err = st;
 552                 }
 553                 datasize -= todo;
 554                 data += todo;
 555                 addr += (todo >> 1);
 556         } while (datasize);
 557
 558         return first_err;
 559 }
 560
 561 /******************************
 562 *
 563 * int drxdap_fasi_write_reg16 (
 564 *     struct i2c_device_addr *dev_addr, -- address of I2C device
 565 *     dr_xaddr_t        addr,    -- address of chip register/memory
 566 *     u16            data,    -- data to send
 567 *     dr_xflags_t       flags)   -- special device flags
 568 *
 569 * Write one 16-bit register or memory location. The data being written is
 570 * converted from the target platform's endianness to little endian.
 571 *
 572 * Output:
 573 * - DRX_STS_OK     if writing was successful
 574 * - DRX_STS_ERROR  if anything went wrong
 575 *
 576 ******************************/
 577
 578 static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr,
 579                                           dr_xaddr_t addr,
 580                                           u16 data, dr_xflags_t flags)
 581 {
 582         u8 buf[sizeof(data)];
 583
 584         buf[0] = (u8) ((data >> 0) & 0xFF);
 585         buf[1] = (u8) ((data >> 8) & 0xFF);
 586
 587         return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
 588 }
 589
 590 /******************************
 591 *
 592 * int drxdap_fasi_write_reg32 (
 593 *     struct i2c_device_addr *dev_addr, -- address of I2C device
 594 *     dr_xaddr_t        addr,    -- address of chip register/memory
 595 *     u32            data,    -- data to send
 596 *     dr_xflags_t       flags)   -- special device flags
 597 *
 598 * Write one 32-bit register or memory location. The data being written is
 599 * converted from the target platform's endianness to little endian.
 600 *
 601 * Output:
 602 * - DRX_STS_OK     if writing was successful
 603 * - DRX_STS_ERROR  if anything went wrong
 604 *
 605 ******************************/
 606
 607 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
 608                                           dr_xaddr_t addr,
 609                                           u32 data, dr_xflags_t flags)
 610 {
 611         u8 buf[sizeof(data)];
 612
 613         buf[0] = (u8) ((data >> 0) & 0xFF);
 614         buf[1] = (u8) ((data >> 8) & 0xFF);
 615         buf[2] = (u8) ((data >> 16) & 0xFF);
 616         buf[3] = (u8) ((data >> 24) & 0xFF);
 617
 618         return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
 619 }