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[media] drx-j: get rid of the integer typedefs
[deliverable/linux.git] / drivers / media / dvb-frontends / drx39xyj / drx_driver.h
1 /*
2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
7
8 * Redistributions of source code must retain the above copyright notice,
9 this list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice,
11 this list of conditions and the following disclaimer in the documentation
12 and/or other materials provided with the distribution.
13 * Neither the name of Trident Microsystems nor Hauppauge Computer Works
14 nor the names of its contributors may be used to endorse or promote
15 products derived from this software without specific prior written
16 permission.
17
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 /**
32 * \file $Id: drx_driver.h,v 1.84 2010/01/14 22:47:50 dingtao Exp $
33 *
34 * \brief DRX driver API
35 *
36 */
37 #ifndef __DRXDRIVER_H__
38 #define __DRXDRIVER_H__
39 /*-------------------------------------------------------------------------
40 INCLUDES
41 -------------------------------------------------------------------------*/
42 #include "bsp_types.h"
43 #include "bsp_i2c.h"
44 #include "bsp_tuner.h"
45 #include "bsp_host.h"
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50 /*-------------------------------------------------------------------------
51 TYPEDEFS
52 -------------------------------------------------------------------------*/
53
54 /*-------------------------------------------------------------------------
55 DEFINES
56 -------------------------------------------------------------------------*/
57
58 /**************
59 *
60 * This section configures the DRX Data Access Protocols (DAPs).
61 *
62 **************/
63
64 /**
65 * \def DRXDAP_SINGLE_MASTER
66 * \brief Enable I2C single or I2C multimaster mode on host.
67 *
68 * Set to 1 to enable single master mode
69 * Set to 0 to enable multi master mode
70 *
71 * The actual DAP implementation may be restricted to only one of the modes.
72 * A compiler warning or error will be generated if the DAP implementation
73 * overides or cannot handle the mode defined below.
74 *
75 */
76 #ifndef DRXDAP_SINGLE_MASTER
77 #define DRXDAP_SINGLE_MASTER 0
78 #endif
79
80 /**
81 * \def DRXDAP_MAX_WCHUNKSIZE
82 * \brief Defines maximum chunksize of an i2c write action by host.
83 *
84 * This indicates the maximum size of data the I2C device driver is able to
85 * write at a time. This includes I2C device address and register addressing.
86 *
87 * This maximum size may be restricted by the actual DAP implementation.
88 * A compiler warning or error will be generated if the DAP implementation
89 * overides or cannot handle the chunksize defined below.
90 *
91 * Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data
92 * buffer. Do not undefine or choose too large, unless your system is able to
93 * handle a stack buffer of that size.
94 *
95 */
96 #ifndef DRXDAP_MAX_WCHUNKSIZE
97 #define DRXDAP_MAX_WCHUNKSIZE 60
98 #endif
99
100 /**
101 * \def DRXDAP_MAX_RCHUNKSIZE
102 * \brief Defines maximum chunksize of an i2c read action by host.
103 *
104 * This indicates the maximum size of data the I2C device driver is able to read
105 * at a time. Minimum value is 2. Also, the read chunk size must be even.
106 *
107 * This maximum size may be restricted by the actual DAP implementation.
108 * A compiler warning or error will be generated if the DAP implementation
109 * overides or cannot handle the chunksize defined below.
110 *
111 */
112 #ifndef DRXDAP_MAX_RCHUNKSIZE
113 #define DRXDAP_MAX_RCHUNKSIZE 60
114 #endif
115
116 /**************
117 *
118 * This section describes drxdriver defines.
119 *
120 **************/
121
122 /**
123 * \def DRX_UNKNOWN
124 * \brief Generic UNKNOWN value for DRX enumerated types.
125 *
126 * Used to indicate that the parameter value is unknown or not yet initalized.
127 */
128 #ifndef DRX_UNKNOWN
129 #define DRX_UNKNOWN (254)
130 #endif
131
132 /**
133 * \def DRX_AUTO
134 * \brief Generic AUTO value for DRX enumerated types.
135 *
136 * Used to instruct the driver to automatically determine the value of the
137 * parameter.
138 */
139 #ifndef DRX_AUTO
140 #define DRX_AUTO (255)
141 #endif
142
143 /**************
144 *
145 * This section describes flag definitions for the device capbilities.
146 *
147 **************/
148
149 /**
150 * \brief LNA capability flag
151 *
152 * Device has a Low Noise Amplifier
153 *
154 */
155 #define DRX_CAPABILITY_HAS_LNA (1UL << 0)
156 /**
157 * \brief OOB-RX capability flag
158 *
159 * Device has OOB-RX
160 *
161 */
162 #define DRX_CAPABILITY_HAS_OOBRX (1UL << 1)
163 /**
164 * \brief ATV capability flag
165 *
166 * Device has ATV
167 *
168 */
169 #define DRX_CAPABILITY_HAS_ATV (1UL << 2)
170 /**
171 * \brief DVB-T capability flag
172 *
173 * Device has DVB-T
174 *
175 */
176 #define DRX_CAPABILITY_HAS_DVBT (1UL << 3)
177 /**
178 * \brief ITU-B capability flag
179 *
180 * Device has ITU-B
181 *
182 */
183 #define DRX_CAPABILITY_HAS_ITUB (1UL << 4)
184 /**
185 * \brief Audio capability flag
186 *
187 * Device has Audio
188 *
189 */
190 #define DRX_CAPABILITY_HAS_AUD (1UL << 5)
191 /**
192 * \brief SAW switch capability flag
193 *
194 * Device has SAW switch
195 *
196 */
197 #define DRX_CAPABILITY_HAS_SAWSW (1UL << 6)
198 /**
199 * \brief GPIO1 capability flag
200 *
201 * Device has GPIO1
202 *
203 */
204 #define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7)
205 /**
206 * \brief GPIO2 capability flag
207 *
208 * Device has GPIO2
209 *
210 */
211 #define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8)
212 /**
213 * \brief IRQN capability flag
214 *
215 * Device has IRQN
216 *
217 */
218 #define DRX_CAPABILITY_HAS_IRQN (1UL << 9)
219 /**
220 * \brief 8VSB capability flag
221 *
222 * Device has 8VSB
223 *
224 */
225 #define DRX_CAPABILITY_HAS_8VSB (1UL << 10)
226 /**
227 * \brief SMA-TX capability flag
228 *
229 * Device has SMATX
230 *
231 */
232 #define DRX_CAPABILITY_HAS_SMATX (1UL << 11)
233 /**
234 * \brief SMA-RX capability flag
235 *
236 * Device has SMARX
237 *
238 */
239 #define DRX_CAPABILITY_HAS_SMARX (1UL << 12)
240 /**
241 * \brief ITU-A/C capability flag
242 *
243 * Device has ITU-A/C
244 *
245 */
246 #define DRX_CAPABILITY_HAS_ITUAC (1UL << 13)
247
248 /*-------------------------------------------------------------------------
249 MACROS
250 -------------------------------------------------------------------------*/
251 /* Macros to stringify the version number */
252 #define DRX_VERSIONSTRING( MAJOR, MINOR, PATCH ) \
253 DRX_VERSIONSTRING_HELP(MAJOR)"." \
254 DRX_VERSIONSTRING_HELP(MINOR)"." \
255 DRX_VERSIONSTRING_HELP(PATCH)
256 #define DRX_VERSIONSTRING_HELP( NUM ) #NUM
257
258 /**
259 * \brief Macro to create byte array elements from 16 bit integers.
260 * This macro is used to create byte arrays for block writes.
261 * Block writes speed up I2C traffic between host and demod.
262 * The macro takes care of the required byte order in a 16 bits word.
263 * x->lowbyte(x), highbyte(x)
264 */
265 #define DRX_16TO8( x ) ((u8) (((u16)x) &0xFF)), \
266 ((u8)((((u16)x)>>8)&0xFF))
267
268 /**
269 * \brief Macro to sign extend signed 9 bit value to signed 16 bit value
270 */
271 #define DRX_S9TOS16(x) ((((u16)x)&0x100 )?((s16)((u16)(x)|0xFF00)):(x))
272
273 /**
274 * \brief Macro to sign extend signed 9 bit value to signed 16 bit value
275 */
276 #define DRX_S24TODRXFREQ(x) ( ( ( (u32) x ) & 0x00800000UL ) ? \
277 ( (DRXFrequency_t) \
278 ( ( (u32) x ) | 0xFF000000 ) ) : \
279 ( (DRXFrequency_t) x ) )
280
281 /**
282 * \brief Macro to convert 16 bit register value to a DRXFrequency_t
283 */
284 #define DRX_U16TODRXFREQ(x) ( ( x & 0x8000 ) ? \
285 ( (DRXFrequency_t) \
286 ( ( (u32) x ) | 0xFFFF0000 ) ) : \
287 ( (DRXFrequency_t) x ) )
288
289 /*-------------------------------------------------------------------------
290 ENUM
291 -------------------------------------------------------------------------*/
292
293 /**
294 * \enum DRXStandard_t
295 * \brief Modulation standards.
296 */
297 typedef enum {
298 DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */
299 DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */
300 DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */
301 DRX_STANDARD_PAL_SECAM_BG,
302 /**< Terrestrial analog PAL/SECAM B/G */
303 DRX_STANDARD_PAL_SECAM_DK,
304 /**< Terrestrial analog PAL/SECAM D/K */
305 DRX_STANDARD_PAL_SECAM_I,
306 /**< Terrestrial analog PAL/SECAM I */
307 DRX_STANDARD_PAL_SECAM_L,
308 /**< Terrestrial analog PAL/SECAM L
309 with negative modulation */
310 DRX_STANDARD_PAL_SECAM_LP,
311 /**< Terrestrial analog PAL/SECAM L
312 with positive modulation */
313 DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */
314 DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */
315 DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */
316 DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */
317 DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */
318 DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/
319 DRX_STANDARD_UNKNOWN = DRX_UNKNOWN,
320 /**< Standard unknown. */
321 DRX_STANDARD_AUTO = DRX_AUTO
322 /**< Autodetect standard. */
323 } DRXStandard_t, *pDRXStandard_t;
324
325 /**
326 * \enum DRXStandard_t
327 * \brief Modulation sub-standards.
328 */
329 typedef enum {
330 DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */
331 DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA,
332 DRX_SUBSTANDARD_ATV_DK_POLAND,
333 DRX_SUBSTANDARD_ATV_DK_CHINA,
334 DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN,
335 /**< Sub-standard unknown. */
336 DRX_SUBSTANDARD_AUTO = DRX_AUTO
337 /**< Auto (default) sub-standard */
338 } DRXSubstandard_t, *pDRXSubstandard_t;
339
340 /**
341 * \enum DRXBandwidth_t
342 * \brief Channel bandwidth or channel spacing.
343 */
344 typedef enum {
345 DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */
346 DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */
347 DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */
348 DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN,
349 /**< Bandwidth unknown. */
350 DRX_BANDWIDTH_AUTO = DRX_AUTO
351 /**< Auto Set Bandwidth */
352 } DRXBandwidth_t, *pDRXBandwidth_t;
353
354 /**
355 * \enum DRXMirror_t
356 * \brief Indicate if channel spectrum is mirrored or not.
357 */
358 typedef enum {
359 DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */
360 DRX_MIRROR_YES, /**< Spectrum is mirrored. */
361 DRX_MIRROR_UNKNOWN = DRX_UNKNOWN,
362 /**< Unknown if spectrum is mirrored. */
363 DRX_MIRROR_AUTO = DRX_AUTO
364 /**< Autodetect if spectrum is mirrored. */
365 } DRXMirror_t, *pDRXMirror_t;
366
367 /**
368 * \enum DRXConstellation_t
369 * \brief Constellation type of the channel.
370 */
371 typedef enum {
372 DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */
373 DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */
374 DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */
375 DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */
376 DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */
377 DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */
378 DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */
379 DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */
380 DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */
381 DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */
382 DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */
383 DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
384 /**< Constellation unknown. */
385 DRX_CONSTELLATION_AUTO = DRX_AUTO
386 /**< Autodetect constellation. */
387 } DRXConstellation_t, *pDRXConstellation_t;
388
389 /**
390 * \enum DRXHierarchy_t
391 * \brief Hierarchy of the channel.
392 */
393 typedef enum {
394 DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */
395 DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */
396 DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */
397 DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */
398 DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN,
399 /**< Hierarchy unknown. */
400 DRX_HIERARCHY_AUTO = DRX_AUTO
401 /**< Autodetect hierarchy. */
402 } DRXHierarchy_t, *pDRXHierarchy_t;
403
404 /**
405 * \enum DRXPriority_t
406 * \brief Channel priority in case of hierarchical transmission.
407 */
408 typedef enum {
409 DRX_PRIORITY_LOW = 0, /**< Low priority channel. */
410 DRX_PRIORITY_HIGH, /**< High priority channel. */
411 DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN
412 /**< Priority unknown. */
413 } DRXPriority_t, *pDRXPriority_t;
414
415 /**
416 * \enum DRXCoderate_t
417 * \brief Channel priority in case of hierarchical transmission.
418 */
419 typedef enum {
420 DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */
421 DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */
422 DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */
423 DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */
424 DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */
425 DRX_CODERATE_UNKNOWN = DRX_UNKNOWN,
426 /**< Code rate unknown. */
427 DRX_CODERATE_AUTO = DRX_AUTO
428 /**< Autodetect code rate. */
429 } DRXCoderate_t, *pDRXCoderate_t;
430
431 /**
432 * \enum DRXGuard_t
433 * \brief Guard interval of a channel.
434 */
435 typedef enum {
436 DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */
437 DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */
438 DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */
439 DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */
440 DRX_GUARD_UNKNOWN = DRX_UNKNOWN,
441 /**< Guard interval unknown. */
442 DRX_GUARD_AUTO = DRX_AUTO
443 /**< Autodetect guard interval. */
444 } DRXGuard_t, *pDRXGuard_t;
445
446 /**
447 * \enum DRXFftmode_t
448 * \brief FFT mode.
449 */
450 typedef enum {
451 DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */
452 DRX_FFTMODE_4K, /**< 4K FFT mode. */
453 DRX_FFTMODE_8K, /**< 8K FFT mode. */
454 DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
455 /**< FFT mode unknown. */
456 DRX_FFTMODE_AUTO = DRX_AUTO
457 /**< Autodetect FFT mode. */
458 } DRXFftmode_t, *pDRXFftmode_t;
459
460 /**
461 * \enum DRXClassification_t
462 * \brief Channel classification.
463 */
464 typedef enum {
465 DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */
466 DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */
467 DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */
468 DRX_CLASSIFICATION_STATIC, /**< Static echo. */
469 DRX_CLASSIFICATION_MOVING, /**< Moving echo. */
470 DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */
471 DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN,
472 /**< Unknown classification */
473 DRX_CLASSIFICATION_AUTO = DRX_AUTO
474 /**< Autodetect classification. */
475 } DRXClassification_t, *pDRXClassification_t;
476
477 /**
478 * /enum DRXInterleaveModes_t
479 * /brief Interleave modes
480 */
481 typedef enum {
482 DRX_INTERLEAVEMODE_I128_J1 = 0,
483 DRX_INTERLEAVEMODE_I128_J1_V2,
484 DRX_INTERLEAVEMODE_I128_J2,
485 DRX_INTERLEAVEMODE_I64_J2,
486 DRX_INTERLEAVEMODE_I128_J3,
487 DRX_INTERLEAVEMODE_I32_J4,
488 DRX_INTERLEAVEMODE_I128_J4,
489 DRX_INTERLEAVEMODE_I16_J8,
490 DRX_INTERLEAVEMODE_I128_J5,
491 DRX_INTERLEAVEMODE_I8_J16,
492 DRX_INTERLEAVEMODE_I128_J6,
493 DRX_INTERLEAVEMODE_RESERVED_11,
494 DRX_INTERLEAVEMODE_I128_J7,
495 DRX_INTERLEAVEMODE_RESERVED_13,
496 DRX_INTERLEAVEMODE_I128_J8,
497 DRX_INTERLEAVEMODE_RESERVED_15,
498 DRX_INTERLEAVEMODE_I12_J17,
499 DRX_INTERLEAVEMODE_I5_J4,
500 DRX_INTERLEAVEMODE_B52_M240,
501 DRX_INTERLEAVEMODE_B52_M720,
502 DRX_INTERLEAVEMODE_B52_M48,
503 DRX_INTERLEAVEMODE_B52_M0,
504 DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN,
505 /**< Unknown interleave mode */
506 DRX_INTERLEAVEMODE_AUTO = DRX_AUTO
507 /**< Autodetect interleave mode */
508 } DRXInterleaveModes_t, *pDRXInterleaveModes_t;
509
510 /**
511 * \enum DRXCarrier_t
512 * \brief Channel Carrier Mode.
513 */
514 typedef enum {
515 DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */
516 DRX_CARRIER_SINGLE, /**< Single carrier mode */
517 DRX_CARRIER_UNKNOWN = DRX_UNKNOWN,
518 /**< Carrier mode unknown. */
519 DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */
520 } DRXCarrier_t, *pDRXCarrier_t;
521
522 /**
523 * \enum DRXFramemode_t
524 * \brief Channel Frame Mode.
525 */
526 typedef enum {
527 DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */
528 DRX_FRAMEMODE_595, /**< 595 */
529 DRX_FRAMEMODE_945, /**< 945 with variable PN */
530 DRX_FRAMEMODE_420_FIXED_PN,
531 /**< 420 with fixed PN */
532 DRX_FRAMEMODE_945_FIXED_PN,
533 /**< 945 with fixed PN */
534 DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN,
535 /**< Frame mode unknown. */
536 DRX_FRAMEMODE_AUTO = DRX_AUTO
537 /**< Autodetect frame mode */
538 } DRXFramemode_t, *pDRXFramemode_t;
539
540 /**
541 * \enum DRXTPSFrame_t
542 * \brief Frame number in current super-frame.
543 */
544 typedef enum {
545 DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */
546 DRX_TPS_FRAME2, /**< TPS frame 2. */
547 DRX_TPS_FRAME3, /**< TPS frame 3. */
548 DRX_TPS_FRAME4, /**< TPS frame 4. */
549 DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN
550 /**< TPS frame unknown. */
551 } DRXTPSFrame_t, *pDRXTPSFrame_t;
552
553 /**
554 * \enum DRXLDPC_t
555 * \brief TPS LDPC .
556 */
557 typedef enum {
558 DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */
559 DRX_LDPC_0_6, /**< LDPC 0.6 */
560 DRX_LDPC_0_8, /**< LDPC 0.8 */
561 DRX_LDPC_UNKNOWN = DRX_UNKNOWN,
562 /**< LDPC unknown. */
563 DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */
564 } DRXLDPC_t, *pDRXLDPC_t;
565
566 /**
567 * \enum DRXPilotMode_t
568 * \brief Pilot modes in DTMB.
569 */
570 typedef enum {
571 DRX_PILOT_ON = 0, /**< Pilot On */
572 DRX_PILOT_OFF, /**< Pilot Off */
573 DRX_PILOT_UNKNOWN = DRX_UNKNOWN,
574 /**< Pilot unknown. */
575 DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */
576 } DRXPilotMode_t, *pDRXPilotMode_t;
577
578 /**
579 * \enum DRXCtrlIndex_t
580 * \brief Indices of the control functions.
581 */
582 typedef u32 DRXCtrlIndex_t, *pDRXCtrlIndex_t;
583
584 #ifndef DRX_CTRL_BASE
585 #define DRX_CTRL_BASE ((DRXCtrlIndex_t)0)
586 #endif
587
588 #define DRX_CTRL_NOP ( DRX_CTRL_BASE + 0)/**< No Operation */
589 #define DRX_CTRL_PROBE_DEVICE ( DRX_CTRL_BASE + 1)/**< Probe device */
590
591 #define DRX_CTRL_LOAD_UCODE ( DRX_CTRL_BASE + 2)/**< Load microcode */
592 #define DRX_CTRL_VERIFY_UCODE ( DRX_CTRL_BASE + 3)/**< Verify microcode */
593 #define DRX_CTRL_SET_CHANNEL ( DRX_CTRL_BASE + 4)/**< Set channel */
594 #define DRX_CTRL_GET_CHANNEL ( DRX_CTRL_BASE + 5)/**< Get channel */
595 #define DRX_CTRL_LOCK_STATUS ( DRX_CTRL_BASE + 6)/**< Get lock status */
596 #define DRX_CTRL_SIG_QUALITY ( DRX_CTRL_BASE + 7)/**< Get signal quality */
597 #define DRX_CTRL_SIG_STRENGTH ( DRX_CTRL_BASE + 8)/**< Get signal strength*/
598 #define DRX_CTRL_RF_POWER ( DRX_CTRL_BASE + 9)/**< Get RF power */
599 #define DRX_CTRL_CONSTEL ( DRX_CTRL_BASE + 10)/**< Get constel point */
600 #define DRX_CTRL_SCAN_INIT ( DRX_CTRL_BASE + 11)/**< Initialize scan */
601 #define DRX_CTRL_SCAN_NEXT ( DRX_CTRL_BASE + 12)/**< Scan for next */
602 #define DRX_CTRL_SCAN_STOP ( DRX_CTRL_BASE + 13)/**< Stop scan */
603 #define DRX_CTRL_TPS_INFO ( DRX_CTRL_BASE + 14)/**< Get TPS info */
604 #define DRX_CTRL_SET_CFG ( DRX_CTRL_BASE + 15)/**< Set configuration */
605 #define DRX_CTRL_GET_CFG ( DRX_CTRL_BASE + 16)/**< Get configuration */
606 #define DRX_CTRL_VERSION ( DRX_CTRL_BASE + 17)/**< Get version info */
607 #define DRX_CTRL_I2C_BRIDGE ( DRX_CTRL_BASE + 18)/**< Open/close bridge */
608 #define DRX_CTRL_SET_STANDARD ( DRX_CTRL_BASE + 19)/**< Set demod std */
609 #define DRX_CTRL_GET_STANDARD ( DRX_CTRL_BASE + 20)/**< Get demod std */
610 #define DRX_CTRL_SET_OOB ( DRX_CTRL_BASE + 21)/**< Set OOB param */
611 #define DRX_CTRL_GET_OOB ( DRX_CTRL_BASE + 22)/**< Get OOB param */
612 #define DRX_CTRL_AUD_SET_STANDARD (DRX_CTRL_BASE + 23)/**< Set audio param */
613 #define DRX_CTRL_AUD_GET_STANDARD (DRX_CTRL_BASE + 24)/**< Get audio param */
614 #define DRX_CTRL_AUD_GET_STATUS ( DRX_CTRL_BASE + 25)/**< Read RDS */
615 #define DRX_CTRL_AUD_BEEP ( DRX_CTRL_BASE + 26)/**< Read RDS */
616 #define DRX_CTRL_I2C_READWRITE ( DRX_CTRL_BASE + 27)/**< Read/write I2C */
617 #define DRX_CTRL_PROGRAM_TUNER ( DRX_CTRL_BASE + 28)/**< Program tuner */
618
619 /* Professional */
620 #define DRX_CTRL_MB_CFG ( DRX_CTRL_BASE + 29) /**< */
621 #define DRX_CTRL_MB_READ ( DRX_CTRL_BASE + 30) /**< */
622 #define DRX_CTRL_MB_WRITE ( DRX_CTRL_BASE + 31) /**< */
623 #define DRX_CTRL_MB_CONSTEL ( DRX_CTRL_BASE + 32) /**< */
624 #define DRX_CTRL_MB_MER ( DRX_CTRL_BASE + 33) /**< */
625
626 /* Misc */
627 #define DRX_CTRL_UIO_CFG DRX_CTRL_SET_UIO_CFG /**< Configure UIO */
628 #define DRX_CTRL_SET_UIO_CFG ( DRX_CTRL_BASE + 34) /**< Configure UIO */
629 #define DRX_CTRL_GET_UIO_CFG ( DRX_CTRL_BASE + 35) /**< Configure UIO */
630 #define DRX_CTRL_UIO_READ ( DRX_CTRL_BASE + 36) /**< Read from UIO */
631 #define DRX_CTRL_UIO_WRITE ( DRX_CTRL_BASE + 37) /**< Write to UIO */
632 #define DRX_CTRL_READ_EVENTS ( DRX_CTRL_BASE + 38) /**< Read events */
633 #define DRX_CTRL_HDL_EVENTS ( DRX_CTRL_BASE + 39) /**< Handle events */
634 #define DRX_CTRL_POWER_MODE ( DRX_CTRL_BASE + 40) /**< Set power mode */
635 #define DRX_CTRL_LOAD_FILTER ( DRX_CTRL_BASE + 41) /**< Load chan. filter */
636 #define DRX_CTRL_VALIDATE_UCODE ( DRX_CTRL_BASE + 42) /**< Validate ucode */
637 #define DRX_CTRL_DUMP_REGISTERS ( DRX_CTRL_BASE + 43) /**< Dump registers */
638
639 #define DRX_CTRL_MAX ( DRX_CTRL_BASE + 44) /* never to be used */
640
641 /**
642 * \enum DRXUCodeAction_t
643 * \brief Used to indicate if firmware has to be uploaded or verified.
644 */
645
646 typedef enum {
647 UCODE_UPLOAD,
648 /**< Upload the microcode image to device */
649 UCODE_VERIFY
650 /**< Compare microcode image with code on device */
651 } DRXUCodeAction_t, *pDRXUCodeAction_t;
652
653 /**
654 * \enum DRXLockStatus_t
655 * \brief Used to reflect current lock status of demodulator.
656 *
657 * The generic lock states have device dependent semantics.
658 */
659 typedef enum {
660 DRX_NEVER_LOCK = 0,
661 /**< Device will never lock on this signal */
662 DRX_NOT_LOCKED,
663 /**< Device has no lock at all */
664 DRX_LOCK_STATE_1,
665 /**< Generic lock state */
666 DRX_LOCK_STATE_2,
667 /**< Generic lock state */
668 DRX_LOCK_STATE_3,
669 /**< Generic lock state */
670 DRX_LOCK_STATE_4,
671 /**< Generic lock state */
672 DRX_LOCK_STATE_5,
673 /**< Generic lock state */
674 DRX_LOCK_STATE_6,
675 /**< Generic lock state */
676 DRX_LOCK_STATE_7,
677 /**< Generic lock state */
678 DRX_LOCK_STATE_8,
679 /**< Generic lock state */
680 DRX_LOCK_STATE_9,
681 /**< Generic lock state */
682 DRX_LOCKED /**< Device is in lock */
683 } DRXLockStatus_t, *pDRXLockStatus_t;
684
685 /**
686 * \enum DRXUIO_t
687 * \brief Used to address a User IO (UIO).
688 */
689 typedef enum {
690 DRX_UIO1,
691 DRX_UIO2,
692 DRX_UIO3,
693 DRX_UIO4,
694 DRX_UIO5,
695 DRX_UIO6,
696 DRX_UIO7,
697 DRX_UIO8,
698 DRX_UIO9,
699 DRX_UIO10,
700 DRX_UIO11,
701 DRX_UIO12,
702 DRX_UIO13,
703 DRX_UIO14,
704 DRX_UIO15,
705 DRX_UIO16,
706 DRX_UIO17,
707 DRX_UIO18,
708 DRX_UIO19,
709 DRX_UIO20,
710 DRX_UIO21,
711 DRX_UIO22,
712 DRX_UIO23,
713 DRX_UIO24,
714 DRX_UIO25,
715 DRX_UIO26,
716 DRX_UIO27,
717 DRX_UIO28,
718 DRX_UIO29,
719 DRX_UIO30,
720 DRX_UIO31,
721 DRX_UIO32,
722 DRX_UIO_MAX = DRX_UIO32
723 } DRXUIO_t, *pDRXUIO_t;
724
725 /**
726 * \enum DRXUIOMode_t
727 * \brief Used to configure the modus oprandi of a UIO.
728 *
729 * DRX_UIO_MODE_FIRMWARE is an old uio mode.
730 * It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9.
731 * To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to
732 * DRX_UIO_MODE_FIRMWARE0.
733 */
734 typedef enum {
735 DRX_UIO_MODE_DISABLE = 0x01,
736 /**< not used, pin is configured as input */
737 DRX_UIO_MODE_READWRITE = 0x02,
738 /**< used for read/write by application */
739 DRX_UIO_MODE_FIRMWARE = 0x04,
740 /**< controlled by firmware, function 0 */
741 DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE,
742 /**< same as above */
743 DRX_UIO_MODE_FIRMWARE1 = 0x08,
744 /**< controlled by firmware, function 1 */
745 DRX_UIO_MODE_FIRMWARE2 = 0x10,
746 /**< controlled by firmware, function 2 */
747 DRX_UIO_MODE_FIRMWARE3 = 0x20,
748 /**< controlled by firmware, function 3 */
749 DRX_UIO_MODE_FIRMWARE4 = 0x40,
750 /**< controlled by firmware, function 4 */
751 DRX_UIO_MODE_FIRMWARE5 = 0x80
752 /**< controlled by firmware, function 5 */
753 } DRXUIOMode_t, *pDRXUIOMode_t;
754
755 /**
756 * \enum DRXOOBDownstreamStandard_t
757 * \brief Used to select OOB standard.
758 *
759 * Based on ANSI 55-1 and 55-2
760 */
761 typedef enum {
762 DRX_OOB_MODE_A = 0,
763 /**< ANSI 55-1 */
764 DRX_OOB_MODE_B_GRADE_A,
765 /**< ANSI 55-2 A */
766 DRX_OOB_MODE_B_GRADE_B
767 /**< ANSI 55-2 B */
768 } DRXOOBDownstreamStandard_t, *pDRXOOBDownstreamStandard_t;
769
770 /*-------------------------------------------------------------------------
771 STRUCTS
772 -------------------------------------------------------------------------*/
773
774 /*============================================================================*/
775 /*============================================================================*/
776 /*== CTRL CFG related data structures ========================================*/
777 /*============================================================================*/
778 /*============================================================================*/
779
780 /**
781 * \enum DRXCfgType_t
782 * \brief Generic configuration function identifiers.
783 */
784 typedef u32 DRXCfgType_t, *pDRXCfgType_t;
785
786 #ifndef DRX_CFG_BASE
787 #define DRX_CFG_BASE ((DRXCfgType_t)0)
788 #endif
789
790 #define DRX_CFG_MPEG_OUTPUT ( DRX_CFG_BASE + 0) /* MPEG TS output */
791 #define DRX_CFG_PKTERR ( DRX_CFG_BASE + 1) /* Packet Error */
792 #define DRX_CFG_SYMCLK_OFFS ( DRX_CFG_BASE + 2) /* Symbol Clk Offset */
793 #define DRX_CFG_SMA ( DRX_CFG_BASE + 3) /* Smart Antenna */
794 #define DRX_CFG_PINSAFE ( DRX_CFG_BASE + 4) /* Pin safe mode */
795 #define DRX_CFG_SUBSTANDARD ( DRX_CFG_BASE + 5) /* substandard */
796 #define DRX_CFG_AUD_VOLUME ( DRX_CFG_BASE + 6) /* volume */
797 #define DRX_CFG_AUD_RDS ( DRX_CFG_BASE + 7) /* rds */
798 #define DRX_CFG_AUD_AUTOSOUND ( DRX_CFG_BASE + 8) /* ASS & ASC */
799 #define DRX_CFG_AUD_ASS_THRES ( DRX_CFG_BASE + 9) /* ASS Thresholds */
800 #define DRX_CFG_AUD_DEVIATION ( DRX_CFG_BASE + 10) /* Deviation */
801 #define DRX_CFG_AUD_PRESCALE ( DRX_CFG_BASE + 11) /* Prescale */
802 #define DRX_CFG_AUD_MIXER ( DRX_CFG_BASE + 12) /* Mixer */
803 #define DRX_CFG_AUD_AVSYNC ( DRX_CFG_BASE + 13) /* AVSync */
804 #define DRX_CFG_AUD_CARRIER ( DRX_CFG_BASE + 14) /* Audio carriers */
805 #define DRX_CFG_I2S_OUTPUT ( DRX_CFG_BASE + 15) /* I2S output */
806 #define DRX_CFG_ATV_STANDARD ( DRX_CFG_BASE + 16) /* ATV standard */
807 #define DRX_CFG_SQI_SPEED ( DRX_CFG_BASE + 17) /* SQI speed */
808 #define DRX_CTRL_CFG_MAX ( DRX_CFG_BASE + 18) /* never to be used */
809
810 #define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE
811 /*============================================================================*/
812 /*============================================================================*/
813 /*== CTRL related data structures ============================================*/
814 /*============================================================================*/
815 /*============================================================================*/
816
817 /**
818 * \struct DRXUCodeInfo_t
819 * \brief Parameters for microcode upload and verfiy.
820 *
821 * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE
822 */
823 typedef struct {
824 u8 *mcData;
825 /**< Pointer to microcode image. */
826 u16 mcSize;
827 /**< Microcode image size. */
828 } DRXUCodeInfo_t, *pDRXUCodeInfo_t;
829
830 /**
831 * \struct DRXMcVersionRec_t
832 * \brief Microcode version record
833 * Version numbers are stored in BCD format, as usual:
834 * o major number = bits 31-20 (first three nibbles of MSW)
835 * o minor number = bits 19-16 (fourth nibble of MSW)
836 * o patch number = bits 15-0 (remaining nibbles in LSW)
837 *
838 * The device type indicates for which the device is meant. It is based on the
839 * JTAG ID, using everything except the bond ID and the metal fix.
840 *
841 * Special values:
842 * - mcDevType == 0 => any device allowed
843 * - mcBaseVersion == 0.0.0 => full microcode (mcVersion is the version)
844 * - mcBaseVersion != 0.0.0 => patch microcode, the base microcode version
845 * (mcVersion is the version)
846 */
847 #define AUX_VER_RECORD 0x8000
848
849 typedef struct {
850 u16 auxType; /* type of aux data - 0x8000 for version record */
851 u32 mcDevType; /* device type, based on JTAG ID */
852 u32 mcVersion; /* version of microcode */
853 u32 mcBaseVersion; /* in case of patch: the original microcode version */
854 } DRXMcVersionRec_t, *pDRXMcVersionRec_t;
855
856 /*========================================*/
857
858 /**
859 * \struct DRXFilterInfo_t
860 * \brief Parameters for loading filter coefficients
861 *
862 * Used by DRX_CTRL_LOAD_FILTER
863 */
864 typedef struct {
865 u8 *dataRe;
866 /**< pointer to coefficients for RE */
867 u8 *dataIm;
868 /**< pointer to coefficients for IM */
869 u16 sizeRe;
870 /**< size of coefficients for RE */
871 u16 sizeIm;
872 /**< size of coefficients for IM */
873 } DRXFilterInfo_t, *pDRXFilterInfo_t;
874
875 /*========================================*/
876
877 /**
878 * \struct DRXChannel_t
879 * \brief The set of parameters describing a single channel.
880 *
881 * Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL.
882 * Only certain fields need to be used for a specfic standard.
883 *
884 */
885 typedef struct {
886 DRXFrequency_t frequency;
887 /**< frequency in kHz */
888 DRXBandwidth_t bandwidth;
889 /**< bandwidth */
890 DRXMirror_t mirror; /**< mirrored or not on RF */
891 DRXConstellation_t constellation;
892 /**< constellation */
893 DRXHierarchy_t hierarchy;
894 /**< hierarchy */
895 DRXPriority_t priority; /**< priority */
896 DRXCoderate_t coderate; /**< coderate */
897 DRXGuard_t guard; /**< guard interval */
898 DRXFftmode_t fftmode; /**< fftmode */
899 DRXClassification_t classification;
900 /**< classification */
901 DRXSymbolrate_t symbolrate;
902 /**< symbolrate in symbols/sec */
903 DRXInterleaveModes_t interleavemode;
904 /**< interleaveMode QAM */
905 DRXLDPC_t ldpc; /**< ldpc */
906 DRXCarrier_t carrier; /**< carrier */
907 DRXFramemode_t framemode;
908 /**< frame mode */
909 DRXPilotMode_t pilot; /**< pilot mode */
910 } DRXChannel_t, *pDRXChannel_t;
911
912 /*========================================*/
913
914 /**
915 * \struct DRXSigQuality_t
916 * Signal quality metrics.
917 *
918 * Used by DRX_CTRL_SIG_QUALITY.
919 */
920 typedef struct {
921 u16 MER; /**< in steps of 0.1 dB */
922 u32 preViterbiBER;
923 /**< in steps of 1/scaleFactorBER */
924 u32 postViterbiBER;
925 /**< in steps of 1/scaleFactorBER */
926 u32 scaleFactorBER;
927 /**< scale factor for BER */
928 u16 packetError;
929 /**< number of packet errors */
930 u32 postReedSolomonBER;
931 /**< in steps of 1/scaleFactorBER */
932 u32 preLdpcBER;
933 /**< in steps of 1/scaleFactorBER */
934 u32 averIter;/**< in steps of 0.01 */
935 u16 indicator;
936 /**< indicative signal quality low=0..100=high */
937 } DRXSigQuality_t, *pDRXSigQuality_t;
938
939 typedef enum {
940 DRX_SQI_SPEED_FAST = 0,
941 DRX_SQI_SPEED_MEDIUM,
942 DRX_SQI_SPEED_SLOW,
943 DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
944 } DRXCfgSqiSpeed_t, *pDRXCfgSqiSpeed_t;
945
946 /*========================================*/
947
948 /**
949 * \struct DRXComplex_t
950 * A complex number.
951 *
952 * Used by DRX_CTRL_CONSTEL.
953 */
954 typedef struct {
955 s16 im;
956 /**< Imaginary part. */
957 s16 re;
958 /**< Real part. */
959 } DRXComplex_t, *pDRXComplex_t;
960
961 /*========================================*/
962
963 /**
964 * \struct DRXFrequencyPlan_t
965 * Array element of a frequency plan.
966 *
967 * Used by DRX_CTRL_SCAN_INIT.
968 */
969 typedef struct {
970 DRXFrequency_t first;
971 /**< First centre frequency in this band */
972 DRXFrequency_t last;
973 /**< Last centre frequency in this band */
974 DRXFrequency_t step;
975 /**< Stepping frequency in this band */
976 DRXBandwidth_t bandwidth;
977 /**< Bandwidth within this frequency band */
978 u16 chNumber;
979 /**< First channel number in this band, or first
980 index in chNames */
981 char **chNames;
982 /**< Optional list of channel names in this
983 band */
984 } DRXFrequencyPlan_t, *pDRXFrequencyPlan_t;
985
986 /*========================================*/
987
988 /**
989 * \struct DRXFrequencyPlanInfo_t
990 * Array element of a list of frequency plans.
991 *
992 * Used by frequency_plan.h
993 */
994 typedef struct {
995 pDRXFrequencyPlan_t freqPlan;
996 int freqPlanSize;
997 char *freqPlanName;
998 } DRXFrequencyPlanInfo_t, *pDRXFrequencyPlanInfo_t;
999
1000 /*========================================*/
1001
1002 /**
1003 * /struct DRXScanDataQam_t
1004 * QAM specific scanning variables
1005 */
1006 typedef struct {
1007 u32 *symbolrate; /**< list of symbolrates to scan */
1008 u16 symbolrateSize; /**< size of symbolrate array */
1009 pDRXConstellation_t constellation;
1010 /**< list of constellations */
1011 u16 constellationSize; /**< size of constellation array */
1012 u16 ifAgcThreshold; /**< thresholf for IF-AGC based
1013 scanning filter */
1014 } DRXScanDataQam_t, *pDRXScanDataQam_t;
1015
1016 /*========================================*/
1017
1018 /**
1019 * /struct DRXScanDataAtv_t
1020 * ATV specific scanning variables
1021 */
1022 typedef struct {
1023 s16 svrThreshold;
1024 /**< threshold of Sound/Video ratio in 0.1dB steps */
1025 } DRXScanDataAtv_t, *pDRXScanDataAtv_t;
1026
1027 /*========================================*/
1028
1029 /**
1030 * \struct DRXScanParam_t
1031 * Parameters for channel scan.
1032 *
1033 * Used by DRX_CTRL_SCAN_INIT.
1034 */
1035 typedef struct {
1036 pDRXFrequencyPlan_t frequencyPlan;
1037 /**< Frequency plan (array)*/
1038 u16 frequencyPlanSize; /**< Number of bands */
1039 u32 numTries; /**< Max channels tried */
1040 DRXFrequency_t skip; /**< Minimum frequency step to take
1041 after a channel is found */
1042 void *extParams; /**< Standard specific params */
1043 } DRXScanParam_t, *pDRXScanParam_t;
1044
1045 /*========================================*/
1046
1047 /**
1048 * \brief Scan commands.
1049 * Used by scanning algorithms.
1050 */
1051 typedef enum {
1052 DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */
1053 DRX_SCAN_COMMAND_NEXT, /**< Next scan */
1054 DRX_SCAN_COMMAND_STOP /**< Stop scanning */
1055 } DRXScanCommand_t, *pDRXScanCommand_t;
1056
1057 /*========================================*/
1058
1059 /**
1060 * \brief Inner scan function prototype.
1061 */
1062 typedef DRXStatus_t(*DRXScanFunc_t) (void *scanContext,
1063 DRXScanCommand_t scanCommand,
1064 pDRXChannel_t scanChannel,
1065 pBool_t getNextChannel);
1066
1067 /*========================================*/
1068
1069 /**
1070 * \struct DRXTPSInfo_t
1071 * TPS information, DVB-T specific.
1072 *
1073 * Used by DRX_CTRL_TPS_INFO.
1074 */
1075 typedef struct {
1076 DRXFftmode_t fftmode; /**< Fft mode */
1077 DRXGuard_t guard; /**< Guard interval */
1078 DRXConstellation_t constellation;
1079 /**< Constellation */
1080 DRXHierarchy_t hierarchy;
1081 /**< Hierarchy */
1082 DRXCoderate_t highCoderate;
1083 /**< High code rate */
1084 DRXCoderate_t lowCoderate;
1085 /**< Low cod rate */
1086 DRXTPSFrame_t frame; /**< Tps frame */
1087 u8 length; /**< Length */
1088 u16 cellId; /**< Cell id */
1089 } DRXTPSInfo_t, *pDRXTPSInfo_t;
1090
1091 /*========================================*/
1092
1093 /**
1094 * \brief Power mode of device.
1095 *
1096 * Used by DRX_CTRL_SET_POWER_MODE.
1097 */
1098 typedef enum {
1099 DRX_POWER_UP = 0,
1100 /**< Generic , Power Up Mode */
1101 DRX_POWER_MODE_1,
1102 /**< Device specific , Power Up Mode */
1103 DRX_POWER_MODE_2,
1104 /**< Device specific , Power Up Mode */
1105 DRX_POWER_MODE_3,
1106 /**< Device specific , Power Up Mode */
1107 DRX_POWER_MODE_4,
1108 /**< Device specific , Power Up Mode */
1109 DRX_POWER_MODE_5,
1110 /**< Device specific , Power Up Mode */
1111 DRX_POWER_MODE_6,
1112 /**< Device specific , Power Up Mode */
1113 DRX_POWER_MODE_7,
1114 /**< Device specific , Power Up Mode */
1115 DRX_POWER_MODE_8,
1116 /**< Device specific , Power Up Mode */
1117
1118 DRX_POWER_MODE_9,
1119 /**< Device specific , Power Down Mode */
1120 DRX_POWER_MODE_10,
1121 /**< Device specific , Power Down Mode */
1122 DRX_POWER_MODE_11,
1123 /**< Device specific , Power Down Mode */
1124 DRX_POWER_MODE_12,
1125 /**< Device specific , Power Down Mode */
1126 DRX_POWER_MODE_13,
1127 /**< Device specific , Power Down Mode */
1128 DRX_POWER_MODE_14,
1129 /**< Device specific , Power Down Mode */
1130 DRX_POWER_MODE_15,
1131 /**< Device specific , Power Down Mode */
1132 DRX_POWER_MODE_16,
1133 /**< Device specific , Power Down Mode */
1134 DRX_POWER_DOWN = 255
1135 /**< Generic , Power Down Mode */
1136 } DRXPowerMode_t, *pDRXPowerMode_t;
1137
1138 /*========================================*/
1139
1140 /**
1141 * \enum DRXModule_t
1142 * \brief Software module identification.
1143 *
1144 * Used by DRX_CTRL_VERSION.
1145 */
1146 typedef enum {
1147 DRX_MODULE_DEVICE,
1148 DRX_MODULE_MICROCODE,
1149 DRX_MODULE_DRIVERCORE,
1150 DRX_MODULE_DEVICEDRIVER,
1151 DRX_MODULE_DAP,
1152 DRX_MODULE_BSP_I2C,
1153 DRX_MODULE_BSP_TUNER,
1154 DRX_MODULE_BSP_HOST,
1155 DRX_MODULE_UNKNOWN
1156 } DRXModule_t, *pDRXModule_t;
1157
1158 /**
1159 * \enum DRXVersion_t
1160 * \brief Version information of one software module.
1161 *
1162 * Used by DRX_CTRL_VERSION.
1163 */
1164 typedef struct {
1165 DRXModule_t moduleType;
1166 /**< Type identifier of the module */
1167 char *moduleName;
1168 /**< Name or description of module */
1169 u16 vMajor; /**< Major version number */
1170 u16 vMinor; /**< Minor version number */
1171 u16 vPatch; /**< Patch version number */
1172 char *vString; /**< Version as text string */
1173 } DRXVersion_t, *pDRXVersion_t;
1174
1175 /**
1176 * \enum DRXVersionList_t
1177 * \brief List element of NULL terminated, linked list for version information.
1178 *
1179 * Used by DRX_CTRL_VERSION.
1180 */
1181 typedef struct DRXVersionList_s {
1182 pDRXVersion_t version;/**< Version information */
1183 struct DRXVersionList_s *next;
1184 /**< Next list element */
1185 } DRXVersionList_t, *pDRXVersionList_t;
1186
1187 /*========================================*/
1188
1189 /**
1190 * \brief Parameters needed to confiugure a UIO.
1191 *
1192 * Used by DRX_CTRL_UIO_CFG.
1193 */
1194 typedef struct {
1195 DRXUIO_t uio;
1196 /**< UIO identifier */
1197 DRXUIOMode_t mode;
1198 /**< UIO operational mode */
1199 } DRXUIOCfg_t, *pDRXUIOCfg_t;
1200
1201 /*========================================*/
1202
1203 /**
1204 * \brief Parameters needed to read from or write to a UIO.
1205 *
1206 * Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE.
1207 */
1208 typedef struct {
1209 DRXUIO_t uio;
1210 /**< UIO identifier */
1211 Bool_t value;
1212 /**< UIO value (TRUE=1, FALSE=0) */
1213 } DRXUIOData_t, *pDRXUIOData_t;
1214
1215 /*========================================*/
1216
1217 /**
1218 * \brief Parameters needed to configure OOB.
1219 *
1220 * Used by DRX_CTRL_SET_OOB.
1221 */
1222 typedef struct {
1223 DRXFrequency_t frequency; /**< Frequency in kHz */
1224 DRXOOBDownstreamStandard_t standard;
1225 /**< OOB standard */
1226 Bool_t spectrumInverted; /**< If TRUE, then spectrum
1227 is inverted */
1228 } DRXOOB_t, *pDRXOOB_t;
1229
1230 /*========================================*/
1231
1232 /**
1233 * \brief Metrics from OOB.
1234 *
1235 * Used by DRX_CTRL_GET_OOB.
1236 */
1237 typedef struct {
1238 DRXFrequency_t frequency; /**< Frequency in Khz */
1239 DRXLockStatus_t lock; /**< Lock status */
1240 u32 mer; /**< MER */
1241 s32 symbolRateOffset; /**< Symbolrate offset in ppm */
1242 } DRXOOBStatus_t, *pDRXOOBStatus_t;
1243
1244 /*========================================*/
1245
1246 /**
1247 * \brief Device dependent configuration data.
1248 *
1249 * Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG.
1250 * A sort of nested DRX_Ctrl() functionality for device specific controls.
1251 */
1252 typedef struct {
1253 DRXCfgType_t cfgType;
1254 /**< Function identifier */
1255 void *cfgData;
1256 /**< Function data */
1257 } DRXCfg_t, *pDRXCfg_t;
1258
1259 /*========================================*/
1260
1261 /**
1262 * /struct DRXMpegStartWidth_t
1263 * MStart width [nr MCLK cycles] for serial MPEG output.
1264 */
1265
1266 typedef enum {
1267 DRX_MPEG_STR_WIDTH_1,
1268 DRX_MPEG_STR_WIDTH_8
1269 } DRXMPEGStrWidth_t, *pDRXMPEGStrWidth_t;
1270
1271 /* CTRL CFG MPEG ouput */
1272 /**
1273 * \struct DRXCfgMPEGOutput_t
1274 * \brief Configuartion parameters for MPEG output control.
1275 *
1276 * Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and
1277 * DRX_CTRL_GET_CFG.
1278 */
1279
1280 typedef struct {
1281 Bool_t enableMPEGOutput;/**< If TRUE, enable MPEG output */
1282 Bool_t insertRSByte; /**< If TRUE, insert RS byte */
1283 Bool_t enableParallel; /**< If TRUE, parallel out otherwise
1284 serial */
1285 Bool_t invertDATA; /**< If TRUE, invert DATA signals */
1286 Bool_t invertERR; /**< If TRUE, invert ERR signal */
1287 Bool_t invertSTR; /**< If TRUE, invert STR signals */
1288 Bool_t invertVAL; /**< If TRUE, invert VAL signals */
1289 Bool_t invertCLK; /**< If TRUE, invert CLK signals */
1290 Bool_t staticCLK; /**< If TRUE, static MPEG clockrate
1291 will be used, otherwise clockrate
1292 will adapt to the bitrate of the
1293 TS */
1294 u32 bitrate; /**< Maximum bitrate in b/s in case
1295 static clockrate is selected */
1296 DRXMPEGStrWidth_t widthSTR;
1297 /**< MPEG start width */
1298 } DRXCfgMPEGOutput_t, *pDRXCfgMPEGOutput_t;
1299
1300 /* CTRL CFG SMA */
1301 /**
1302 * /struct DRXCfgSMAIO_t
1303 * smart antenna i/o.
1304 */
1305 typedef enum DRXCfgSMAIO_t {
1306 DRX_SMA_OUTPUT = 0,
1307 DRX_SMA_INPUT
1308 } DRXCfgSMAIO_t, *pDRXCfgSMAIO_t;
1309
1310 /**
1311 * /struct DRXCfgSMA_t
1312 * Set smart antenna.
1313 */
1314 typedef struct {
1315 DRXCfgSMAIO_t io;
1316 u16 ctrlData;
1317 Bool_t smartAntInverted;
1318 } DRXCfgSMA_t, *pDRXCfgSMA_t;
1319
1320 /*========================================*/
1321
1322 /**
1323 * \struct DRXI2CData_t
1324 * \brief Data for I2C via 2nd or 3rd or etc I2C port.
1325 *
1326 * Used by DRX_CTRL_I2C_READWRITE.
1327 * If portNr is equal to primairy portNr BSPI2C will be used.
1328 *
1329 */
1330 typedef struct {
1331 u16 portNr; /**< I2C port number */
1332 struct i2c_device_addr *wDevAddr;
1333 /**< Write device address */
1334 u16 wCount; /**< Size of write data in bytes */
1335 u8 *wData; /**< Pointer to write data */
1336 struct i2c_device_addr *rDevAddr;
1337 /**< Read device address */
1338 u16 rCount; /**< Size of data to read in bytes */
1339 u8 *rData; /**< Pointer to read buffer */
1340 } DRXI2CData_t, *pDRXI2CData_t;
1341
1342 /*========================================*/
1343
1344 /**
1345 * \enum DRXAudStandard_t
1346 * \brief Audio standard identifier.
1347 *
1348 * Used by DRX_CTRL_SET_AUD.
1349 */
1350 typedef enum {
1351 DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */
1352 DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */
1353 DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */
1354 DRX_AUD_STANDARD_FM_STEREO,/**< set to FM-Stereo Radio */
1355 DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */
1356 DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */
1357 DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */
1358 DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */
1359 DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */
1360 DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */
1361 DRX_AUD_STANDARD_BG_NICAM_FM,
1362 /**< set BG_NICAM_FM standard */
1363 DRX_AUD_STANDARD_L_NICAM_AM,
1364 /**< set L_NICAM_AM standard */
1365 DRX_AUD_STANDARD_I_NICAM_FM,
1366 /**< set I_NICAM_FM standard */
1367 DRX_AUD_STANDARD_D_K_NICAM_FM,
1368 /**< set D_K_NICAM_FM standard */
1369 DRX_AUD_STANDARD_NOT_READY,/**< used to detect audio standard */
1370 DRX_AUD_STANDARD_AUTO = DRX_AUTO,
1371 /**< Automatic Standard Detection */
1372 DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN
1373 /**< used as auto and for readback */
1374 } DRXAudStandard_t, *pDRXAudStandard_t;
1375
1376 /* CTRL_AUD_GET_STATUS - DRXAudStatus_t */
1377 /**
1378 * \enum DRXAudNICAMStatus_t
1379 * \brief Status of NICAM carrier.
1380 */
1381 typedef enum {
1382 DRX_AUD_NICAM_DETECTED = 0,
1383 /**< NICAM carrier detected */
1384 DRX_AUD_NICAM_NOT_DETECTED,
1385 /**< NICAM carrier not detected */
1386 DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */
1387 } DRXAudNICAMStatus_t, *pDRXAudNICAMStatus_t;
1388
1389 /**
1390 * \struct DRXAudStatus_t
1391 * \brief Audio status characteristics.
1392 */
1393 typedef struct {
1394 Bool_t stereo; /**< stereo detection */
1395 Bool_t carrierA; /**< carrier A detected */
1396 Bool_t carrierB; /**< carrier B detected */
1397 Bool_t sap; /**< sap / bilingual detection */
1398 Bool_t rds; /**< RDS data array present */
1399 DRXAudNICAMStatus_t nicamStatus;
1400 /**< status of NICAM carrier */
1401 s8 fmIdent; /**< FM Identification value */
1402 } DRXAudStatus_t, *pDRXAudStatus_t;
1403
1404 /* CTRL_AUD_READ_RDS - DRXRDSdata_t */
1405
1406 /**
1407 * \struct DRXRDSdata_t
1408 * \brief Raw RDS data array.
1409 */
1410 typedef struct {
1411 Bool_t valid; /**< RDS data validation */
1412 u16 data[18]; /**< data from one RDS data array */
1413 } DRXCfgAudRDS_t, *pDRXCfgAudRDS_t;
1414
1415 /* DRX_CFG_AUD_VOLUME - DRXCfgAudVolume_t - set/get */
1416 /**
1417 * \enum DRXAudAVCDecayTime_t
1418 * \brief Automatic volume control configuration.
1419 */
1420 typedef enum {
1421 DRX_AUD_AVC_OFF, /**< Automatic volume control off */
1422 DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */
1423 DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */
1424 DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */
1425 DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */
1426 } DRXAudAVCMode_t, *pDRXAudAVCMode_t;
1427
1428 /**
1429 * /enum DRXAudMaxAVCGain_t
1430 * /brief Automatic volume control max gain in audio baseband.
1431 */
1432 typedef enum {
1433 DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */
1434 DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */
1435 DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */
1436 } DRXAudAVCMaxGain_t, *pDRXAudAVCMaxGain_t;
1437
1438 /**
1439 * /enum DRXAudMaxAVCAtten_t
1440 * /brief Automatic volume control max attenuation in audio baseband.
1441 */
1442 typedef enum {
1443 DRX_AUD_AVC_MAX_ATTEN_12DB,
1444 /**< maximum AVC attenuation 12 dB */
1445 DRX_AUD_AVC_MAX_ATTEN_18DB,
1446 /**< maximum AVC attenuation 18 dB */
1447 DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */
1448 } DRXAudAVCMaxAtten_t, *pDRXAudAVCMaxAtten_t;
1449 /**
1450 * \struct DRXCfgAudVolume_t
1451 * \brief Audio volume configuration.
1452 */
1453 typedef struct {
1454 Bool_t mute; /**< mute overrides volume setting */
1455 s16 volume; /**< volume, range -114 to 12 dB */
1456 DRXAudAVCMode_t avcMode; /**< AVC auto volume control mode */
1457 u16 avcRefLevel; /**< AVC reference level */
1458 DRXAudAVCMaxGain_t avcMaxGain;
1459 /**< AVC max gain selection */
1460 DRXAudAVCMaxAtten_t avcMaxAtten;
1461 /**< AVC max attenuation selection */
1462 s16 strengthLeft; /**< quasi-peak, left speaker */
1463 s16 strengthRight; /**< quasi-peak, right speaker */
1464 } DRXCfgAudVolume_t, *pDRXCfgAudVolume_t;
1465
1466 /* DRX_CFG_I2S_OUTPUT - DRXCfgI2SOutput_t - set/get */
1467 /**
1468 * \enum DRXI2SMode_t
1469 * \brief I2S output mode.
1470 */
1471 typedef enum {
1472 DRX_I2S_MODE_MASTER, /**< I2S is in master mode */
1473 DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */
1474 } DRXI2SMode_t, *pDRXI2SMode_t;
1475
1476 /**
1477 * \enum DRXI2SWordLength_t
1478 * \brief Width of I2S data.
1479 */
1480 typedef enum {
1481 DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */
1482 DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */
1483 } DRXI2SWordLength_t, *pDRXI2SWordLength_t;
1484
1485 /**
1486 * \enum DRXI2SFormat_t
1487 * \brief Data wordstrobe alignment for I2S.
1488 */
1489 typedef enum {
1490 DRX_I2S_FORMAT_WS_WITH_DATA,
1491 /**< I2S data and wordstrobe are aligned */
1492 DRX_I2S_FORMAT_WS_ADVANCED
1493 /**< I2S data one cycle after wordstrobe */
1494 } DRXI2SFormat_t, *pDRXI2SFormat_t;
1495
1496 /**
1497 * \enum DRXI2SPolarity_t
1498 * \brief Polarity of I2S data.
1499 */
1500 typedef enum {
1501 DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */
1502 DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */
1503 } DRXI2SPolarity_t, *pDRXI2SPolarity_t;
1504
1505 /**
1506 * \struct DRXCfgI2SOutput_t
1507 * \brief I2S output configuration.
1508 */
1509 typedef struct {
1510 Bool_t outputEnable; /**< I2S output enable */
1511 u32 frequency; /**< range from 8000-48000 Hz */
1512 DRXI2SMode_t mode; /**< I2S mode, master or slave */
1513 DRXI2SWordLength_t wordLength;
1514 /**< I2S wordlength, 16 or 32 bits */
1515 DRXI2SPolarity_t polarity;/**< I2S wordstrobe polarity */
1516 DRXI2SFormat_t format; /**< I2S wordstrobe delay to data */
1517 } DRXCfgI2SOutput_t, *pDRXCfgI2SOutput_t;
1518
1519 /* ------------------------------expert interface-----------------------------*/
1520 /**
1521 * /enum DRXAudFMDeemphasis_t
1522 * setting for FM-Deemphasis in audio demodulator.
1523 *
1524 */
1525 typedef enum {
1526 DRX_AUD_FM_DEEMPH_50US,
1527 DRX_AUD_FM_DEEMPH_75US,
1528 DRX_AUD_FM_DEEMPH_OFF
1529 } DRXAudFMDeemphasis_t, *pDRXAudFMDeemphasis_t;
1530
1531 /**
1532 * /enum DRXAudDeviation_t
1533 * setting for deviation mode in audio demodulator.
1534 *
1535 */
1536 typedef enum {
1537 DRX_AUD_DEVIATION_NORMAL,
1538 DRX_AUD_DEVIATION_HIGH
1539 } DRXCfgAudDeviation_t, *pDRXCfgAudDeviation_t;
1540
1541 /**
1542 * /enum DRXNoCarrierOption_t
1543 * setting for carrier, mute/noise.
1544 *
1545 */
1546 typedef enum {
1547 DRX_NO_CARRIER_MUTE,
1548 DRX_NO_CARRIER_NOISE
1549 } DRXNoCarrierOption_t, *pDRXNoCarrierOption_t;
1550
1551 /**
1552 * \enum DRXAudAutoSound_t
1553 * \brief Automatic Sound
1554 */
1555 typedef enum {
1556 DRX_AUD_AUTO_SOUND_OFF = 0,
1557 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,
1558 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF
1559 } DRXCfgAudAutoSound_t, *pDRXCfgAudAutoSound_t;
1560
1561 /**
1562 * \enum DRXAudASSThres_t
1563 * \brief Automatic Sound Select Thresholds
1564 */
1565 typedef struct {
1566 u16 a2; /* A2 Threshold for ASS configuration */
1567 u16 btsc; /* BTSC Threshold for ASS configuration */
1568 u16 nicam; /* Nicam Threshold for ASS configuration */
1569 } DRXCfgAudASSThres_t, *pDRXCfgAudASSThres_t;
1570
1571 /**
1572 * \struct DRXAudCarrier_t
1573 * \brief Carrier detection related parameters
1574 */
1575 typedef struct {
1576 u16 thres; /* carrier detetcion threshold for primary carrier (A) */
1577 DRXNoCarrierOption_t opt; /* Mute or noise at no carrier detection (A) */
1578 DRXFrequency_t shift; /* DC level of incoming signal (A) */
1579 DRXFrequency_t dco; /* frequency adjustment (A) */
1580 } DRXAudCarrier_t, *pDRXCfgAudCarrier_t;
1581
1582 /**
1583 * \struct DRXCfgAudCarriers_t
1584 * \brief combining carrier A & B to one struct
1585 */
1586 typedef struct {
1587 DRXAudCarrier_t a;
1588 DRXAudCarrier_t b;
1589 } DRXCfgAudCarriers_t, *pDRXCfgAudCarriers_t;
1590
1591 /**
1592 * /enum DRXAudI2SSrc_t
1593 * Selection of audio source
1594 */
1595 typedef enum {
1596 DRX_AUD_SRC_MONO,
1597 DRX_AUD_SRC_STEREO_OR_AB,
1598 DRX_AUD_SRC_STEREO_OR_A,
1599 DRX_AUD_SRC_STEREO_OR_B
1600 } DRXAudI2SSrc_t, *pDRXAudI2SSrc_t;
1601
1602 /**
1603 * \enum DRXAudI2SMatrix_t
1604 * \brief Used for selecting I2S output.
1605 */
1606 typedef enum {
1607 DRX_AUD_I2S_MATRIX_A_MONO,
1608 /**< A sound only, stereo or mono */
1609 DRX_AUD_I2S_MATRIX_B_MONO,
1610 /**< B sound only, stereo or mono */
1611 DRX_AUD_I2S_MATRIX_STEREO,
1612 /**< A+B sound, transparant */
1613 DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */
1614 } DRXAudI2SMatrix_t, *pDRXAudI2SMatrix_t;
1615
1616 /**
1617 * /enum DRXAudFMMatrix_t
1618 * setting for FM-Matrix in audio demodulator.
1619 *
1620 */
1621 typedef enum {
1622 DRX_AUD_FM_MATRIX_NO_MATRIX,
1623 DRX_AUD_FM_MATRIX_GERMAN,
1624 DRX_AUD_FM_MATRIX_KOREAN,
1625 DRX_AUD_FM_MATRIX_SOUND_A,
1626 DRX_AUD_FM_MATRIX_SOUND_B
1627 } DRXAudFMMatrix_t, *pDRXAudFMMatrix_t;
1628
1629 /**
1630 * \struct DRXAudMatrices_t
1631 * \brief Mixer settings
1632 */
1633 typedef struct {
1634 DRXAudI2SSrc_t sourceI2S;
1635 DRXAudI2SMatrix_t matrixI2S;
1636 DRXAudFMMatrix_t matrixFm;
1637 } DRXCfgAudMixer_t, *pDRXCfgAudMixer_t;
1638
1639 /**
1640 * \enum DRXI2SVidSync_t
1641 * \brief Audio/video synchronization, interacts with I2S mode.
1642 * AUTO_1 and AUTO_2 are for automatic video standard detection with preference
1643 * for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz)
1644 */
1645 typedef enum {
1646 DRX_AUD_AVSYNC_OFF,/**< audio/video synchronization is off */
1647 DRX_AUD_AVSYNC_NTSC,
1648 /**< it is an NTSC system */
1649 DRX_AUD_AVSYNC_MONOCHROME,
1650 /**< it is a MONOCHROME system */
1651 DRX_AUD_AVSYNC_PAL_SECAM
1652 /**< it is a PAL/SECAM system */
1653 } DRXCfgAudAVSync_t, *pDRXCfgAudAVSync_t;
1654
1655 /**
1656 * \struct DRXCfgAudPrescale_t
1657 * \brief Prescalers
1658 */
1659 typedef struct {
1660 u16 fmDeviation;
1661 s16 nicamGain;
1662 } DRXCfgAudPrescale_t, *pDRXCfgAudPrescale_t;
1663
1664 /**
1665 * \struct DRXAudBeep_t
1666 * \brief Beep
1667 */
1668 typedef struct {
1669 s16 volume; /* dB */
1670 u16 frequency; /* Hz */
1671 Bool_t mute;
1672 } DRXAudBeep_t, *pDRXAudBeep_t;
1673
1674 /**
1675 * \enum DRXAudBtscDetect_t
1676 * \brief BTSC detetcion mode
1677 */
1678 typedef enum {
1679 DRX_BTSC_STEREO,
1680 DRX_BTSC_MONO_AND_SAP
1681 } DRXAudBtscDetect_t, *pDRXAudBtscDetect_t;
1682
1683 /**
1684 * \struct DRXAudData_t
1685 * \brief Audio data structure
1686 */
1687 typedef struct {
1688 /* audio storage */
1689 Bool_t audioIsActive;
1690 DRXAudStandard_t audioStandard;
1691 DRXCfgI2SOutput_t i2sdata;
1692 DRXCfgAudVolume_t volume;
1693 DRXCfgAudAutoSound_t autoSound;
1694 DRXCfgAudASSThres_t assThresholds;
1695 DRXCfgAudCarriers_t carriers;
1696 DRXCfgAudMixer_t mixer;
1697 DRXCfgAudDeviation_t deviation;
1698 DRXCfgAudAVSync_t avSync;
1699 DRXCfgAudPrescale_t prescale;
1700 DRXAudFMDeemphasis_t deemph;
1701 DRXAudBtscDetect_t btscDetect;
1702 /* rds */
1703 u16 rdsDataCounter;
1704 Bool_t rdsDataPresent;
1705 } DRXAudData_t, *pDRXAudData_t;
1706
1707 /**
1708 * \enum DRXQamLockRange_t
1709 * \brief QAM lock range mode
1710 */
1711 typedef enum {
1712 DRX_QAM_LOCKRANGE_NORMAL,
1713 DRX_QAM_LOCKRANGE_EXTENDED
1714 } DRXQamLockRange_t, *pDRXQamLockRange_t;
1715
1716 /*============================================================================*/
1717 /*============================================================================*/
1718 /*== Data access structures ==================================================*/
1719 /*============================================================================*/
1720 /*============================================================================*/
1721
1722 /* Address on device */
1723 typedef u32 DRXaddr_t, *pDRXaddr_t;
1724
1725 /* Protocol specific flags */
1726 typedef u32 DRXflags_t, *pDRXflags_t;
1727
1728 /* Write block of data to device */
1729 typedef DRXStatus_t(*DRXWriteBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
1730 DRXaddr_t addr, /* address of register/memory */
1731 u16 datasize, /* size of data in bytes */
1732 u8 *data, /* data to send */
1733 DRXflags_t flags);
1734
1735 /* Read block of data from device */
1736 typedef DRXStatus_t(*DRXReadBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
1737 DRXaddr_t addr, /* address of register/memory */
1738 u16 datasize, /* size of data in bytes */
1739 u8 *data, /* receive buffer */
1740 DRXflags_t flags);
1741
1742 /* Write 8-bits value to device */
1743 typedef DRXStatus_t(*DRXWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
1744 DRXaddr_t addr, /* address of register/memory */
1745 u8 data, /* data to send */
1746 DRXflags_t flags);
1747
1748 /* Read 8-bits value to device */
1749 typedef DRXStatus_t(*DRXReadReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
1750 DRXaddr_t addr, /* address of register/memory */
1751 u8 *data, /* receive buffer */
1752 DRXflags_t flags);
1753
1754 /* Read modify write 8-bits value to device */
1755 typedef DRXStatus_t(*DRXReadModifyWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
1756 DRXaddr_t waddr, /* write address of register */
1757 DRXaddr_t raddr, /* read address of register */
1758 u8 wdata, /* data to write */
1759 u8 *rdata); /* data to read */
1760
1761 /* Write 16-bits value to device */
1762 typedef DRXStatus_t(*DRXWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
1763 DRXaddr_t addr, /* address of register/memory */
1764 u16 data, /* data to send */
1765 DRXflags_t flags);
1766
1767 /* Read 16-bits value to device */
1768 typedef DRXStatus_t(*DRXReadReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
1769 DRXaddr_t addr, /* address of register/memory */
1770 u16 *data, /* receive buffer */
1771 DRXflags_t flags);
1772
1773 /* Read modify write 16-bits value to device */
1774 typedef DRXStatus_t(*DRXReadModifyWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
1775 DRXaddr_t waddr, /* write address of register */
1776 DRXaddr_t raddr, /* read address of register */
1777 u16 wdata, /* data to write */
1778 u16 *rdata); /* data to read */
1779
1780 /* Write 32-bits value to device */
1781 typedef DRXStatus_t(*DRXWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
1782 DRXaddr_t addr, /* address of register/memory */
1783 u32 data, /* data to send */
1784 DRXflags_t flags);
1785
1786 /* Read 32-bits value to device */
1787 typedef DRXStatus_t(*DRXReadReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
1788 DRXaddr_t addr, /* address of register/memory */
1789 u32 *data, /* receive buffer */
1790 DRXflags_t flags);
1791
1792 /* Read modify write 32-bits value to device */
1793 typedef DRXStatus_t(*DRXReadModifyWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
1794 DRXaddr_t waddr, /* write address of register */
1795 DRXaddr_t raddr, /* read address of register */
1796 u32 wdata, /* data to write */
1797 u32 *rdata); /* data to read */
1798
1799 /**
1800 * \struct DRXAccessFunc_t
1801 * \brief Interface to an access protocol.
1802 */
1803 typedef struct {
1804 pDRXVersion_t protocolVersion;
1805 DRXWriteBlockFunc_t writeBlockFunc;
1806 DRXReadBlockFunc_t readBlockFunc;
1807 DRXWriteReg8Func_t writeReg8Func;
1808 DRXReadReg8Func_t readReg8Func;
1809 DRXReadModifyWriteReg8Func_t readModifyWriteReg8Func;
1810 DRXWriteReg16Func_t writeReg16Func;
1811 DRXReadReg16Func_t readReg16Func;
1812 DRXReadModifyWriteReg16Func_t readModifyWriteReg16Func;
1813 DRXWriteReg32Func_t writeReg32Func;
1814 DRXReadReg32Func_t readReg32Func;
1815 DRXReadModifyWriteReg32Func_t readModifyWriteReg32Func;
1816 } DRXAccessFunc_t, *pDRXAccessFunc_t;
1817
1818 /* Register address and data for register dump function */
1819 typedef struct {
1820
1821 DRXaddr_t address;
1822 u32 data;
1823
1824 } DRXRegDump_t, *pDRXRegDump_t;
1825
1826 /*============================================================================*/
1827 /*============================================================================*/
1828 /*== Demod instance data structures ==========================================*/
1829 /*============================================================================*/
1830 /*============================================================================*/
1831
1832 /**
1833 * \struct DRXCommonAttr_t
1834 * \brief Set of common attributes, shared by all DRX devices.
1835 */
1836 typedef struct {
1837 /* Microcode (firmware) attributes */
1838 u8 *microcode; /**< Pointer to microcode image. */
1839 u16 microcodeSize;
1840 /**< Size of microcode image in bytes. */
1841 Bool_t verifyMicrocode;
1842 /**< Use microcode verify or not. */
1843 DRXMcVersionRec_t mcversion;
1844 /**< Version record of microcode from file */
1845
1846 /* Clocks and tuner attributes */
1847 DRXFrequency_t intermediateFreq;
1848 /**< IF,if tuner instance not used. (kHz)*/
1849 DRXFrequency_t sysClockFreq;
1850 /**< Systemclock frequency. (kHz) */
1851 DRXFrequency_t oscClockFreq;
1852 /**< Oscillator clock frequency. (kHz) */
1853 s16 oscClockDeviation;
1854 /**< Oscillator clock deviation. (ppm) */
1855 Bool_t mirrorFreqSpect;
1856 /**< Mirror IF frequency spectrum or not.*/
1857
1858 /* Initial MPEG output attributes */
1859 DRXCfgMPEGOutput_t mpegCfg;
1860 /**< MPEG configuration */
1861
1862 Bool_t isOpened; /**< if TRUE instance is already opened. */
1863
1864 /* Channel scan */
1865 pDRXScanParam_t scanParam;
1866 /**< scan parameters */
1867 u16 scanFreqPlanIndex;
1868 /**< next index in freq plan */
1869 DRXFrequency_t scanNextFrequency;
1870 /**< next freq to scan */
1871 Bool_t scanReady; /**< scan ready flag */
1872 u32 scanMaxChannels;/**< number of channels in freqplan */
1873 u32 scanChannelsScanned;
1874 /**< number of channels scanned */
1875 /* Channel scan - inner loop: demod related */
1876 DRXScanFunc_t scanFunction;
1877 /**< function to check channel */
1878 /* Channel scan - inner loop: SYSObj related */
1879 void *scanContext; /**< Context Pointer of SYSObj */
1880 /* Channel scan - parameters for default DTV scan function in core driver */
1881 u16 scanDemodLockTimeout;
1882 /**< millisecs to wait for lock */
1883 DRXLockStatus_t scanDesiredLock;
1884 /**< lock requirement for channel found */
1885 /* scanActive can be used by SetChannel to decide how to program the tuner,
1886 fast or slow (but stable). Usually fast during scan. */
1887 Bool_t scanActive; /**< TRUE when scan routines are active */
1888
1889 /* Power management */
1890 DRXPowerMode_t currentPowerMode;
1891 /**< current power management mode */
1892
1893 /* Tuner */
1894 u8 tunerPortNr; /**< nr of I2C port to wich tuner is */
1895 DRXFrequency_t tunerMinFreqRF;
1896 /**< minimum RF input frequency, in kHz */
1897 DRXFrequency_t tunerMaxFreqRF;
1898 /**< maximum RF input frequency, in kHz */
1899 Bool_t tunerRfAgcPol; /**< if TRUE invert RF AGC polarity */
1900 Bool_t tunerIfAgcPol; /**< if TRUE invert IF AGC polarity */
1901 Bool_t tunerSlowMode; /**< if TRUE invert IF AGC polarity */
1902
1903 DRXChannel_t currentChannel;
1904 /**< current channel parameters */
1905 DRXStandard_t currentStandard;
1906 /**< current standard selection */
1907 DRXStandard_t prevStandard;
1908 /**< previous standard selection */
1909 DRXStandard_t diCacheStandard;
1910 /**< standard in DI cache if available */
1911 Bool_t useBootloader; /**< use bootloader in open */
1912 u32 capabilities; /**< capabilities flags */
1913 u32 productId; /**< product ID inc. metal fix number */
1914
1915 } DRXCommonAttr_t, *pDRXCommonAttr_t;
1916
1917 /*
1918 * Generic functions for DRX devices.
1919 */
1920 typedef struct DRXDemodInstance_s *pDRXDemodInstance_t;
1921
1922 typedef DRXStatus_t(*DRXOpenFunc_t) (pDRXDemodInstance_t demod);
1923 typedef DRXStatus_t(*DRXCloseFunc_t) (pDRXDemodInstance_t demod);
1924 typedef DRXStatus_t(*DRXCtrlFunc_t) (pDRXDemodInstance_t demod,
1925 DRXCtrlIndex_t ctrl,
1926 void *ctrlData);
1927
1928 /**
1929 * \struct DRXDemodFunc_t
1930 * \brief A stucture containing all functions of a demodulator.
1931 */
1932 typedef struct {
1933 u32 typeId; /**< Device type identifier. */
1934 DRXOpenFunc_t openFunc; /**< Pointer to Open() function. */
1935 DRXCloseFunc_t closeFunc;/**< Pointer to Close() function. */
1936 DRXCtrlFunc_t ctrlFunc; /**< Pointer to Ctrl() function. */
1937 } DRXDemodFunc_t, *pDRXDemodFunc_t;
1938
1939 /**
1940 * \struct DRXDemodInstance_t
1941 * \brief Top structure of demodulator instance.
1942 */
1943 typedef struct DRXDemodInstance_s {
1944 /* type specific demodulator data */
1945 pDRXDemodFunc_t myDemodFunct;
1946 /**< demodulator functions */
1947 pDRXAccessFunc_t myAccessFunct;
1948 /**< data access protocol functions */
1949 pTUNERInstance_t myTuner;
1950 /**< tuner instance,if NULL then baseband */
1951 struct i2c_device_addr *myI2CDevAddr;
1952 /**< i2c address and device identifier */
1953 pDRXCommonAttr_t myCommonAttr;
1954 /**< common DRX attributes */
1955 void *myExtAttr; /**< device specific attributes */
1956 /* generic demodulator data */
1957 } DRXDemodInstance_t;
1958
1959 /*-------------------------------------------------------------------------
1960 MACROS
1961 Conversion from enum values to human readable form.
1962 -------------------------------------------------------------------------*/
1963
1964 /* standard */
1965
1966 #define DRX_STR_STANDARD(x) ( \
1967 ( x == DRX_STANDARD_DVBT ) ? "DVB-T" : \
1968 ( x == DRX_STANDARD_8VSB ) ? "8VSB" : \
1969 ( x == DRX_STANDARD_NTSC ) ? "NTSC" : \
1970 ( x == DRX_STANDARD_PAL_SECAM_BG ) ? "PAL/SECAM B/G" : \
1971 ( x == DRX_STANDARD_PAL_SECAM_DK ) ? "PAL/SECAM D/K" : \
1972 ( x == DRX_STANDARD_PAL_SECAM_I ) ? "PAL/SECAM I" : \
1973 ( x == DRX_STANDARD_PAL_SECAM_L ) ? "PAL/SECAM L" : \
1974 ( x == DRX_STANDARD_PAL_SECAM_LP ) ? "PAL/SECAM LP" : \
1975 ( x == DRX_STANDARD_ITU_A ) ? "ITU-A" : \
1976 ( x == DRX_STANDARD_ITU_B ) ? "ITU-B" : \
1977 ( x == DRX_STANDARD_ITU_C ) ? "ITU-C" : \
1978 ( x == DRX_STANDARD_ITU_D ) ? "ITU-D" : \
1979 ( x == DRX_STANDARD_FM ) ? "FM" : \
1980 ( x == DRX_STANDARD_DTMB ) ? "DTMB" : \
1981 ( x == DRX_STANDARD_AUTO ) ? "Auto" : \
1982 ( x == DRX_STANDARD_UNKNOWN ) ? "Unknown" : \
1983 "(Invalid)" )
1984
1985 /* channel */
1986
1987 #define DRX_STR_BANDWIDTH(x) ( \
1988 ( x == DRX_BANDWIDTH_8MHZ ) ? "8 MHz" : \
1989 ( x == DRX_BANDWIDTH_7MHZ ) ? "7 MHz" : \
1990 ( x == DRX_BANDWIDTH_6MHZ ) ? "6 MHz" : \
1991 ( x == DRX_BANDWIDTH_AUTO ) ? "Auto" : \
1992 ( x == DRX_BANDWIDTH_UNKNOWN ) ? "Unknown" : \
1993 "(Invalid)" )
1994 #define DRX_STR_FFTMODE(x) ( \
1995 ( x == DRX_FFTMODE_2K ) ? "2k" : \
1996 ( x == DRX_FFTMODE_4K ) ? "4k" : \
1997 ( x == DRX_FFTMODE_8K ) ? "8k" : \
1998 ( x == DRX_FFTMODE_AUTO ) ? "Auto" : \
1999 ( x == DRX_FFTMODE_UNKNOWN ) ? "Unknown" : \
2000 "(Invalid)" )
2001 #define DRX_STR_GUARD(x) ( \
2002 ( x == DRX_GUARD_1DIV32 ) ? "1/32nd" : \
2003 ( x == DRX_GUARD_1DIV16 ) ? "1/16th" : \
2004 ( x == DRX_GUARD_1DIV8 ) ? "1/8th" : \
2005 ( x == DRX_GUARD_1DIV4 ) ? "1/4th" : \
2006 ( x == DRX_GUARD_AUTO ) ? "Auto" : \
2007 ( x == DRX_GUARD_UNKNOWN ) ? "Unknown" : \
2008 "(Invalid)" )
2009 #define DRX_STR_CONSTELLATION(x) ( \
2010 ( x == DRX_CONSTELLATION_BPSK ) ? "BPSK" : \
2011 ( x == DRX_CONSTELLATION_QPSK ) ? "QPSK" : \
2012 ( x == DRX_CONSTELLATION_PSK8 ) ? "PSK8" : \
2013 ( x == DRX_CONSTELLATION_QAM16 ) ? "QAM16" : \
2014 ( x == DRX_CONSTELLATION_QAM32 ) ? "QAM32" : \
2015 ( x == DRX_CONSTELLATION_QAM64 ) ? "QAM64" : \
2016 ( x == DRX_CONSTELLATION_QAM128 ) ? "QAM128" : \
2017 ( x == DRX_CONSTELLATION_QAM256 ) ? "QAM256" : \
2018 ( x == DRX_CONSTELLATION_QAM512 ) ? "QAM512" : \
2019 ( x == DRX_CONSTELLATION_QAM1024 ) ? "QAM1024" : \
2020 ( x == DRX_CONSTELLATION_QPSK_NR ) ? "QPSK_NR" : \
2021 ( x == DRX_CONSTELLATION_AUTO ) ? "Auto" : \
2022 ( x == DRX_CONSTELLATION_UNKNOWN ) ? "Unknown" : \
2023 "(Invalid)" )
2024 #define DRX_STR_CODERATE(x) ( \
2025 ( x == DRX_CODERATE_1DIV2 ) ? "1/2nd" : \
2026 ( x == DRX_CODERATE_2DIV3 ) ? "2/3rd" : \
2027 ( x == DRX_CODERATE_3DIV4 ) ? "3/4th" : \
2028 ( x == DRX_CODERATE_5DIV6 ) ? "5/6th" : \
2029 ( x == DRX_CODERATE_7DIV8 ) ? "7/8th" : \
2030 ( x == DRX_CODERATE_AUTO ) ? "Auto" : \
2031 ( x == DRX_CODERATE_UNKNOWN ) ? "Unknown" : \
2032 "(Invalid)" )
2033 #define DRX_STR_HIERARCHY(x) ( \
2034 ( x == DRX_HIERARCHY_NONE ) ? "None" : \
2035 ( x == DRX_HIERARCHY_ALPHA1 ) ? "Alpha=1" : \
2036 ( x == DRX_HIERARCHY_ALPHA2 ) ? "Alpha=2" : \
2037 ( x == DRX_HIERARCHY_ALPHA4 ) ? "Alpha=4" : \
2038 ( x == DRX_HIERARCHY_AUTO ) ? "Auto" : \
2039 ( x == DRX_HIERARCHY_UNKNOWN ) ? "Unknown" : \
2040 "(Invalid)" )
2041 #define DRX_STR_PRIORITY(x) ( \
2042 ( x == DRX_PRIORITY_LOW ) ? "Low" : \
2043 ( x == DRX_PRIORITY_HIGH ) ? "High" : \
2044 ( x == DRX_PRIORITY_UNKNOWN ) ? "Unknown" : \
2045 "(Invalid)" )
2046 #define DRX_STR_MIRROR(x) ( \
2047 ( x == DRX_MIRROR_NO ) ? "Normal" : \
2048 ( x == DRX_MIRROR_YES ) ? "Mirrored" : \
2049 ( x == DRX_MIRROR_AUTO ) ? "Auto" : \
2050 ( x == DRX_MIRROR_UNKNOWN ) ? "Unknown" : \
2051 "(Invalid)" )
2052 #define DRX_STR_CLASSIFICATION(x) ( \
2053 ( x == DRX_CLASSIFICATION_GAUSS ) ? "Gaussion" : \
2054 ( x == DRX_CLASSIFICATION_HVY_GAUSS ) ? "Heavy Gaussion" : \
2055 ( x == DRX_CLASSIFICATION_COCHANNEL ) ? "Co-channel" : \
2056 ( x == DRX_CLASSIFICATION_STATIC ) ? "Static echo" : \
2057 ( x == DRX_CLASSIFICATION_MOVING ) ? "Moving echo" : \
2058 ( x == DRX_CLASSIFICATION_ZERODB ) ? "Zero dB echo" : \
2059 ( x == DRX_CLASSIFICATION_UNKNOWN ) ? "Unknown" : \
2060 ( x == DRX_CLASSIFICATION_AUTO ) ? "Auto" : \
2061 "(Invalid)" )
2062
2063 #define DRX_STR_INTERLEAVEMODE(x) ( \
2064 ( x == DRX_INTERLEAVEMODE_I128_J1 ) ? "I128_J1" : \
2065 ( x == DRX_INTERLEAVEMODE_I128_J1_V2 ) ? "I128_J1_V2" : \
2066 ( x == DRX_INTERLEAVEMODE_I128_J2 ) ? "I128_J2" : \
2067 ( x == DRX_INTERLEAVEMODE_I64_J2 ) ? "I64_J2" : \
2068 ( x == DRX_INTERLEAVEMODE_I128_J3 ) ? "I128_J3" : \
2069 ( x == DRX_INTERLEAVEMODE_I32_J4 ) ? "I32_J4" : \
2070 ( x == DRX_INTERLEAVEMODE_I128_J4 ) ? "I128_J4" : \
2071 ( x == DRX_INTERLEAVEMODE_I16_J8 ) ? "I16_J8" : \
2072 ( x == DRX_INTERLEAVEMODE_I128_J5 ) ? "I128_J5" : \
2073 ( x == DRX_INTERLEAVEMODE_I8_J16 ) ? "I8_J16" : \
2074 ( x == DRX_INTERLEAVEMODE_I128_J6 ) ? "I128_J6" : \
2075 ( x == DRX_INTERLEAVEMODE_RESERVED_11 ) ? "Reserved 11" : \
2076 ( x == DRX_INTERLEAVEMODE_I128_J7 ) ? "I128_J7" : \
2077 ( x == DRX_INTERLEAVEMODE_RESERVED_13 ) ? "Reserved 13" : \
2078 ( x == DRX_INTERLEAVEMODE_I128_J8 ) ? "I128_J8" : \
2079 ( x == DRX_INTERLEAVEMODE_RESERVED_15 ) ? "Reserved 15" : \
2080 ( x == DRX_INTERLEAVEMODE_I12_J17 ) ? "I12_J17" : \
2081 ( x == DRX_INTERLEAVEMODE_I5_J4 ) ? "I5_J4" : \
2082 ( x == DRX_INTERLEAVEMODE_B52_M240 ) ? "B52_M240" : \
2083 ( x == DRX_INTERLEAVEMODE_B52_M720 ) ? "B52_M720" : \
2084 ( x == DRX_INTERLEAVEMODE_B52_M48 ) ? "B52_M48" : \
2085 ( x == DRX_INTERLEAVEMODE_B52_M0 ) ? "B52_M0" : \
2086 ( x == DRX_INTERLEAVEMODE_UNKNOWN ) ? "Unknown" : \
2087 ( x == DRX_INTERLEAVEMODE_AUTO ) ? "Auto" : \
2088 "(Invalid)" )
2089
2090 #define DRX_STR_LDPC(x) ( \
2091 ( x == DRX_LDPC_0_4 ) ? "0.4" : \
2092 ( x == DRX_LDPC_0_6 ) ? "0.6" : \
2093 ( x == DRX_LDPC_0_8 ) ? "0.8" : \
2094 ( x == DRX_LDPC_AUTO ) ? "Auto" : \
2095 ( x == DRX_LDPC_UNKNOWN ) ? "Unknown" : \
2096 "(Invalid)" )
2097
2098 #define DRX_STR_CARRIER(x) ( \
2099 ( x == DRX_CARRIER_MULTI ) ? "Multi" : \
2100 ( x == DRX_CARRIER_SINGLE ) ? "Single" : \
2101 ( x == DRX_CARRIER_AUTO ) ? "Auto" : \
2102 ( x == DRX_CARRIER_UNKNOWN ) ? "Unknown" : \
2103 "(Invalid)" )
2104
2105 #define DRX_STR_FRAMEMODE(x) ( \
2106 ( x == DRX_FRAMEMODE_420 ) ? "420" : \
2107 ( x == DRX_FRAMEMODE_595 ) ? "595" : \
2108 ( x == DRX_FRAMEMODE_945 ) ? "945" : \
2109 ( x == DRX_FRAMEMODE_420_FIXED_PN ) ? "420 with fixed PN" : \
2110 ( x == DRX_FRAMEMODE_945_FIXED_PN ) ? "945 with fixed PN" : \
2111 ( x == DRX_FRAMEMODE_AUTO ) ? "Auto" : \
2112 ( x == DRX_FRAMEMODE_UNKNOWN ) ? "Unknown" : \
2113 "(Invalid)" )
2114
2115 #define DRX_STR_PILOT(x) ( \
2116 ( x == DRX_PILOT_ON ) ? "On" : \
2117 ( x == DRX_PILOT_OFF ) ? "Off" : \
2118 ( x == DRX_PILOT_AUTO ) ? "Auto" : \
2119 ( x == DRX_PILOT_UNKNOWN ) ? "Unknown" : \
2120 "(Invalid)" )
2121 /* TPS */
2122
2123 #define DRX_STR_TPS_FRAME(x) ( \
2124 ( x == DRX_TPS_FRAME1 ) ? "Frame1" : \
2125 ( x == DRX_TPS_FRAME2 ) ? "Frame2" : \
2126 ( x == DRX_TPS_FRAME3 ) ? "Frame3" : \
2127 ( x == DRX_TPS_FRAME4 ) ? "Frame4" : \
2128 ( x == DRX_TPS_FRAME_UNKNOWN ) ? "Unknown" : \
2129 "(Invalid)" )
2130
2131 /* lock status */
2132
2133 #define DRX_STR_LOCKSTATUS(x) ( \
2134 ( x == DRX_NEVER_LOCK ) ? "Never" : \
2135 ( x == DRX_NOT_LOCKED ) ? "No" : \
2136 ( x == DRX_LOCKED ) ? "Locked" : \
2137 ( x == DRX_LOCK_STATE_1 ) ? "Lock state 1" : \
2138 ( x == DRX_LOCK_STATE_2 ) ? "Lock state 2" : \
2139 ( x == DRX_LOCK_STATE_3 ) ? "Lock state 3" : \
2140 ( x == DRX_LOCK_STATE_4 ) ? "Lock state 4" : \
2141 ( x == DRX_LOCK_STATE_5 ) ? "Lock state 5" : \
2142 ( x == DRX_LOCK_STATE_6 ) ? "Lock state 6" : \
2143 ( x == DRX_LOCK_STATE_7 ) ? "Lock state 7" : \
2144 ( x == DRX_LOCK_STATE_8 ) ? "Lock state 8" : \
2145 ( x == DRX_LOCK_STATE_9 ) ? "Lock state 9" : \
2146 "(Invalid)" )
2147
2148 /* version information , modules */
2149 #define DRX_STR_MODULE(x) ( \
2150 ( x == DRX_MODULE_DEVICE ) ? "Device" : \
2151 ( x == DRX_MODULE_MICROCODE ) ? "Microcode" : \
2152 ( x == DRX_MODULE_DRIVERCORE ) ? "CoreDriver" : \
2153 ( x == DRX_MODULE_DEVICEDRIVER ) ? "DeviceDriver" : \
2154 ( x == DRX_MODULE_BSP_I2C ) ? "BSP I2C" : \
2155 ( x == DRX_MODULE_BSP_TUNER ) ? "BSP Tuner" : \
2156 ( x == DRX_MODULE_BSP_HOST ) ? "BSP Host" : \
2157 ( x == DRX_MODULE_DAP ) ? "Data Access Protocol" : \
2158 ( x == DRX_MODULE_UNKNOWN ) ? "Unknown" : \
2159 "(Invalid)" )
2160
2161 #define DRX_STR_POWER_MODE(x) ( \
2162 ( x == DRX_POWER_UP ) ? "DRX_POWER_UP " : \
2163 ( x == DRX_POWER_MODE_1 ) ? "DRX_POWER_MODE_1" : \
2164 ( x == DRX_POWER_MODE_2 ) ? "DRX_POWER_MODE_2" : \
2165 ( x == DRX_POWER_MODE_3 ) ? "DRX_POWER_MODE_3" : \
2166 ( x == DRX_POWER_MODE_4 ) ? "DRX_POWER_MODE_4" : \
2167 ( x == DRX_POWER_MODE_5 ) ? "DRX_POWER_MODE_5" : \
2168 ( x == DRX_POWER_MODE_6 ) ? "DRX_POWER_MODE_6" : \
2169 ( x == DRX_POWER_MODE_7 ) ? "DRX_POWER_MODE_7" : \
2170 ( x == DRX_POWER_MODE_8 ) ? "DRX_POWER_MODE_8" : \
2171 ( x == DRX_POWER_MODE_9 ) ? "DRX_POWER_MODE_9" : \
2172 ( x == DRX_POWER_MODE_10 ) ? "DRX_POWER_MODE_10" : \
2173 ( x == DRX_POWER_MODE_11 ) ? "DRX_POWER_MODE_11" : \
2174 ( x == DRX_POWER_MODE_12 ) ? "DRX_POWER_MODE_12" : \
2175 ( x == DRX_POWER_MODE_13 ) ? "DRX_POWER_MODE_13" : \
2176 ( x == DRX_POWER_MODE_14 ) ? "DRX_POWER_MODE_14" : \
2177 ( x == DRX_POWER_MODE_15 ) ? "DRX_POWER_MODE_15" : \
2178 ( x == DRX_POWER_MODE_16 ) ? "DRX_POWER_MODE_16" : \
2179 ( x == DRX_POWER_DOWN ) ? "DRX_POWER_DOWN " : \
2180 "(Invalid)" )
2181
2182 #define DRX_STR_OOB_STANDARD(x) ( \
2183 ( x == DRX_OOB_MODE_A ) ? "ANSI 55-1 " : \
2184 ( x == DRX_OOB_MODE_B_GRADE_A ) ? "ANSI 55-2 A" : \
2185 ( x == DRX_OOB_MODE_B_GRADE_B ) ? "ANSI 55-2 B" : \
2186 "(Invalid)" )
2187
2188 #define DRX_STR_AUD_STANDARD(x) ( \
2189 ( x == DRX_AUD_STANDARD_BTSC ) ? "BTSC" : \
2190 ( x == DRX_AUD_STANDARD_A2 ) ? "A2" : \
2191 ( x == DRX_AUD_STANDARD_EIAJ ) ? "EIAJ" : \
2192 ( x == DRX_AUD_STANDARD_FM_STEREO ) ? "FM Stereo" : \
2193 ( x == DRX_AUD_STANDARD_AUTO ) ? "Auto" : \
2194 ( x == DRX_AUD_STANDARD_M_MONO ) ? "M-Standard Mono" : \
2195 ( x == DRX_AUD_STANDARD_D_K_MONO ) ? "D/K Mono FM" : \
2196 ( x == DRX_AUD_STANDARD_BG_FM ) ? "B/G-Dual Carrier FM (A2)" : \
2197 ( x == DRX_AUD_STANDARD_D_K1 ) ? "D/K1-Dual Carrier FM" : \
2198 ( x == DRX_AUD_STANDARD_D_K2 ) ? "D/K2-Dual Carrier FM" : \
2199 ( x == DRX_AUD_STANDARD_D_K3 ) ? "D/K3-Dual Carrier FM" : \
2200 ( x == DRX_AUD_STANDARD_BG_NICAM_FM ) ? "B/G-NICAM-FM" : \
2201 ( x == DRX_AUD_STANDARD_L_NICAM_AM ) ? "L-NICAM-AM" : \
2202 ( x == DRX_AUD_STANDARD_I_NICAM_FM ) ? "I-NICAM-FM" : \
2203 ( x == DRX_AUD_STANDARD_D_K_NICAM_FM ) ? "D/K-NICAM-FM" : \
2204 ( x == DRX_AUD_STANDARD_UNKNOWN ) ? "Unknown" : \
2205 "(Invalid)" )
2206 #define DRX_STR_AUD_STEREO(x) ( \
2207 ( x == TRUE ) ? "Stereo" : \
2208 ( x == FALSE ) ? "Mono" : \
2209 "(Invalid)" )
2210
2211 #define DRX_STR_AUD_SAP(x) ( \
2212 ( x == TRUE ) ? "Present" : \
2213 ( x == FALSE ) ? "Not present" : \
2214 "(Invalid)" )
2215
2216 #define DRX_STR_AUD_CARRIER(x) ( \
2217 ( x == TRUE ) ? "Present" : \
2218 ( x == FALSE ) ? "Not present" : \
2219 "(Invalid)" )
2220
2221 #define DRX_STR_AUD_RDS(x) ( \
2222 ( x == TRUE ) ? "Available" : \
2223 ( x == FALSE ) ? "Not Available" : \
2224 "(Invalid)" )
2225
2226 #define DRX_STR_AUD_NICAM_STATUS(x) ( \
2227 ( x == DRX_AUD_NICAM_DETECTED ) ? "Detected" : \
2228 ( x == DRX_AUD_NICAM_NOT_DETECTED ) ? "Not detected" : \
2229 ( x == DRX_AUD_NICAM_BAD ) ? "Bad" : \
2230 "(Invalid)" )
2231
2232 #define DRX_STR_RDS_VALID(x) ( \
2233 ( x == TRUE ) ? "Valid" : \
2234 ( x == FALSE ) ? "Not Valid" : \
2235 "(Invalid)" )
2236
2237 /*-------------------------------------------------------------------------
2238 Access macros
2239 -------------------------------------------------------------------------*/
2240
2241 /**
2242 * \brief Create a compilable reference to the microcode attribute
2243 * \param d pointer to demod instance
2244 *
2245 * Used as main reference to an attribute field.
2246 * Used by both macro implementation and function implementation.
2247 * These macros are defined to avoid duplication of code in macro and function
2248 * definitions that handle access of demod common or extended attributes.
2249 *
2250 */
2251
2252 #define DRX_ATTR_MCRECORD( d ) ((d)->myCommonAttr->mcversion)
2253 #define DRX_ATTR_MIRRORFREQSPECT( d ) ((d)->myCommonAttr->mirrorFreqSpect)
2254 #define DRX_ATTR_CURRENTPOWERMODE( d )((d)->myCommonAttr->currentPowerMode)
2255 #define DRX_ATTR_ISOPENED( d ) ((d)->myCommonAttr->isOpened)
2256 #define DRX_ATTR_USEBOOTLOADER( d ) ((d)->myCommonAttr->useBootloader)
2257 #define DRX_ATTR_CURRENTSTANDARD( d ) ((d)->myCommonAttr->currentStandard)
2258 #define DRX_ATTR_PREVSTANDARD( d ) ((d)->myCommonAttr->prevStandard)
2259 #define DRX_ATTR_CACHESTANDARD( d ) ((d)->myCommonAttr->diCacheStandard)
2260 #define DRX_ATTR_CURRENTCHANNEL( d ) ((d)->myCommonAttr->currentChannel)
2261 #define DRX_ATTR_MICROCODE( d ) ((d)->myCommonAttr->microcode)
2262 #define DRX_ATTR_MICROCODESIZE( d ) ((d)->myCommonAttr->microcodeSize)
2263 #define DRX_ATTR_VERIFYMICROCODE( d ) ((d)->myCommonAttr->verifyMicrocode)
2264 #define DRX_ATTR_CAPABILITIES( d ) ((d)->myCommonAttr->capabilities)
2265 #define DRX_ATTR_PRODUCTID( d ) ((d)->myCommonAttr->productId)
2266 #define DRX_ATTR_INTERMEDIATEFREQ( d) ((d)->myCommonAttr->intermediateFreq)
2267 #define DRX_ATTR_SYSCLOCKFREQ( d) ((d)->myCommonAttr->sysClockFreq)
2268 #define DRX_ATTR_TUNERRFAGCPOL( d ) ((d)->myCommonAttr->tunerRfAgcPol)
2269 #define DRX_ATTR_TUNERIFAGCPOL( d) ((d)->myCommonAttr->tunerIfAgcPol)
2270 #define DRX_ATTR_TUNERSLOWMODE( d) ((d)->myCommonAttr->tunerSlowMode)
2271 #define DRX_ATTR_TUNERSPORTNR( d) ((d)->myCommonAttr->tunerPortNr)
2272 #define DRX_ATTR_TUNER( d ) ((d)->myTuner)
2273 #define DRX_ATTR_I2CADDR( d ) ((d)->myI2CDevAddr->i2cAddr)
2274 #define DRX_ATTR_I2CDEVID( d ) ((d)->myI2CDevAddr->i2cDevId)
2275
2276 /**
2277 * \brief Actual access macro's
2278 * \param d pointer to demod instance
2279 * \param x value to set ar to get
2280 *
2281 * SET macro's must be used to set the value of an attribute.
2282 * GET macro's must be used to retrieve the value of an attribute.
2283 *
2284 */
2285
2286 /**************************/
2287
2288 #define DRX_SET_MIRRORFREQSPECT( d, x ) \
2289 do { \
2290 DRX_ATTR_MIRRORFREQSPECT( d ) = (x); \
2291 } while(0)
2292
2293 #define DRX_GET_MIRRORFREQSPECT( d, x ) \
2294 do { \
2295 (x)=DRX_ATTR_MIRRORFREQSPECT( d ); \
2296 } while(0)
2297
2298 /**************************/
2299
2300 #define DRX_SET_CURRENTPOWERMODE( d, x ) \
2301 do { \
2302 DRX_ATTR_CURRENTPOWERMODE( d ) = (x); \
2303 } while(0)
2304
2305 #define DRX_GET_CURRENTPOWERMODE( d, x ) \
2306 do { \
2307 (x)=DRX_ATTR_CURRENTPOWERMODE( d ); \
2308 } while(0)
2309
2310 /**************************/
2311
2312 #define DRX_SET_MICROCODE( d, x ) \
2313 do { \
2314 DRX_ATTR_MICROCODE( d ) = (x); \
2315 } while(0)
2316
2317 #define DRX_GET_MICROCODE( d, x ) \
2318 do { \
2319 (x)=DRX_ATTR_MICROCODE( d ); \
2320 } while(0)
2321
2322 /**************************/
2323
2324 #define DRX_SET_MICROCODESIZE( d, x ) \
2325 do { \
2326 DRX_ATTR_MICROCODESIZE(d) = (x); \
2327 } while(0)
2328
2329 #define DRX_GET_MICROCODESIZE( d, x ) \
2330 do { \
2331 (x)=DRX_ATTR_MICROCODESIZE(d); \
2332 } while(0)
2333
2334 /**************************/
2335
2336 #define DRX_SET_VERIFYMICROCODE( d, x ) \
2337 do { \
2338 DRX_ATTR_VERIFYMICROCODE(d) = (x); \
2339 } while(0)
2340
2341 #define DRX_GET_VERIFYMICROCODE( d, x ) \
2342 do { \
2343 (x)=DRX_ATTR_VERIFYMICROCODE(d); \
2344 } while(0)
2345
2346 /**************************/
2347
2348 #define DRX_SET_MCVERTYPE( d, x ) \
2349 do { \
2350 DRX_ATTR_MCRECORD(d).auxType = (x); \
2351 } while (0)
2352
2353 #define DRX_GET_MCVERTYPE( d, x ) \
2354 do { \
2355 (x) = DRX_ATTR_MCRECORD(d).auxType; \
2356 } while (0)
2357
2358 /**************************/
2359
2360 #define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD)
2361
2362 /**************************/
2363
2364 #define DRX_SET_MCDEV( d, x ) \
2365 do { \
2366 DRX_ATTR_MCRECORD(d).mcDevType = (x); \
2367 } while (0)
2368
2369 #define DRX_GET_MCDEV( d, x ) \
2370 do { \
2371 (x) = DRX_ATTR_MCRECORD(d).mcDevType; \
2372 } while (0)
2373
2374 /**************************/
2375
2376 #define DRX_SET_MCVERSION( d, x ) \
2377 do { \
2378 DRX_ATTR_MCRECORD(d).mcVersion = (x); \
2379 } while (0)
2380
2381 #define DRX_GET_MCVERSION( d, x ) \
2382 do { \
2383 (x) = DRX_ATTR_MCRECORD(d).mcVersion; \
2384 } while (0)
2385
2386 /**************************/
2387 #define DRX_SET_MCPATCH( d, x ) \
2388 do { \
2389 DRX_ATTR_MCRECORD(d).mcBaseVersion = (x); \
2390 } while (0)
2391
2392 #define DRX_GET_MCPATCH( d, x ) \
2393 do { \
2394 (x) = DRX_ATTR_MCRECORD(d).mcBaseVersion; \
2395 } while (0)
2396
2397 /**************************/
2398
2399 #define DRX_SET_I2CADDR( d, x ) \
2400 do { \
2401 DRX_ATTR_I2CADDR(d) = (x); \
2402 } while(0)
2403
2404 #define DRX_GET_I2CADDR( d, x ) \
2405 do { \
2406 (x)=DRX_ATTR_I2CADDR(d); \
2407 } while(0)
2408
2409 /**************************/
2410
2411 #define DRX_SET_I2CDEVID( d, x ) \
2412 do { \
2413 DRX_ATTR_I2CDEVID(d) = (x); \
2414 } while(0)
2415
2416 #define DRX_GET_I2CDEVID( d, x ) \
2417 do { \
2418 (x)=DRX_ATTR_I2CDEVID(d); \
2419 } while(0)
2420
2421 /**************************/
2422
2423 #define DRX_SET_USEBOOTLOADER( d, x ) \
2424 do { \
2425 DRX_ATTR_USEBOOTLOADER(d) = (x); \
2426 } while(0)
2427
2428 #define DRX_GET_USEBOOTLOADER( d, x) \
2429 do { \
2430 (x)=DRX_ATTR_USEBOOTLOADER(d); \
2431 } while(0)
2432
2433 /**************************/
2434
2435 #define DRX_SET_CURRENTSTANDARD( d, x ) \
2436 do { \
2437 DRX_ATTR_CURRENTSTANDARD(d) = (x); \
2438 } while(0)
2439
2440 #define DRX_GET_CURRENTSTANDARD( d, x) \
2441 do { \
2442 (x)=DRX_ATTR_CURRENTSTANDARD(d); \
2443 } while(0)
2444
2445 /**************************/
2446
2447 #define DRX_SET_PREVSTANDARD( d, x ) \
2448 do { \
2449 DRX_ATTR_PREVSTANDARD(d) = (x); \
2450 } while(0)
2451
2452 #define DRX_GET_PREVSTANDARD( d, x) \
2453 do { \
2454 (x)=DRX_ATTR_PREVSTANDARD(d); \
2455 } while(0)
2456
2457 /**************************/
2458
2459 #define DRX_SET_CACHESTANDARD( d, x ) \
2460 do { \
2461 DRX_ATTR_CACHESTANDARD(d) = (x); \
2462 } while(0)
2463
2464 #define DRX_GET_CACHESTANDARD( d, x) \
2465 do { \
2466 (x)=DRX_ATTR_CACHESTANDARD(d); \
2467 } while(0)
2468
2469 /**************************/
2470
2471 #define DRX_SET_CURRENTCHANNEL( d, x ) \
2472 do { \
2473 DRX_ATTR_CURRENTCHANNEL(d) = (x); \
2474 } while(0)
2475
2476 #define DRX_GET_CURRENTCHANNEL( d, x) \
2477 do { \
2478 (x)=DRX_ATTR_CURRENTCHANNEL(d); \
2479 } while(0)
2480
2481 /**************************/
2482
2483 #define DRX_SET_ISOPENED( d, x ) \
2484 do { \
2485 DRX_ATTR_ISOPENED(d) = (x); \
2486 } while(0)
2487
2488 #define DRX_GET_ISOPENED( d, x) \
2489 do { \
2490 (x) = DRX_ATTR_ISOPENED(d); \
2491 } while(0)
2492
2493 /**************************/
2494
2495 #define DRX_SET_TUNER( d, x ) \
2496 do { \
2497 DRX_ATTR_TUNER(d) = (x); \
2498 } while(0)
2499
2500 #define DRX_GET_TUNER( d, x) \
2501 do { \
2502 (x) = DRX_ATTR_TUNER(d); \
2503 } while(0)
2504
2505 /**************************/
2506
2507 #define DRX_SET_CAPABILITIES( d, x ) \
2508 do { \
2509 DRX_ATTR_CAPABILITIES(d) = (x); \
2510 } while(0)
2511
2512 #define DRX_GET_CAPABILITIES( d, x) \
2513 do { \
2514 (x) = DRX_ATTR_CAPABILITIES(d); \
2515 } while(0)
2516
2517 /**************************/
2518
2519 #define DRX_SET_PRODUCTID( d, x ) \
2520 do { \
2521 DRX_ATTR_PRODUCTID(d) |= (x << 4); \
2522 } while(0)
2523
2524 #define DRX_GET_PRODUCTID( d, x) \
2525 do { \
2526 (x) = (DRX_ATTR_PRODUCTID(d) >> 4); \
2527 } while(0)
2528
2529 /**************************/
2530
2531 #define DRX_SET_MFX( d, x ) \
2532 do { \
2533 DRX_ATTR_PRODUCTID(d) |= (x); \
2534 } while(0)
2535
2536 #define DRX_GET_MFX( d, x) \
2537 do { \
2538 (x) = (DRX_ATTR_PRODUCTID(d) & 0xF); \
2539 } while(0)
2540
2541 /**************************/
2542
2543 #define DRX_SET_INTERMEDIATEFREQ( d, x ) \
2544 do { \
2545 DRX_ATTR_INTERMEDIATEFREQ(d) = (x); \
2546 } while(0)
2547
2548 #define DRX_GET_INTERMEDIATEFREQ( d, x) \
2549 do { \
2550 (x) = DRX_ATTR_INTERMEDIATEFREQ(d); \
2551 } while(0)
2552
2553 /**************************/
2554
2555 #define DRX_SET_SYSCLOCKFREQ( d, x ) \
2556 do { \
2557 DRX_ATTR_SYSCLOCKFREQ(d) = (x); \
2558 } while(0)
2559
2560 #define DRX_GET_SYSCLOCKFREQ( d, x) \
2561 do { \
2562 (x) = DRX_ATTR_SYSCLOCKFREQ(d); \
2563 } while(0)
2564
2565 /**************************/
2566
2567 #define DRX_SET_TUNERRFAGCPOL( d, x ) \
2568 do { \
2569 DRX_ATTR_TUNERRFAGCPOL(d) = (x); \
2570 } while(0)
2571
2572 #define DRX_GET_TUNERRFAGCPOL( d, x) \
2573 do { \
2574 (x) = DRX_ATTR_TUNERRFAGCPOL(d); \
2575 } while(0)
2576
2577 /**************************/
2578
2579 #define DRX_SET_TUNERIFAGCPOL( d, x ) \
2580 do { \
2581 DRX_ATTR_TUNERIFAGCPOL(d) = (x); \
2582 } while(0)
2583
2584 #define DRX_GET_TUNERIFAGCPOL( d, x) \
2585 do { \
2586 (x) = DRX_ATTR_TUNERIFAGCPOL(d); \
2587 } while(0)
2588
2589 /**************************/
2590
2591 #define DRX_SET_TUNERSLOWMODE( d, x ) \
2592 do { \
2593 DRX_ATTR_TUNERSLOWMODE(d) = (x); \
2594 } while(0)
2595
2596 #define DRX_GET_TUNERSLOWMODE( d, x) \
2597 do { \
2598 (x) = DRX_ATTR_TUNERSLOWMODE(d); \
2599 } while(0)
2600
2601 /**************************/
2602
2603 #define DRX_SET_TUNERPORTNR( d, x ) \
2604 do { \
2605 DRX_ATTR_TUNERSPORTNR(d) = (x); \
2606 } while(0)
2607
2608 /**************************/
2609
2610 /* Macros with device-specific handling are converted to CFG functions */
2611
2612 #define DRX_ACCESSMACRO_SET( demod, value, cfgName, dataType ) \
2613 do { \
2614 DRXCfg_t config; \
2615 dataType cfgData; \
2616 config.cfgType = cfgName; \
2617 config.cfgData = &cfgData; \
2618 cfgData = value; \
2619 DRX_Ctrl( demod, DRX_CTRL_SET_CFG, &config ); \
2620 } while ( 0 )
2621
2622 #define DRX_ACCESSMACRO_GET( demod, value, cfgName, dataType, errorValue ) \
2623 do { \
2624 DRXStatus_t cfgStatus; \
2625 DRXCfg_t config; \
2626 dataType cfgData; \
2627 config.cfgType = cfgName; \
2628 config.cfgData = &cfgData; \
2629 cfgStatus = DRX_Ctrl( demod, DRX_CTRL_GET_CFG, &config ); \
2630 if ( cfgStatus == DRX_STS_OK ) { \
2631 value = cfgData; \
2632 } else { \
2633 value = (dataType)errorValue; \
2634 } \
2635 } while ( 0 )
2636
2637 /* Configuration functions for usage by Access (XS) Macros */
2638
2639 #ifndef DRX_XS_CFG_BASE
2640 #define DRX_XS_CFG_BASE (500)
2641 #endif
2642
2643 #define DRX_XS_CFG_PRESET ( DRX_XS_CFG_BASE + 0 )
2644 #define DRX_XS_CFG_AUD_BTSC_DETECT ( DRX_XS_CFG_BASE + 1 )
2645 #define DRX_XS_CFG_QAM_LOCKRANGE ( DRX_XS_CFG_BASE + 2 )
2646
2647 /* Access Macros with device-specific handling */
2648
2649 #define DRX_SET_PRESET( d, x ) \
2650 DRX_ACCESSMACRO_SET( (d), (x), DRX_XS_CFG_PRESET, char* )
2651 #define DRX_GET_PRESET( d, x ) \
2652 DRX_ACCESSMACRO_GET( (d), (x), DRX_XS_CFG_PRESET, char*, "ERROR" )
2653
2654 #define DRX_SET_AUD_BTSC_DETECT( d, x ) DRX_ACCESSMACRO_SET( (d), (x), \
2655 DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t )
2656 #define DRX_GET_AUD_BTSC_DETECT( d, x ) DRX_ACCESSMACRO_GET( (d), (x), \
2657 DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t, DRX_UNKNOWN )
2658
2659 #define DRX_SET_QAM_LOCKRANGE( d, x ) DRX_ACCESSMACRO_SET( (d), (x), \
2660 DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t )
2661 #define DRX_GET_QAM_LOCKRANGE( d, x ) DRX_ACCESSMACRO_GET( (d), (x), \
2662 DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t, DRX_UNKNOWN )
2663
2664 /**
2665 * \brief Macro to check if std is an ATV standard
2666 * \retval TRUE std is an ATV standard
2667 * \retval FALSE std is an ATV standard
2668 */
2669 #define DRX_ISATVSTD( std ) ( ( (std) == DRX_STANDARD_PAL_SECAM_BG ) || \
2670 ( (std) == DRX_STANDARD_PAL_SECAM_DK ) || \
2671 ( (std) == DRX_STANDARD_PAL_SECAM_I ) || \
2672 ( (std) == DRX_STANDARD_PAL_SECAM_L ) || \
2673 ( (std) == DRX_STANDARD_PAL_SECAM_LP ) || \
2674 ( (std) == DRX_STANDARD_NTSC ) || \
2675 ( (std) == DRX_STANDARD_FM ) )
2676
2677 /**
2678 * \brief Macro to check if std is an QAM standard
2679 * \retval TRUE std is an QAM standards
2680 * \retval FALSE std is an QAM standards
2681 */
2682 #define DRX_ISQAMSTD( std ) ( ( (std) == DRX_STANDARD_ITU_A ) || \
2683 ( (std) == DRX_STANDARD_ITU_B ) || \
2684 ( (std) == DRX_STANDARD_ITU_C ) || \
2685 ( (std) == DRX_STANDARD_ITU_D ))
2686
2687 /**
2688 * \brief Macro to check if std is VSB standard
2689 * \retval TRUE std is VSB standard
2690 * \retval FALSE std is not VSB standard
2691 */
2692 #define DRX_ISVSBSTD( std ) ( (std) == DRX_STANDARD_8VSB )
2693
2694 /**
2695 * \brief Macro to check if std is DVBT standard
2696 * \retval TRUE std is DVBT standard
2697 * \retval FALSE std is not DVBT standard
2698 */
2699 #define DRX_ISDVBTSTD( std ) ( (std) == DRX_STANDARD_DVBT )
2700
2701 /*-------------------------------------------------------------------------
2702 Exported FUNCTIONS
2703 -------------------------------------------------------------------------*/
2704
2705 DRXStatus_t DRX_Init(pDRXDemodInstance_t demods[]);
2706
2707 DRXStatus_t DRX_Term(void);
2708
2709 DRXStatus_t DRX_Open(pDRXDemodInstance_t demod);
2710
2711 DRXStatus_t DRX_Close(pDRXDemodInstance_t demod);
2712
2713 DRXStatus_t DRX_Ctrl(pDRXDemodInstance_t demod,
2714 DRXCtrlIndex_t ctrl, void *ctrlData);
2715
2716 /*-------------------------------------------------------------------------
2717 THE END
2718 -------------------------------------------------------------------------*/
2719 #ifdef __cplusplus
2720 }
2721 #endif
2722 #endif /* __DRXDRIVER_H__ */
Linux kernel - Deliverables
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