2 * Support for LG Electronics LGDT3304 and LGDT3305 - VSB/QAM
4 * Copyright (C) 2008, 2009, 2010 Michael Krufky <mkrufky@linuxtv.org>
6 * LGDT3304 support by Jarod Wilson <jarod@redhat.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <asm/div64.h>
25 #include <linux/dvb/frontend.h>
26 #include <linux/slab.h>
31 module_param(debug
, int, 0644);
32 MODULE_PARM_DESC(debug
, "set debug level (info=1, reg=2 (or-able))");
37 #define lg_printk(kern, fmt, arg...) \
38 printk(kern "%s: " fmt, __func__, ##arg)
40 #define lg_info(fmt, arg...) printk(KERN_INFO "lgdt3305: " fmt, ##arg)
41 #define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg)
42 #define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg)
43 #define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \
44 lg_printk(KERN_DEBUG, fmt, ##arg)
45 #define lg_reg(fmt, arg...) if (debug & DBG_REG) \
46 lg_printk(KERN_DEBUG, fmt, ##arg)
48 #define lg_fail(ret) \
53 lg_err("error %d on line %d\n", ret, __LINE__); \
57 struct lgdt3305_state
{
58 struct i2c_adapter
*i2c_adap
;
59 const struct lgdt3305_config
*cfg
;
61 struct dvb_frontend frontend
;
63 fe_modulation_t current_modulation
;
64 u32 current_frequency
;
68 /* ------------------------------------------------------------------------ */
70 /* FIXME: verify & document the LGDT3304 registers */
72 #define LGDT3305_GEN_CTRL_1 0x0000
73 #define LGDT3305_GEN_CTRL_2 0x0001
74 #define LGDT3305_GEN_CTRL_3 0x0002
75 #define LGDT3305_GEN_STATUS 0x0003
76 #define LGDT3305_GEN_CONTROL 0x0007
77 #define LGDT3305_GEN_CTRL_4 0x000a
78 #define LGDT3305_DGTL_AGC_REF_1 0x0012
79 #define LGDT3305_DGTL_AGC_REF_2 0x0013
80 #define LGDT3305_CR_CTR_FREQ_1 0x0106
81 #define LGDT3305_CR_CTR_FREQ_2 0x0107
82 #define LGDT3305_CR_CTR_FREQ_3 0x0108
83 #define LGDT3305_CR_CTR_FREQ_4 0x0109
84 #define LGDT3305_CR_MSE_1 0x011b
85 #define LGDT3305_CR_MSE_2 0x011c
86 #define LGDT3305_CR_LOCK_STATUS 0x011d
87 #define LGDT3305_CR_CTRL_7 0x0126
88 #define LGDT3305_AGC_POWER_REF_1 0x0300
89 #define LGDT3305_AGC_POWER_REF_2 0x0301
90 #define LGDT3305_AGC_DELAY_PT_1 0x0302
91 #define LGDT3305_AGC_DELAY_PT_2 0x0303
92 #define LGDT3305_RFAGC_LOOP_FLTR_BW_1 0x0306
93 #define LGDT3305_RFAGC_LOOP_FLTR_BW_2 0x0307
94 #define LGDT3305_IFBW_1 0x0308
95 #define LGDT3305_IFBW_2 0x0309
96 #define LGDT3305_AGC_CTRL_1 0x030c
97 #define LGDT3305_AGC_CTRL_4 0x0314
98 #define LGDT3305_EQ_MSE_1 0x0413
99 #define LGDT3305_EQ_MSE_2 0x0414
100 #define LGDT3305_EQ_MSE_3 0x0415
101 #define LGDT3305_PT_MSE_1 0x0417
102 #define LGDT3305_PT_MSE_2 0x0418
103 #define LGDT3305_PT_MSE_3 0x0419
104 #define LGDT3305_FEC_BLOCK_CTRL 0x0504
105 #define LGDT3305_FEC_LOCK_STATUS 0x050a
106 #define LGDT3305_FEC_PKT_ERR_1 0x050c
107 #define LGDT3305_FEC_PKT_ERR_2 0x050d
108 #define LGDT3305_TP_CTRL_1 0x050e
109 #define LGDT3305_BERT_PERIOD 0x0801
110 #define LGDT3305_BERT_ERROR_COUNT_1 0x080a
111 #define LGDT3305_BERT_ERROR_COUNT_2 0x080b
112 #define LGDT3305_BERT_ERROR_COUNT_3 0x080c
113 #define LGDT3305_BERT_ERROR_COUNT_4 0x080d
115 static int lgdt3305_write_reg(struct lgdt3305_state
*state
, u16 reg
, u8 val
)
118 u8 buf
[] = { reg
>> 8, reg
& 0xff, val
};
119 struct i2c_msg msg
= {
120 .addr
= state
->cfg
->i2c_addr
, .flags
= 0,
121 .buf
= buf
, .len
= 3,
124 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg
, val
);
126 ret
= i2c_transfer(state
->i2c_adap
, &msg
, 1);
129 lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
130 msg
.buf
[0], msg
.buf
[1], msg
.buf
[2], ret
);
139 static int lgdt3305_read_reg(struct lgdt3305_state
*state
, u16 reg
, u8
*val
)
142 u8 reg_buf
[] = { reg
>> 8, reg
& 0xff };
143 struct i2c_msg msg
[] = {
144 { .addr
= state
->cfg
->i2c_addr
,
145 .flags
= 0, .buf
= reg_buf
, .len
= 2 },
146 { .addr
= state
->cfg
->i2c_addr
,
147 .flags
= I2C_M_RD
, .buf
= val
, .len
= 1 },
150 lg_reg("reg: 0x%04x\n", reg
);
152 ret
= i2c_transfer(state
->i2c_adap
, msg
, 2);
155 lg_err("error (addr %02x reg %04x error (ret == %i)\n",
156 state
->cfg
->i2c_addr
, reg
, ret
);
165 #define read_reg(state, reg) \
168 int ret = lgdt3305_read_reg(state, reg, &__val); \
174 static int lgdt3305_set_reg_bit(struct lgdt3305_state
*state
,
175 u16 reg
, int bit
, int onoff
)
180 lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg
, bit
, onoff
);
182 ret
= lgdt3305_read_reg(state
, reg
, &val
);
187 val
|= (onoff
& 1) << bit
;
189 ret
= lgdt3305_write_reg(state
, reg
, val
);
194 struct lgdt3305_reg
{
199 static int lgdt3305_write_regs(struct lgdt3305_state
*state
,
200 struct lgdt3305_reg
*regs
, int len
)
204 lg_reg("writing %d registers...\n", len
);
206 for (i
= 0; i
< len
- 1; i
++) {
207 ret
= lgdt3305_write_reg(state
, regs
[i
].reg
, regs
[i
].val
);
214 /* ------------------------------------------------------------------------ */
216 static int lgdt3305_soft_reset(struct lgdt3305_state
*state
)
222 ret
= lgdt3305_set_reg_bit(state
, LGDT3305_GEN_CTRL_3
, 0, 0);
227 ret
= lgdt3305_set_reg_bit(state
, LGDT3305_GEN_CTRL_3
, 0, 1);
232 static inline int lgdt3305_mpeg_mode(struct lgdt3305_state
*state
,
233 enum lgdt3305_mpeg_mode mode
)
235 lg_dbg("(%d)\n", mode
);
236 return lgdt3305_set_reg_bit(state
, LGDT3305_TP_CTRL_1
, 5, mode
);
239 static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state
*state
)
243 enum lgdt3305_tp_clock_edge edge
= state
->cfg
->tpclk_edge
;
244 enum lgdt3305_tp_valid_polarity valid
= state
->cfg
->tpvalid_polarity
;
246 lg_dbg("edge = %d, valid = %d\n", edge
, valid
);
248 ret
= lgdt3305_read_reg(state
, LGDT3305_TP_CTRL_1
, &val
);
259 ret
= lgdt3305_write_reg(state
, LGDT3305_TP_CTRL_1
, val
);
263 ret
= lgdt3305_soft_reset(state
);
268 static int lgdt3305_set_modulation(struct lgdt3305_state
*state
,
269 struct dtv_frontend_properties
*p
)
276 ret
= lgdt3305_read_reg(state
, LGDT3305_GEN_CTRL_1
, &opermode
);
282 switch (p
->modulation
) {
295 ret
= lgdt3305_write_reg(state
, LGDT3305_GEN_CTRL_1
, opermode
);
300 static int lgdt3305_set_filter_extension(struct lgdt3305_state
*state
,
301 struct dtv_frontend_properties
*p
)
305 switch (p
->modulation
) {
316 lg_dbg("val = %d\n", val
);
318 return lgdt3305_set_reg_bit(state
, 0x043f, 2, val
);
321 /* ------------------------------------------------------------------------ */
323 static int lgdt3305_passband_digital_agc(struct lgdt3305_state
*state
,
324 struct dtv_frontend_properties
*p
)
328 switch (p
->modulation
) {
342 lg_dbg("agc ref: 0x%04x\n", agc_ref
);
344 lgdt3305_write_reg(state
, LGDT3305_DGTL_AGC_REF_1
, agc_ref
>> 8);
345 lgdt3305_write_reg(state
, LGDT3305_DGTL_AGC_REF_2
, agc_ref
& 0xff);
350 static int lgdt3305_rfagc_loop(struct lgdt3305_state
*state
,
351 struct dtv_frontend_properties
*p
)
353 u16 ifbw
, rfbw
, agcdelay
;
355 switch (p
->modulation
) {
365 /* FIXME: investigate optimal ifbw & rfbw values for the
366 * DT3304 and re-write this switch..case block */
367 if (state
->cfg
->demod_chip
== LGDT3304
)
369 else /* (state->cfg->demod_chip == LGDT3305) */
376 if (state
->cfg
->rf_agc_loop
) {
377 lg_dbg("agcdelay: 0x%04x, rfbw: 0x%04x\n", agcdelay
, rfbw
);
379 /* rf agc loop filter bandwidth */
380 lgdt3305_write_reg(state
, LGDT3305_AGC_DELAY_PT_1
,
382 lgdt3305_write_reg(state
, LGDT3305_AGC_DELAY_PT_2
,
385 lgdt3305_write_reg(state
, LGDT3305_RFAGC_LOOP_FLTR_BW_1
,
387 lgdt3305_write_reg(state
, LGDT3305_RFAGC_LOOP_FLTR_BW_2
,
390 lg_dbg("ifbw: 0x%04x\n", ifbw
);
392 /* if agc loop filter bandwidth */
393 lgdt3305_write_reg(state
, LGDT3305_IFBW_1
, ifbw
>> 8);
394 lgdt3305_write_reg(state
, LGDT3305_IFBW_2
, ifbw
& 0xff);
400 static int lgdt3305_agc_setup(struct lgdt3305_state
*state
,
401 struct dtv_frontend_properties
*p
)
405 switch (p
->modulation
) {
419 lg_dbg("lockdten = %d, acqen = %d\n", lockdten
, acqen
);
421 /* control agc function */
422 switch (state
->cfg
->demod_chip
) {
424 lgdt3305_write_reg(state
, 0x0314, 0xe1 | lockdten
<< 1);
425 lgdt3305_set_reg_bit(state
, 0x030e, 2, acqen
);
428 lgdt3305_write_reg(state
, LGDT3305_AGC_CTRL_4
, 0xe1 | lockdten
<< 1);
429 lgdt3305_set_reg_bit(state
, LGDT3305_AGC_CTRL_1
, 2, acqen
);
435 return lgdt3305_rfagc_loop(state
, p
);
438 static int lgdt3305_set_agc_power_ref(struct lgdt3305_state
*state
,
439 struct dtv_frontend_properties
*p
)
443 switch (p
->modulation
) {
445 if (state
->cfg
->usref_8vsb
)
446 usref
= state
->cfg
->usref_8vsb
;
449 if (state
->cfg
->usref_qam64
)
450 usref
= state
->cfg
->usref_qam64
;
453 if (state
->cfg
->usref_qam256
)
454 usref
= state
->cfg
->usref_qam256
;
461 lg_dbg("set manual mode: 0x%04x\n", usref
);
463 lgdt3305_set_reg_bit(state
, LGDT3305_AGC_CTRL_1
, 3, 1);
465 lgdt3305_write_reg(state
, LGDT3305_AGC_POWER_REF_1
,
466 0xff & (usref
>> 8));
467 lgdt3305_write_reg(state
, LGDT3305_AGC_POWER_REF_2
,
468 0xff & (usref
>> 0));
473 /* ------------------------------------------------------------------------ */
475 static int lgdt3305_spectral_inversion(struct lgdt3305_state
*state
,
476 struct dtv_frontend_properties
*p
,
481 lg_dbg("(%d)\n", inversion
);
483 switch (p
->modulation
) {
485 ret
= lgdt3305_write_reg(state
, LGDT3305_CR_CTRL_7
,
486 inversion
? 0xf9 : 0x79);
490 ret
= lgdt3305_write_reg(state
, LGDT3305_FEC_BLOCK_CTRL
,
491 inversion
? 0xfd : 0xff);
499 static int lgdt3305_set_if(struct lgdt3305_state
*state
,
500 struct dtv_frontend_properties
*p
)
503 u8 nco1
, nco2
, nco3
, nco4
;
506 switch (p
->modulation
) {
508 if_freq_khz
= state
->cfg
->vsb_if_khz
;
512 if_freq_khz
= state
->cfg
->qam_if_khz
;
518 nco
= if_freq_khz
/ 10;
520 switch (p
->modulation
) {
534 nco1
= (nco
>> 24) & 0x3f;
536 nco2
= (nco
>> 16) & 0xff;
537 nco3
= (nco
>> 8) & 0xff;
540 lgdt3305_write_reg(state
, LGDT3305_CR_CTR_FREQ_1
, nco1
);
541 lgdt3305_write_reg(state
, LGDT3305_CR_CTR_FREQ_2
, nco2
);
542 lgdt3305_write_reg(state
, LGDT3305_CR_CTR_FREQ_3
, nco3
);
543 lgdt3305_write_reg(state
, LGDT3305_CR_CTR_FREQ_4
, nco4
);
545 lg_dbg("%d KHz -> [%02x%02x%02x%02x]\n",
546 if_freq_khz
, nco1
, nco2
, nco3
, nco4
);
551 /* ------------------------------------------------------------------------ */
553 static int lgdt3305_i2c_gate_ctrl(struct dvb_frontend
*fe
, int enable
)
555 struct lgdt3305_state
*state
= fe
->demodulator_priv
;
557 if (state
->cfg
->deny_i2c_rptr
)
560 lg_dbg("(%d)\n", enable
);
562 return lgdt3305_set_reg_bit(state
, LGDT3305_GEN_CTRL_2
, 5,
566 static int lgdt3305_sleep(struct dvb_frontend
*fe
)
568 struct lgdt3305_state
*state
= fe
->demodulator_priv
;
569 u8 gen_ctrl_3
, gen_ctrl_4
;
573 gen_ctrl_3
= read_reg(state
, LGDT3305_GEN_CTRL_3
);
574 gen_ctrl_4
= read_reg(state
, LGDT3305_GEN_CTRL_4
);
576 /* hold in software reset while sleeping */
578 /* tristate the IF-AGC pin */
580 /* tristate the RF-AGC pin */
583 /* disable vsb/qam module */
585 /* disable adc module */
588 lgdt3305_write_reg(state
, LGDT3305_GEN_CTRL_3
, gen_ctrl_3
);
589 lgdt3305_write_reg(state
, LGDT3305_GEN_CTRL_4
, gen_ctrl_4
);
594 static int lgdt3305_init(struct dvb_frontend
*fe
)
596 struct lgdt3305_state
*state
= fe
->demodulator_priv
;
599 static struct lgdt3305_reg lgdt3304_init_data
[] = {
600 { .reg
= LGDT3305_GEN_CTRL_1
, .val
= 0x03, },
601 { .reg
= 0x000d, .val
= 0x02, },
602 { .reg
= 0x000e, .val
= 0x02, },
603 { .reg
= LGDT3305_DGTL_AGC_REF_1
, .val
= 0x32, },
604 { .reg
= LGDT3305_DGTL_AGC_REF_2
, .val
= 0xc4, },
605 { .reg
= LGDT3305_CR_CTR_FREQ_1
, .val
= 0x00, },
606 { .reg
= LGDT3305_CR_CTR_FREQ_2
, .val
= 0x00, },
607 { .reg
= LGDT3305_CR_CTR_FREQ_3
, .val
= 0x00, },
608 { .reg
= LGDT3305_CR_CTR_FREQ_4
, .val
= 0x00, },
609 { .reg
= LGDT3305_CR_CTRL_7
, .val
= 0xf9, },
610 { .reg
= 0x0112, .val
= 0x17, },
611 { .reg
= 0x0113, .val
= 0x15, },
612 { .reg
= 0x0114, .val
= 0x18, },
613 { .reg
= 0x0115, .val
= 0xff, },
614 { .reg
= 0x0116, .val
= 0x3c, },
615 { .reg
= 0x0214, .val
= 0x67, },
616 { .reg
= 0x0424, .val
= 0x8d, },
617 { .reg
= 0x0427, .val
= 0x12, },
618 { .reg
= 0x0428, .val
= 0x4f, },
619 { .reg
= LGDT3305_IFBW_1
, .val
= 0x80, },
620 { .reg
= LGDT3305_IFBW_2
, .val
= 0x00, },
621 { .reg
= 0x030a, .val
= 0x08, },
622 { .reg
= 0x030b, .val
= 0x9b, },
623 { .reg
= 0x030d, .val
= 0x00, },
624 { .reg
= 0x030e, .val
= 0x1c, },
625 { .reg
= 0x0314, .val
= 0xe1, },
626 { .reg
= 0x000d, .val
= 0x82, },
627 { .reg
= LGDT3305_TP_CTRL_1
, .val
= 0x5b, },
628 { .reg
= LGDT3305_TP_CTRL_1
, .val
= 0x5b, },
631 static struct lgdt3305_reg lgdt3305_init_data
[] = {
632 { .reg
= LGDT3305_GEN_CTRL_1
, .val
= 0x03, },
633 { .reg
= LGDT3305_GEN_CTRL_2
, .val
= 0xb0, },
634 { .reg
= LGDT3305_GEN_CTRL_3
, .val
= 0x01, },
635 { .reg
= LGDT3305_GEN_CONTROL
, .val
= 0x6f, },
636 { .reg
= LGDT3305_GEN_CTRL_4
, .val
= 0x03, },
637 { .reg
= LGDT3305_DGTL_AGC_REF_1
, .val
= 0x32, },
638 { .reg
= LGDT3305_DGTL_AGC_REF_2
, .val
= 0xc4, },
639 { .reg
= LGDT3305_CR_CTR_FREQ_1
, .val
= 0x00, },
640 { .reg
= LGDT3305_CR_CTR_FREQ_2
, .val
= 0x00, },
641 { .reg
= LGDT3305_CR_CTR_FREQ_3
, .val
= 0x00, },
642 { .reg
= LGDT3305_CR_CTR_FREQ_4
, .val
= 0x00, },
643 { .reg
= LGDT3305_CR_CTRL_7
, .val
= 0x79, },
644 { .reg
= LGDT3305_AGC_POWER_REF_1
, .val
= 0x32, },
645 { .reg
= LGDT3305_AGC_POWER_REF_2
, .val
= 0xc4, },
646 { .reg
= LGDT3305_AGC_DELAY_PT_1
, .val
= 0x0d, },
647 { .reg
= LGDT3305_AGC_DELAY_PT_2
, .val
= 0x30, },
648 { .reg
= LGDT3305_RFAGC_LOOP_FLTR_BW_1
, .val
= 0x80, },
649 { .reg
= LGDT3305_RFAGC_LOOP_FLTR_BW_2
, .val
= 0x00, },
650 { .reg
= LGDT3305_IFBW_1
, .val
= 0x80, },
651 { .reg
= LGDT3305_IFBW_2
, .val
= 0x00, },
652 { .reg
= LGDT3305_AGC_CTRL_1
, .val
= 0x30, },
653 { .reg
= LGDT3305_AGC_CTRL_4
, .val
= 0x61, },
654 { .reg
= LGDT3305_FEC_BLOCK_CTRL
, .val
= 0xff, },
655 { .reg
= LGDT3305_TP_CTRL_1
, .val
= 0x1b, },
660 switch (state
->cfg
->demod_chip
) {
662 ret
= lgdt3305_write_regs(state
, lgdt3304_init_data
,
663 ARRAY_SIZE(lgdt3304_init_data
));
666 ret
= lgdt3305_write_regs(state
, lgdt3305_init_data
,
667 ARRAY_SIZE(lgdt3305_init_data
));
675 ret
= lgdt3305_soft_reset(state
);
680 static int lgdt3304_set_parameters(struct dvb_frontend
*fe
)
682 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
683 struct lgdt3305_state
*state
= fe
->demodulator_priv
;
686 lg_dbg("(%d, %d)\n", p
->frequency
, p
->modulation
);
688 if (fe
->ops
.tuner_ops
.set_params
) {
689 ret
= fe
->ops
.tuner_ops
.set_params(fe
);
690 if (fe
->ops
.i2c_gate_ctrl
)
691 fe
->ops
.i2c_gate_ctrl(fe
, 0);
694 state
->current_frequency
= p
->frequency
;
697 ret
= lgdt3305_set_modulation(state
, p
);
701 ret
= lgdt3305_passband_digital_agc(state
, p
);
705 ret
= lgdt3305_agc_setup(state
, p
);
709 /* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */
710 switch (p
->modulation
) {
712 lgdt3305_write_reg(state
, 0x030d, 0x00);
713 lgdt3305_write_reg(state
, LGDT3305_CR_CTR_FREQ_1
, 0x4f);
714 lgdt3305_write_reg(state
, LGDT3305_CR_CTR_FREQ_2
, 0x0c);
715 lgdt3305_write_reg(state
, LGDT3305_CR_CTR_FREQ_3
, 0xac);
716 lgdt3305_write_reg(state
, LGDT3305_CR_CTR_FREQ_4
, 0xba);
720 lgdt3305_write_reg(state
, 0x030d, 0x14);
721 ret
= lgdt3305_set_if(state
, p
);
730 ret
= lgdt3305_spectral_inversion(state
, p
,
731 state
->cfg
->spectral_inversion
736 state
->current_modulation
= p
->modulation
;
738 ret
= lgdt3305_mpeg_mode(state
, state
->cfg
->mpeg_mode
);
742 /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
743 ret
= lgdt3305_mpeg_mode_polarity(state
);
748 static int lgdt3305_set_parameters(struct dvb_frontend
*fe
)
750 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
751 struct lgdt3305_state
*state
= fe
->demodulator_priv
;
754 lg_dbg("(%d, %d)\n", p
->frequency
, p
->modulation
);
756 if (fe
->ops
.tuner_ops
.set_params
) {
757 ret
= fe
->ops
.tuner_ops
.set_params(fe
);
758 if (fe
->ops
.i2c_gate_ctrl
)
759 fe
->ops
.i2c_gate_ctrl(fe
, 0);
762 state
->current_frequency
= p
->frequency
;
765 ret
= lgdt3305_set_modulation(state
, p
);
769 ret
= lgdt3305_passband_digital_agc(state
, p
);
772 ret
= lgdt3305_set_agc_power_ref(state
, p
);
775 ret
= lgdt3305_agc_setup(state
, p
);
780 ret
= lgdt3305_write_reg(state
, LGDT3305_GEN_CONTROL
, 0x2f);
783 ret
= lgdt3305_set_reg_bit(state
, LGDT3305_CR_CTR_FREQ_1
, 6, 1);
787 ret
= lgdt3305_set_if(state
, p
);
790 ret
= lgdt3305_spectral_inversion(state
, p
,
791 state
->cfg
->spectral_inversion
796 ret
= lgdt3305_set_filter_extension(state
, p
);
800 state
->current_modulation
= p
->modulation
;
802 ret
= lgdt3305_mpeg_mode(state
, state
->cfg
->mpeg_mode
);
806 /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
807 ret
= lgdt3305_mpeg_mode_polarity(state
);
812 static int lgdt3305_get_frontend(struct dvb_frontend
*fe
)
814 struct dtv_frontend_properties
*p
= &fe
->dtv_property_cache
;
815 struct lgdt3305_state
*state
= fe
->demodulator_priv
;
819 p
->modulation
= state
->current_modulation
;
820 p
->frequency
= state
->current_frequency
;
824 /* ------------------------------------------------------------------------ */
826 static int lgdt3305_read_cr_lock_status(struct lgdt3305_state
*state
,
831 char *cr_lock_state
= "";
835 ret
= lgdt3305_read_reg(state
, LGDT3305_CR_LOCK_STATUS
, &val
);
839 switch (state
->current_modulation
) {
845 switch (val
& 0x07) {
847 cr_lock_state
= "QAM UNLOCK";
850 cr_lock_state
= "QAM 1stLock";
853 cr_lock_state
= "QAM 2ndLock";
856 cr_lock_state
= "QAM FinalLock";
859 cr_lock_state
= "CLOCKQAM-INVALID!";
864 if (val
& (1 << 7)) {
866 cr_lock_state
= "CLOCKVSB";
872 lg_dbg("(%d) %s\n", *locked
, cr_lock_state
);
877 static int lgdt3305_read_fec_lock_status(struct lgdt3305_state
*state
,
881 int ret
, mpeg_lock
, fec_lock
, viterbi_lock
;
885 switch (state
->current_modulation
) {
888 ret
= lgdt3305_read_reg(state
,
889 LGDT3305_FEC_LOCK_STATUS
, &val
);
893 mpeg_lock
= (val
& (1 << 0)) ? 1 : 0;
894 fec_lock
= (val
& (1 << 2)) ? 1 : 0;
895 viterbi_lock
= (val
& (1 << 3)) ? 1 : 0;
897 *locked
= mpeg_lock
&& fec_lock
&& viterbi_lock
;
899 lg_dbg("(%d) %s%s%s\n", *locked
,
900 mpeg_lock
? "mpeg lock " : "",
901 fec_lock
? "fec lock " : "",
902 viterbi_lock
? "viterbi lock" : "");
912 static int lgdt3305_read_status(struct dvb_frontend
*fe
, fe_status_t
*status
)
914 struct lgdt3305_state
*state
= fe
->demodulator_priv
;
916 int ret
, signal
, inlock
, nofecerr
, snrgood
,
917 cr_lock
, fec_lock
, sync_lock
;
921 ret
= lgdt3305_read_reg(state
, LGDT3305_GEN_STATUS
, &val
);
925 signal
= (val
& (1 << 4)) ? 1 : 0;
926 inlock
= (val
& (1 << 3)) ? 0 : 1;
927 sync_lock
= (val
& (1 << 2)) ? 1 : 0;
928 nofecerr
= (val
& (1 << 1)) ? 1 : 0;
929 snrgood
= (val
& (1 << 0)) ? 1 : 0;
931 lg_dbg("%s%s%s%s%s\n",
932 signal
? "SIGNALEXIST " : "",
933 inlock
? "INLOCK " : "",
934 sync_lock
? "SYNCLOCK " : "",
935 nofecerr
? "NOFECERR " : "",
936 snrgood
? "SNRGOOD " : "");
938 ret
= lgdt3305_read_cr_lock_status(state
, &cr_lock
);
943 *status
|= FE_HAS_SIGNAL
;
945 *status
|= FE_HAS_CARRIER
;
947 *status
|= FE_HAS_VITERBI
;
949 *status
|= FE_HAS_SYNC
;
951 switch (state
->current_modulation
) {
954 /* signal bit is unreliable on the DT3304 in QAM mode */
955 if (((LGDT3304
== state
->cfg
->demod_chip
)) && (cr_lock
))
956 *status
|= FE_HAS_SIGNAL
;
958 ret
= lgdt3305_read_fec_lock_status(state
, &fec_lock
);
963 *status
|= FE_HAS_LOCK
;
967 *status
|= FE_HAS_LOCK
;
976 /* ------------------------------------------------------------------------ */
978 /* borrowed from lgdt330x.c */
979 static u32
calculate_snr(u32 mse
, u32 c
)
981 if (mse
== 0) /* no signal */
986 /* Negative SNR, which is possible, but realisticly the
987 demod will lose lock before the signal gets this bad. The
988 API only allows for unsigned values, so just return 0 */
994 static int lgdt3305_read_snr(struct dvb_frontend
*fe
, u16
*snr
)
996 struct lgdt3305_state
*state
= fe
->demodulator_priv
;
997 u32 noise
; /* noise value */
998 u32 c
; /* per-modulation SNR calculation constant */
1000 switch (state
->current_modulation
) {
1003 /* Use Phase Tracker Mean-Square Error Register */
1004 /* SNR for ranges from -13.11 to +44.08 */
1005 noise
= ((read_reg(state
, LGDT3305_PT_MSE_1
) & 0x07) << 16) |
1006 (read_reg(state
, LGDT3305_PT_MSE_2
) << 8) |
1007 (read_reg(state
, LGDT3305_PT_MSE_3
) & 0xff);
1008 c
= 73957994; /* log10(25*32^2)*2^24 */
1010 /* Use Equalizer Mean-Square Error Register */
1011 /* SNR for ranges from -16.12 to +44.08 */
1012 noise
= ((read_reg(state
, LGDT3305_EQ_MSE_1
) & 0x0f) << 16) |
1013 (read_reg(state
, LGDT3305_EQ_MSE_2
) << 8) |
1014 (read_reg(state
, LGDT3305_EQ_MSE_3
) & 0xff);
1015 c
= 73957994; /* log10(25*32^2)*2^24 */
1020 noise
= (read_reg(state
, LGDT3305_CR_MSE_1
) << 8) |
1021 (read_reg(state
, LGDT3305_CR_MSE_2
) & 0xff);
1023 c
= (state
->current_modulation
== QAM_64
) ?
1024 97939837 : 98026066;
1025 /* log10(688128)*2^24 and log10(696320)*2^24 */
1030 state
->snr
= calculate_snr(noise
, c
);
1031 /* report SNR in dB * 10 */
1032 *snr
= (state
->snr
/ ((1 << 24) / 10));
1033 lg_dbg("noise = 0x%08x, snr = %d.%02d dB\n", noise
,
1034 state
->snr
>> 24, (((state
->snr
>> 8) & 0xffff) * 100) >> 16);
1039 static int lgdt3305_read_signal_strength(struct dvb_frontend
*fe
,
1042 /* borrowed from lgdt330x.c
1044 * Calculate strength from SNR up to 35dB
1045 * Even though the SNR can go higher than 35dB,
1046 * there is some comfort factor in having a range of
1047 * strong signals that can show at 100%
1049 struct lgdt3305_state
*state
= fe
->demodulator_priv
;
1055 ret
= fe
->ops
.read_snr(fe
, &snr
);
1058 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
1059 /* scale the range 0 - 35*2^24 into 0 - 65535 */
1060 if (state
->snr
>= 8960 * 0x10000)
1063 *strength
= state
->snr
/ 8960;
1068 /* ------------------------------------------------------------------------ */
1070 static int lgdt3305_read_ber(struct dvb_frontend
*fe
, u32
*ber
)
1076 static int lgdt3305_read_ucblocks(struct dvb_frontend
*fe
, u32
*ucblocks
)
1078 struct lgdt3305_state
*state
= fe
->demodulator_priv
;
1081 (read_reg(state
, LGDT3305_FEC_PKT_ERR_1
) << 8) |
1082 (read_reg(state
, LGDT3305_FEC_PKT_ERR_2
) & 0xff);
1087 static int lgdt3305_get_tune_settings(struct dvb_frontend
*fe
,
1088 struct dvb_frontend_tune_settings
1091 fe_tune_settings
->min_delay_ms
= 500;
1096 static void lgdt3305_release(struct dvb_frontend
*fe
)
1098 struct lgdt3305_state
*state
= fe
->demodulator_priv
;
1103 static struct dvb_frontend_ops lgdt3304_ops
;
1104 static struct dvb_frontend_ops lgdt3305_ops
;
1106 struct dvb_frontend
*lgdt3305_attach(const struct lgdt3305_config
*config
,
1107 struct i2c_adapter
*i2c_adap
)
1109 struct lgdt3305_state
*state
= NULL
;
1113 lg_dbg("(%d-%04x)\n",
1114 i2c_adap
? i2c_adapter_id(i2c_adap
) : 0,
1115 config
? config
->i2c_addr
: 0);
1117 state
= kzalloc(sizeof(struct lgdt3305_state
), GFP_KERNEL
);
1121 state
->cfg
= config
;
1122 state
->i2c_adap
= i2c_adap
;
1124 switch (config
->demod_chip
) {
1126 memcpy(&state
->frontend
.ops
, &lgdt3304_ops
,
1127 sizeof(struct dvb_frontend_ops
));
1130 memcpy(&state
->frontend
.ops
, &lgdt3305_ops
,
1131 sizeof(struct dvb_frontend_ops
));
1136 state
->frontend
.demodulator_priv
= state
;
1138 /* verify that we're talking to a lg dt3304/5 */
1139 ret
= lgdt3305_read_reg(state
, LGDT3305_GEN_CTRL_2
, &val
);
1140 if ((lg_fail(ret
)) | (val
== 0))
1142 ret
= lgdt3305_write_reg(state
, 0x0808, 0x80);
1145 ret
= lgdt3305_read_reg(state
, 0x0808, &val
);
1146 if ((lg_fail(ret
)) | (val
!= 0x80))
1148 ret
= lgdt3305_write_reg(state
, 0x0808, 0x00);
1152 state
->current_frequency
= -1;
1153 state
->current_modulation
= -1;
1155 return &state
->frontend
;
1157 lg_warn("unable to detect %s hardware\n",
1158 config
->demod_chip
? "LGDT3304" : "LGDT3305");
1162 EXPORT_SYMBOL(lgdt3305_attach
);
1164 static struct dvb_frontend_ops lgdt3304_ops
= {
1165 .delsys
= { SYS_ATSC
, SYS_DVBC_ANNEX_B
},
1167 .name
= "LG Electronics LGDT3304 VSB/QAM Frontend",
1168 .frequency_min
= 54000000,
1169 .frequency_max
= 858000000,
1170 .frequency_stepsize
= 62500,
1171 .caps
= FE_CAN_QAM_64
| FE_CAN_QAM_256
| FE_CAN_8VSB
1173 .i2c_gate_ctrl
= lgdt3305_i2c_gate_ctrl
,
1174 .init
= lgdt3305_init
,
1175 .sleep
= lgdt3305_sleep
,
1176 .set_frontend
= lgdt3304_set_parameters
,
1177 .get_frontend
= lgdt3305_get_frontend
,
1178 .get_tune_settings
= lgdt3305_get_tune_settings
,
1179 .read_status
= lgdt3305_read_status
,
1180 .read_ber
= lgdt3305_read_ber
,
1181 .read_signal_strength
= lgdt3305_read_signal_strength
,
1182 .read_snr
= lgdt3305_read_snr
,
1183 .read_ucblocks
= lgdt3305_read_ucblocks
,
1184 .release
= lgdt3305_release
,
1187 static struct dvb_frontend_ops lgdt3305_ops
= {
1188 .delsys
= { SYS_ATSC
, SYS_DVBC_ANNEX_B
},
1190 .name
= "LG Electronics LGDT3305 VSB/QAM Frontend",
1191 .frequency_min
= 54000000,
1192 .frequency_max
= 858000000,
1193 .frequency_stepsize
= 62500,
1194 .caps
= FE_CAN_QAM_64
| FE_CAN_QAM_256
| FE_CAN_8VSB
1196 .i2c_gate_ctrl
= lgdt3305_i2c_gate_ctrl
,
1197 .init
= lgdt3305_init
,
1198 .sleep
= lgdt3305_sleep
,
1199 .set_frontend
= lgdt3305_set_parameters
,
1200 .get_frontend
= lgdt3305_get_frontend
,
1201 .get_tune_settings
= lgdt3305_get_tune_settings
,
1202 .read_status
= lgdt3305_read_status
,
1203 .read_ber
= lgdt3305_read_ber
,
1204 .read_signal_strength
= lgdt3305_read_signal_strength
,
1205 .read_snr
= lgdt3305_read_snr
,
1206 .read_ucblocks
= lgdt3305_read_ucblocks
,
1207 .release
= lgdt3305_release
,
1210 MODULE_DESCRIPTION("LG Electronics LGDT3304/5 ATSC/QAM-B Demodulator Driver");
1211 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
1212 MODULE_LICENSE("GPL");
1213 MODULE_VERSION("0.2");