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[media] m88ds3103: calculate DiSEqC message sending time
[deliverable/linux.git] / drivers / media / dvb-frontends / m88ds3103.c
1 /*
2 * Montage Technology M88DS3103/M88RS6000 demodulator driver
3 *
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include "m88ds3103_priv.h"
18
19 static struct dvb_frontend_ops m88ds3103_ops;
20
21 /* write single register with mask */
22 static int m88ds3103_update_bits(struct m88ds3103_dev *dev,
23 u8 reg, u8 mask, u8 val)
24 {
25 int ret;
26 u8 tmp;
27
28 /* no need for read if whole reg is written */
29 if (mask != 0xff) {
30 ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1);
31 if (ret)
32 return ret;
33
34 val &= mask;
35 tmp &= ~mask;
36 val |= tmp;
37 }
38
39 return regmap_bulk_write(dev->regmap, reg, &val, 1);
40 }
41
42 /* write reg val table using reg addr auto increment */
43 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev,
44 const struct m88ds3103_reg_val *tab, int tab_len)
45 {
46 struct i2c_client *client = dev->client;
47 int ret, i, j;
48 u8 buf[83];
49
50 dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
51
52 if (tab_len > 86) {
53 ret = -EINVAL;
54 goto err;
55 }
56
57 for (i = 0, j = 0; i < tab_len; i++, j++) {
58 buf[j] = tab[i].val;
59
60 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
61 !((j + 1) % (dev->cfg->i2c_wr_max - 1))) {
62 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1);
63 if (ret)
64 goto err;
65
66 j = -1;
67 }
68 }
69
70 return 0;
71 err:
72 dev_dbg(&client->dev, "failed=%d\n", ret);
73 return ret;
74 }
75
76 /*
77 * Get the demodulator AGC PWM voltage setting supplied to the tuner.
78 */
79 int m88ds3103_get_agc_pwm(struct dvb_frontend *fe, u8 *_agc_pwm)
80 {
81 struct m88ds3103_dev *dev = fe->demodulator_priv;
82 unsigned tmp;
83 int ret;
84
85 ret = regmap_read(dev->regmap, 0x3f, &tmp);
86 if (ret == 0)
87 *_agc_pwm = tmp;
88 return ret;
89 }
90 EXPORT_SYMBOL(m88ds3103_get_agc_pwm);
91
92 static int m88ds3103_read_status(struct dvb_frontend *fe,
93 enum fe_status *status)
94 {
95 struct m88ds3103_dev *dev = fe->demodulator_priv;
96 struct i2c_client *client = dev->client;
97 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
98 int ret, i, itmp;
99 unsigned int utmp;
100 u8 buf[3];
101
102 *status = 0;
103
104 if (!dev->warm) {
105 ret = -EAGAIN;
106 goto err;
107 }
108
109 switch (c->delivery_system) {
110 case SYS_DVBS:
111 ret = regmap_read(dev->regmap, 0xd1, &utmp);
112 if (ret)
113 goto err;
114
115 if ((utmp & 0x07) == 0x07)
116 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
117 FE_HAS_VITERBI | FE_HAS_SYNC |
118 FE_HAS_LOCK;
119 break;
120 case SYS_DVBS2:
121 ret = regmap_read(dev->regmap, 0x0d, &utmp);
122 if (ret)
123 goto err;
124
125 if ((utmp & 0x8f) == 0x8f)
126 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
127 FE_HAS_VITERBI | FE_HAS_SYNC |
128 FE_HAS_LOCK;
129 break;
130 default:
131 dev_dbg(&client->dev, "invalid delivery_system\n");
132 ret = -EINVAL;
133 goto err;
134 }
135
136 dev->fe_status = *status;
137 dev_dbg(&client->dev, "lock=%02x status=%02x\n", utmp, *status);
138
139 /* CNR */
140 if (dev->fe_status & FE_HAS_VITERBI) {
141 unsigned int cnr, noise, signal, noise_tot, signal_tot;
142
143 cnr = 0;
144 /* more iterations for more accurate estimation */
145 #define M88DS3103_SNR_ITERATIONS 3
146
147 switch (c->delivery_system) {
148 case SYS_DVBS:
149 itmp = 0;
150
151 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
152 ret = regmap_read(dev->regmap, 0xff, &utmp);
153 if (ret)
154 goto err;
155
156 itmp += utmp;
157 }
158
159 /* use of single register limits max value to 15 dB */
160 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
161 itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS);
162 if (itmp)
163 cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10));
164 break;
165 case SYS_DVBS2:
166 noise_tot = 0;
167 signal_tot = 0;
168
169 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
170 ret = regmap_bulk_read(dev->regmap, 0x8c, buf, 3);
171 if (ret)
172 goto err;
173
174 noise = buf[1] << 6; /* [13:6] */
175 noise |= buf[0] & 0x3f; /* [5:0] */
176 noise >>= 2;
177 signal = buf[2] * buf[2];
178 signal >>= 1;
179
180 noise_tot += noise;
181 signal_tot += signal;
182 }
183
184 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
185 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
186
187 /* SNR(X) dB = 10 * log10(X) dB */
188 if (signal > noise) {
189 itmp = signal / noise;
190 cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24));
191 }
192 break;
193 default:
194 dev_dbg(&client->dev, "invalid delivery_system\n");
195 ret = -EINVAL;
196 goto err;
197 }
198
199 if (cnr) {
200 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
201 c->cnr.stat[0].svalue = cnr;
202 } else {
203 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
204 }
205 } else {
206 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
207 }
208
209 /* BER */
210 if (dev->fe_status & FE_HAS_LOCK) {
211 unsigned int utmp, post_bit_error, post_bit_count;
212
213 switch (c->delivery_system) {
214 case SYS_DVBS:
215 ret = regmap_write(dev->regmap, 0xf9, 0x04);
216 if (ret)
217 goto err;
218
219 ret = regmap_read(dev->regmap, 0xf8, &utmp);
220 if (ret)
221 goto err;
222
223 /* measurement ready? */
224 if (!(utmp & 0x10)) {
225 ret = regmap_bulk_read(dev->regmap, 0xf6, buf, 2);
226 if (ret)
227 goto err;
228
229 post_bit_error = buf[1] << 8 | buf[0] << 0;
230 post_bit_count = 0x800000;
231 dev->post_bit_error += post_bit_error;
232 dev->post_bit_count += post_bit_count;
233 dev->dvbv3_ber = post_bit_error;
234
235 /* restart measurement */
236 utmp |= 0x10;
237 ret = regmap_write(dev->regmap, 0xf8, utmp);
238 if (ret)
239 goto err;
240 }
241 break;
242 case SYS_DVBS2:
243 ret = regmap_bulk_read(dev->regmap, 0xd5, buf, 3);
244 if (ret)
245 goto err;
246
247 utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
248
249 /* enough data? */
250 if (utmp > 4000) {
251 ret = regmap_bulk_read(dev->regmap, 0xf7, buf, 2);
252 if (ret)
253 goto err;
254
255 post_bit_error = buf[1] << 8 | buf[0] << 0;
256 post_bit_count = 32 * utmp; /* TODO: FEC */
257 dev->post_bit_error += post_bit_error;
258 dev->post_bit_count += post_bit_count;
259 dev->dvbv3_ber = post_bit_error;
260
261 /* restart measurement */
262 ret = regmap_write(dev->regmap, 0xd1, 0x01);
263 if (ret)
264 goto err;
265
266 ret = regmap_write(dev->regmap, 0xf9, 0x01);
267 if (ret)
268 goto err;
269
270 ret = regmap_write(dev->regmap, 0xf9, 0x00);
271 if (ret)
272 goto err;
273
274 ret = regmap_write(dev->regmap, 0xd1, 0x00);
275 if (ret)
276 goto err;
277 }
278 break;
279 default:
280 dev_dbg(&client->dev, "invalid delivery_system\n");
281 ret = -EINVAL;
282 goto err;
283 }
284
285 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
286 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
287 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
288 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
289 } else {
290 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
291 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
292 }
293
294 return 0;
295 err:
296 dev_dbg(&client->dev, "failed=%d\n", ret);
297 return ret;
298 }
299
300 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
301 {
302 struct m88ds3103_dev *dev = fe->demodulator_priv;
303 struct i2c_client *client = dev->client;
304 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
305 int ret, len;
306 const struct m88ds3103_reg_val *init;
307 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
308 u8 buf[3];
309 u16 u16tmp, divide_ratio = 0;
310 u32 tuner_frequency, target_mclk;
311 s32 s32tmp;
312
313 dev_dbg(&client->dev,
314 "delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
315 c->delivery_system, c->modulation, c->frequency, c->symbol_rate,
316 c->inversion, c->pilot, c->rolloff);
317
318 if (!dev->warm) {
319 ret = -EAGAIN;
320 goto err;
321 }
322
323 /* reset */
324 ret = regmap_write(dev->regmap, 0x07, 0x80);
325 if (ret)
326 goto err;
327
328 ret = regmap_write(dev->regmap, 0x07, 0x00);
329 if (ret)
330 goto err;
331
332 /* Disable demod clock path */
333 if (dev->chip_id == M88RS6000_CHIP_ID) {
334 ret = regmap_write(dev->regmap, 0x06, 0xe0);
335 if (ret)
336 goto err;
337 }
338
339 /* program tuner */
340 if (fe->ops.tuner_ops.set_params) {
341 ret = fe->ops.tuner_ops.set_params(fe);
342 if (ret)
343 goto err;
344 }
345
346 if (fe->ops.tuner_ops.get_frequency) {
347 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
348 if (ret)
349 goto err;
350 } else {
351 /*
352 * Use nominal target frequency as tuner driver does not provide
353 * actual frequency used. Carrier offset calculation is not
354 * valid.
355 */
356 tuner_frequency = c->frequency;
357 }
358
359 /* select M88RS6000 demod main mclk and ts mclk from tuner die. */
360 if (dev->chip_id == M88RS6000_CHIP_ID) {
361 if (c->symbol_rate > 45010000)
362 dev->mclk_khz = 110250;
363 else
364 dev->mclk_khz = 96000;
365
366 if (c->delivery_system == SYS_DVBS)
367 target_mclk = 96000;
368 else
369 target_mclk = 144000;
370
371 /* Enable demod clock path */
372 ret = regmap_write(dev->regmap, 0x06, 0x00);
373 if (ret)
374 goto err;
375 usleep_range(10000, 20000);
376 } else {
377 /* set M88DS3103 mclk and ts mclk. */
378 dev->mclk_khz = 96000;
379
380 switch (dev->cfg->ts_mode) {
381 case M88DS3103_TS_SERIAL:
382 case M88DS3103_TS_SERIAL_D7:
383 target_mclk = dev->cfg->ts_clk;
384 break;
385 case M88DS3103_TS_PARALLEL:
386 case M88DS3103_TS_CI:
387 if (c->delivery_system == SYS_DVBS)
388 target_mclk = 96000;
389 else {
390 if (c->symbol_rate < 18000000)
391 target_mclk = 96000;
392 else if (c->symbol_rate < 28000000)
393 target_mclk = 144000;
394 else
395 target_mclk = 192000;
396 }
397 break;
398 default:
399 dev_dbg(&client->dev, "invalid ts_mode\n");
400 ret = -EINVAL;
401 goto err;
402 }
403
404 switch (target_mclk) {
405 case 96000:
406 u8tmp1 = 0x02; /* 0b10 */
407 u8tmp2 = 0x01; /* 0b01 */
408 break;
409 case 144000:
410 u8tmp1 = 0x00; /* 0b00 */
411 u8tmp2 = 0x01; /* 0b01 */
412 break;
413 case 192000:
414 u8tmp1 = 0x03; /* 0b11 */
415 u8tmp2 = 0x00; /* 0b00 */
416 break;
417 }
418 ret = m88ds3103_update_bits(dev, 0x22, 0xc0, u8tmp1 << 6);
419 if (ret)
420 goto err;
421 ret = m88ds3103_update_bits(dev, 0x24, 0xc0, u8tmp2 << 6);
422 if (ret)
423 goto err;
424 }
425
426 ret = regmap_write(dev->regmap, 0xb2, 0x01);
427 if (ret)
428 goto err;
429
430 ret = regmap_write(dev->regmap, 0x00, 0x01);
431 if (ret)
432 goto err;
433
434 switch (c->delivery_system) {
435 case SYS_DVBS:
436 if (dev->chip_id == M88RS6000_CHIP_ID) {
437 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
438 init = m88rs6000_dvbs_init_reg_vals;
439 } else {
440 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
441 init = m88ds3103_dvbs_init_reg_vals;
442 }
443 break;
444 case SYS_DVBS2:
445 if (dev->chip_id == M88RS6000_CHIP_ID) {
446 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
447 init = m88rs6000_dvbs2_init_reg_vals;
448 } else {
449 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
450 init = m88ds3103_dvbs2_init_reg_vals;
451 }
452 break;
453 default:
454 dev_dbg(&client->dev, "invalid delivery_system\n");
455 ret = -EINVAL;
456 goto err;
457 }
458
459 /* program init table */
460 if (c->delivery_system != dev->delivery_system) {
461 ret = m88ds3103_wr_reg_val_tab(dev, init, len);
462 if (ret)
463 goto err;
464 }
465
466 if (dev->chip_id == M88RS6000_CHIP_ID) {
467 if ((c->delivery_system == SYS_DVBS2)
468 && ((c->symbol_rate / 1000) <= 5000)) {
469 ret = regmap_write(dev->regmap, 0xc0, 0x04);
470 if (ret)
471 goto err;
472 buf[0] = 0x09;
473 buf[1] = 0x22;
474 buf[2] = 0x88;
475 ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3);
476 if (ret)
477 goto err;
478 }
479 ret = m88ds3103_update_bits(dev, 0x9d, 0x08, 0x08);
480 if (ret)
481 goto err;
482 ret = regmap_write(dev->regmap, 0xf1, 0x01);
483 if (ret)
484 goto err;
485 ret = m88ds3103_update_bits(dev, 0x30, 0x80, 0x80);
486 if (ret)
487 goto err;
488 }
489
490 switch (dev->cfg->ts_mode) {
491 case M88DS3103_TS_SERIAL:
492 u8tmp1 = 0x00;
493 u8tmp = 0x06;
494 break;
495 case M88DS3103_TS_SERIAL_D7:
496 u8tmp1 = 0x20;
497 u8tmp = 0x06;
498 break;
499 case M88DS3103_TS_PARALLEL:
500 u8tmp = 0x02;
501 break;
502 case M88DS3103_TS_CI:
503 u8tmp = 0x03;
504 break;
505 default:
506 dev_dbg(&client->dev, "invalid ts_mode\n");
507 ret = -EINVAL;
508 goto err;
509 }
510
511 if (dev->cfg->ts_clk_pol)
512 u8tmp |= 0x40;
513
514 /* TS mode */
515 ret = regmap_write(dev->regmap, 0xfd, u8tmp);
516 if (ret)
517 goto err;
518
519 switch (dev->cfg->ts_mode) {
520 case M88DS3103_TS_SERIAL:
521 case M88DS3103_TS_SERIAL_D7:
522 ret = m88ds3103_update_bits(dev, 0x29, 0x20, u8tmp1);
523 if (ret)
524 goto err;
525 u8tmp1 = 0;
526 u8tmp2 = 0;
527 break;
528 default:
529 if (dev->cfg->ts_clk) {
530 divide_ratio = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk);
531 u8tmp1 = divide_ratio / 2;
532 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
533 }
534 }
535
536 dev_dbg(&client->dev,
537 "target_mclk=%d ts_clk=%d divide_ratio=%d\n",
538 target_mclk, dev->cfg->ts_clk, divide_ratio);
539
540 u8tmp1--;
541 u8tmp2--;
542 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
543 u8tmp1 &= 0x3f;
544 /* u8tmp2[5:0] => ea[5:0] */
545 u8tmp2 &= 0x3f;
546
547 ret = regmap_bulk_read(dev->regmap, 0xfe, &u8tmp, 1);
548 if (ret)
549 goto err;
550
551 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
552 ret = regmap_write(dev->regmap, 0xfe, u8tmp);
553 if (ret)
554 goto err;
555
556 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
557 ret = regmap_write(dev->regmap, 0xea, u8tmp);
558 if (ret)
559 goto err;
560
561 if (c->symbol_rate <= 3000000)
562 u8tmp = 0x20;
563 else if (c->symbol_rate <= 10000000)
564 u8tmp = 0x10;
565 else
566 u8tmp = 0x06;
567
568 ret = regmap_write(dev->regmap, 0xc3, 0x08);
569 if (ret)
570 goto err;
571
572 ret = regmap_write(dev->regmap, 0xc8, u8tmp);
573 if (ret)
574 goto err;
575
576 ret = regmap_write(dev->regmap, 0xc4, 0x08);
577 if (ret)
578 goto err;
579
580 ret = regmap_write(dev->regmap, 0xc7, 0x00);
581 if (ret)
582 goto err;
583
584 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, dev->mclk_khz / 2);
585 buf[0] = (u16tmp >> 0) & 0xff;
586 buf[1] = (u16tmp >> 8) & 0xff;
587 ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2);
588 if (ret)
589 goto err;
590
591 ret = m88ds3103_update_bits(dev, 0x4d, 0x02, dev->cfg->spec_inv << 1);
592 if (ret)
593 goto err;
594
595 ret = m88ds3103_update_bits(dev, 0x30, 0x10, dev->cfg->agc_inv << 4);
596 if (ret)
597 goto err;
598
599 ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc);
600 if (ret)
601 goto err;
602
603 dev_dbg(&client->dev, "carrier offset=%d\n",
604 (tuner_frequency - c->frequency));
605
606 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
607 s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk_khz);
608 buf[0] = (s32tmp >> 0) & 0xff;
609 buf[1] = (s32tmp >> 8) & 0xff;
610 ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2);
611 if (ret)
612 goto err;
613
614 ret = regmap_write(dev->regmap, 0x00, 0x00);
615 if (ret)
616 goto err;
617
618 ret = regmap_write(dev->regmap, 0xb2, 0x00);
619 if (ret)
620 goto err;
621
622 dev->delivery_system = c->delivery_system;
623
624 return 0;
625 err:
626 dev_dbg(&client->dev, "failed=%d\n", ret);
627 return ret;
628 }
629
630 static int m88ds3103_init(struct dvb_frontend *fe)
631 {
632 struct m88ds3103_dev *dev = fe->demodulator_priv;
633 struct i2c_client *client = dev->client;
634 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
635 int ret, len, remaining;
636 unsigned int utmp;
637 const struct firmware *fw = NULL;
638 u8 *fw_file;
639
640 dev_dbg(&client->dev, "\n");
641
642 /* set cold state by default */
643 dev->warm = false;
644
645 /* wake up device from sleep */
646 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x01);
647 if (ret)
648 goto err;
649 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x00);
650 if (ret)
651 goto err;
652 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x00);
653 if (ret)
654 goto err;
655
656 /* firmware status */
657 ret = regmap_read(dev->regmap, 0xb9, &utmp);
658 if (ret)
659 goto err;
660
661 dev_dbg(&client->dev, "firmware=%02x\n", utmp);
662
663 if (utmp)
664 goto skip_fw_download;
665
666 /* global reset, global diseqc reset, golbal fec reset */
667 ret = regmap_write(dev->regmap, 0x07, 0xe0);
668 if (ret)
669 goto err;
670 ret = regmap_write(dev->regmap, 0x07, 0x00);
671 if (ret)
672 goto err;
673
674 /* cold state - try to download firmware */
675 dev_info(&client->dev, "found a '%s' in cold state\n",
676 m88ds3103_ops.info.name);
677
678 if (dev->chip_id == M88RS6000_CHIP_ID)
679 fw_file = M88RS6000_FIRMWARE;
680 else
681 fw_file = M88DS3103_FIRMWARE;
682 /* request the firmware, this will block and timeout */
683 ret = request_firmware(&fw, fw_file, &client->dev);
684 if (ret) {
685 dev_err(&client->dev, "firmware file '%s' not found\n", fw_file);
686 goto err;
687 }
688
689 dev_info(&client->dev, "downloading firmware from file '%s'\n",
690 fw_file);
691
692 ret = regmap_write(dev->regmap, 0xb2, 0x01);
693 if (ret)
694 goto error_fw_release;
695
696 for (remaining = fw->size; remaining > 0;
697 remaining -= (dev->cfg->i2c_wr_max - 1)) {
698 len = remaining;
699 if (len > (dev->cfg->i2c_wr_max - 1))
700 len = (dev->cfg->i2c_wr_max - 1);
701
702 ret = regmap_bulk_write(dev->regmap, 0xb0,
703 &fw->data[fw->size - remaining], len);
704 if (ret) {
705 dev_err(&client->dev, "firmware download failed=%d\n",
706 ret);
707 goto error_fw_release;
708 }
709 }
710
711 ret = regmap_write(dev->regmap, 0xb2, 0x00);
712 if (ret)
713 goto error_fw_release;
714
715 release_firmware(fw);
716 fw = NULL;
717
718 ret = regmap_read(dev->regmap, 0xb9, &utmp);
719 if (ret)
720 goto err;
721
722 if (!utmp) {
723 dev_info(&client->dev, "firmware did not run\n");
724 ret = -EFAULT;
725 goto err;
726 }
727
728 dev_info(&client->dev, "found a '%s' in warm state\n",
729 m88ds3103_ops.info.name);
730 dev_info(&client->dev, "firmware version: %X.%X\n",
731 (utmp >> 4) & 0xf, (utmp >> 0 & 0xf));
732
733 skip_fw_download:
734 /* warm state */
735 dev->warm = true;
736
737 /* init stats here in order signal app which stats are supported */
738 c->cnr.len = 1;
739 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
740 c->post_bit_error.len = 1;
741 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
742 c->post_bit_count.len = 1;
743 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
744
745 return 0;
746 error_fw_release:
747 release_firmware(fw);
748 err:
749 dev_dbg(&client->dev, "failed=%d\n", ret);
750 return ret;
751 }
752
753 static int m88ds3103_sleep(struct dvb_frontend *fe)
754 {
755 struct m88ds3103_dev *dev = fe->demodulator_priv;
756 struct i2c_client *client = dev->client;
757 int ret;
758 unsigned int utmp;
759
760 dev_dbg(&client->dev, "\n");
761
762 dev->fe_status = 0;
763 dev->delivery_system = SYS_UNDEFINED;
764
765 /* TS Hi-Z */
766 if (dev->chip_id == M88RS6000_CHIP_ID)
767 utmp = 0x29;
768 else
769 utmp = 0x27;
770 ret = m88ds3103_update_bits(dev, utmp, 0x01, 0x00);
771 if (ret)
772 goto err;
773
774 /* sleep */
775 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
776 if (ret)
777 goto err;
778 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
779 if (ret)
780 goto err;
781 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
782 if (ret)
783 goto err;
784
785 return 0;
786 err:
787 dev_dbg(&client->dev, "failed=%d\n", ret);
788 return ret;
789 }
790
791 static int m88ds3103_get_frontend(struct dvb_frontend *fe,
792 struct dtv_frontend_properties *c)
793 {
794 struct m88ds3103_dev *dev = fe->demodulator_priv;
795 struct i2c_client *client = dev->client;
796 int ret;
797 u8 buf[3];
798
799 dev_dbg(&client->dev, "\n");
800
801 if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) {
802 ret = 0;
803 goto err;
804 }
805
806 switch (c->delivery_system) {
807 case SYS_DVBS:
808 ret = regmap_bulk_read(dev->regmap, 0xe0, &buf[0], 1);
809 if (ret)
810 goto err;
811
812 ret = regmap_bulk_read(dev->regmap, 0xe6, &buf[1], 1);
813 if (ret)
814 goto err;
815
816 switch ((buf[0] >> 2) & 0x01) {
817 case 0:
818 c->inversion = INVERSION_OFF;
819 break;
820 case 1:
821 c->inversion = INVERSION_ON;
822 break;
823 }
824
825 switch ((buf[1] >> 5) & 0x07) {
826 case 0:
827 c->fec_inner = FEC_7_8;
828 break;
829 case 1:
830 c->fec_inner = FEC_5_6;
831 break;
832 case 2:
833 c->fec_inner = FEC_3_4;
834 break;
835 case 3:
836 c->fec_inner = FEC_2_3;
837 break;
838 case 4:
839 c->fec_inner = FEC_1_2;
840 break;
841 default:
842 dev_dbg(&client->dev, "invalid fec_inner\n");
843 }
844
845 c->modulation = QPSK;
846
847 break;
848 case SYS_DVBS2:
849 ret = regmap_bulk_read(dev->regmap, 0x7e, &buf[0], 1);
850 if (ret)
851 goto err;
852
853 ret = regmap_bulk_read(dev->regmap, 0x89, &buf[1], 1);
854 if (ret)
855 goto err;
856
857 ret = regmap_bulk_read(dev->regmap, 0xf2, &buf[2], 1);
858 if (ret)
859 goto err;
860
861 switch ((buf[0] >> 0) & 0x0f) {
862 case 2:
863 c->fec_inner = FEC_2_5;
864 break;
865 case 3:
866 c->fec_inner = FEC_1_2;
867 break;
868 case 4:
869 c->fec_inner = FEC_3_5;
870 break;
871 case 5:
872 c->fec_inner = FEC_2_3;
873 break;
874 case 6:
875 c->fec_inner = FEC_3_4;
876 break;
877 case 7:
878 c->fec_inner = FEC_4_5;
879 break;
880 case 8:
881 c->fec_inner = FEC_5_6;
882 break;
883 case 9:
884 c->fec_inner = FEC_8_9;
885 break;
886 case 10:
887 c->fec_inner = FEC_9_10;
888 break;
889 default:
890 dev_dbg(&client->dev, "invalid fec_inner\n");
891 }
892
893 switch ((buf[0] >> 5) & 0x01) {
894 case 0:
895 c->pilot = PILOT_OFF;
896 break;
897 case 1:
898 c->pilot = PILOT_ON;
899 break;
900 }
901
902 switch ((buf[0] >> 6) & 0x07) {
903 case 0:
904 c->modulation = QPSK;
905 break;
906 case 1:
907 c->modulation = PSK_8;
908 break;
909 case 2:
910 c->modulation = APSK_16;
911 break;
912 case 3:
913 c->modulation = APSK_32;
914 break;
915 default:
916 dev_dbg(&client->dev, "invalid modulation\n");
917 }
918
919 switch ((buf[1] >> 7) & 0x01) {
920 case 0:
921 c->inversion = INVERSION_OFF;
922 break;
923 case 1:
924 c->inversion = INVERSION_ON;
925 break;
926 }
927
928 switch ((buf[2] >> 0) & 0x03) {
929 case 0:
930 c->rolloff = ROLLOFF_35;
931 break;
932 case 1:
933 c->rolloff = ROLLOFF_25;
934 break;
935 case 2:
936 c->rolloff = ROLLOFF_20;
937 break;
938 default:
939 dev_dbg(&client->dev, "invalid rolloff\n");
940 }
941 break;
942 default:
943 dev_dbg(&client->dev, "invalid delivery_system\n");
944 ret = -EINVAL;
945 goto err;
946 }
947
948 ret = regmap_bulk_read(dev->regmap, 0x6d, buf, 2);
949 if (ret)
950 goto err;
951
952 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
953 dev->mclk_khz * 1000 / 0x10000;
954
955 return 0;
956 err:
957 dev_dbg(&client->dev, "failed=%d\n", ret);
958 return ret;
959 }
960
961 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
962 {
963 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
964
965 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
966 *snr = div_s64(c->cnr.stat[0].svalue, 100);
967 else
968 *snr = 0;
969
970 return 0;
971 }
972
973 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
974 {
975 struct m88ds3103_dev *dev = fe->demodulator_priv;
976
977 *ber = dev->dvbv3_ber;
978
979 return 0;
980 }
981
982 static int m88ds3103_set_tone(struct dvb_frontend *fe,
983 enum fe_sec_tone_mode fe_sec_tone_mode)
984 {
985 struct m88ds3103_dev *dev = fe->demodulator_priv;
986 struct i2c_client *client = dev->client;
987 int ret;
988 unsigned int utmp, tone, reg_a1_mask;
989
990 dev_dbg(&client->dev, "fe_sec_tone_mode=%d\n", fe_sec_tone_mode);
991
992 if (!dev->warm) {
993 ret = -EAGAIN;
994 goto err;
995 }
996
997 switch (fe_sec_tone_mode) {
998 case SEC_TONE_ON:
999 tone = 0;
1000 reg_a1_mask = 0x47;
1001 break;
1002 case SEC_TONE_OFF:
1003 tone = 1;
1004 reg_a1_mask = 0x00;
1005 break;
1006 default:
1007 dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n");
1008 ret = -EINVAL;
1009 goto err;
1010 }
1011
1012 utmp = tone << 7 | dev->cfg->envelope_mode << 5;
1013 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1014 if (ret)
1015 goto err;
1016
1017 utmp = 1 << 2;
1018 ret = m88ds3103_update_bits(dev, 0xa1, reg_a1_mask, utmp);
1019 if (ret)
1020 goto err;
1021
1022 return 0;
1023 err:
1024 dev_dbg(&client->dev, "failed=%d\n", ret);
1025 return ret;
1026 }
1027
1028 static int m88ds3103_set_voltage(struct dvb_frontend *fe,
1029 enum fe_sec_voltage fe_sec_voltage)
1030 {
1031 struct m88ds3103_dev *dev = fe->demodulator_priv;
1032 struct i2c_client *client = dev->client;
1033 int ret;
1034 unsigned int utmp;
1035 bool voltage_sel, voltage_dis;
1036
1037 dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage);
1038
1039 if (!dev->warm) {
1040 ret = -EAGAIN;
1041 goto err;
1042 }
1043
1044 switch (fe_sec_voltage) {
1045 case SEC_VOLTAGE_18:
1046 voltage_sel = true;
1047 voltage_dis = false;
1048 break;
1049 case SEC_VOLTAGE_13:
1050 voltage_sel = false;
1051 voltage_dis = false;
1052 break;
1053 case SEC_VOLTAGE_OFF:
1054 voltage_sel = false;
1055 voltage_dis = true;
1056 break;
1057 default:
1058 dev_dbg(&client->dev, "invalid fe_sec_voltage\n");
1059 ret = -EINVAL;
1060 goto err;
1061 }
1062
1063 /* output pin polarity */
1064 voltage_sel ^= dev->cfg->lnb_hv_pol;
1065 voltage_dis ^= dev->cfg->lnb_en_pol;
1066
1067 utmp = voltage_dis << 1 | voltage_sel << 0;
1068 ret = m88ds3103_update_bits(dev, 0xa2, 0x03, utmp);
1069 if (ret)
1070 goto err;
1071
1072 return 0;
1073 err:
1074 dev_dbg(&client->dev, "failed=%d\n", ret);
1075 return ret;
1076 }
1077
1078 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1079 struct dvb_diseqc_master_cmd *diseqc_cmd)
1080 {
1081 struct m88ds3103_dev *dev = fe->demodulator_priv;
1082 struct i2c_client *client = dev->client;
1083 int ret;
1084 unsigned int utmp;
1085 unsigned long timeout;
1086
1087 dev_dbg(&client->dev, "msg=%*ph\n",
1088 diseqc_cmd->msg_len, diseqc_cmd->msg);
1089
1090 if (!dev->warm) {
1091 ret = -EAGAIN;
1092 goto err;
1093 }
1094
1095 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1096 ret = -EINVAL;
1097 goto err;
1098 }
1099
1100 utmp = dev->cfg->envelope_mode << 5;
1101 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1102 if (ret)
1103 goto err;
1104
1105 ret = regmap_bulk_write(dev->regmap, 0xa3, diseqc_cmd->msg,
1106 diseqc_cmd->msg_len);
1107 if (ret)
1108 goto err;
1109
1110 ret = regmap_write(dev->regmap, 0xa1,
1111 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1112 if (ret)
1113 goto err;
1114
1115 /* wait DiSEqC TX ready */
1116 #define SEND_MASTER_CMD_TIMEOUT 120
1117 timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT);
1118
1119 /* DiSEqC message period is 13.5 ms per byte */
1120 utmp = diseqc_cmd->msg_len * 13500;
1121 usleep_range(utmp - 4000, utmp);
1122
1123 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1124 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1125 if (ret)
1126 goto err;
1127 utmp = (utmp >> 6) & 0x1;
1128 }
1129
1130 if (utmp == 0) {
1131 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1132 jiffies_to_msecs(jiffies) -
1133 (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT));
1134 } else {
1135 dev_dbg(&client->dev, "diseqc tx timeout\n");
1136
1137 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1138 if (ret)
1139 goto err;
1140 }
1141
1142 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1143 if (ret)
1144 goto err;
1145
1146 if (utmp == 1) {
1147 ret = -ETIMEDOUT;
1148 goto err;
1149 }
1150
1151 return 0;
1152 err:
1153 dev_dbg(&client->dev, "failed=%d\n", ret);
1154 return ret;
1155 }
1156
1157 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1158 enum fe_sec_mini_cmd fe_sec_mini_cmd)
1159 {
1160 struct m88ds3103_dev *dev = fe->demodulator_priv;
1161 struct i2c_client *client = dev->client;
1162 int ret;
1163 unsigned int utmp, burst;
1164 unsigned long timeout;
1165
1166 dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd);
1167
1168 if (!dev->warm) {
1169 ret = -EAGAIN;
1170 goto err;
1171 }
1172
1173 utmp = dev->cfg->envelope_mode << 5;
1174 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1175 if (ret)
1176 goto err;
1177
1178 switch (fe_sec_mini_cmd) {
1179 case SEC_MINI_A:
1180 burst = 0x02;
1181 break;
1182 case SEC_MINI_B:
1183 burst = 0x01;
1184 break;
1185 default:
1186 dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n");
1187 ret = -EINVAL;
1188 goto err;
1189 }
1190
1191 ret = regmap_write(dev->regmap, 0xa1, burst);
1192 if (ret)
1193 goto err;
1194
1195 /* wait DiSEqC TX ready */
1196 #define SEND_BURST_TIMEOUT 40
1197 timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT);
1198
1199 /* DiSEqC ToneBurst period is 12.5 ms */
1200 usleep_range(8500, 12500);
1201
1202 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1203 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1204 if (ret)
1205 goto err;
1206 utmp = (utmp >> 6) & 0x1;
1207 }
1208
1209 if (utmp == 0) {
1210 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1211 jiffies_to_msecs(jiffies) -
1212 (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT));
1213 } else {
1214 dev_dbg(&client->dev, "diseqc tx timeout\n");
1215
1216 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1217 if (ret)
1218 goto err;
1219 }
1220
1221 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1222 if (ret)
1223 goto err;
1224
1225 if (utmp == 1) {
1226 ret = -ETIMEDOUT;
1227 goto err;
1228 }
1229
1230 return 0;
1231 err:
1232 dev_dbg(&client->dev, "failed=%d\n", ret);
1233 return ret;
1234 }
1235
1236 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1237 struct dvb_frontend_tune_settings *s)
1238 {
1239 s->min_delay_ms = 3000;
1240
1241 return 0;
1242 }
1243
1244 static void m88ds3103_release(struct dvb_frontend *fe)
1245 {
1246 struct m88ds3103_dev *dev = fe->demodulator_priv;
1247 struct i2c_client *client = dev->client;
1248
1249 i2c_unregister_device(client);
1250 }
1251
1252 static int m88ds3103_select(struct i2c_mux_core *muxc, u32 chan)
1253 {
1254 struct m88ds3103_dev *dev = i2c_mux_priv(muxc);
1255 struct i2c_client *client = dev->client;
1256 int ret;
1257 struct i2c_msg msg = {
1258 .addr = client->addr,
1259 .flags = 0,
1260 .len = 2,
1261 .buf = "\x03\x11",
1262 };
1263
1264 /* Open tuner I2C repeater for 1 xfer, closes automatically */
1265 ret = __i2c_transfer(client->adapter, &msg, 1);
1266 if (ret != 1) {
1267 dev_warn(&client->dev, "i2c wr failed=%d\n", ret);
1268 if (ret >= 0)
1269 ret = -EREMOTEIO;
1270 return ret;
1271 }
1272
1273 return 0;
1274 }
1275
1276 /*
1277 * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide
1278 * proper I2C client for legacy media attach binding.
1279 * New users must use I2C client binding directly!
1280 */
1281 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1282 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1283 {
1284 struct i2c_client *client;
1285 struct i2c_board_info board_info;
1286 struct m88ds3103_platform_data pdata;
1287
1288 pdata.clk = cfg->clock;
1289 pdata.i2c_wr_max = cfg->i2c_wr_max;
1290 pdata.ts_mode = cfg->ts_mode;
1291 pdata.ts_clk = cfg->ts_clk;
1292 pdata.ts_clk_pol = cfg->ts_clk_pol;
1293 pdata.spec_inv = cfg->spec_inv;
1294 pdata.agc = cfg->agc;
1295 pdata.agc_inv = cfg->agc_inv;
1296 pdata.clk_out = cfg->clock_out;
1297 pdata.envelope_mode = cfg->envelope_mode;
1298 pdata.lnb_hv_pol = cfg->lnb_hv_pol;
1299 pdata.lnb_en_pol = cfg->lnb_en_pol;
1300 pdata.attach_in_use = true;
1301
1302 memset(&board_info, 0, sizeof(board_info));
1303 strlcpy(board_info.type, "m88ds3103", I2C_NAME_SIZE);
1304 board_info.addr = cfg->i2c_addr;
1305 board_info.platform_data = &pdata;
1306 client = i2c_new_device(i2c, &board_info);
1307 if (!client || !client->dev.driver)
1308 return NULL;
1309
1310 *tuner_i2c_adapter = pdata.get_i2c_adapter(client);
1311 return pdata.get_dvb_frontend(client);
1312 }
1313 EXPORT_SYMBOL(m88ds3103_attach);
1314
1315 static struct dvb_frontend_ops m88ds3103_ops = {
1316 .delsys = {SYS_DVBS, SYS_DVBS2},
1317 .info = {
1318 .name = "Montage Technology M88DS3103",
1319 .frequency_min = 950000,
1320 .frequency_max = 2150000,
1321 .frequency_tolerance = 5000,
1322 .symbol_rate_min = 1000000,
1323 .symbol_rate_max = 45000000,
1324 .caps = FE_CAN_INVERSION_AUTO |
1325 FE_CAN_FEC_1_2 |
1326 FE_CAN_FEC_2_3 |
1327 FE_CAN_FEC_3_4 |
1328 FE_CAN_FEC_4_5 |
1329 FE_CAN_FEC_5_6 |
1330 FE_CAN_FEC_6_7 |
1331 FE_CAN_FEC_7_8 |
1332 FE_CAN_FEC_8_9 |
1333 FE_CAN_FEC_AUTO |
1334 FE_CAN_QPSK |
1335 FE_CAN_RECOVER |
1336 FE_CAN_2G_MODULATION
1337 },
1338
1339 .release = m88ds3103_release,
1340
1341 .get_tune_settings = m88ds3103_get_tune_settings,
1342
1343 .init = m88ds3103_init,
1344 .sleep = m88ds3103_sleep,
1345
1346 .set_frontend = m88ds3103_set_frontend,
1347 .get_frontend = m88ds3103_get_frontend,
1348
1349 .read_status = m88ds3103_read_status,
1350 .read_snr = m88ds3103_read_snr,
1351 .read_ber = m88ds3103_read_ber,
1352
1353 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1354 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1355
1356 .set_tone = m88ds3103_set_tone,
1357 .set_voltage = m88ds3103_set_voltage,
1358 };
1359
1360 static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client)
1361 {
1362 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1363
1364 dev_dbg(&client->dev, "\n");
1365
1366 return &dev->fe;
1367 }
1368
1369 static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client)
1370 {
1371 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1372
1373 dev_dbg(&client->dev, "\n");
1374
1375 return dev->muxc->adapter[0];
1376 }
1377
1378 static int m88ds3103_probe(struct i2c_client *client,
1379 const struct i2c_device_id *id)
1380 {
1381 struct m88ds3103_dev *dev;
1382 struct m88ds3103_platform_data *pdata = client->dev.platform_data;
1383 int ret;
1384 unsigned int utmp;
1385
1386 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1387 if (!dev) {
1388 ret = -ENOMEM;
1389 goto err;
1390 }
1391
1392 dev->client = client;
1393 dev->config.clock = pdata->clk;
1394 dev->config.i2c_wr_max = pdata->i2c_wr_max;
1395 dev->config.ts_mode = pdata->ts_mode;
1396 dev->config.ts_clk = pdata->ts_clk;
1397 dev->config.ts_clk_pol = pdata->ts_clk_pol;
1398 dev->config.spec_inv = pdata->spec_inv;
1399 dev->config.agc_inv = pdata->agc_inv;
1400 dev->config.clock_out = pdata->clk_out;
1401 dev->config.envelope_mode = pdata->envelope_mode;
1402 dev->config.agc = pdata->agc;
1403 dev->config.lnb_hv_pol = pdata->lnb_hv_pol;
1404 dev->config.lnb_en_pol = pdata->lnb_en_pol;
1405 dev->cfg = &dev->config;
1406 /* create regmap */
1407 dev->regmap_config.reg_bits = 8,
1408 dev->regmap_config.val_bits = 8,
1409 dev->regmap_config.lock_arg = dev,
1410 dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config);
1411 if (IS_ERR(dev->regmap)) {
1412 ret = PTR_ERR(dev->regmap);
1413 goto err_kfree;
1414 }
1415
1416 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
1417 ret = regmap_read(dev->regmap, 0x00, &utmp);
1418 if (ret)
1419 goto err_kfree;
1420
1421 dev->chip_id = utmp >> 1;
1422 dev_dbg(&client->dev, "chip_id=%02x\n", dev->chip_id);
1423
1424 switch (dev->chip_id) {
1425 case M88RS6000_CHIP_ID:
1426 case M88DS3103_CHIP_ID:
1427 break;
1428 default:
1429 goto err_kfree;
1430 }
1431
1432 switch (dev->cfg->clock_out) {
1433 case M88DS3103_CLOCK_OUT_DISABLED:
1434 utmp = 0x80;
1435 break;
1436 case M88DS3103_CLOCK_OUT_ENABLED:
1437 utmp = 0x00;
1438 break;
1439 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1440 utmp = 0x10;
1441 break;
1442 default:
1443 ret = -EINVAL;
1444 goto err_kfree;
1445 }
1446
1447 /* 0x29 register is defined differently for m88rs6000. */
1448 /* set internal tuner address to 0x21 */
1449 if (dev->chip_id == M88RS6000_CHIP_ID)
1450 utmp = 0x00;
1451
1452 ret = regmap_write(dev->regmap, 0x29, utmp);
1453 if (ret)
1454 goto err_kfree;
1455
1456 /* sleep */
1457 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
1458 if (ret)
1459 goto err_kfree;
1460 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
1461 if (ret)
1462 goto err_kfree;
1463 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
1464 if (ret)
1465 goto err_kfree;
1466
1467 /* create mux i2c adapter for tuner */
1468 dev->muxc = i2c_mux_alloc(client->adapter, &client->dev, 1, 0, 0,
1469 m88ds3103_select, NULL);
1470 if (!dev->muxc) {
1471 ret = -ENOMEM;
1472 goto err_kfree;
1473 }
1474 dev->muxc->priv = dev;
1475 ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
1476 if (ret)
1477 goto err_kfree;
1478
1479 /* create dvb_frontend */
1480 memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1481 if (dev->chip_id == M88RS6000_CHIP_ID)
1482 strncpy(dev->fe.ops.info.name, "Montage Technology M88RS6000",
1483 sizeof(dev->fe.ops.info.name));
1484 if (!pdata->attach_in_use)
1485 dev->fe.ops.release = NULL;
1486 dev->fe.demodulator_priv = dev;
1487 i2c_set_clientdata(client, dev);
1488
1489 /* setup callbacks */
1490 pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend;
1491 pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter;
1492 return 0;
1493 err_kfree:
1494 kfree(dev);
1495 err:
1496 dev_dbg(&client->dev, "failed=%d\n", ret);
1497 return ret;
1498 }
1499
1500 static int m88ds3103_remove(struct i2c_client *client)
1501 {
1502 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1503
1504 dev_dbg(&client->dev, "\n");
1505
1506 i2c_mux_del_adapters(dev->muxc);
1507
1508 kfree(dev);
1509 return 0;
1510 }
1511
1512 static const struct i2c_device_id m88ds3103_id_table[] = {
1513 {"m88ds3103", 0},
1514 {}
1515 };
1516 MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table);
1517
1518 static struct i2c_driver m88ds3103_driver = {
1519 .driver = {
1520 .name = "m88ds3103",
1521 .suppress_bind_attrs = true,
1522 },
1523 .probe = m88ds3103_probe,
1524 .remove = m88ds3103_remove,
1525 .id_table = m88ds3103_id_table,
1526 };
1527
1528 module_i2c_driver(m88ds3103_driver);
1529
1530 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1531 MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver");
1532 MODULE_LICENSE("GPL");
1533 MODULE_FIRMWARE(M88DS3103_FIRMWARE);
1534 MODULE_FIRMWARE(M88RS6000_FIRMWARE);
Linux kernel - Deliverables
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