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[media] rtl2832: remove exported resources
[deliverable/linux.git] / drivers / media / dvb-frontends / rtl2832.c
1 /*
2 * Realtek RTL2832 DVB-T demodulator driver
3 *
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21 #include "rtl2832_priv.h"
22 #include "dvb_math.h"
23 #include <linux/bitops.h>
24
25 /* Max transfer size done by I2C transfer functions */
26 #define MAX_XFER_SIZE 64
27 #define REG_MASK(b) (BIT(b + 1) - 1)
28
29 static const struct rtl2832_reg_entry registers[] = {
30 [DVBT_SOFT_RST] = {0x1, 0x1, 2, 2},
31 [DVBT_IIC_REPEAT] = {0x1, 0x1, 3, 3},
32 [DVBT_TR_WAIT_MIN_8K] = {0x1, 0x88, 11, 2},
33 [DVBT_RSD_BER_FAIL_VAL] = {0x1, 0x8f, 15, 0},
34 [DVBT_EN_BK_TRK] = {0x1, 0xa6, 7, 7},
35 [DVBT_AD_EN_REG] = {0x0, 0x8, 7, 7},
36 [DVBT_AD_EN_REG1] = {0x0, 0x8, 6, 6},
37 [DVBT_EN_BBIN] = {0x1, 0xb1, 0, 0},
38 [DVBT_MGD_THD0] = {0x1, 0x95, 7, 0},
39 [DVBT_MGD_THD1] = {0x1, 0x96, 7, 0},
40 [DVBT_MGD_THD2] = {0x1, 0x97, 7, 0},
41 [DVBT_MGD_THD3] = {0x1, 0x98, 7, 0},
42 [DVBT_MGD_THD4] = {0x1, 0x99, 7, 0},
43 [DVBT_MGD_THD5] = {0x1, 0x9a, 7, 0},
44 [DVBT_MGD_THD6] = {0x1, 0x9b, 7, 0},
45 [DVBT_MGD_THD7] = {0x1, 0x9c, 7, 0},
46 [DVBT_EN_CACQ_NOTCH] = {0x1, 0x61, 4, 4},
47 [DVBT_AD_AV_REF] = {0x0, 0x9, 6, 0},
48 [DVBT_REG_PI] = {0x0, 0xa, 2, 0},
49 [DVBT_PIP_ON] = {0x0, 0x21, 3, 3},
50 [DVBT_SCALE1_B92] = {0x2, 0x92, 7, 0},
51 [DVBT_SCALE1_B93] = {0x2, 0x93, 7, 0},
52 [DVBT_SCALE1_BA7] = {0x2, 0xa7, 7, 0},
53 [DVBT_SCALE1_BA9] = {0x2, 0xa9, 7, 0},
54 [DVBT_SCALE1_BAA] = {0x2, 0xaa, 7, 0},
55 [DVBT_SCALE1_BAB] = {0x2, 0xab, 7, 0},
56 [DVBT_SCALE1_BAC] = {0x2, 0xac, 7, 0},
57 [DVBT_SCALE1_BB0] = {0x2, 0xb0, 7, 0},
58 [DVBT_SCALE1_BB1] = {0x2, 0xb1, 7, 0},
59 [DVBT_KB_P1] = {0x1, 0x64, 3, 1},
60 [DVBT_KB_P2] = {0x1, 0x64, 6, 4},
61 [DVBT_KB_P3] = {0x1, 0x65, 2, 0},
62 [DVBT_OPT_ADC_IQ] = {0x0, 0x6, 5, 4},
63 [DVBT_AD_AVI] = {0x0, 0x9, 1, 0},
64 [DVBT_AD_AVQ] = {0x0, 0x9, 3, 2},
65 [DVBT_K1_CR_STEP12] = {0x2, 0xad, 9, 4},
66 [DVBT_TRK_KS_P2] = {0x1, 0x6f, 2, 0},
67 [DVBT_TRK_KS_I2] = {0x1, 0x70, 5, 3},
68 [DVBT_TR_THD_SET2] = {0x1, 0x72, 3, 0},
69 [DVBT_TRK_KC_P2] = {0x1, 0x73, 5, 3},
70 [DVBT_TRK_KC_I2] = {0x1, 0x75, 2, 0},
71 [DVBT_CR_THD_SET2] = {0x1, 0x76, 7, 6},
72 [DVBT_PSET_IFFREQ] = {0x1, 0x19, 21, 0},
73 [DVBT_SPEC_INV] = {0x1, 0x15, 0, 0},
74 [DVBT_RSAMP_RATIO] = {0x1, 0x9f, 27, 2},
75 [DVBT_CFREQ_OFF_RATIO] = {0x1, 0x9d, 23, 4},
76 [DVBT_FSM_STAGE] = {0x3, 0x51, 6, 3},
77 [DVBT_RX_CONSTEL] = {0x3, 0x3c, 3, 2},
78 [DVBT_RX_HIER] = {0x3, 0x3c, 6, 4},
79 [DVBT_RX_C_RATE_LP] = {0x3, 0x3d, 2, 0},
80 [DVBT_RX_C_RATE_HP] = {0x3, 0x3d, 5, 3},
81 [DVBT_GI_IDX] = {0x3, 0x51, 1, 0},
82 [DVBT_FFT_MODE_IDX] = {0x3, 0x51, 2, 2},
83 [DVBT_RSD_BER_EST] = {0x3, 0x4e, 15, 0},
84 [DVBT_CE_EST_EVM] = {0x4, 0xc, 15, 0},
85 [DVBT_RF_AGC_VAL] = {0x3, 0x5b, 13, 0},
86 [DVBT_IF_AGC_VAL] = {0x3, 0x59, 13, 0},
87 [DVBT_DAGC_VAL] = {0x3, 0x5, 7, 0},
88 [DVBT_SFREQ_OFF] = {0x3, 0x18, 13, 0},
89 [DVBT_CFREQ_OFF] = {0x3, 0x5f, 17, 0},
90 [DVBT_POLAR_RF_AGC] = {0x0, 0xe, 1, 1},
91 [DVBT_POLAR_IF_AGC] = {0x0, 0xe, 0, 0},
92 [DVBT_AAGC_HOLD] = {0x1, 0x4, 5, 5},
93 [DVBT_EN_RF_AGC] = {0x1, 0x4, 6, 6},
94 [DVBT_EN_IF_AGC] = {0x1, 0x4, 7, 7},
95 [DVBT_IF_AGC_MIN] = {0x1, 0x8, 7, 0},
96 [DVBT_IF_AGC_MAX] = {0x1, 0x9, 7, 0},
97 [DVBT_RF_AGC_MIN] = {0x1, 0xa, 7, 0},
98 [DVBT_RF_AGC_MAX] = {0x1, 0xb, 7, 0},
99 [DVBT_IF_AGC_MAN] = {0x1, 0xc, 6, 6},
100 [DVBT_IF_AGC_MAN_VAL] = {0x1, 0xc, 13, 0},
101 [DVBT_RF_AGC_MAN] = {0x1, 0xe, 6, 6},
102 [DVBT_RF_AGC_MAN_VAL] = {0x1, 0xe, 13, 0},
103 [DVBT_DAGC_TRG_VAL] = {0x1, 0x12, 7, 0},
104 [DVBT_AGC_TARG_VAL_0] = {0x1, 0x2, 0, 0},
105 [DVBT_AGC_TARG_VAL_8_1] = {0x1, 0x3, 7, 0},
106 [DVBT_AAGC_LOOP_GAIN] = {0x1, 0xc7, 5, 1},
107 [DVBT_LOOP_GAIN2_3_0] = {0x1, 0x4, 4, 1},
108 [DVBT_LOOP_GAIN2_4] = {0x1, 0x5, 7, 7},
109 [DVBT_LOOP_GAIN3] = {0x1, 0xc8, 4, 0},
110 [DVBT_VTOP1] = {0x1, 0x6, 5, 0},
111 [DVBT_VTOP2] = {0x1, 0xc9, 5, 0},
112 [DVBT_VTOP3] = {0x1, 0xca, 5, 0},
113 [DVBT_KRF1] = {0x1, 0xcb, 7, 0},
114 [DVBT_KRF2] = {0x1, 0x7, 7, 0},
115 [DVBT_KRF3] = {0x1, 0xcd, 7, 0},
116 [DVBT_KRF4] = {0x1, 0xce, 7, 0},
117 [DVBT_EN_GI_PGA] = {0x1, 0xe5, 0, 0},
118 [DVBT_THD_LOCK_UP] = {0x1, 0xd9, 8, 0},
119 [DVBT_THD_LOCK_DW] = {0x1, 0xdb, 8, 0},
120 [DVBT_THD_UP1] = {0x1, 0xdd, 7, 0},
121 [DVBT_THD_DW1] = {0x1, 0xde, 7, 0},
122 [DVBT_INTER_CNT_LEN] = {0x1, 0xd8, 3, 0},
123 [DVBT_GI_PGA_STATE] = {0x1, 0xe6, 3, 3},
124 [DVBT_EN_AGC_PGA] = {0x1, 0xd7, 0, 0},
125 [DVBT_CKOUTPAR] = {0x1, 0x7b, 5, 5},
126 [DVBT_CKOUT_PWR] = {0x1, 0x7b, 6, 6},
127 [DVBT_SYNC_DUR] = {0x1, 0x7b, 7, 7},
128 [DVBT_ERR_DUR] = {0x1, 0x7c, 0, 0},
129 [DVBT_SYNC_LVL] = {0x1, 0x7c, 1, 1},
130 [DVBT_ERR_LVL] = {0x1, 0x7c, 2, 2},
131 [DVBT_VAL_LVL] = {0x1, 0x7c, 3, 3},
132 [DVBT_SERIAL] = {0x1, 0x7c, 4, 4},
133 [DVBT_SER_LSB] = {0x1, 0x7c, 5, 5},
134 [DVBT_CDIV_PH0] = {0x1, 0x7d, 3, 0},
135 [DVBT_CDIV_PH1] = {0x1, 0x7d, 7, 4},
136 [DVBT_MPEG_IO_OPT_2_2] = {0x0, 0x6, 7, 7},
137 [DVBT_MPEG_IO_OPT_1_0] = {0x0, 0x7, 7, 6},
138 [DVBT_CKOUTPAR_PIP] = {0x0, 0xb7, 4, 4},
139 [DVBT_CKOUT_PWR_PIP] = {0x0, 0xb7, 3, 3},
140 [DVBT_SYNC_LVL_PIP] = {0x0, 0xb7, 2, 2},
141 [DVBT_ERR_LVL_PIP] = {0x0, 0xb7, 1, 1},
142 [DVBT_VAL_LVL_PIP] = {0x0, 0xb7, 0, 0},
143 [DVBT_CKOUTPAR_PID] = {0x0, 0xb9, 4, 4},
144 [DVBT_CKOUT_PWR_PID] = {0x0, 0xb9, 3, 3},
145 [DVBT_SYNC_LVL_PID] = {0x0, 0xb9, 2, 2},
146 [DVBT_ERR_LVL_PID] = {0x0, 0xb9, 1, 1},
147 [DVBT_VAL_LVL_PID] = {0x0, 0xb9, 0, 0},
148 [DVBT_SM_PASS] = {0x1, 0x93, 11, 0},
149 [DVBT_AD7_SETTING] = {0x0, 0x11, 15, 0},
150 [DVBT_RSSI_R] = {0x3, 0x1, 6, 0},
151 [DVBT_ACI_DET_IND] = {0x3, 0x12, 0, 0},
152 [DVBT_REG_MON] = {0x0, 0xd, 1, 0},
153 [DVBT_REG_MONSEL] = {0x0, 0xd, 2, 2},
154 [DVBT_REG_GPE] = {0x0, 0xd, 7, 7},
155 [DVBT_REG_GPO] = {0x0, 0x10, 0, 0},
156 [DVBT_REG_4MSEL] = {0x0, 0x13, 0, 0},
157 };
158
159 /* write multiple hardware registers */
160 static int rtl2832_wr(struct rtl2832_priv *priv, u8 reg, u8 *val, int len)
161 {
162 int ret;
163 u8 buf[MAX_XFER_SIZE];
164 struct i2c_msg msg[1] = {
165 {
166 .addr = priv->cfg.i2c_addr,
167 .flags = 0,
168 .len = 1 + len,
169 .buf = buf,
170 }
171 };
172
173 if (1 + len > sizeof(buf)) {
174 dev_warn(&priv->i2c->dev,
175 "%s: i2c wr reg=%04x: len=%d is too big!\n",
176 KBUILD_MODNAME, reg, len);
177 return -EINVAL;
178 }
179
180 buf[0] = reg;
181 memcpy(&buf[1], val, len);
182
183 ret = i2c_transfer(priv->i2c_adapter, msg, 1);
184 if (ret == 1) {
185 ret = 0;
186 } else {
187 dev_warn(&priv->i2c->dev,
188 "%s: i2c wr failed=%d reg=%02x len=%d\n",
189 KBUILD_MODNAME, ret, reg, len);
190 ret = -EREMOTEIO;
191 }
192 return ret;
193 }
194
195 /* read multiple hardware registers */
196 static int rtl2832_rd(struct rtl2832_priv *priv, u8 reg, u8 *val, int len)
197 {
198 int ret;
199 struct i2c_msg msg[2] = {
200 {
201 .addr = priv->cfg.i2c_addr,
202 .flags = 0,
203 .len = 1,
204 .buf = &reg,
205 }, {
206 .addr = priv->cfg.i2c_addr,
207 .flags = I2C_M_RD,
208 .len = len,
209 .buf = val,
210 }
211 };
212
213 ret = i2c_transfer(priv->i2c_adapter, msg, 2);
214 if (ret == 2) {
215 ret = 0;
216 } else {
217 dev_warn(&priv->i2c->dev,
218 "%s: i2c rd failed=%d reg=%02x len=%d\n",
219 KBUILD_MODNAME, ret, reg, len);
220 ret = -EREMOTEIO;
221 }
222 return ret;
223 }
224
225 /* write multiple registers */
226 static int rtl2832_wr_regs(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val,
227 int len)
228 {
229 int ret;
230
231 /* switch bank if needed */
232 if (page != priv->page) {
233 ret = rtl2832_wr(priv, 0x00, &page, 1);
234 if (ret)
235 return ret;
236
237 priv->page = page;
238 }
239
240 return rtl2832_wr(priv, reg, val, len);
241 }
242
243 /* read multiple registers */
244 static int rtl2832_rd_regs(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val,
245 int len)
246 {
247 int ret;
248
249 /* switch bank if needed */
250 if (page != priv->page) {
251 ret = rtl2832_wr(priv, 0x00, &page, 1);
252 if (ret)
253 return ret;
254
255 priv->page = page;
256 }
257
258 return rtl2832_rd(priv, reg, val, len);
259 }
260
261 /* write single register */
262 static int rtl2832_wr_reg(struct rtl2832_priv *priv, u8 reg, u8 page, u8 val)
263 {
264 return rtl2832_wr_regs(priv, reg, page, &val, 1);
265 }
266
267 /* read single register */
268 static int rtl2832_rd_reg(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val)
269 {
270 return rtl2832_rd_regs(priv, reg, page, val, 1);
271 }
272
273 static int rtl2832_rd_demod_reg(struct rtl2832_priv *priv, int reg, u32 *val)
274 {
275 int ret;
276
277 u8 reg_start_addr;
278 u8 msb, lsb;
279 u8 page;
280 u8 reading[4];
281 u32 reading_tmp;
282 int i;
283
284 u8 len;
285 u32 mask;
286
287 reg_start_addr = registers[reg].start_address;
288 msb = registers[reg].msb;
289 lsb = registers[reg].lsb;
290 page = registers[reg].page;
291
292 len = (msb >> 3) + 1;
293 mask = REG_MASK(msb - lsb);
294
295 ret = rtl2832_rd_regs(priv, reg_start_addr, page, &reading[0], len);
296 if (ret)
297 goto err;
298
299 reading_tmp = 0;
300 for (i = 0; i < len; i++)
301 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
302
303 *val = (reading_tmp >> lsb) & mask;
304
305 return ret;
306
307 err:
308 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
309 return ret;
310
311 }
312
313 static int rtl2832_wr_demod_reg(struct rtl2832_priv *priv, int reg, u32 val)
314 {
315 int ret, i;
316 u8 len;
317 u8 reg_start_addr;
318 u8 msb, lsb;
319 u8 page;
320 u32 mask;
321
322
323 u8 reading[4];
324 u8 writing[4];
325 u32 reading_tmp;
326 u32 writing_tmp;
327
328
329 reg_start_addr = registers[reg].start_address;
330 msb = registers[reg].msb;
331 lsb = registers[reg].lsb;
332 page = registers[reg].page;
333
334 len = (msb >> 3) + 1;
335 mask = REG_MASK(msb - lsb);
336
337
338 ret = rtl2832_rd_regs(priv, reg_start_addr, page, &reading[0], len);
339 if (ret)
340 goto err;
341
342 reading_tmp = 0;
343 for (i = 0; i < len; i++)
344 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
345
346 writing_tmp = reading_tmp & ~(mask << lsb);
347 writing_tmp |= ((val & mask) << lsb);
348
349
350 for (i = 0; i < len; i++)
351 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
352
353 ret = rtl2832_wr_regs(priv, reg_start_addr, page, &writing[0], len);
354 if (ret)
355 goto err;
356
357 return ret;
358
359 err:
360 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
361 return ret;
362
363 }
364
365 static int rtl2832_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
366 {
367 int ret;
368 struct rtl2832_priv *priv = fe->demodulator_priv;
369
370 dev_dbg(&priv->i2c->dev, "%s: enable=%d\n", __func__, enable);
371
372 /* gate already open or close */
373 if (priv->i2c_gate_state == enable)
374 return 0;
375
376 ret = rtl2832_wr_demod_reg(priv, DVBT_IIC_REPEAT, (enable ? 0x1 : 0x0));
377 if (ret)
378 goto err;
379
380 priv->i2c_gate_state = enable;
381
382 return ret;
383 err:
384 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
385 return ret;
386 }
387
388
389 static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
390 {
391 struct rtl2832_priv *priv = fe->demodulator_priv;
392 int ret;
393 u64 pset_iffreq;
394 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
395
396 /*
397 * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
398 * / CrystalFreqHz)
399 */
400
401 pset_iffreq = if_freq % priv->cfg.xtal;
402 pset_iffreq *= 0x400000;
403 pset_iffreq = div_u64(pset_iffreq, priv->cfg.xtal);
404 pset_iffreq = -pset_iffreq;
405 pset_iffreq = pset_iffreq & 0x3fffff;
406 dev_dbg(&priv->i2c->dev, "%s: if_frequency=%d pset_iffreq=%08x\n",
407 __func__, if_freq, (unsigned)pset_iffreq);
408
409 ret = rtl2832_wr_demod_reg(priv, DVBT_EN_BBIN, en_bbin);
410 if (ret)
411 return ret;
412
413 ret = rtl2832_wr_demod_reg(priv, DVBT_PSET_IFFREQ, pset_iffreq);
414
415 return ret;
416 }
417
418 static int rtl2832_init(struct dvb_frontend *fe)
419 {
420 struct rtl2832_priv *priv = fe->demodulator_priv;
421 const struct rtl2832_reg_value *init;
422 int i, ret, len;
423
424 /* initialization values for the demodulator registers */
425 struct rtl2832_reg_value rtl2832_initial_regs[] = {
426 {DVBT_AD_EN_REG, 0x1},
427 {DVBT_AD_EN_REG1, 0x1},
428 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
429 {DVBT_MGD_THD0, 0x10},
430 {DVBT_MGD_THD1, 0x20},
431 {DVBT_MGD_THD2, 0x20},
432 {DVBT_MGD_THD3, 0x40},
433 {DVBT_MGD_THD4, 0x22},
434 {DVBT_MGD_THD5, 0x32},
435 {DVBT_MGD_THD6, 0x37},
436 {DVBT_MGD_THD7, 0x39},
437 {DVBT_EN_BK_TRK, 0x0},
438 {DVBT_EN_CACQ_NOTCH, 0x0},
439 {DVBT_AD_AV_REF, 0x2a},
440 {DVBT_REG_PI, 0x6},
441 {DVBT_PIP_ON, 0x0},
442 {DVBT_CDIV_PH0, 0x8},
443 {DVBT_CDIV_PH1, 0x8},
444 {DVBT_SCALE1_B92, 0x4},
445 {DVBT_SCALE1_B93, 0xb0},
446 {DVBT_SCALE1_BA7, 0x78},
447 {DVBT_SCALE1_BA9, 0x28},
448 {DVBT_SCALE1_BAA, 0x59},
449 {DVBT_SCALE1_BAB, 0x83},
450 {DVBT_SCALE1_BAC, 0xd4},
451 {DVBT_SCALE1_BB0, 0x65},
452 {DVBT_SCALE1_BB1, 0x43},
453 {DVBT_KB_P1, 0x1},
454 {DVBT_KB_P2, 0x4},
455 {DVBT_KB_P3, 0x7},
456 {DVBT_K1_CR_STEP12, 0xa},
457 {DVBT_REG_GPE, 0x1},
458 {DVBT_SERIAL, 0x0},
459 {DVBT_CDIV_PH0, 0x9},
460 {DVBT_CDIV_PH1, 0x9},
461 {DVBT_MPEG_IO_OPT_2_2, 0x0},
462 {DVBT_MPEG_IO_OPT_1_0, 0x0},
463 {DVBT_TRK_KS_P2, 0x4},
464 {DVBT_TRK_KS_I2, 0x7},
465 {DVBT_TR_THD_SET2, 0x6},
466 {DVBT_TRK_KC_I2, 0x5},
467 {DVBT_CR_THD_SET2, 0x1},
468 };
469
470 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
471
472 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
473 ret = rtl2832_wr_demod_reg(priv, rtl2832_initial_regs[i].reg,
474 rtl2832_initial_regs[i].value);
475 if (ret)
476 goto err;
477 }
478
479 /* load tuner specific settings */
480 dev_dbg(&priv->i2c->dev, "%s: load settings for tuner=%02x\n",
481 __func__, priv->cfg.tuner);
482 switch (priv->cfg.tuner) {
483 case RTL2832_TUNER_FC0012:
484 case RTL2832_TUNER_FC0013:
485 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
486 init = rtl2832_tuner_init_fc0012;
487 break;
488 case RTL2832_TUNER_TUA9001:
489 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
490 init = rtl2832_tuner_init_tua9001;
491 break;
492 case RTL2832_TUNER_E4000:
493 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
494 init = rtl2832_tuner_init_e4000;
495 break;
496 case RTL2832_TUNER_R820T:
497 case RTL2832_TUNER_R828D:
498 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
499 init = rtl2832_tuner_init_r820t;
500 break;
501 default:
502 ret = -EINVAL;
503 goto err;
504 }
505
506 for (i = 0; i < len; i++) {
507 ret = rtl2832_wr_demod_reg(priv, init[i].reg, init[i].value);
508 if (ret)
509 goto err;
510 }
511
512 /*
513 * r820t NIM code does a software reset here at the demod -
514 * may not be needed, as there's already a software reset at
515 * set_params()
516 */
517 #if 1
518 /* soft reset */
519 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x1);
520 if (ret)
521 goto err;
522
523 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x0);
524 if (ret)
525 goto err;
526 #endif
527
528 priv->sleeping = false;
529
530 return ret;
531
532 err:
533 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
534 return ret;
535 }
536
537 static int rtl2832_sleep(struct dvb_frontend *fe)
538 {
539 struct rtl2832_priv *priv = fe->demodulator_priv;
540
541 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
542 priv->sleeping = true;
543 return 0;
544 }
545
546 static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
547 struct dvb_frontend_tune_settings *s)
548 {
549 struct rtl2832_priv *priv = fe->demodulator_priv;
550
551 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
552 s->min_delay_ms = 1000;
553 s->step_size = fe->ops.info.frequency_stepsize * 2;
554 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
555 return 0;
556 }
557
558 static int rtl2832_set_frontend(struct dvb_frontend *fe)
559 {
560 struct rtl2832_priv *priv = fe->demodulator_priv;
561 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
562 int ret, i, j;
563 u64 bw_mode, num, num2;
564 u32 resamp_ratio, cfreq_off_ratio;
565 static u8 bw_params[3][32] = {
566 /* 6 MHz bandwidth */
567 {
568 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
569 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
570 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
571 0x19, 0xe0,
572 },
573
574 /* 7 MHz bandwidth */
575 {
576 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
577 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
578 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
579 0x19, 0x10,
580 },
581
582 /* 8 MHz bandwidth */
583 {
584 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
585 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
586 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
587 0x19, 0xe0,
588 },
589 };
590
591
592 dev_dbg(&priv->i2c->dev,
593 "%s: frequency=%d bandwidth_hz=%d inversion=%d\n",
594 __func__, c->frequency, c->bandwidth_hz, c->inversion);
595
596 /* program tuner */
597 if (fe->ops.tuner_ops.set_params)
598 fe->ops.tuner_ops.set_params(fe);
599
600 /* PIP mode related */
601 ret = rtl2832_wr_regs(priv, 0x92, 1, "\x00\x0f\xff", 3);
602 if (ret)
603 goto err;
604
605 /* If the frontend has get_if_frequency(), use it */
606 if (fe->ops.tuner_ops.get_if_frequency) {
607 u32 if_freq;
608
609 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
610 if (ret)
611 goto err;
612
613 ret = rtl2832_set_if(fe, if_freq);
614 if (ret)
615 goto err;
616 }
617
618 switch (c->bandwidth_hz) {
619 case 6000000:
620 i = 0;
621 bw_mode = 48000000;
622 break;
623 case 7000000:
624 i = 1;
625 bw_mode = 56000000;
626 break;
627 case 8000000:
628 i = 2;
629 bw_mode = 64000000;
630 break;
631 default:
632 dev_dbg(&priv->i2c->dev, "%s: invalid bandwidth\n", __func__);
633 return -EINVAL;
634 }
635
636 for (j = 0; j < sizeof(bw_params[0]); j++) {
637 ret = rtl2832_wr_regs(priv, 0x1c+j, 1, &bw_params[i][j], 1);
638 if (ret)
639 goto err;
640 }
641
642 /* calculate and set resample ratio
643 * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
644 * / ConstWithBandwidthMode)
645 */
646 num = priv->cfg.xtal * 7;
647 num *= 0x400000;
648 num = div_u64(num, bw_mode);
649 resamp_ratio = num & 0x3ffffff;
650 ret = rtl2832_wr_demod_reg(priv, DVBT_RSAMP_RATIO, resamp_ratio);
651 if (ret)
652 goto err;
653
654 /* calculate and set cfreq off ratio
655 * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
656 * / (CrystalFreqHz * 7))
657 */
658 num = bw_mode << 20;
659 num2 = priv->cfg.xtal * 7;
660 num = div_u64(num, num2);
661 num = -num;
662 cfreq_off_ratio = num & 0xfffff;
663 ret = rtl2832_wr_demod_reg(priv, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
664 if (ret)
665 goto err;
666
667 /* soft reset */
668 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x1);
669 if (ret)
670 goto err;
671
672 ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x0);
673 if (ret)
674 goto err;
675
676 return ret;
677 err:
678 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
679 return ret;
680 }
681
682 static int rtl2832_get_frontend(struct dvb_frontend *fe)
683 {
684 struct rtl2832_priv *priv = fe->demodulator_priv;
685 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
686 int ret;
687 u8 buf[3];
688
689 if (priv->sleeping)
690 return 0;
691
692 ret = rtl2832_rd_regs(priv, 0x3c, 3, buf, 2);
693 if (ret)
694 goto err;
695
696 ret = rtl2832_rd_reg(priv, 0x51, 3, &buf[2]);
697 if (ret)
698 goto err;
699
700 dev_dbg(&priv->i2c->dev, "%s: TPS=%*ph\n", __func__, 3, buf);
701
702 switch ((buf[0] >> 2) & 3) {
703 case 0:
704 c->modulation = QPSK;
705 break;
706 case 1:
707 c->modulation = QAM_16;
708 break;
709 case 2:
710 c->modulation = QAM_64;
711 break;
712 }
713
714 switch ((buf[2] >> 2) & 1) {
715 case 0:
716 c->transmission_mode = TRANSMISSION_MODE_2K;
717 break;
718 case 1:
719 c->transmission_mode = TRANSMISSION_MODE_8K;
720 }
721
722 switch ((buf[2] >> 0) & 3) {
723 case 0:
724 c->guard_interval = GUARD_INTERVAL_1_32;
725 break;
726 case 1:
727 c->guard_interval = GUARD_INTERVAL_1_16;
728 break;
729 case 2:
730 c->guard_interval = GUARD_INTERVAL_1_8;
731 break;
732 case 3:
733 c->guard_interval = GUARD_INTERVAL_1_4;
734 break;
735 }
736
737 switch ((buf[0] >> 4) & 7) {
738 case 0:
739 c->hierarchy = HIERARCHY_NONE;
740 break;
741 case 1:
742 c->hierarchy = HIERARCHY_1;
743 break;
744 case 2:
745 c->hierarchy = HIERARCHY_2;
746 break;
747 case 3:
748 c->hierarchy = HIERARCHY_4;
749 break;
750 }
751
752 switch ((buf[1] >> 3) & 7) {
753 case 0:
754 c->code_rate_HP = FEC_1_2;
755 break;
756 case 1:
757 c->code_rate_HP = FEC_2_3;
758 break;
759 case 2:
760 c->code_rate_HP = FEC_3_4;
761 break;
762 case 3:
763 c->code_rate_HP = FEC_5_6;
764 break;
765 case 4:
766 c->code_rate_HP = FEC_7_8;
767 break;
768 }
769
770 switch ((buf[1] >> 0) & 7) {
771 case 0:
772 c->code_rate_LP = FEC_1_2;
773 break;
774 case 1:
775 c->code_rate_LP = FEC_2_3;
776 break;
777 case 2:
778 c->code_rate_LP = FEC_3_4;
779 break;
780 case 3:
781 c->code_rate_LP = FEC_5_6;
782 break;
783 case 4:
784 c->code_rate_LP = FEC_7_8;
785 break;
786 }
787
788 return 0;
789 err:
790 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
791 return ret;
792 }
793
794 static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
795 {
796 struct rtl2832_priv *priv = fe->demodulator_priv;
797 int ret;
798 u32 tmp;
799 *status = 0;
800
801 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
802 if (priv->sleeping)
803 return 0;
804
805 ret = rtl2832_rd_demod_reg(priv, DVBT_FSM_STAGE, &tmp);
806 if (ret)
807 goto err;
808
809 if (tmp == 11) {
810 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
811 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
812 }
813 /* TODO find out if this is also true for rtl2832? */
814 /*else if (tmp == 10) {
815 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
816 FE_HAS_VITERBI;
817 }*/
818
819 return ret;
820 err:
821 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
822 return ret;
823 }
824
825 static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
826 {
827 struct rtl2832_priv *priv = fe->demodulator_priv;
828 int ret, hierarchy, constellation;
829 u8 buf[2], tmp;
830 u16 tmp16;
831 #define CONSTELLATION_NUM 3
832 #define HIERARCHY_NUM 4
833 static const u32 snr_constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
834 { 85387325, 85387325, 85387325, 85387325 },
835 { 86676178, 86676178, 87167949, 87795660 },
836 { 87659938, 87659938, 87885178, 88241743 },
837 };
838
839 /* reports SNR in resolution of 0.1 dB */
840
841 ret = rtl2832_rd_reg(priv, 0x3c, 3, &tmp);
842 if (ret)
843 goto err;
844
845 constellation = (tmp >> 2) & 0x03; /* [3:2] */
846 if (constellation > CONSTELLATION_NUM - 1)
847 goto err;
848
849 hierarchy = (tmp >> 4) & 0x07; /* [6:4] */
850 if (hierarchy > HIERARCHY_NUM - 1)
851 goto err;
852
853 ret = rtl2832_rd_regs(priv, 0x0c, 4, buf, 2);
854 if (ret)
855 goto err;
856
857 tmp16 = buf[0] << 8 | buf[1];
858
859 if (tmp16)
860 *snr = (snr_constant[constellation][hierarchy] -
861 intlog10(tmp16)) / ((1 << 24) / 100);
862 else
863 *snr = 0;
864
865 return 0;
866 err:
867 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
868 return ret;
869 }
870
871 static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
872 {
873 struct rtl2832_priv *priv = fe->demodulator_priv;
874 int ret;
875 u8 buf[2];
876
877 ret = rtl2832_rd_regs(priv, 0x4e, 3, buf, 2);
878 if (ret)
879 goto err;
880
881 *ber = buf[0] << 8 | buf[1];
882
883 return 0;
884 err:
885 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
886 return ret;
887 }
888
889 /*
890 * Delay mechanism to avoid unneeded I2C gate open / close. Gate close is
891 * delayed here a little bit in order to see if there is sequence of I2C
892 * messages sent to same I2C bus.
893 * We must use unlocked version of __i2c_transfer() in order to avoid deadlock
894 * as lock is already taken by calling muxed i2c_transfer().
895 */
896 static void rtl2832_i2c_gate_work(struct work_struct *work)
897 {
898 struct rtl2832_priv *priv = container_of(work,
899 struct rtl2832_priv, i2c_gate_work.work);
900 struct i2c_adapter *adap = priv->i2c;
901 int ret;
902 u8 buf[2];
903 struct i2c_msg msg[1] = {
904 {
905 .addr = priv->cfg.i2c_addr,
906 .flags = 0,
907 .len = sizeof(buf),
908 .buf = buf,
909 }
910 };
911
912 /* select reg bank 1 */
913 buf[0] = 0x00;
914 buf[1] = 0x01;
915 ret = __i2c_transfer(adap, msg, 1);
916 if (ret != 1)
917 goto err;
918
919 priv->page = 1;
920
921 /* close I2C repeater gate */
922 buf[0] = 0x01;
923 buf[1] = 0x10;
924 ret = __i2c_transfer(adap, msg, 1);
925 if (ret != 1)
926 goto err;
927
928 priv->i2c_gate_state = false;
929
930 return;
931 err:
932 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
933
934 return;
935 }
936
937 static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id)
938 {
939 struct rtl2832_priv *priv = mux_priv;
940 int ret;
941 u8 buf[2], val;
942 struct i2c_msg msg[1] = {
943 {
944 .addr = priv->cfg.i2c_addr,
945 .flags = 0,
946 .len = sizeof(buf),
947 .buf = buf,
948 }
949 };
950 struct i2c_msg msg_rd[2] = {
951 {
952 .addr = priv->cfg.i2c_addr,
953 .flags = 0,
954 .len = 1,
955 .buf = "\x01",
956 }, {
957 .addr = priv->cfg.i2c_addr,
958 .flags = I2C_M_RD,
959 .len = 1,
960 .buf = &val,
961 }
962 };
963
964 /* terminate possible gate closing */
965 cancel_delayed_work_sync(&priv->i2c_gate_work);
966
967 if (priv->i2c_gate_state == chan_id)
968 return 0;
969
970 /* select reg bank 1 */
971 buf[0] = 0x00;
972 buf[1] = 0x01;
973 ret = __i2c_transfer(adap, msg, 1);
974 if (ret != 1)
975 goto err;
976
977 priv->page = 1;
978
979 /* we must read that register, otherwise there will be errors */
980 ret = __i2c_transfer(adap, msg_rd, 2);
981 if (ret != 2)
982 goto err;
983
984 /* open or close I2C repeater gate */
985 buf[0] = 0x01;
986 if (chan_id == 1)
987 buf[1] = 0x18; /* open */
988 else
989 buf[1] = 0x10; /* close */
990
991 ret = __i2c_transfer(adap, msg, 1);
992 if (ret != 1)
993 goto err;
994
995 priv->i2c_gate_state = chan_id;
996
997 return 0;
998 err:
999 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1000
1001 return -EREMOTEIO;
1002 }
1003
1004 static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv,
1005 u32 chan_id)
1006 {
1007 struct rtl2832_priv *priv = mux_priv;
1008 schedule_delayed_work(&priv->i2c_gate_work, usecs_to_jiffies(100));
1009 return 0;
1010 }
1011
1012 static struct dvb_frontend_ops rtl2832_ops = {
1013 .delsys = { SYS_DVBT },
1014 .info = {
1015 .name = "Realtek RTL2832 (DVB-T)",
1016 .frequency_min = 174000000,
1017 .frequency_max = 862000000,
1018 .frequency_stepsize = 166667,
1019 .caps = FE_CAN_FEC_1_2 |
1020 FE_CAN_FEC_2_3 |
1021 FE_CAN_FEC_3_4 |
1022 FE_CAN_FEC_5_6 |
1023 FE_CAN_FEC_7_8 |
1024 FE_CAN_FEC_AUTO |
1025 FE_CAN_QPSK |
1026 FE_CAN_QAM_16 |
1027 FE_CAN_QAM_64 |
1028 FE_CAN_QAM_AUTO |
1029 FE_CAN_TRANSMISSION_MODE_AUTO |
1030 FE_CAN_GUARD_INTERVAL_AUTO |
1031 FE_CAN_HIERARCHY_AUTO |
1032 FE_CAN_RECOVER |
1033 FE_CAN_MUTE_TS
1034 },
1035
1036 .init = rtl2832_init,
1037 .sleep = rtl2832_sleep,
1038
1039 .get_tune_settings = rtl2832_get_tune_settings,
1040
1041 .set_frontend = rtl2832_set_frontend,
1042 .get_frontend = rtl2832_get_frontend,
1043
1044 .read_status = rtl2832_read_status,
1045 .read_snr = rtl2832_read_snr,
1046 .read_ber = rtl2832_read_ber,
1047
1048 .i2c_gate_ctrl = rtl2832_i2c_gate_ctrl,
1049 };
1050
1051 static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
1052 {
1053 struct rtl2832_priv *dev = i2c_get_clientdata(client);
1054
1055 dev_dbg(&client->dev, "\n");
1056 return &dev->fe;
1057 }
1058
1059 static struct i2c_adapter *rtl2832_get_i2c_adapter_(struct i2c_client *client)
1060 {
1061 struct rtl2832_priv *dev = i2c_get_clientdata(client);
1062
1063 dev_dbg(&client->dev, "\n");
1064 return dev->i2c_adapter_tuner;
1065 }
1066
1067 static struct i2c_adapter *rtl2832_get_private_i2c_adapter_(struct i2c_client *client)
1068 {
1069 struct rtl2832_priv *dev = i2c_get_clientdata(client);
1070
1071 dev_dbg(&client->dev, "\n");
1072 return dev->i2c_adapter;
1073 }
1074
1075 static int rtl2832_enable_slave_ts(struct i2c_client *client)
1076 {
1077 struct rtl2832_priv *dev = i2c_get_clientdata(client);
1078 int ret;
1079
1080 dev_dbg(&client->dev, "setting PIP mode\n");
1081
1082 ret = rtl2832_wr_regs(dev, 0x0c, 1, "\x5f\xff", 2);
1083 if (ret)
1084 goto err;
1085
1086 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
1087 if (ret)
1088 goto err;
1089
1090 ret = rtl2832_wr_reg(dev, 0xbc, 0, 0x18);
1091 if (ret)
1092 goto err;
1093
1094 ret = rtl2832_wr_reg(dev, 0x22, 0, 0x01);
1095 if (ret)
1096 goto err;
1097
1098 ret = rtl2832_wr_reg(dev, 0x26, 0, 0x1f);
1099 if (ret)
1100 goto err;
1101
1102 ret = rtl2832_wr_reg(dev, 0x27, 0, 0xff);
1103 if (ret)
1104 goto err;
1105
1106 ret = rtl2832_wr_regs(dev, 0x92, 1, "\x7f\xf7\xff", 3);
1107 if (ret)
1108 goto err;
1109
1110 /* soft reset */
1111 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
1112 if (ret)
1113 goto err;
1114
1115 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
1116 if (ret)
1117 goto err;
1118
1119 return 0;
1120 err:
1121 dev_dbg(&client->dev, "failed=%d\n", ret);
1122 return ret;
1123 }
1124
1125 static int rtl2832_probe(struct i2c_client *client,
1126 const struct i2c_device_id *id)
1127 {
1128 struct rtl2832_platform_data *pdata = client->dev.platform_data;
1129 const struct rtl2832_config *config = pdata->config;
1130 struct i2c_adapter *i2c = client->adapter;
1131 struct rtl2832_priv *priv;
1132 int ret;
1133 u8 tmp;
1134
1135 dev_dbg(&client->dev, "\n");
1136
1137 /* allocate memory for the internal state */
1138 priv = kzalloc(sizeof(struct rtl2832_priv), GFP_KERNEL);
1139 if (priv == NULL) {
1140 ret = -ENOMEM;
1141 goto err;
1142 }
1143
1144 /* setup the priv */
1145 priv->client = client;
1146 priv->i2c = i2c;
1147 priv->tuner = config->tuner;
1148 priv->sleeping = true;
1149 memcpy(&priv->cfg, config, sizeof(struct rtl2832_config));
1150 INIT_DELAYED_WORK(&priv->i2c_gate_work, rtl2832_i2c_gate_work);
1151
1152 /* create muxed i2c adapter for demod itself */
1153 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0,
1154 rtl2832_select, NULL);
1155 if (priv->i2c_adapter == NULL) {
1156 ret = -ENODEV;
1157 goto err_kfree;
1158 }
1159
1160 /* check if the demod is there */
1161 ret = rtl2832_rd_reg(priv, 0x00, 0x0, &tmp);
1162 if (ret)
1163 goto err_i2c_del_mux_adapter;
1164
1165 /* create muxed i2c adapter for demod tuner bus */
1166 priv->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, priv,
1167 0, 1, 0, rtl2832_select, rtl2832_deselect);
1168 if (priv->i2c_adapter_tuner == NULL) {
1169 ret = -ENODEV;
1170 goto err_i2c_del_mux_adapter;
1171 }
1172
1173 /* create dvb_frontend */
1174 memcpy(&priv->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1175 priv->fe.demodulator_priv = priv;
1176 i2c_set_clientdata(client, priv);
1177
1178 /* setup callbacks */
1179 pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
1180 pdata->get_i2c_adapter = rtl2832_get_i2c_adapter_;
1181 pdata->get_private_i2c_adapter = rtl2832_get_private_i2c_adapter_;
1182 pdata->enable_slave_ts = rtl2832_enable_slave_ts;
1183
1184 dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
1185 return 0;
1186 err_i2c_del_mux_adapter:
1187 i2c_del_mux_adapter(priv->i2c_adapter);
1188 err_kfree:
1189 kfree(priv);
1190 err:
1191 dev_dbg(&client->dev, "failed=%d\n", ret);
1192 return ret;
1193 }
1194
1195 static int rtl2832_remove(struct i2c_client *client)
1196 {
1197 struct rtl2832_priv *priv = i2c_get_clientdata(client);
1198
1199 dev_dbg(&client->dev, "\n");
1200
1201 cancel_delayed_work_sync(&priv->i2c_gate_work);
1202
1203 i2c_del_mux_adapter(priv->i2c_adapter_tuner);
1204
1205 i2c_del_mux_adapter(priv->i2c_adapter);
1206
1207 kfree(priv);
1208
1209 return 0;
1210 }
1211
1212 static const struct i2c_device_id rtl2832_id_table[] = {
1213 {"rtl2832", 0},
1214 {}
1215 };
1216 MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
1217
1218 static struct i2c_driver rtl2832_driver = {
1219 .driver = {
1220 .owner = THIS_MODULE,
1221 .name = "rtl2832",
1222 },
1223 .probe = rtl2832_probe,
1224 .remove = rtl2832_remove,
1225 .id_table = rtl2832_id_table,
1226 };
1227
1228 module_i2c_driver(rtl2832_driver);
1229
1230 MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
1231 MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1232 MODULE_LICENSE("GPL");
1233 MODULE_VERSION("0.5");
Linux kernel - Deliverables
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