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[media] rtl2832: implement DVBv5 signal strength statistics
[deliverable/linux.git] / drivers / media / dvb-frontends / rtl2832.c
1 /*
2 * Realtek RTL2832 DVB-T demodulator driver
3 *
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21 #include "rtl2832_priv.h"
22 #include "dvb_math.h"
23 #include <linux/bitops.h>
24
25 #define REG_MASK(b) (BIT(b + 1) - 1)
26
27 static const struct rtl2832_reg_entry registers[] = {
28 [DVBT_SOFT_RST] = {0x1, 0x1, 2, 2},
29 [DVBT_IIC_REPEAT] = {0x1, 0x1, 3, 3},
30 [DVBT_TR_WAIT_MIN_8K] = {0x1, 0x88, 11, 2},
31 [DVBT_RSD_BER_FAIL_VAL] = {0x1, 0x8f, 15, 0},
32 [DVBT_EN_BK_TRK] = {0x1, 0xa6, 7, 7},
33 [DVBT_AD_EN_REG] = {0x0, 0x8, 7, 7},
34 [DVBT_AD_EN_REG1] = {0x0, 0x8, 6, 6},
35 [DVBT_EN_BBIN] = {0x1, 0xb1, 0, 0},
36 [DVBT_MGD_THD0] = {0x1, 0x95, 7, 0},
37 [DVBT_MGD_THD1] = {0x1, 0x96, 7, 0},
38 [DVBT_MGD_THD2] = {0x1, 0x97, 7, 0},
39 [DVBT_MGD_THD3] = {0x1, 0x98, 7, 0},
40 [DVBT_MGD_THD4] = {0x1, 0x99, 7, 0},
41 [DVBT_MGD_THD5] = {0x1, 0x9a, 7, 0},
42 [DVBT_MGD_THD6] = {0x1, 0x9b, 7, 0},
43 [DVBT_MGD_THD7] = {0x1, 0x9c, 7, 0},
44 [DVBT_EN_CACQ_NOTCH] = {0x1, 0x61, 4, 4},
45 [DVBT_AD_AV_REF] = {0x0, 0x9, 6, 0},
46 [DVBT_REG_PI] = {0x0, 0xa, 2, 0},
47 [DVBT_PIP_ON] = {0x0, 0x21, 3, 3},
48 [DVBT_SCALE1_B92] = {0x2, 0x92, 7, 0},
49 [DVBT_SCALE1_B93] = {0x2, 0x93, 7, 0},
50 [DVBT_SCALE1_BA7] = {0x2, 0xa7, 7, 0},
51 [DVBT_SCALE1_BA9] = {0x2, 0xa9, 7, 0},
52 [DVBT_SCALE1_BAA] = {0x2, 0xaa, 7, 0},
53 [DVBT_SCALE1_BAB] = {0x2, 0xab, 7, 0},
54 [DVBT_SCALE1_BAC] = {0x2, 0xac, 7, 0},
55 [DVBT_SCALE1_BB0] = {0x2, 0xb0, 7, 0},
56 [DVBT_SCALE1_BB1] = {0x2, 0xb1, 7, 0},
57 [DVBT_KB_P1] = {0x1, 0x64, 3, 1},
58 [DVBT_KB_P2] = {0x1, 0x64, 6, 4},
59 [DVBT_KB_P3] = {0x1, 0x65, 2, 0},
60 [DVBT_OPT_ADC_IQ] = {0x0, 0x6, 5, 4},
61 [DVBT_AD_AVI] = {0x0, 0x9, 1, 0},
62 [DVBT_AD_AVQ] = {0x0, 0x9, 3, 2},
63 [DVBT_K1_CR_STEP12] = {0x2, 0xad, 9, 4},
64 [DVBT_TRK_KS_P2] = {0x1, 0x6f, 2, 0},
65 [DVBT_TRK_KS_I2] = {0x1, 0x70, 5, 3},
66 [DVBT_TR_THD_SET2] = {0x1, 0x72, 3, 0},
67 [DVBT_TRK_KC_P2] = {0x1, 0x73, 5, 3},
68 [DVBT_TRK_KC_I2] = {0x1, 0x75, 2, 0},
69 [DVBT_CR_THD_SET2] = {0x1, 0x76, 7, 6},
70 [DVBT_PSET_IFFREQ] = {0x1, 0x19, 21, 0},
71 [DVBT_SPEC_INV] = {0x1, 0x15, 0, 0},
72 [DVBT_RSAMP_RATIO] = {0x1, 0x9f, 27, 2},
73 [DVBT_CFREQ_OFF_RATIO] = {0x1, 0x9d, 23, 4},
74 [DVBT_FSM_STAGE] = {0x3, 0x51, 6, 3},
75 [DVBT_RX_CONSTEL] = {0x3, 0x3c, 3, 2},
76 [DVBT_RX_HIER] = {0x3, 0x3c, 6, 4},
77 [DVBT_RX_C_RATE_LP] = {0x3, 0x3d, 2, 0},
78 [DVBT_RX_C_RATE_HP] = {0x3, 0x3d, 5, 3},
79 [DVBT_GI_IDX] = {0x3, 0x51, 1, 0},
80 [DVBT_FFT_MODE_IDX] = {0x3, 0x51, 2, 2},
81 [DVBT_RSD_BER_EST] = {0x3, 0x4e, 15, 0},
82 [DVBT_CE_EST_EVM] = {0x4, 0xc, 15, 0},
83 [DVBT_RF_AGC_VAL] = {0x3, 0x5b, 13, 0},
84 [DVBT_IF_AGC_VAL] = {0x3, 0x59, 13, 0},
85 [DVBT_DAGC_VAL] = {0x3, 0x5, 7, 0},
86 [DVBT_SFREQ_OFF] = {0x3, 0x18, 13, 0},
87 [DVBT_CFREQ_OFF] = {0x3, 0x5f, 17, 0},
88 [DVBT_POLAR_RF_AGC] = {0x0, 0xe, 1, 1},
89 [DVBT_POLAR_IF_AGC] = {0x0, 0xe, 0, 0},
90 [DVBT_AAGC_HOLD] = {0x1, 0x4, 5, 5},
91 [DVBT_EN_RF_AGC] = {0x1, 0x4, 6, 6},
92 [DVBT_EN_IF_AGC] = {0x1, 0x4, 7, 7},
93 [DVBT_IF_AGC_MIN] = {0x1, 0x8, 7, 0},
94 [DVBT_IF_AGC_MAX] = {0x1, 0x9, 7, 0},
95 [DVBT_RF_AGC_MIN] = {0x1, 0xa, 7, 0},
96 [DVBT_RF_AGC_MAX] = {0x1, 0xb, 7, 0},
97 [DVBT_IF_AGC_MAN] = {0x1, 0xc, 6, 6},
98 [DVBT_IF_AGC_MAN_VAL] = {0x1, 0xc, 13, 0},
99 [DVBT_RF_AGC_MAN] = {0x1, 0xe, 6, 6},
100 [DVBT_RF_AGC_MAN_VAL] = {0x1, 0xe, 13, 0},
101 [DVBT_DAGC_TRG_VAL] = {0x1, 0x12, 7, 0},
102 [DVBT_AGC_TARG_VAL_0] = {0x1, 0x2, 0, 0},
103 [DVBT_AGC_TARG_VAL_8_1] = {0x1, 0x3, 7, 0},
104 [DVBT_AAGC_LOOP_GAIN] = {0x1, 0xc7, 5, 1},
105 [DVBT_LOOP_GAIN2_3_0] = {0x1, 0x4, 4, 1},
106 [DVBT_LOOP_GAIN2_4] = {0x1, 0x5, 7, 7},
107 [DVBT_LOOP_GAIN3] = {0x1, 0xc8, 4, 0},
108 [DVBT_VTOP1] = {0x1, 0x6, 5, 0},
109 [DVBT_VTOP2] = {0x1, 0xc9, 5, 0},
110 [DVBT_VTOP3] = {0x1, 0xca, 5, 0},
111 [DVBT_KRF1] = {0x1, 0xcb, 7, 0},
112 [DVBT_KRF2] = {0x1, 0x7, 7, 0},
113 [DVBT_KRF3] = {0x1, 0xcd, 7, 0},
114 [DVBT_KRF4] = {0x1, 0xce, 7, 0},
115 [DVBT_EN_GI_PGA] = {0x1, 0xe5, 0, 0},
116 [DVBT_THD_LOCK_UP] = {0x1, 0xd9, 8, 0},
117 [DVBT_THD_LOCK_DW] = {0x1, 0xdb, 8, 0},
118 [DVBT_THD_UP1] = {0x1, 0xdd, 7, 0},
119 [DVBT_THD_DW1] = {0x1, 0xde, 7, 0},
120 [DVBT_INTER_CNT_LEN] = {0x1, 0xd8, 3, 0},
121 [DVBT_GI_PGA_STATE] = {0x1, 0xe6, 3, 3},
122 [DVBT_EN_AGC_PGA] = {0x1, 0xd7, 0, 0},
123 [DVBT_CKOUTPAR] = {0x1, 0x7b, 5, 5},
124 [DVBT_CKOUT_PWR] = {0x1, 0x7b, 6, 6},
125 [DVBT_SYNC_DUR] = {0x1, 0x7b, 7, 7},
126 [DVBT_ERR_DUR] = {0x1, 0x7c, 0, 0},
127 [DVBT_SYNC_LVL] = {0x1, 0x7c, 1, 1},
128 [DVBT_ERR_LVL] = {0x1, 0x7c, 2, 2},
129 [DVBT_VAL_LVL] = {0x1, 0x7c, 3, 3},
130 [DVBT_SERIAL] = {0x1, 0x7c, 4, 4},
131 [DVBT_SER_LSB] = {0x1, 0x7c, 5, 5},
132 [DVBT_CDIV_PH0] = {0x1, 0x7d, 3, 0},
133 [DVBT_CDIV_PH1] = {0x1, 0x7d, 7, 4},
134 [DVBT_MPEG_IO_OPT_2_2] = {0x0, 0x6, 7, 7},
135 [DVBT_MPEG_IO_OPT_1_0] = {0x0, 0x7, 7, 6},
136 [DVBT_CKOUTPAR_PIP] = {0x0, 0xb7, 4, 4},
137 [DVBT_CKOUT_PWR_PIP] = {0x0, 0xb7, 3, 3},
138 [DVBT_SYNC_LVL_PIP] = {0x0, 0xb7, 2, 2},
139 [DVBT_ERR_LVL_PIP] = {0x0, 0xb7, 1, 1},
140 [DVBT_VAL_LVL_PIP] = {0x0, 0xb7, 0, 0},
141 [DVBT_CKOUTPAR_PID] = {0x0, 0xb9, 4, 4},
142 [DVBT_CKOUT_PWR_PID] = {0x0, 0xb9, 3, 3},
143 [DVBT_SYNC_LVL_PID] = {0x0, 0xb9, 2, 2},
144 [DVBT_ERR_LVL_PID] = {0x0, 0xb9, 1, 1},
145 [DVBT_VAL_LVL_PID] = {0x0, 0xb9, 0, 0},
146 [DVBT_SM_PASS] = {0x1, 0x93, 11, 0},
147 [DVBT_AD7_SETTING] = {0x0, 0x11, 15, 0},
148 [DVBT_RSSI_R] = {0x3, 0x1, 6, 0},
149 [DVBT_ACI_DET_IND] = {0x3, 0x12, 0, 0},
150 [DVBT_REG_MON] = {0x0, 0xd, 1, 0},
151 [DVBT_REG_MONSEL] = {0x0, 0xd, 2, 2},
152 [DVBT_REG_GPE] = {0x0, 0xd, 7, 7},
153 [DVBT_REG_GPO] = {0x0, 0x10, 0, 0},
154 [DVBT_REG_4MSEL] = {0x0, 0x13, 0, 0},
155 };
156
157 /* Our regmap is bypassing I2C adapter lock, thus we do it! */
158 int rtl2832_bulk_write(struct i2c_client *client, unsigned int reg,
159 const void *val, size_t val_count)
160 {
161 struct rtl2832_dev *dev = i2c_get_clientdata(client);
162 int ret;
163
164 i2c_lock_adapter(client->adapter);
165 ret = regmap_bulk_write(dev->regmap, reg, val, val_count);
166 i2c_unlock_adapter(client->adapter);
167 return ret;
168 }
169
170 int rtl2832_update_bits(struct i2c_client *client, unsigned int reg,
171 unsigned int mask, unsigned int val)
172 {
173 struct rtl2832_dev *dev = i2c_get_clientdata(client);
174 int ret;
175
176 i2c_lock_adapter(client->adapter);
177 ret = regmap_update_bits(dev->regmap, reg, mask, val);
178 i2c_unlock_adapter(client->adapter);
179 return ret;
180 }
181
182 int rtl2832_bulk_read(struct i2c_client *client, unsigned int reg, void *val,
183 size_t val_count)
184 {
185 struct rtl2832_dev *dev = i2c_get_clientdata(client);
186 int ret;
187
188 i2c_lock_adapter(client->adapter);
189 ret = regmap_bulk_read(dev->regmap, reg, val, val_count);
190 i2c_unlock_adapter(client->adapter);
191 return ret;
192 }
193
194 /* write multiple registers */
195 static int rtl2832_wr_regs(struct rtl2832_dev *dev, u8 reg, u8 page, u8 *val, int len)
196 {
197 return rtl2832_bulk_write(dev->client, page << 8 | reg, val, len);
198 }
199
200 /* read multiple registers */
201 static int rtl2832_rd_regs(struct rtl2832_dev *dev, u8 reg, u8 page, u8 *val, int len)
202 {
203 return rtl2832_bulk_read(dev->client, page << 8 | reg, val, len);
204 }
205
206 /* write single register */
207 static int rtl2832_wr_reg(struct rtl2832_dev *dev, u8 reg, u8 page, u8 val)
208 {
209 return rtl2832_wr_regs(dev, reg, page, &val, 1);
210 }
211
212 /* read single register */
213 static int rtl2832_rd_reg(struct rtl2832_dev *dev, u8 reg, u8 page, u8 *val)
214 {
215 return rtl2832_rd_regs(dev, reg, page, val, 1);
216 }
217
218 static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
219 {
220 struct i2c_client *client = dev->client;
221 int ret;
222
223 u8 reg_start_addr;
224 u8 msb, lsb;
225 u8 page;
226 u8 reading[4];
227 u32 reading_tmp;
228 int i;
229
230 u8 len;
231 u32 mask;
232
233 reg_start_addr = registers[reg].start_address;
234 msb = registers[reg].msb;
235 lsb = registers[reg].lsb;
236 page = registers[reg].page;
237
238 len = (msb >> 3) + 1;
239 mask = REG_MASK(msb - lsb);
240
241 ret = rtl2832_rd_regs(dev, reg_start_addr, page, &reading[0], len);
242 if (ret)
243 goto err;
244
245 reading_tmp = 0;
246 for (i = 0; i < len; i++)
247 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
248
249 *val = (reading_tmp >> lsb) & mask;
250
251 return ret;
252
253 err:
254 dev_dbg(&client->dev, "failed=%d\n", ret);
255 return ret;
256
257 }
258
259 static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
260 {
261 struct i2c_client *client = dev->client;
262 int ret, i;
263 u8 len;
264 u8 reg_start_addr;
265 u8 msb, lsb;
266 u8 page;
267 u32 mask;
268
269
270 u8 reading[4];
271 u8 writing[4];
272 u32 reading_tmp;
273 u32 writing_tmp;
274
275
276 reg_start_addr = registers[reg].start_address;
277 msb = registers[reg].msb;
278 lsb = registers[reg].lsb;
279 page = registers[reg].page;
280
281 len = (msb >> 3) + 1;
282 mask = REG_MASK(msb - lsb);
283
284
285 ret = rtl2832_rd_regs(dev, reg_start_addr, page, &reading[0], len);
286 if (ret)
287 goto err;
288
289 reading_tmp = 0;
290 for (i = 0; i < len; i++)
291 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
292
293 writing_tmp = reading_tmp & ~(mask << lsb);
294 writing_tmp |= ((val & mask) << lsb);
295
296
297 for (i = 0; i < len; i++)
298 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
299
300 ret = rtl2832_wr_regs(dev, reg_start_addr, page, &writing[0], len);
301 if (ret)
302 goto err;
303
304 return ret;
305
306 err:
307 dev_dbg(&client->dev, "failed=%d\n", ret);
308 return ret;
309
310 }
311
312 static int rtl2832_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
313 {
314 struct rtl2832_dev *dev = fe->demodulator_priv;
315 struct i2c_client *client = dev->client;
316 int ret;
317
318 dev_dbg(&client->dev, "enable=%d\n", enable);
319
320 /* gate already open or close */
321 if (dev->i2c_gate_state == enable)
322 return 0;
323
324 ret = rtl2832_wr_demod_reg(dev, DVBT_IIC_REPEAT, (enable ? 0x1 : 0x0));
325 if (ret)
326 goto err;
327
328 dev->i2c_gate_state = enable;
329
330 return ret;
331 err:
332 dev_dbg(&client->dev, "failed=%d\n", ret);
333 return ret;
334 }
335
336 static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
337 {
338 struct rtl2832_dev *dev = fe->demodulator_priv;
339 struct i2c_client *client = dev->client;
340 int ret;
341 u64 pset_iffreq;
342 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
343
344 /*
345 * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
346 * / CrystalFreqHz)
347 */
348
349 pset_iffreq = if_freq % dev->pdata->clk;
350 pset_iffreq *= 0x400000;
351 pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
352 pset_iffreq = -pset_iffreq;
353 pset_iffreq = pset_iffreq & 0x3fffff;
354 dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
355 if_freq, (unsigned)pset_iffreq);
356
357 ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
358 if (ret)
359 return ret;
360
361 ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
362
363 return ret;
364 }
365
366 static int rtl2832_init(struct dvb_frontend *fe)
367 {
368 struct rtl2832_dev *dev = fe->demodulator_priv;
369 struct i2c_client *client = dev->client;
370 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
371 const struct rtl2832_reg_value *init;
372 int i, ret, len;
373 /* initialization values for the demodulator registers */
374 struct rtl2832_reg_value rtl2832_initial_regs[] = {
375 {DVBT_AD_EN_REG, 0x1},
376 {DVBT_AD_EN_REG1, 0x1},
377 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
378 {DVBT_MGD_THD0, 0x10},
379 {DVBT_MGD_THD1, 0x20},
380 {DVBT_MGD_THD2, 0x20},
381 {DVBT_MGD_THD3, 0x40},
382 {DVBT_MGD_THD4, 0x22},
383 {DVBT_MGD_THD5, 0x32},
384 {DVBT_MGD_THD6, 0x37},
385 {DVBT_MGD_THD7, 0x39},
386 {DVBT_EN_BK_TRK, 0x0},
387 {DVBT_EN_CACQ_NOTCH, 0x0},
388 {DVBT_AD_AV_REF, 0x2a},
389 {DVBT_REG_PI, 0x6},
390 {DVBT_PIP_ON, 0x0},
391 {DVBT_CDIV_PH0, 0x8},
392 {DVBT_CDIV_PH1, 0x8},
393 {DVBT_SCALE1_B92, 0x4},
394 {DVBT_SCALE1_B93, 0xb0},
395 {DVBT_SCALE1_BA7, 0x78},
396 {DVBT_SCALE1_BA9, 0x28},
397 {DVBT_SCALE1_BAA, 0x59},
398 {DVBT_SCALE1_BAB, 0x83},
399 {DVBT_SCALE1_BAC, 0xd4},
400 {DVBT_SCALE1_BB0, 0x65},
401 {DVBT_SCALE1_BB1, 0x43},
402 {DVBT_KB_P1, 0x1},
403 {DVBT_KB_P2, 0x4},
404 {DVBT_KB_P3, 0x7},
405 {DVBT_K1_CR_STEP12, 0xa},
406 {DVBT_REG_GPE, 0x1},
407 {DVBT_SERIAL, 0x0},
408 {DVBT_CDIV_PH0, 0x9},
409 {DVBT_CDIV_PH1, 0x9},
410 {DVBT_MPEG_IO_OPT_2_2, 0x0},
411 {DVBT_MPEG_IO_OPT_1_0, 0x0},
412 {DVBT_TRK_KS_P2, 0x4},
413 {DVBT_TRK_KS_I2, 0x7},
414 {DVBT_TR_THD_SET2, 0x6},
415 {DVBT_TRK_KC_I2, 0x5},
416 {DVBT_CR_THD_SET2, 0x1},
417 };
418
419 dev_dbg(&client->dev, "\n");
420
421 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
422 ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
423 rtl2832_initial_regs[i].value);
424 if (ret)
425 goto err;
426 }
427
428 /* load tuner specific settings */
429 dev_dbg(&client->dev, "load settings for tuner=%02x\n",
430 dev->pdata->tuner);
431 switch (dev->pdata->tuner) {
432 case RTL2832_TUNER_FC0012:
433 case RTL2832_TUNER_FC0013:
434 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
435 init = rtl2832_tuner_init_fc0012;
436 break;
437 case RTL2832_TUNER_TUA9001:
438 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
439 init = rtl2832_tuner_init_tua9001;
440 break;
441 case RTL2832_TUNER_E4000:
442 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
443 init = rtl2832_tuner_init_e4000;
444 break;
445 case RTL2832_TUNER_R820T:
446 case RTL2832_TUNER_R828D:
447 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
448 init = rtl2832_tuner_init_r820t;
449 break;
450 default:
451 ret = -EINVAL;
452 goto err;
453 }
454
455 for (i = 0; i < len; i++) {
456 ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
457 if (ret)
458 goto err;
459 }
460
461 /*
462 * r820t NIM code does a software reset here at the demod -
463 * may not be needed, as there's already a software reset at
464 * set_params()
465 */
466 #if 1
467 /* soft reset */
468 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
469 if (ret)
470 goto err;
471
472 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
473 if (ret)
474 goto err;
475 #endif
476 /* init stats here in order signal app which stats are supported */
477 c->strength.len = 1;
478 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
479 c->cnr.len = 1;
480 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
481 c->post_bit_error.len = 1;
482 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
483 c->post_bit_count.len = 1;
484 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
485 /* start statistics polling */
486 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
487 dev->sleeping = false;
488
489 return ret;
490 err:
491 dev_dbg(&client->dev, "failed=%d\n", ret);
492 return ret;
493 }
494
495 static int rtl2832_sleep(struct dvb_frontend *fe)
496 {
497 struct rtl2832_dev *dev = fe->demodulator_priv;
498 struct i2c_client *client = dev->client;
499
500 dev_dbg(&client->dev, "\n");
501 dev->sleeping = true;
502 /* stop statistics polling */
503 cancel_delayed_work_sync(&dev->stat_work);
504 dev->fe_status = 0;
505 return 0;
506 }
507
508 static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
509 struct dvb_frontend_tune_settings *s)
510 {
511 struct rtl2832_dev *dev = fe->demodulator_priv;
512 struct i2c_client *client = dev->client;
513
514 dev_dbg(&client->dev, "\n");
515 s->min_delay_ms = 1000;
516 s->step_size = fe->ops.info.frequency_stepsize * 2;
517 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
518 return 0;
519 }
520
521 static int rtl2832_set_frontend(struct dvb_frontend *fe)
522 {
523 struct rtl2832_dev *dev = fe->demodulator_priv;
524 struct i2c_client *client = dev->client;
525 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
526 int ret, i, j;
527 u64 bw_mode, num, num2;
528 u32 resamp_ratio, cfreq_off_ratio;
529 static u8 bw_params[3][32] = {
530 /* 6 MHz bandwidth */
531 {
532 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
533 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
534 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
535 0x19, 0xe0,
536 },
537
538 /* 7 MHz bandwidth */
539 {
540 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
541 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
542 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
543 0x19, 0x10,
544 },
545
546 /* 8 MHz bandwidth */
547 {
548 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
549 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
550 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
551 0x19, 0xe0,
552 },
553 };
554
555
556 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
557 c->frequency, c->bandwidth_hz, c->inversion);
558
559 /* program tuner */
560 if (fe->ops.tuner_ops.set_params)
561 fe->ops.tuner_ops.set_params(fe);
562
563 /* PIP mode related */
564 ret = rtl2832_wr_regs(dev, 0x92, 1, "\x00\x0f\xff", 3);
565 if (ret)
566 goto err;
567
568 /* If the frontend has get_if_frequency(), use it */
569 if (fe->ops.tuner_ops.get_if_frequency) {
570 u32 if_freq;
571
572 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
573 if (ret)
574 goto err;
575
576 ret = rtl2832_set_if(fe, if_freq);
577 if (ret)
578 goto err;
579 }
580
581 switch (c->bandwidth_hz) {
582 case 6000000:
583 i = 0;
584 bw_mode = 48000000;
585 break;
586 case 7000000:
587 i = 1;
588 bw_mode = 56000000;
589 break;
590 case 8000000:
591 i = 2;
592 bw_mode = 64000000;
593 break;
594 default:
595 dev_err(&client->dev, "invalid bandwidth_hz %u\n",
596 c->bandwidth_hz);
597 ret = -EINVAL;
598 goto err;
599 }
600
601 for (j = 0; j < sizeof(bw_params[0]); j++) {
602 ret = rtl2832_wr_regs(dev, 0x1c+j, 1, &bw_params[i][j], 1);
603 if (ret)
604 goto err;
605 }
606
607 /* calculate and set resample ratio
608 * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
609 * / ConstWithBandwidthMode)
610 */
611 num = dev->pdata->clk * 7;
612 num *= 0x400000;
613 num = div_u64(num, bw_mode);
614 resamp_ratio = num & 0x3ffffff;
615 ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
616 if (ret)
617 goto err;
618
619 /* calculate and set cfreq off ratio
620 * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
621 * / (CrystalFreqHz * 7))
622 */
623 num = bw_mode << 20;
624 num2 = dev->pdata->clk * 7;
625 num = div_u64(num, num2);
626 num = -num;
627 cfreq_off_ratio = num & 0xfffff;
628 ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
629 if (ret)
630 goto err;
631
632 /* soft reset */
633 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
634 if (ret)
635 goto err;
636
637 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
638 if (ret)
639 goto err;
640
641 return ret;
642 err:
643 dev_dbg(&client->dev, "failed=%d\n", ret);
644 return ret;
645 }
646
647 static int rtl2832_get_frontend(struct dvb_frontend *fe)
648 {
649 struct rtl2832_dev *dev = fe->demodulator_priv;
650 struct i2c_client *client = dev->client;
651 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
652 int ret;
653 u8 buf[3];
654
655 if (dev->sleeping)
656 return 0;
657
658 ret = rtl2832_rd_regs(dev, 0x3c, 3, buf, 2);
659 if (ret)
660 goto err;
661
662 ret = rtl2832_rd_reg(dev, 0x51, 3, &buf[2]);
663 if (ret)
664 goto err;
665
666 dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
667
668 switch ((buf[0] >> 2) & 3) {
669 case 0:
670 c->modulation = QPSK;
671 break;
672 case 1:
673 c->modulation = QAM_16;
674 break;
675 case 2:
676 c->modulation = QAM_64;
677 break;
678 }
679
680 switch ((buf[2] >> 2) & 1) {
681 case 0:
682 c->transmission_mode = TRANSMISSION_MODE_2K;
683 break;
684 case 1:
685 c->transmission_mode = TRANSMISSION_MODE_8K;
686 }
687
688 switch ((buf[2] >> 0) & 3) {
689 case 0:
690 c->guard_interval = GUARD_INTERVAL_1_32;
691 break;
692 case 1:
693 c->guard_interval = GUARD_INTERVAL_1_16;
694 break;
695 case 2:
696 c->guard_interval = GUARD_INTERVAL_1_8;
697 break;
698 case 3:
699 c->guard_interval = GUARD_INTERVAL_1_4;
700 break;
701 }
702
703 switch ((buf[0] >> 4) & 7) {
704 case 0:
705 c->hierarchy = HIERARCHY_NONE;
706 break;
707 case 1:
708 c->hierarchy = HIERARCHY_1;
709 break;
710 case 2:
711 c->hierarchy = HIERARCHY_2;
712 break;
713 case 3:
714 c->hierarchy = HIERARCHY_4;
715 break;
716 }
717
718 switch ((buf[1] >> 3) & 7) {
719 case 0:
720 c->code_rate_HP = FEC_1_2;
721 break;
722 case 1:
723 c->code_rate_HP = FEC_2_3;
724 break;
725 case 2:
726 c->code_rate_HP = FEC_3_4;
727 break;
728 case 3:
729 c->code_rate_HP = FEC_5_6;
730 break;
731 case 4:
732 c->code_rate_HP = FEC_7_8;
733 break;
734 }
735
736 switch ((buf[1] >> 0) & 7) {
737 case 0:
738 c->code_rate_LP = FEC_1_2;
739 break;
740 case 1:
741 c->code_rate_LP = FEC_2_3;
742 break;
743 case 2:
744 c->code_rate_LP = FEC_3_4;
745 break;
746 case 3:
747 c->code_rate_LP = FEC_5_6;
748 break;
749 case 4:
750 c->code_rate_LP = FEC_7_8;
751 break;
752 }
753
754 return 0;
755 err:
756 dev_dbg(&client->dev, "failed=%d\n", ret);
757 return ret;
758 }
759
760 static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
761 {
762 struct rtl2832_dev *dev = fe->demodulator_priv;
763 struct i2c_client *client = dev->client;
764 int ret;
765 u32 tmp;
766
767 dev_dbg(&client->dev, "\n");
768
769 *status = 0;
770 if (dev->sleeping)
771 return 0;
772
773 ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
774 if (ret)
775 goto err;
776
777 if (tmp == 11) {
778 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
779 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
780 }
781 /* TODO find out if this is also true for rtl2832? */
782 /*else if (tmp == 10) {
783 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
784 FE_HAS_VITERBI;
785 }*/
786
787 dev->fe_status = *status;
788 return ret;
789 err:
790 dev_dbg(&client->dev, "failed=%d\n", ret);
791 return ret;
792 }
793
794 static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
795 {
796 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
797
798 /* report SNR in resolution of 0.1 dB */
799 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
800 *snr = div_s64(c->cnr.stat[0].svalue, 100);
801 else
802 *snr = 0;
803
804 return 0;
805 }
806
807 static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
808 {
809 struct rtl2832_dev *dev = fe->demodulator_priv;
810
811 *ber = (dev->post_bit_error - dev->post_bit_error_prev);
812 dev->post_bit_error_prev = dev->post_bit_error;
813
814 return 0;
815 }
816
817 static void rtl2832_stat_work(struct work_struct *work)
818 {
819 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, stat_work.work);
820 struct i2c_client *client = dev->client;
821 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
822 int ret, tmp;
823 u8 u8tmp, buf[2];
824 u16 u16tmp;
825
826 dev_dbg(&client->dev, "\n");
827
828 /* signal strength */
829 if (dev->fe_status & FE_HAS_SIGNAL) {
830 /* read digital AGC */
831 ret = rtl2832_bulk_read(client, 0x305, &u8tmp, 1);
832 if (ret)
833 goto err;
834
835 dev_dbg(&client->dev, "digital agc=%02x", u8tmp);
836
837 u8tmp = ~u8tmp;
838 u16tmp = u8tmp << 8 | u8tmp << 0;
839
840 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
841 c->strength.stat[0].uvalue = u16tmp;
842 } else {
843 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
844 }
845
846 /* CNR */
847 if (dev->fe_status & FE_HAS_VITERBI) {
848 unsigned hierarchy, constellation;
849 #define CONSTELLATION_NUM 3
850 #define HIERARCHY_NUM 4
851 static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
852 {85387325, 85387325, 85387325, 85387325},
853 {86676178, 86676178, 87167949, 87795660},
854 {87659938, 87659938, 87885178, 88241743},
855 };
856
857 ret = rtl2832_bulk_read(client, 0x33c, &u8tmp, 1);
858 if (ret)
859 goto err;
860
861 constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
862 if (constellation > CONSTELLATION_NUM - 1)
863 goto err_schedule_delayed_work;
864
865 hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
866 if (hierarchy > HIERARCHY_NUM - 1)
867 goto err_schedule_delayed_work;
868
869 ret = rtl2832_bulk_read(client, 0x40c, buf, 2);
870 if (ret)
871 goto err;
872
873 u16tmp = buf[0] << 8 | buf[1] << 0;
874 if (u16tmp)
875 tmp = (constant[constellation][hierarchy] -
876 intlog10(u16tmp)) / ((1 << 24) / 10000);
877 else
878 tmp = 0;
879
880 dev_dbg(&client->dev, "cnr raw=%u\n", u16tmp);
881
882 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
883 c->cnr.stat[0].svalue = tmp;
884 } else {
885 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
886 }
887
888 /* BER */
889 if (dev->fe_status & FE_HAS_LOCK) {
890 ret = rtl2832_bulk_read(client, 0x34e, buf, 2);
891 if (ret)
892 goto err;
893
894 u16tmp = buf[0] << 8 | buf[1] << 0;
895 dev->post_bit_error += u16tmp;
896 dev->post_bit_count += 1000000;
897
898 dev_dbg(&client->dev, "ber errors=%u total=1000000\n", u16tmp);
899
900 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
901 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
902 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
903 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
904 } else {
905 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
906 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
907 }
908
909 err_schedule_delayed_work:
910 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
911 return;
912 err:
913 dev_dbg(&client->dev, "failed=%d\n", ret);
914 }
915
916 /*
917 * I2C gate/mux/repeater logic
918 * We must use unlocked __i2c_transfer() here (through regmap) because of I2C
919 * adapter lock is already taken by tuner driver.
920 * There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
921 * is delayed here a little bit in order to see if there is sequence of I2C
922 * messages sent to same I2C bus.
923 */
924 static void rtl2832_i2c_gate_work(struct work_struct *work)
925 {
926 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
927 struct i2c_client *client = dev->client;
928 int ret;
929
930 /* close gate */
931 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
932 if (ret)
933 goto err;
934
935 dev->i2c_gate_state = false;
936
937 return;
938 err:
939 dev_dbg(&client->dev, "failed=%d\n", ret);
940 return;
941 }
942
943 static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id)
944 {
945 struct rtl2832_dev *dev = mux_priv;
946 struct i2c_client *client = dev->client;
947 int ret;
948
949 /* terminate possible gate closing */
950 cancel_delayed_work(&dev->i2c_gate_work);
951
952 if (dev->i2c_gate_state == chan_id)
953 return 0;
954
955 /*
956 * chan_id 1 is muxed adapter demod provides and chan_id 0 is demod
957 * itself. We need open gate when request is for chan_id 1. On that case
958 * I2C adapter lock is already taken and due to that we will use
959 * regmap_update_bits() which does not lock again I2C adapter.
960 */
961 if (chan_id == 1)
962 ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
963 else
964 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
965 if (ret)
966 goto err;
967
968 dev->i2c_gate_state = chan_id;
969
970 return 0;
971 err:
972 dev_dbg(&client->dev, "failed=%d\n", ret);
973 return ret;
974 }
975
976 static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv,
977 u32 chan_id)
978 {
979 struct rtl2832_dev *dev = mux_priv;
980
981 schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
982 return 0;
983 }
984
985 static struct dvb_frontend_ops rtl2832_ops = {
986 .delsys = { SYS_DVBT },
987 .info = {
988 .name = "Realtek RTL2832 (DVB-T)",
989 .frequency_min = 174000000,
990 .frequency_max = 862000000,
991 .frequency_stepsize = 166667,
992 .caps = FE_CAN_FEC_1_2 |
993 FE_CAN_FEC_2_3 |
994 FE_CAN_FEC_3_4 |
995 FE_CAN_FEC_5_6 |
996 FE_CAN_FEC_7_8 |
997 FE_CAN_FEC_AUTO |
998 FE_CAN_QPSK |
999 FE_CAN_QAM_16 |
1000 FE_CAN_QAM_64 |
1001 FE_CAN_QAM_AUTO |
1002 FE_CAN_TRANSMISSION_MODE_AUTO |
1003 FE_CAN_GUARD_INTERVAL_AUTO |
1004 FE_CAN_HIERARCHY_AUTO |
1005 FE_CAN_RECOVER |
1006 FE_CAN_MUTE_TS
1007 },
1008
1009 .init = rtl2832_init,
1010 .sleep = rtl2832_sleep,
1011
1012 .get_tune_settings = rtl2832_get_tune_settings,
1013
1014 .set_frontend = rtl2832_set_frontend,
1015 .get_frontend = rtl2832_get_frontend,
1016
1017 .read_status = rtl2832_read_status,
1018 .read_snr = rtl2832_read_snr,
1019 .read_ber = rtl2832_read_ber,
1020
1021 .i2c_gate_ctrl = rtl2832_i2c_gate_ctrl,
1022 };
1023
1024 /*
1025 * We implement own I2C access routines for regmap in order to get manual access
1026 * to I2C adapter lock, which is needed for I2C mux adapter.
1027 */
1028 static int rtl2832_regmap_read(void *context, const void *reg_buf,
1029 size_t reg_size, void *val_buf, size_t val_size)
1030 {
1031 struct i2c_client *client = context;
1032 int ret;
1033 struct i2c_msg msg[2] = {
1034 {
1035 .addr = client->addr,
1036 .flags = 0,
1037 .len = reg_size,
1038 .buf = (u8 *)reg_buf,
1039 }, {
1040 .addr = client->addr,
1041 .flags = I2C_M_RD,
1042 .len = val_size,
1043 .buf = val_buf,
1044 }
1045 };
1046
1047 ret = __i2c_transfer(client->adapter, msg, 2);
1048 if (ret != 2) {
1049 dev_warn(&client->dev, "i2c reg read failed %d\n", ret);
1050 if (ret >= 0)
1051 ret = -EREMOTEIO;
1052 return ret;
1053 }
1054 return 0;
1055 }
1056
1057 static int rtl2832_regmap_write(void *context, const void *data, size_t count)
1058 {
1059 struct i2c_client *client = context;
1060 int ret;
1061 struct i2c_msg msg[1] = {
1062 {
1063 .addr = client->addr,
1064 .flags = 0,
1065 .len = count,
1066 .buf = (u8 *)data,
1067 }
1068 };
1069
1070 ret = __i2c_transfer(client->adapter, msg, 1);
1071 if (ret != 1) {
1072 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
1073 if (ret >= 0)
1074 ret = -EREMOTEIO;
1075 return ret;
1076 }
1077 return 0;
1078 }
1079
1080 static int rtl2832_regmap_gather_write(void *context, const void *reg,
1081 size_t reg_len, const void *val,
1082 size_t val_len)
1083 {
1084 struct i2c_client *client = context;
1085 int ret;
1086 u8 buf[256];
1087 struct i2c_msg msg[1] = {
1088 {
1089 .addr = client->addr,
1090 .flags = 0,
1091 .len = 1 + val_len,
1092 .buf = buf,
1093 }
1094 };
1095
1096 buf[0] = *(u8 const *)reg;
1097 memcpy(&buf[1], val, val_len);
1098
1099 ret = __i2c_transfer(client->adapter, msg, 1);
1100 if (ret != 1) {
1101 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
1102 if (ret >= 0)
1103 ret = -EREMOTEIO;
1104 return ret;
1105 }
1106 return 0;
1107 }
1108
1109 static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
1110 {
1111 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1112
1113 dev_dbg(&client->dev, "\n");
1114 return &dev->fe;
1115 }
1116
1117 static struct i2c_adapter *rtl2832_get_i2c_adapter_(struct i2c_client *client)
1118 {
1119 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1120
1121 dev_dbg(&client->dev, "\n");
1122 return dev->i2c_adapter_tuner;
1123 }
1124
1125 static struct i2c_adapter *rtl2832_get_private_i2c_adapter_(struct i2c_client *client)
1126 {
1127 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1128
1129 dev_dbg(&client->dev, "\n");
1130 return dev->i2c_adapter;
1131 }
1132
1133 static int rtl2832_enable_slave_ts(struct i2c_client *client)
1134 {
1135 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1136 int ret;
1137
1138 dev_dbg(&client->dev, "\n");
1139
1140 ret = rtl2832_wr_regs(dev, 0x0c, 1, "\x5f\xff", 2);
1141 if (ret)
1142 goto err;
1143
1144 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
1145 if (ret)
1146 goto err;
1147
1148 ret = rtl2832_wr_reg(dev, 0xbc, 0, 0x18);
1149 if (ret)
1150 goto err;
1151
1152 ret = rtl2832_wr_reg(dev, 0x22, 0, 0x01);
1153 if (ret)
1154 goto err;
1155
1156 ret = rtl2832_wr_reg(dev, 0x26, 0, 0x1f);
1157 if (ret)
1158 goto err;
1159
1160 ret = rtl2832_wr_reg(dev, 0x27, 0, 0xff);
1161 if (ret)
1162 goto err;
1163
1164 ret = rtl2832_wr_regs(dev, 0x92, 1, "\x7f\xf7\xff", 3);
1165 if (ret)
1166 goto err;
1167
1168 /* soft reset */
1169 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
1170 if (ret)
1171 goto err;
1172
1173 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
1174 if (ret)
1175 goto err;
1176
1177 return 0;
1178 err:
1179 dev_dbg(&client->dev, "failed=%d\n", ret);
1180 return ret;
1181 }
1182
1183 static int rtl2832_probe(struct i2c_client *client,
1184 const struct i2c_device_id *id)
1185 {
1186 struct rtl2832_platform_data *pdata = client->dev.platform_data;
1187 struct i2c_adapter *i2c = client->adapter;
1188 struct rtl2832_dev *dev;
1189 int ret;
1190 u8 tmp;
1191 static const struct regmap_bus regmap_bus = {
1192 .read = rtl2832_regmap_read,
1193 .write = rtl2832_regmap_write,
1194 .gather_write = rtl2832_regmap_gather_write,
1195 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1196 };
1197 static const struct regmap_range_cfg regmap_range_cfg[] = {
1198 {
1199 .selector_reg = 0x00,
1200 .selector_mask = 0xff,
1201 .selector_shift = 0,
1202 .window_start = 0,
1203 .window_len = 0x100,
1204 .range_min = 0 * 0x100,
1205 .range_max = 5 * 0x100,
1206 },
1207 };
1208 static const struct regmap_config regmap_config = {
1209 .reg_bits = 8,
1210 .val_bits = 8,
1211 .max_register = 5 * 0x100,
1212 .ranges = regmap_range_cfg,
1213 .num_ranges = ARRAY_SIZE(regmap_range_cfg),
1214 };
1215
1216 dev_dbg(&client->dev, "\n");
1217
1218 /* allocate memory for the internal state */
1219 dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
1220 if (dev == NULL) {
1221 ret = -ENOMEM;
1222 goto err;
1223 }
1224
1225 /* setup the state */
1226 i2c_set_clientdata(client, dev);
1227 dev->client = client;
1228 dev->pdata = client->dev.platform_data;
1229 if (pdata->config) {
1230 dev->pdata->clk = pdata->config->xtal;
1231 dev->pdata->tuner = pdata->config->tuner;
1232 }
1233 dev->sleeping = true;
1234 INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
1235 INIT_DELAYED_WORK(&dev->stat_work, rtl2832_stat_work);
1236 /* create regmap */
1237 dev->regmap = regmap_init(&client->dev, &regmap_bus, client,
1238 &regmap_config);
1239 if (IS_ERR(dev->regmap)) {
1240 ret = PTR_ERR(dev->regmap);
1241 goto err_kfree;
1242 }
1243 /* create muxed i2c adapter for demod itself */
1244 dev->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, dev, 0, 0, 0,
1245 rtl2832_select, NULL);
1246 if (dev->i2c_adapter == NULL) {
1247 ret = -ENODEV;
1248 goto err_regmap_exit;
1249 }
1250
1251 /* check if the demod is there */
1252 ret = rtl2832_rd_reg(dev, 0x00, 0x0, &tmp);
1253 if (ret)
1254 goto err_i2c_del_mux_adapter;
1255
1256 /* create muxed i2c adapter for demod tuner bus */
1257 dev->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, dev,
1258 0, 1, 0, rtl2832_select, rtl2832_deselect);
1259 if (dev->i2c_adapter_tuner == NULL) {
1260 ret = -ENODEV;
1261 goto err_i2c_del_mux_adapter;
1262 }
1263
1264 /* create dvb_frontend */
1265 memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1266 dev->fe.demodulator_priv = dev;
1267
1268 /* setup callbacks */
1269 pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
1270 pdata->get_i2c_adapter = rtl2832_get_i2c_adapter_;
1271 pdata->get_private_i2c_adapter = rtl2832_get_private_i2c_adapter_;
1272 pdata->enable_slave_ts = rtl2832_enable_slave_ts;
1273
1274 dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
1275 return 0;
1276 err_i2c_del_mux_adapter:
1277 i2c_del_mux_adapter(dev->i2c_adapter);
1278 err_regmap_exit:
1279 regmap_exit(dev->regmap);
1280 err_kfree:
1281 kfree(dev);
1282 err:
1283 dev_dbg(&client->dev, "failed=%d\n", ret);
1284 return ret;
1285 }
1286
1287 static int rtl2832_remove(struct i2c_client *client)
1288 {
1289 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1290
1291 dev_dbg(&client->dev, "\n");
1292
1293 cancel_delayed_work_sync(&dev->i2c_gate_work);
1294
1295 i2c_del_mux_adapter(dev->i2c_adapter_tuner);
1296
1297 i2c_del_mux_adapter(dev->i2c_adapter);
1298
1299 regmap_exit(dev->regmap);
1300
1301 kfree(dev);
1302
1303 return 0;
1304 }
1305
1306 static const struct i2c_device_id rtl2832_id_table[] = {
1307 {"rtl2832", 0},
1308 {}
1309 };
1310 MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
1311
1312 static struct i2c_driver rtl2832_driver = {
1313 .driver = {
1314 .owner = THIS_MODULE,
1315 .name = "rtl2832",
1316 },
1317 .probe = rtl2832_probe,
1318 .remove = rtl2832_remove,
1319 .id_table = rtl2832_id_table,
1320 };
1321
1322 module_i2c_driver(rtl2832_driver);
1323
1324 MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
1325 MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1326 MODULE_LICENSE("GPL");
1327 MODULE_VERSION("0.5");
Linux kernel - Deliverables
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