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7070713775e8753072436e676bfdc28e391fe1e9
[deliverable/linux.git] / drivers / media / dvb-frontends / rtl2832.c
1 /*
2 * Realtek RTL2832 DVB-T demodulator driver
3 *
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21 #include "rtl2832_priv.h"
22 #include "dvb_math.h"
23 #include <linux/bitops.h>
24
25 #define REG_MASK(b) (BIT(b + 1) - 1)
26
27 static const struct rtl2832_reg_entry registers[] = {
28 [DVBT_SOFT_RST] = {0x101, 2, 2},
29 [DVBT_IIC_REPEAT] = {0x101, 3, 3},
30 [DVBT_TR_WAIT_MIN_8K] = {0x188, 11, 2},
31 [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
32 [DVBT_EN_BK_TRK] = {0x1a6, 7, 7},
33 [DVBT_AD_EN_REG] = {0x008, 7, 7},
34 [DVBT_AD_EN_REG1] = {0x008, 6, 6},
35 [DVBT_EN_BBIN] = {0x1b1, 0, 0},
36 [DVBT_MGD_THD0] = {0x195, 7, 0},
37 [DVBT_MGD_THD1] = {0x196, 7, 0},
38 [DVBT_MGD_THD2] = {0x197, 7, 0},
39 [DVBT_MGD_THD3] = {0x198, 7, 0},
40 [DVBT_MGD_THD4] = {0x199, 7, 0},
41 [DVBT_MGD_THD5] = {0x19a, 7, 0},
42 [DVBT_MGD_THD6] = {0x19b, 7, 0},
43 [DVBT_MGD_THD7] = {0x19c, 7, 0},
44 [DVBT_EN_CACQ_NOTCH] = {0x161, 4, 4},
45 [DVBT_AD_AV_REF] = {0x009, 6, 0},
46 [DVBT_REG_PI] = {0x00a, 2, 0},
47 [DVBT_PIP_ON] = {0x021, 3, 3},
48 [DVBT_SCALE1_B92] = {0x292, 7, 0},
49 [DVBT_SCALE1_B93] = {0x293, 7, 0},
50 [DVBT_SCALE1_BA7] = {0x2a7, 7, 0},
51 [DVBT_SCALE1_BA9] = {0x2a9, 7, 0},
52 [DVBT_SCALE1_BAA] = {0x2aa, 7, 0},
53 [DVBT_SCALE1_BAB] = {0x2ab, 7, 0},
54 [DVBT_SCALE1_BAC] = {0x2ac, 7, 0},
55 [DVBT_SCALE1_BB0] = {0x2b0, 7, 0},
56 [DVBT_SCALE1_BB1] = {0x2b1, 7, 0},
57 [DVBT_KB_P1] = {0x164, 3, 1},
58 [DVBT_KB_P2] = {0x164, 6, 4},
59 [DVBT_KB_P3] = {0x165, 2, 0},
60 [DVBT_OPT_ADC_IQ] = {0x006, 5, 4},
61 [DVBT_AD_AVI] = {0x009, 1, 0},
62 [DVBT_AD_AVQ] = {0x009, 3, 2},
63 [DVBT_K1_CR_STEP12] = {0x2ad, 9, 4},
64 [DVBT_TRK_KS_P2] = {0x16f, 2, 0},
65 [DVBT_TRK_KS_I2] = {0x170, 5, 3},
66 [DVBT_TR_THD_SET2] = {0x172, 3, 0},
67 [DVBT_TRK_KC_P2] = {0x173, 5, 3},
68 [DVBT_TRK_KC_I2] = {0x175, 2, 0},
69 [DVBT_CR_THD_SET2] = {0x176, 7, 6},
70 [DVBT_PSET_IFFREQ] = {0x119, 21, 0},
71 [DVBT_SPEC_INV] = {0x115, 0, 0},
72 [DVBT_RSAMP_RATIO] = {0x19f, 27, 2},
73 [DVBT_CFREQ_OFF_RATIO] = {0x19d, 23, 4},
74 [DVBT_FSM_STAGE] = {0x351, 6, 3},
75 [DVBT_RX_CONSTEL] = {0x33c, 3, 2},
76 [DVBT_RX_HIER] = {0x33c, 6, 4},
77 [DVBT_RX_C_RATE_LP] = {0x33d, 2, 0},
78 [DVBT_RX_C_RATE_HP] = {0x33d, 5, 3},
79 [DVBT_GI_IDX] = {0x351, 1, 0},
80 [DVBT_FFT_MODE_IDX] = {0x351, 2, 2},
81 [DVBT_RSD_BER_EST] = {0x34e, 15, 0},
82 [DVBT_CE_EST_EVM] = {0x40c, 15, 0},
83 [DVBT_RF_AGC_VAL] = {0x35b, 13, 0},
84 [DVBT_IF_AGC_VAL] = {0x359, 13, 0},
85 [DVBT_DAGC_VAL] = {0x305, 7, 0},
86 [DVBT_SFREQ_OFF] = {0x318, 13, 0},
87 [DVBT_CFREQ_OFF] = {0x35f, 17, 0},
88 [DVBT_POLAR_RF_AGC] = {0x00e, 1, 1},
89 [DVBT_POLAR_IF_AGC] = {0x00e, 0, 0},
90 [DVBT_AAGC_HOLD] = {0x104, 5, 5},
91 [DVBT_EN_RF_AGC] = {0x104, 6, 6},
92 [DVBT_EN_IF_AGC] = {0x104, 7, 7},
93 [DVBT_IF_AGC_MIN] = {0x108, 7, 0},
94 [DVBT_IF_AGC_MAX] = {0x109, 7, 0},
95 [DVBT_RF_AGC_MIN] = {0x10a, 7, 0},
96 [DVBT_RF_AGC_MAX] = {0x10b, 7, 0},
97 [DVBT_IF_AGC_MAN] = {0x10c, 6, 6},
98 [DVBT_IF_AGC_MAN_VAL] = {0x10c, 13, 0},
99 [DVBT_RF_AGC_MAN] = {0x10e, 6, 6},
100 [DVBT_RF_AGC_MAN_VAL] = {0x10e, 13, 0},
101 [DVBT_DAGC_TRG_VAL] = {0x112, 7, 0},
102 [DVBT_AGC_TARG_VAL_0] = {0x102, 0, 0},
103 [DVBT_AGC_TARG_VAL_8_1] = {0x103, 7, 0},
104 [DVBT_AAGC_LOOP_GAIN] = {0x1c7, 5, 1},
105 [DVBT_LOOP_GAIN2_3_0] = {0x104, 4, 1},
106 [DVBT_LOOP_GAIN2_4] = {0x105, 7, 7},
107 [DVBT_LOOP_GAIN3] = {0x1c8, 4, 0},
108 [DVBT_VTOP1] = {0x106, 5, 0},
109 [DVBT_VTOP2] = {0x1c9, 5, 0},
110 [DVBT_VTOP3] = {0x1ca, 5, 0},
111 [DVBT_KRF1] = {0x1cb, 7, 0},
112 [DVBT_KRF2] = {0x107, 7, 0},
113 [DVBT_KRF3] = {0x1cd, 7, 0},
114 [DVBT_KRF4] = {0x1ce, 7, 0},
115 [DVBT_EN_GI_PGA] = {0x1e5, 0, 0},
116 [DVBT_THD_LOCK_UP] = {0x1d9, 8, 0},
117 [DVBT_THD_LOCK_DW] = {0x1db, 8, 0},
118 [DVBT_THD_UP1] = {0x1dd, 7, 0},
119 [DVBT_THD_DW1] = {0x1de, 7, 0},
120 [DVBT_INTER_CNT_LEN] = {0x1d8, 3, 0},
121 [DVBT_GI_PGA_STATE] = {0x1e6, 3, 3},
122 [DVBT_EN_AGC_PGA] = {0x1d7, 0, 0},
123 [DVBT_CKOUTPAR] = {0x17b, 5, 5},
124 [DVBT_CKOUT_PWR] = {0x17b, 6, 6},
125 [DVBT_SYNC_DUR] = {0x17b, 7, 7},
126 [DVBT_ERR_DUR] = {0x17c, 0, 0},
127 [DVBT_SYNC_LVL] = {0x17c, 1, 1},
128 [DVBT_ERR_LVL] = {0x17c, 2, 2},
129 [DVBT_VAL_LVL] = {0x17c, 3, 3},
130 [DVBT_SERIAL] = {0x17c, 4, 4},
131 [DVBT_SER_LSB] = {0x17c, 5, 5},
132 [DVBT_CDIV_PH0] = {0x17d, 3, 0},
133 [DVBT_CDIV_PH1] = {0x17d, 7, 4},
134 [DVBT_MPEG_IO_OPT_2_2] = {0x006, 7, 7},
135 [DVBT_MPEG_IO_OPT_1_0] = {0x007, 7, 6},
136 [DVBT_CKOUTPAR_PIP] = {0x0b7, 4, 4},
137 [DVBT_CKOUT_PWR_PIP] = {0x0b7, 3, 3},
138 [DVBT_SYNC_LVL_PIP] = {0x0b7, 2, 2},
139 [DVBT_ERR_LVL_PIP] = {0x0b7, 1, 1},
140 [DVBT_VAL_LVL_PIP] = {0x0b7, 0, 0},
141 [DVBT_CKOUTPAR_PID] = {0x0b9, 4, 4},
142 [DVBT_CKOUT_PWR_PID] = {0x0b9, 3, 3},
143 [DVBT_SYNC_LVL_PID] = {0x0b9, 2, 2},
144 [DVBT_ERR_LVL_PID] = {0x0b9, 1, 1},
145 [DVBT_VAL_LVL_PID] = {0x0b9, 0, 0},
146 [DVBT_SM_PASS] = {0x193, 11, 0},
147 [DVBT_AD7_SETTING] = {0x011, 15, 0},
148 [DVBT_RSSI_R] = {0x301, 6, 0},
149 [DVBT_ACI_DET_IND] = {0x312, 0, 0},
150 [DVBT_REG_MON] = {0x00d, 1, 0},
151 [DVBT_REG_MONSEL] = {0x00d, 2, 2},
152 [DVBT_REG_GPE] = {0x00d, 7, 7},
153 [DVBT_REG_GPO] = {0x010, 0, 0},
154 [DVBT_REG_4MSEL] = {0x013, 0, 0},
155 };
156
157 /* Our regmap is bypassing I2C adapter lock, thus we do it! */
158 int rtl2832_bulk_write(struct i2c_client *client, unsigned int reg,
159 const void *val, size_t val_count)
160 {
161 struct rtl2832_dev *dev = i2c_get_clientdata(client);
162 int ret;
163
164 i2c_lock_adapter(client->adapter);
165 ret = regmap_bulk_write(dev->regmap, reg, val, val_count);
166 i2c_unlock_adapter(client->adapter);
167 return ret;
168 }
169
170 int rtl2832_update_bits(struct i2c_client *client, unsigned int reg,
171 unsigned int mask, unsigned int val)
172 {
173 struct rtl2832_dev *dev = i2c_get_clientdata(client);
174 int ret;
175
176 i2c_lock_adapter(client->adapter);
177 ret = regmap_update_bits(dev->regmap, reg, mask, val);
178 i2c_unlock_adapter(client->adapter);
179 return ret;
180 }
181
182 int rtl2832_bulk_read(struct i2c_client *client, unsigned int reg, void *val,
183 size_t val_count)
184 {
185 struct rtl2832_dev *dev = i2c_get_clientdata(client);
186 int ret;
187
188 i2c_lock_adapter(client->adapter);
189 ret = regmap_bulk_read(dev->regmap, reg, val, val_count);
190 i2c_unlock_adapter(client->adapter);
191 return ret;
192 }
193
194 static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
195 {
196 struct i2c_client *client = dev->client;
197 int ret;
198
199 u16 reg_start_addr;
200 u8 msb, lsb;
201 u8 reading[4];
202 u32 reading_tmp;
203 int i;
204
205 u8 len;
206 u32 mask;
207
208 reg_start_addr = registers[reg].start_address;
209 msb = registers[reg].msb;
210 lsb = registers[reg].lsb;
211
212 len = (msb >> 3) + 1;
213 mask = REG_MASK(msb - lsb);
214
215 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
216 if (ret)
217 goto err;
218
219 reading_tmp = 0;
220 for (i = 0; i < len; i++)
221 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
222
223 *val = (reading_tmp >> lsb) & mask;
224
225 return ret;
226
227 err:
228 dev_dbg(&client->dev, "failed=%d\n", ret);
229 return ret;
230
231 }
232
233 static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
234 {
235 struct i2c_client *client = dev->client;
236 int ret, i;
237 u8 len;
238 u16 reg_start_addr;
239 u8 msb, lsb;
240 u32 mask;
241
242
243 u8 reading[4];
244 u8 writing[4];
245 u32 reading_tmp;
246 u32 writing_tmp;
247
248
249 reg_start_addr = registers[reg].start_address;
250 msb = registers[reg].msb;
251 lsb = registers[reg].lsb;
252
253 len = (msb >> 3) + 1;
254 mask = REG_MASK(msb - lsb);
255
256
257 ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
258 if (ret)
259 goto err;
260
261 reading_tmp = 0;
262 for (i = 0; i < len; i++)
263 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
264
265 writing_tmp = reading_tmp & ~(mask << lsb);
266 writing_tmp |= ((val & mask) << lsb);
267
268
269 for (i = 0; i < len; i++)
270 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
271
272 ret = rtl2832_bulk_write(client, reg_start_addr, writing, len);
273 if (ret)
274 goto err;
275
276 return ret;
277
278 err:
279 dev_dbg(&client->dev, "failed=%d\n", ret);
280 return ret;
281
282 }
283
284 static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
285 {
286 struct rtl2832_dev *dev = fe->demodulator_priv;
287 struct i2c_client *client = dev->client;
288 int ret;
289 u64 pset_iffreq;
290 u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
291
292 /*
293 * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
294 * / CrystalFreqHz)
295 */
296
297 pset_iffreq = if_freq % dev->pdata->clk;
298 pset_iffreq *= 0x400000;
299 pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
300 pset_iffreq = -pset_iffreq;
301 pset_iffreq = pset_iffreq & 0x3fffff;
302 dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
303 if_freq, (unsigned)pset_iffreq);
304
305 ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
306 if (ret)
307 return ret;
308
309 ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
310
311 return ret;
312 }
313
314 static int rtl2832_init(struct dvb_frontend *fe)
315 {
316 struct rtl2832_dev *dev = fe->demodulator_priv;
317 struct i2c_client *client = dev->client;
318 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
319 const struct rtl2832_reg_value *init;
320 int i, ret, len;
321 /* initialization values for the demodulator registers */
322 struct rtl2832_reg_value rtl2832_initial_regs[] = {
323 {DVBT_AD_EN_REG, 0x1},
324 {DVBT_AD_EN_REG1, 0x1},
325 {DVBT_RSD_BER_FAIL_VAL, 0x2800},
326 {DVBT_MGD_THD0, 0x10},
327 {DVBT_MGD_THD1, 0x20},
328 {DVBT_MGD_THD2, 0x20},
329 {DVBT_MGD_THD3, 0x40},
330 {DVBT_MGD_THD4, 0x22},
331 {DVBT_MGD_THD5, 0x32},
332 {DVBT_MGD_THD6, 0x37},
333 {DVBT_MGD_THD7, 0x39},
334 {DVBT_EN_BK_TRK, 0x0},
335 {DVBT_EN_CACQ_NOTCH, 0x0},
336 {DVBT_AD_AV_REF, 0x2a},
337 {DVBT_REG_PI, 0x6},
338 {DVBT_PIP_ON, 0x0},
339 {DVBT_CDIV_PH0, 0x8},
340 {DVBT_CDIV_PH1, 0x8},
341 {DVBT_SCALE1_B92, 0x4},
342 {DVBT_SCALE1_B93, 0xb0},
343 {DVBT_SCALE1_BA7, 0x78},
344 {DVBT_SCALE1_BA9, 0x28},
345 {DVBT_SCALE1_BAA, 0x59},
346 {DVBT_SCALE1_BAB, 0x83},
347 {DVBT_SCALE1_BAC, 0xd4},
348 {DVBT_SCALE1_BB0, 0x65},
349 {DVBT_SCALE1_BB1, 0x43},
350 {DVBT_KB_P1, 0x1},
351 {DVBT_KB_P2, 0x4},
352 {DVBT_KB_P3, 0x7},
353 {DVBT_K1_CR_STEP12, 0xa},
354 {DVBT_REG_GPE, 0x1},
355 {DVBT_SERIAL, 0x0},
356 {DVBT_CDIV_PH0, 0x9},
357 {DVBT_CDIV_PH1, 0x9},
358 {DVBT_MPEG_IO_OPT_2_2, 0x0},
359 {DVBT_MPEG_IO_OPT_1_0, 0x0},
360 {DVBT_TRK_KS_P2, 0x4},
361 {DVBT_TRK_KS_I2, 0x7},
362 {DVBT_TR_THD_SET2, 0x6},
363 {DVBT_TRK_KC_I2, 0x5},
364 {DVBT_CR_THD_SET2, 0x1},
365 };
366
367 dev_dbg(&client->dev, "\n");
368
369 for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
370 ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
371 rtl2832_initial_regs[i].value);
372 if (ret)
373 goto err;
374 }
375
376 /* load tuner specific settings */
377 dev_dbg(&client->dev, "load settings for tuner=%02x\n",
378 dev->pdata->tuner);
379 switch (dev->pdata->tuner) {
380 case RTL2832_TUNER_FC0012:
381 case RTL2832_TUNER_FC0013:
382 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
383 init = rtl2832_tuner_init_fc0012;
384 break;
385 case RTL2832_TUNER_TUA9001:
386 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
387 init = rtl2832_tuner_init_tua9001;
388 break;
389 case RTL2832_TUNER_E4000:
390 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
391 init = rtl2832_tuner_init_e4000;
392 break;
393 case RTL2832_TUNER_R820T:
394 case RTL2832_TUNER_R828D:
395 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
396 init = rtl2832_tuner_init_r820t;
397 break;
398 default:
399 ret = -EINVAL;
400 goto err;
401 }
402
403 for (i = 0; i < len; i++) {
404 ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
405 if (ret)
406 goto err;
407 }
408
409 /* init stats here in order signal app which stats are supported */
410 c->strength.len = 1;
411 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
412 c->cnr.len = 1;
413 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
414 c->post_bit_error.len = 1;
415 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
416 c->post_bit_count.len = 1;
417 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
418 /* start statistics polling */
419 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
420 dev->sleeping = false;
421
422 return ret;
423 err:
424 dev_dbg(&client->dev, "failed=%d\n", ret);
425 return ret;
426 }
427
428 static int rtl2832_sleep(struct dvb_frontend *fe)
429 {
430 struct rtl2832_dev *dev = fe->demodulator_priv;
431 struct i2c_client *client = dev->client;
432
433 dev_dbg(&client->dev, "\n");
434 dev->sleeping = true;
435 /* stop statistics polling */
436 cancel_delayed_work_sync(&dev->stat_work);
437 dev->fe_status = 0;
438 return 0;
439 }
440
441 static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
442 struct dvb_frontend_tune_settings *s)
443 {
444 struct rtl2832_dev *dev = fe->demodulator_priv;
445 struct i2c_client *client = dev->client;
446
447 dev_dbg(&client->dev, "\n");
448 s->min_delay_ms = 1000;
449 s->step_size = fe->ops.info.frequency_stepsize * 2;
450 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
451 return 0;
452 }
453
454 static int rtl2832_set_frontend(struct dvb_frontend *fe)
455 {
456 struct rtl2832_dev *dev = fe->demodulator_priv;
457 struct i2c_client *client = dev->client;
458 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
459 int ret, i, j;
460 u64 bw_mode, num, num2;
461 u32 resamp_ratio, cfreq_off_ratio;
462 static u8 bw_params[3][32] = {
463 /* 6 MHz bandwidth */
464 {
465 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
466 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
467 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
468 0x19, 0xe0,
469 },
470
471 /* 7 MHz bandwidth */
472 {
473 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
474 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
475 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
476 0x19, 0x10,
477 },
478
479 /* 8 MHz bandwidth */
480 {
481 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
482 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
483 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
484 0x19, 0xe0,
485 },
486 };
487
488
489 dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
490 c->frequency, c->bandwidth_hz, c->inversion);
491
492 /* program tuner */
493 if (fe->ops.tuner_ops.set_params)
494 fe->ops.tuner_ops.set_params(fe);
495
496 /* PIP mode related */
497 ret = rtl2832_bulk_write(client, 0x192, "\x00\x0f\xff", 3);
498 if (ret)
499 goto err;
500
501 /* If the frontend has get_if_frequency(), use it */
502 if (fe->ops.tuner_ops.get_if_frequency) {
503 u32 if_freq;
504
505 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
506 if (ret)
507 goto err;
508
509 ret = rtl2832_set_if(fe, if_freq);
510 if (ret)
511 goto err;
512 }
513
514 switch (c->bandwidth_hz) {
515 case 6000000:
516 i = 0;
517 bw_mode = 48000000;
518 break;
519 case 7000000:
520 i = 1;
521 bw_mode = 56000000;
522 break;
523 case 8000000:
524 i = 2;
525 bw_mode = 64000000;
526 break;
527 default:
528 dev_err(&client->dev, "invalid bandwidth_hz %u\n",
529 c->bandwidth_hz);
530 ret = -EINVAL;
531 goto err;
532 }
533
534 for (j = 0; j < sizeof(bw_params[0]); j++) {
535 ret = rtl2832_bulk_write(client, 0x11c + j, &bw_params[i][j], 1);
536 if (ret)
537 goto err;
538 }
539
540 /* calculate and set resample ratio
541 * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
542 * / ConstWithBandwidthMode)
543 */
544 num = dev->pdata->clk * 7;
545 num *= 0x400000;
546 num = div_u64(num, bw_mode);
547 resamp_ratio = num & 0x3ffffff;
548 ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
549 if (ret)
550 goto err;
551
552 /* calculate and set cfreq off ratio
553 * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
554 * / (CrystalFreqHz * 7))
555 */
556 num = bw_mode << 20;
557 num2 = dev->pdata->clk * 7;
558 num = div_u64(num, num2);
559 num = -num;
560 cfreq_off_ratio = num & 0xfffff;
561 ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
562 if (ret)
563 goto err;
564
565 /* soft reset */
566 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
567 if (ret)
568 goto err;
569
570 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
571 if (ret)
572 goto err;
573
574 return ret;
575 err:
576 dev_dbg(&client->dev, "failed=%d\n", ret);
577 return ret;
578 }
579
580 static int rtl2832_get_frontend(struct dvb_frontend *fe)
581 {
582 struct rtl2832_dev *dev = fe->demodulator_priv;
583 struct i2c_client *client = dev->client;
584 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
585 int ret;
586 u8 buf[3];
587
588 if (dev->sleeping)
589 return 0;
590
591 ret = rtl2832_bulk_read(client, 0x33c, buf, 2);
592 if (ret)
593 goto err;
594
595 ret = rtl2832_bulk_read(client, 0x351, &buf[2], 1);
596 if (ret)
597 goto err;
598
599 dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
600
601 switch ((buf[0] >> 2) & 3) {
602 case 0:
603 c->modulation = QPSK;
604 break;
605 case 1:
606 c->modulation = QAM_16;
607 break;
608 case 2:
609 c->modulation = QAM_64;
610 break;
611 }
612
613 switch ((buf[2] >> 2) & 1) {
614 case 0:
615 c->transmission_mode = TRANSMISSION_MODE_2K;
616 break;
617 case 1:
618 c->transmission_mode = TRANSMISSION_MODE_8K;
619 }
620
621 switch ((buf[2] >> 0) & 3) {
622 case 0:
623 c->guard_interval = GUARD_INTERVAL_1_32;
624 break;
625 case 1:
626 c->guard_interval = GUARD_INTERVAL_1_16;
627 break;
628 case 2:
629 c->guard_interval = GUARD_INTERVAL_1_8;
630 break;
631 case 3:
632 c->guard_interval = GUARD_INTERVAL_1_4;
633 break;
634 }
635
636 switch ((buf[0] >> 4) & 7) {
637 case 0:
638 c->hierarchy = HIERARCHY_NONE;
639 break;
640 case 1:
641 c->hierarchy = HIERARCHY_1;
642 break;
643 case 2:
644 c->hierarchy = HIERARCHY_2;
645 break;
646 case 3:
647 c->hierarchy = HIERARCHY_4;
648 break;
649 }
650
651 switch ((buf[1] >> 3) & 7) {
652 case 0:
653 c->code_rate_HP = FEC_1_2;
654 break;
655 case 1:
656 c->code_rate_HP = FEC_2_3;
657 break;
658 case 2:
659 c->code_rate_HP = FEC_3_4;
660 break;
661 case 3:
662 c->code_rate_HP = FEC_5_6;
663 break;
664 case 4:
665 c->code_rate_HP = FEC_7_8;
666 break;
667 }
668
669 switch ((buf[1] >> 0) & 7) {
670 case 0:
671 c->code_rate_LP = FEC_1_2;
672 break;
673 case 1:
674 c->code_rate_LP = FEC_2_3;
675 break;
676 case 2:
677 c->code_rate_LP = FEC_3_4;
678 break;
679 case 3:
680 c->code_rate_LP = FEC_5_6;
681 break;
682 case 4:
683 c->code_rate_LP = FEC_7_8;
684 break;
685 }
686
687 return 0;
688 err:
689 dev_dbg(&client->dev, "failed=%d\n", ret);
690 return ret;
691 }
692
693 static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
694 {
695 struct rtl2832_dev *dev = fe->demodulator_priv;
696 struct i2c_client *client = dev->client;
697 int ret;
698 u32 tmp;
699
700 dev_dbg(&client->dev, "\n");
701
702 *status = 0;
703 if (dev->sleeping)
704 return 0;
705
706 ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
707 if (ret)
708 goto err;
709
710 if (tmp == 11) {
711 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
712 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
713 } else if (tmp == 10) {
714 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
715 FE_HAS_VITERBI;
716 }
717
718 dev->fe_status = *status;
719 return ret;
720 err:
721 dev_dbg(&client->dev, "failed=%d\n", ret);
722 return ret;
723 }
724
725 static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
726 {
727 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
728
729 /* report SNR in resolution of 0.1 dB */
730 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
731 *snr = div_s64(c->cnr.stat[0].svalue, 100);
732 else
733 *snr = 0;
734
735 return 0;
736 }
737
738 static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
739 {
740 struct rtl2832_dev *dev = fe->demodulator_priv;
741
742 *ber = (dev->post_bit_error - dev->post_bit_error_prev);
743 dev->post_bit_error_prev = dev->post_bit_error;
744
745 return 0;
746 }
747
748 static void rtl2832_stat_work(struct work_struct *work)
749 {
750 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, stat_work.work);
751 struct i2c_client *client = dev->client;
752 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
753 int ret, tmp;
754 u8 u8tmp, buf[2];
755 u16 u16tmp;
756
757 dev_dbg(&client->dev, "\n");
758
759 /* signal strength */
760 if (dev->fe_status & FE_HAS_SIGNAL) {
761 /* read digital AGC */
762 ret = rtl2832_bulk_read(client, 0x305, &u8tmp, 1);
763 if (ret)
764 goto err;
765
766 dev_dbg(&client->dev, "digital agc=%02x", u8tmp);
767
768 u8tmp = ~u8tmp;
769 u16tmp = u8tmp << 8 | u8tmp << 0;
770
771 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
772 c->strength.stat[0].uvalue = u16tmp;
773 } else {
774 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
775 }
776
777 /* CNR */
778 if (dev->fe_status & FE_HAS_VITERBI) {
779 unsigned hierarchy, constellation;
780 #define CONSTELLATION_NUM 3
781 #define HIERARCHY_NUM 4
782 static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
783 {85387325, 85387325, 85387325, 85387325},
784 {86676178, 86676178, 87167949, 87795660},
785 {87659938, 87659938, 87885178, 88241743},
786 };
787
788 ret = rtl2832_bulk_read(client, 0x33c, &u8tmp, 1);
789 if (ret)
790 goto err;
791
792 constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
793 if (constellation > CONSTELLATION_NUM - 1)
794 goto err_schedule_delayed_work;
795
796 hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
797 if (hierarchy > HIERARCHY_NUM - 1)
798 goto err_schedule_delayed_work;
799
800 ret = rtl2832_bulk_read(client, 0x40c, buf, 2);
801 if (ret)
802 goto err;
803
804 u16tmp = buf[0] << 8 | buf[1] << 0;
805 if (u16tmp)
806 tmp = (constant[constellation][hierarchy] -
807 intlog10(u16tmp)) / ((1 << 24) / 10000);
808 else
809 tmp = 0;
810
811 dev_dbg(&client->dev, "cnr raw=%u\n", u16tmp);
812
813 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
814 c->cnr.stat[0].svalue = tmp;
815 } else {
816 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
817 }
818
819 /* BER */
820 if (dev->fe_status & FE_HAS_LOCK) {
821 ret = rtl2832_bulk_read(client, 0x34e, buf, 2);
822 if (ret)
823 goto err;
824
825 u16tmp = buf[0] << 8 | buf[1] << 0;
826 dev->post_bit_error += u16tmp;
827 dev->post_bit_count += 1000000;
828
829 dev_dbg(&client->dev, "ber errors=%u total=1000000\n", u16tmp);
830
831 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
832 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
833 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
834 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
835 } else {
836 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
837 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
838 }
839
840 err_schedule_delayed_work:
841 schedule_delayed_work(&dev->stat_work, msecs_to_jiffies(2000));
842 return;
843 err:
844 dev_dbg(&client->dev, "failed=%d\n", ret);
845 }
846
847 /*
848 * I2C gate/mux/repeater logic
849 * We must use unlocked __i2c_transfer() here (through regmap) because of I2C
850 * adapter lock is already taken by tuner driver.
851 * There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
852 * is delayed here a little bit in order to see if there is sequence of I2C
853 * messages sent to same I2C bus.
854 */
855 static void rtl2832_i2c_gate_work(struct work_struct *work)
856 {
857 struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
858 struct i2c_client *client = dev->client;
859 int ret;
860
861 /* close gate */
862 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
863 if (ret)
864 goto err;
865
866 return;
867 err:
868 dev_dbg(&client->dev, "failed=%d\n", ret);
869 return;
870 }
871
872 static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id)
873 {
874 struct rtl2832_dev *dev = mux_priv;
875 struct i2c_client *client = dev->client;
876 int ret;
877
878 /* terminate possible gate closing */
879 cancel_delayed_work(&dev->i2c_gate_work);
880
881 /*
882 * chan_id 1 is muxed adapter demod provides and chan_id 0 is demod
883 * itself. We need open gate when request is for chan_id 1. On that case
884 * I2C adapter lock is already taken and due to that we will use
885 * regmap_update_bits() which does not lock again I2C adapter.
886 */
887 if (chan_id == 1)
888 ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
889 else
890 ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
891 if (ret)
892 goto err;
893
894 return 0;
895 err:
896 dev_dbg(&client->dev, "failed=%d\n", ret);
897 return ret;
898 }
899
900 static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv,
901 u32 chan_id)
902 {
903 struct rtl2832_dev *dev = mux_priv;
904
905 schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
906 return 0;
907 }
908
909 static struct dvb_frontend_ops rtl2832_ops = {
910 .delsys = { SYS_DVBT },
911 .info = {
912 .name = "Realtek RTL2832 (DVB-T)",
913 .frequency_min = 174000000,
914 .frequency_max = 862000000,
915 .frequency_stepsize = 166667,
916 .caps = FE_CAN_FEC_1_2 |
917 FE_CAN_FEC_2_3 |
918 FE_CAN_FEC_3_4 |
919 FE_CAN_FEC_5_6 |
920 FE_CAN_FEC_7_8 |
921 FE_CAN_FEC_AUTO |
922 FE_CAN_QPSK |
923 FE_CAN_QAM_16 |
924 FE_CAN_QAM_64 |
925 FE_CAN_QAM_AUTO |
926 FE_CAN_TRANSMISSION_MODE_AUTO |
927 FE_CAN_GUARD_INTERVAL_AUTO |
928 FE_CAN_HIERARCHY_AUTO |
929 FE_CAN_RECOVER |
930 FE_CAN_MUTE_TS
931 },
932
933 .init = rtl2832_init,
934 .sleep = rtl2832_sleep,
935
936 .get_tune_settings = rtl2832_get_tune_settings,
937
938 .set_frontend = rtl2832_set_frontend,
939 .get_frontend = rtl2832_get_frontend,
940
941 .read_status = rtl2832_read_status,
942 .read_snr = rtl2832_read_snr,
943 .read_ber = rtl2832_read_ber,
944 };
945
946 static bool rtl2832_volatile_reg(struct device *dev, unsigned int reg)
947 {
948 switch (reg) {
949 case 0x305:
950 case 0x33c:
951 case 0x34e:
952 case 0x351:
953 case 0x40c ... 0x40d:
954 return true;
955 default:
956 break;
957 }
958
959 return false;
960 }
961
962 /*
963 * We implement own I2C access routines for regmap in order to get manual access
964 * to I2C adapter lock, which is needed for I2C mux adapter.
965 */
966 static int rtl2832_regmap_read(void *context, const void *reg_buf,
967 size_t reg_size, void *val_buf, size_t val_size)
968 {
969 struct i2c_client *client = context;
970 int ret;
971 struct i2c_msg msg[2] = {
972 {
973 .addr = client->addr,
974 .flags = 0,
975 .len = reg_size,
976 .buf = (u8 *)reg_buf,
977 }, {
978 .addr = client->addr,
979 .flags = I2C_M_RD,
980 .len = val_size,
981 .buf = val_buf,
982 }
983 };
984
985 ret = __i2c_transfer(client->adapter, msg, 2);
986 if (ret != 2) {
987 dev_warn(&client->dev, "i2c reg read failed %d\n", ret);
988 if (ret >= 0)
989 ret = -EREMOTEIO;
990 return ret;
991 }
992 return 0;
993 }
994
995 static int rtl2832_regmap_write(void *context, const void *data, size_t count)
996 {
997 struct i2c_client *client = context;
998 int ret;
999 struct i2c_msg msg[1] = {
1000 {
1001 .addr = client->addr,
1002 .flags = 0,
1003 .len = count,
1004 .buf = (u8 *)data,
1005 }
1006 };
1007
1008 ret = __i2c_transfer(client->adapter, msg, 1);
1009 if (ret != 1) {
1010 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
1011 if (ret >= 0)
1012 ret = -EREMOTEIO;
1013 return ret;
1014 }
1015 return 0;
1016 }
1017
1018 static int rtl2832_regmap_gather_write(void *context, const void *reg,
1019 size_t reg_len, const void *val,
1020 size_t val_len)
1021 {
1022 struct i2c_client *client = context;
1023 int ret;
1024 u8 buf[256];
1025 struct i2c_msg msg[1] = {
1026 {
1027 .addr = client->addr,
1028 .flags = 0,
1029 .len = 1 + val_len,
1030 .buf = buf,
1031 }
1032 };
1033
1034 buf[0] = *(u8 const *)reg;
1035 memcpy(&buf[1], val, val_len);
1036
1037 ret = __i2c_transfer(client->adapter, msg, 1);
1038 if (ret != 1) {
1039 dev_warn(&client->dev, "i2c reg write failed %d\n", ret);
1040 if (ret >= 0)
1041 ret = -EREMOTEIO;
1042 return ret;
1043 }
1044 return 0;
1045 }
1046
1047 static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
1048 {
1049 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1050
1051 dev_dbg(&client->dev, "\n");
1052 return &dev->fe;
1053 }
1054
1055 static struct i2c_adapter *rtl2832_get_i2c_adapter_(struct i2c_client *client)
1056 {
1057 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1058
1059 dev_dbg(&client->dev, "\n");
1060 return dev->i2c_adapter_tuner;
1061 }
1062
1063 static struct i2c_adapter *rtl2832_get_private_i2c_adapter_(struct i2c_client *client)
1064 {
1065 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1066
1067 dev_dbg(&client->dev, "\n");
1068 return dev->i2c_adapter;
1069 }
1070
1071 static int rtl2832_enable_slave_ts(struct i2c_client *client)
1072 {
1073 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1074 int ret;
1075
1076 dev_dbg(&client->dev, "\n");
1077
1078 ret = rtl2832_bulk_write(client, 0x10c, "\x5f\xff", 2);
1079 if (ret)
1080 goto err;
1081
1082 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
1083 if (ret)
1084 goto err;
1085
1086 ret = rtl2832_bulk_write(client, 0x0bc, "\x18", 1);
1087 if (ret)
1088 goto err;
1089
1090 ret = rtl2832_bulk_write(client, 0x022, "\x01", 1);
1091 if (ret)
1092 goto err;
1093
1094 ret = rtl2832_bulk_write(client, 0x026, "\x1f", 1);
1095 if (ret)
1096 goto err;
1097
1098 ret = rtl2832_bulk_write(client, 0x027, "\xff", 1);
1099 if (ret)
1100 goto err;
1101
1102 ret = rtl2832_bulk_write(client, 0x192, "\x7f\xf7\xff", 3);
1103 if (ret)
1104 goto err;
1105
1106 /* soft reset */
1107 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
1108 if (ret)
1109 goto err;
1110
1111 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
1112 if (ret)
1113 goto err;
1114
1115 return 0;
1116 err:
1117 dev_dbg(&client->dev, "failed=%d\n", ret);
1118 return ret;
1119 }
1120
1121 static int rtl2832_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
1122 {
1123 struct rtl2832_dev *dev = fe->demodulator_priv;
1124 struct i2c_client *client = dev->client;
1125 int ret;
1126 u8 u8tmp;
1127
1128 dev_dbg(&client->dev, "onoff=%d\n", onoff);
1129
1130 /* enable / disable PID filter */
1131 if (onoff)
1132 u8tmp = 0x80;
1133 else
1134 u8tmp = 0x00;
1135
1136 ret = rtl2832_update_bits(client, 0x061, 0xc0, u8tmp);
1137 if (ret)
1138 goto err;
1139
1140 return 0;
1141 err:
1142 dev_dbg(&client->dev, "failed=%d\n", ret);
1143 return ret;
1144 }
1145
1146 static int rtl2832_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid,
1147 int onoff)
1148 {
1149 struct rtl2832_dev *dev = fe->demodulator_priv;
1150 struct i2c_client *client = dev->client;
1151 int ret;
1152 u8 buf[4];
1153
1154 dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
1155 index, pid, onoff);
1156
1157 /* skip invalid PIDs (0x2000) */
1158 if (pid > 0x1fff || index > 32)
1159 return 0;
1160
1161 if (onoff)
1162 set_bit(index, &dev->filters);
1163 else
1164 clear_bit(index, &dev->filters);
1165
1166 /* enable / disable PIDs */
1167 buf[0] = (dev->filters >> 0) & 0xff;
1168 buf[1] = (dev->filters >> 8) & 0xff;
1169 buf[2] = (dev->filters >> 16) & 0xff;
1170 buf[3] = (dev->filters >> 24) & 0xff;
1171 ret = rtl2832_bulk_write(client, 0x062, buf, 4);
1172 if (ret)
1173 goto err;
1174
1175 /* add PID */
1176 buf[0] = (pid >> 8) & 0xff;
1177 buf[1] = (pid >> 0) & 0xff;
1178 ret = rtl2832_bulk_write(client, 0x066 + 2 * index, buf, 2);
1179 if (ret)
1180 goto err;
1181
1182 return 0;
1183 err:
1184 dev_dbg(&client->dev, "failed=%d\n", ret);
1185 return ret;
1186 }
1187
1188 static int rtl2832_probe(struct i2c_client *client,
1189 const struct i2c_device_id *id)
1190 {
1191 struct rtl2832_platform_data *pdata = client->dev.platform_data;
1192 struct i2c_adapter *i2c = client->adapter;
1193 struct rtl2832_dev *dev;
1194 int ret;
1195 u8 tmp;
1196 static const struct regmap_bus regmap_bus = {
1197 .read = rtl2832_regmap_read,
1198 .write = rtl2832_regmap_write,
1199 .gather_write = rtl2832_regmap_gather_write,
1200 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1201 };
1202 static const struct regmap_range_cfg regmap_range_cfg[] = {
1203 {
1204 .selector_reg = 0x00,
1205 .selector_mask = 0xff,
1206 .selector_shift = 0,
1207 .window_start = 0,
1208 .window_len = 0x100,
1209 .range_min = 0 * 0x100,
1210 .range_max = 5 * 0x100,
1211 },
1212 };
1213 static const struct regmap_config regmap_config = {
1214 .reg_bits = 8,
1215 .val_bits = 8,
1216 .volatile_reg = rtl2832_volatile_reg,
1217 .max_register = 5 * 0x100,
1218 .ranges = regmap_range_cfg,
1219 .num_ranges = ARRAY_SIZE(regmap_range_cfg),
1220 .cache_type = REGCACHE_RBTREE,
1221 };
1222
1223 dev_dbg(&client->dev, "\n");
1224
1225 /* allocate memory for the internal state */
1226 dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
1227 if (dev == NULL) {
1228 ret = -ENOMEM;
1229 goto err;
1230 }
1231
1232 /* setup the state */
1233 i2c_set_clientdata(client, dev);
1234 dev->client = client;
1235 dev->pdata = client->dev.platform_data;
1236 if (pdata->config) {
1237 dev->pdata->clk = pdata->config->xtal;
1238 dev->pdata->tuner = pdata->config->tuner;
1239 }
1240 dev->sleeping = true;
1241 INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
1242 INIT_DELAYED_WORK(&dev->stat_work, rtl2832_stat_work);
1243 /* create regmap */
1244 dev->regmap = regmap_init(&client->dev, &regmap_bus, client,
1245 &regmap_config);
1246 if (IS_ERR(dev->regmap)) {
1247 ret = PTR_ERR(dev->regmap);
1248 goto err_kfree;
1249 }
1250 /* create muxed i2c adapter for demod itself */
1251 dev->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, dev, 0, 0, 0,
1252 rtl2832_select, NULL);
1253 if (dev->i2c_adapter == NULL) {
1254 ret = -ENODEV;
1255 goto err_regmap_exit;
1256 }
1257
1258 /* check if the demod is there */
1259 ret = rtl2832_bulk_read(client, 0x000, &tmp, 1);
1260 if (ret)
1261 goto err_i2c_del_mux_adapter;
1262
1263 /* create muxed i2c adapter for demod tuner bus */
1264 dev->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, dev,
1265 0, 1, 0, rtl2832_select, rtl2832_deselect);
1266 if (dev->i2c_adapter_tuner == NULL) {
1267 ret = -ENODEV;
1268 goto err_i2c_del_mux_adapter;
1269 }
1270
1271 /* create dvb_frontend */
1272 memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1273 dev->fe.demodulator_priv = dev;
1274
1275 /* setup callbacks */
1276 pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
1277 pdata->get_i2c_adapter = rtl2832_get_i2c_adapter_;
1278 pdata->get_private_i2c_adapter = rtl2832_get_private_i2c_adapter_;
1279 pdata->enable_slave_ts = rtl2832_enable_slave_ts;
1280 pdata->pid_filter = rtl2832_pid_filter;
1281 pdata->pid_filter_ctrl = rtl2832_pid_filter_ctrl;
1282 pdata->bulk_read = rtl2832_bulk_read;
1283 pdata->bulk_write = rtl2832_bulk_write;
1284 pdata->update_bits = rtl2832_update_bits;
1285
1286 dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
1287 return 0;
1288 err_i2c_del_mux_adapter:
1289 i2c_del_mux_adapter(dev->i2c_adapter);
1290 err_regmap_exit:
1291 regmap_exit(dev->regmap);
1292 err_kfree:
1293 kfree(dev);
1294 err:
1295 dev_dbg(&client->dev, "failed=%d\n", ret);
1296 return ret;
1297 }
1298
1299 static int rtl2832_remove(struct i2c_client *client)
1300 {
1301 struct rtl2832_dev *dev = i2c_get_clientdata(client);
1302
1303 dev_dbg(&client->dev, "\n");
1304
1305 cancel_delayed_work_sync(&dev->i2c_gate_work);
1306
1307 i2c_del_mux_adapter(dev->i2c_adapter_tuner);
1308
1309 i2c_del_mux_adapter(dev->i2c_adapter);
1310
1311 regmap_exit(dev->regmap);
1312
1313 kfree(dev);
1314
1315 return 0;
1316 }
1317
1318 static const struct i2c_device_id rtl2832_id_table[] = {
1319 {"rtl2832", 0},
1320 {}
1321 };
1322 MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
1323
1324 static struct i2c_driver rtl2832_driver = {
1325 .driver = {
1326 .owner = THIS_MODULE,
1327 .name = "rtl2832",
1328 },
1329 .probe = rtl2832_probe,
1330 .remove = rtl2832_remove,
1331 .id_table = rtl2832_id_table,
1332 };
1333
1334 module_i2c_driver(rtl2832_driver);
1335
1336 MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
1337 MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1338 MODULE_LICENSE("GPL");
1339 MODULE_VERSION("0.5");
Linux kernel - Deliverables
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