drivers/media/dvb-frontends/rtl2832.c

   1 /*
   2  * Realtek RTL2832 DVB-T demodulator driver
   3  *
   4  * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
   5  *
   6  *      This program is free software; you can redistribute it and/or modify
   7  *      it under the terms of the GNU General Public License as published by
   8  *      the Free Software Foundation; either version 2 of the License, or
   9  *      (at your option) any later version.
  10  *
  11  *      This program is distributed in the hope that it will be useful,
  12  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *      GNU General Public License for more details.
  15  *
  16  *      You should have received a copy of the GNU General Public License along
  17  *      with this program; if not, write to the Free Software Foundation, Inc.,
  18  *      51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 #include "rtl2832_priv.h"
  22 #include "dvb_math.h"
  23 #include <linux/bitops.h>
  24
  25 /* Max transfer size done by I2C transfer functions */
  26 #define MAX_XFER_SIZE  64
  27 #define REG_MASK(b) (BIT(b + 1) - 1)
  28
  29 static const struct rtl2832_reg_entry registers[] = {
  30         [DVBT_SOFT_RST]         = {0x1, 0x1,   2, 2},
  31         [DVBT_IIC_REPEAT]       = {0x1, 0x1,   3, 3},
  32         [DVBT_TR_WAIT_MIN_8K]   = {0x1, 0x88, 11, 2},
  33         [DVBT_RSD_BER_FAIL_VAL] = {0x1, 0x8f, 15, 0},
  34         [DVBT_EN_BK_TRK]        = {0x1, 0xa6,  7, 7},
  35         [DVBT_AD_EN_REG]        = {0x0, 0x8,   7, 7},
  36         [DVBT_AD_EN_REG1]       = {0x0, 0x8,   6, 6},
  37         [DVBT_EN_BBIN]          = {0x1, 0xb1,  0, 0},
  38         [DVBT_MGD_THD0]         = {0x1, 0x95,  7, 0},
  39         [DVBT_MGD_THD1]         = {0x1, 0x96,  7, 0},
  40         [DVBT_MGD_THD2]         = {0x1, 0x97,  7, 0},
  41         [DVBT_MGD_THD3]         = {0x1, 0x98,  7, 0},
  42         [DVBT_MGD_THD4]         = {0x1, 0x99,  7, 0},
  43         [DVBT_MGD_THD5]         = {0x1, 0x9a,  7, 0},
  44         [DVBT_MGD_THD6]         = {0x1, 0x9b,  7, 0},
  45         [DVBT_MGD_THD7]         = {0x1, 0x9c,  7, 0},
  46         [DVBT_EN_CACQ_NOTCH]    = {0x1, 0x61,  4, 4},
  47         [DVBT_AD_AV_REF]        = {0x0, 0x9,   6, 0},
  48         [DVBT_REG_PI]           = {0x0, 0xa,   2, 0},
  49         [DVBT_PIP_ON]           = {0x0, 0x21,  3, 3},
  50         [DVBT_SCALE1_B92]       = {0x2, 0x92,  7, 0},
  51         [DVBT_SCALE1_B93]       = {0x2, 0x93,  7, 0},
  52         [DVBT_SCALE1_BA7]       = {0x2, 0xa7,  7, 0},
  53         [DVBT_SCALE1_BA9]       = {0x2, 0xa9,  7, 0},
  54         [DVBT_SCALE1_BAA]       = {0x2, 0xaa,  7, 0},
  55         [DVBT_SCALE1_BAB]       = {0x2, 0xab,  7, 0},
  56         [DVBT_SCALE1_BAC]       = {0x2, 0xac,  7, 0},
  57         [DVBT_SCALE1_BB0]       = {0x2, 0xb0,  7, 0},
  58         [DVBT_SCALE1_BB1]       = {0x2, 0xb1,  7, 0},
  59         [DVBT_KB_P1]            = {0x1, 0x64,  3, 1},
  60         [DVBT_KB_P2]            = {0x1, 0x64,  6, 4},
  61         [DVBT_KB_P3]            = {0x1, 0x65,  2, 0},
  62         [DVBT_OPT_ADC_IQ]       = {0x0, 0x6,   5, 4},
  63         [DVBT_AD_AVI]           = {0x0, 0x9,   1, 0},
  64         [DVBT_AD_AVQ]           = {0x0, 0x9,   3, 2},
  65         [DVBT_K1_CR_STEP12]     = {0x2, 0xad,  9, 4},
  66         [DVBT_TRK_KS_P2]        = {0x1, 0x6f,  2, 0},
  67         [DVBT_TRK_KS_I2]        = {0x1, 0x70,  5, 3},
  68         [DVBT_TR_THD_SET2]      = {0x1, 0x72,  3, 0},
  69         [DVBT_TRK_KC_P2]        = {0x1, 0x73,  5, 3},
  70         [DVBT_TRK_KC_I2]        = {0x1, 0x75,  2, 0},
  71         [DVBT_CR_THD_SET2]      = {0x1, 0x76,  7, 6},
  72         [DVBT_PSET_IFFREQ]      = {0x1, 0x19, 21, 0},
  73         [DVBT_SPEC_INV]         = {0x1, 0x15,  0, 0},
  74         [DVBT_RSAMP_RATIO]      = {0x1, 0x9f, 27, 2},
  75         [DVBT_CFREQ_OFF_RATIO]  = {0x1, 0x9d, 23, 4},
  76         [DVBT_FSM_STAGE]        = {0x3, 0x51,  6, 3},
  77         [DVBT_RX_CONSTEL]       = {0x3, 0x3c,  3, 2},
  78         [DVBT_RX_HIER]          = {0x3, 0x3c,  6, 4},
  79         [DVBT_RX_C_RATE_LP]     = {0x3, 0x3d,  2, 0},
  80         [DVBT_RX_C_RATE_HP]     = {0x3, 0x3d,  5, 3},
  81         [DVBT_GI_IDX]           = {0x3, 0x51,  1, 0},
  82         [DVBT_FFT_MODE_IDX]     = {0x3, 0x51,  2, 2},
  83         [DVBT_RSD_BER_EST]      = {0x3, 0x4e, 15, 0},
  84         [DVBT_CE_EST_EVM]       = {0x4, 0xc,  15, 0},
  85         [DVBT_RF_AGC_VAL]       = {0x3, 0x5b, 13, 0},
  86         [DVBT_IF_AGC_VAL]       = {0x3, 0x59, 13, 0},
  87         [DVBT_DAGC_VAL]         = {0x3, 0x5,   7, 0},
  88         [DVBT_SFREQ_OFF]        = {0x3, 0x18, 13, 0},
  89         [DVBT_CFREQ_OFF]        = {0x3, 0x5f, 17, 0},
  90         [DVBT_POLAR_RF_AGC]     = {0x0, 0xe,   1, 1},
  91         [DVBT_POLAR_IF_AGC]     = {0x0, 0xe,   0, 0},
  92         [DVBT_AAGC_HOLD]        = {0x1, 0x4,   5, 5},
  93         [DVBT_EN_RF_AGC]        = {0x1, 0x4,   6, 6},
  94         [DVBT_EN_IF_AGC]        = {0x1, 0x4,   7, 7},
  95         [DVBT_IF_AGC_MIN]       = {0x1, 0x8,   7, 0},
  96         [DVBT_IF_AGC_MAX]       = {0x1, 0x9,   7, 0},
  97         [DVBT_RF_AGC_MIN]       = {0x1, 0xa,   7, 0},
  98         [DVBT_RF_AGC_MAX]       = {0x1, 0xb,   7, 0},
  99         [DVBT_IF_AGC_MAN]       = {0x1, 0xc,   6, 6},
 100         [DVBT_IF_AGC_MAN_VAL]   = {0x1, 0xc,  13, 0},
 101         [DVBT_RF_AGC_MAN]       = {0x1, 0xe,   6, 6},
 102         [DVBT_RF_AGC_MAN_VAL]   = {0x1, 0xe,  13, 0},
 103         [DVBT_DAGC_TRG_VAL]     = {0x1, 0x12,  7, 0},
 104         [DVBT_AGC_TARG_VAL_0]   = {0x1, 0x2,   0, 0},
 105         [DVBT_AGC_TARG_VAL_8_1] = {0x1, 0x3,   7, 0},
 106         [DVBT_AAGC_LOOP_GAIN]   = {0x1, 0xc7,  5, 1},
 107         [DVBT_LOOP_GAIN2_3_0]   = {0x1, 0x4,   4, 1},
 108         [DVBT_LOOP_GAIN2_4]     = {0x1, 0x5,   7, 7},
 109         [DVBT_LOOP_GAIN3]       = {0x1, 0xc8,  4, 0},
 110         [DVBT_VTOP1]            = {0x1, 0x6,   5, 0},
 111         [DVBT_VTOP2]            = {0x1, 0xc9,  5, 0},
 112         [DVBT_VTOP3]            = {0x1, 0xca,  5, 0},
 113         [DVBT_KRF1]             = {0x1, 0xcb,  7, 0},
 114         [DVBT_KRF2]             = {0x1, 0x7,   7, 0},
 115         [DVBT_KRF3]             = {0x1, 0xcd,  7, 0},
 116         [DVBT_KRF4]             = {0x1, 0xce,  7, 0},
 117         [DVBT_EN_GI_PGA]        = {0x1, 0xe5,  0, 0},
 118         [DVBT_THD_LOCK_UP]      = {0x1, 0xd9,  8, 0},
 119         [DVBT_THD_LOCK_DW]      = {0x1, 0xdb,  8, 0},
 120         [DVBT_THD_UP1]          = {0x1, 0xdd,  7, 0},
 121         [DVBT_THD_DW1]          = {0x1, 0xde,  7, 0},
 122         [DVBT_INTER_CNT_LEN]    = {0x1, 0xd8,  3, 0},
 123         [DVBT_GI_PGA_STATE]     = {0x1, 0xe6,  3, 3},
 124         [DVBT_EN_AGC_PGA]       = {0x1, 0xd7,  0, 0},
 125         [DVBT_CKOUTPAR]         = {0x1, 0x7b,  5, 5},
 126         [DVBT_CKOUT_PWR]        = {0x1, 0x7b,  6, 6},
 127         [DVBT_SYNC_DUR]         = {0x1, 0x7b,  7, 7},
 128         [DVBT_ERR_DUR]          = {0x1, 0x7c,  0, 0},
 129         [DVBT_SYNC_LVL]         = {0x1, 0x7c,  1, 1},
 130         [DVBT_ERR_LVL]          = {0x1, 0x7c,  2, 2},
 131         [DVBT_VAL_LVL]          = {0x1, 0x7c,  3, 3},
 132         [DVBT_SERIAL]           = {0x1, 0x7c,  4, 4},
 133         [DVBT_SER_LSB]          = {0x1, 0x7c,  5, 5},
 134         [DVBT_CDIV_PH0]         = {0x1, 0x7d,  3, 0},
 135         [DVBT_CDIV_PH1]         = {0x1, 0x7d,  7, 4},
 136         [DVBT_MPEG_IO_OPT_2_2]  = {0x0, 0x6,   7, 7},
 137         [DVBT_MPEG_IO_OPT_1_0]  = {0x0, 0x7,   7, 6},
 138         [DVBT_CKOUTPAR_PIP]     = {0x0, 0xb7,  4, 4},
 139         [DVBT_CKOUT_PWR_PIP]    = {0x0, 0xb7,  3, 3},
 140         [DVBT_SYNC_LVL_PIP]     = {0x0, 0xb7,  2, 2},
 141         [DVBT_ERR_LVL_PIP]      = {0x0, 0xb7,  1, 1},
 142         [DVBT_VAL_LVL_PIP]      = {0x0, 0xb7,  0, 0},
 143         [DVBT_CKOUTPAR_PID]     = {0x0, 0xb9,  4, 4},
 144         [DVBT_CKOUT_PWR_PID]    = {0x0, 0xb9,  3, 3},
 145         [DVBT_SYNC_LVL_PID]     = {0x0, 0xb9,  2, 2},
 146         [DVBT_ERR_LVL_PID]      = {0x0, 0xb9,  1, 1},
 147         [DVBT_VAL_LVL_PID]      = {0x0, 0xb9,  0, 0},
 148         [DVBT_SM_PASS]          = {0x1, 0x93, 11, 0},
 149         [DVBT_AD7_SETTING]      = {0x0, 0x11, 15, 0},
 150         [DVBT_RSSI_R]           = {0x3, 0x1,   6, 0},
 151         [DVBT_ACI_DET_IND]      = {0x3, 0x12,  0, 0},
 152         [DVBT_REG_MON]          = {0x0, 0xd,   1, 0},
 153         [DVBT_REG_MONSEL]       = {0x0, 0xd,   2, 2},
 154         [DVBT_REG_GPE]          = {0x0, 0xd,   7, 7},
 155         [DVBT_REG_GPO]          = {0x0, 0x10,  0, 0},
 156         [DVBT_REG_4MSEL]        = {0x0, 0x13,  0, 0},
 157 };
 158
 159 /* write multiple hardware registers */
 160 static int rtl2832_wr(struct rtl2832_priv *priv, u8 reg, u8 *val, int len)
 161 {
 162         int ret;
 163         u8 buf[MAX_XFER_SIZE];
 164         struct i2c_msg msg[1] = {
 165                 {
 166                         .addr = priv->cfg.i2c_addr,
 167                         .flags = 0,
 168                         .len = 1 + len,
 169                         .buf = buf,
 170                 }
 171         };
 172
 173         if (1 + len > sizeof(buf)) {
 174                 dev_warn(&priv->i2c->dev,
 175                          "%s: i2c wr reg=%04x: len=%d is too big!\n",
 176                          KBUILD_MODNAME, reg, len);
 177                 return -EINVAL;
 178         }
 179
 180         buf[0] = reg;
 181         memcpy(&buf[1], val, len);
 182
 183         ret = i2c_transfer(priv->i2c, msg, 1);
 184         if (ret == 1) {
 185                 ret = 0;
 186         } else {
 187                 dev_warn(&priv->i2c->dev,
 188                                 "%s: i2c wr failed=%d reg=%02x len=%d\n",
 189                                 KBUILD_MODNAME, ret, reg, len);
 190                 ret = -EREMOTEIO;
 191         }
 192         return ret;
 193 }
 194
 195 /* read multiple hardware registers */
 196 static int rtl2832_rd(struct rtl2832_priv *priv, u8 reg, u8 *val, int len)
 197 {
 198         int ret;
 199         struct i2c_msg msg[2] = {
 200                 {
 201                         .addr = priv->cfg.i2c_addr,
 202                         .flags = 0,
 203                         .len = 1,
 204                         .buf = &reg,
 205                 }, {
 206                         .addr = priv->cfg.i2c_addr,
 207                         .flags = I2C_M_RD,
 208                         .len = len,
 209                         .buf = val,
 210                 }
 211         };
 212
 213         ret = i2c_transfer(priv->i2c, msg, 2);
 214         if (ret == 2) {
 215                 ret = 0;
 216         } else {
 217                 dev_warn(&priv->i2c->dev,
 218                                 "%s: i2c rd failed=%d reg=%02x len=%d\n",
 219                                 KBUILD_MODNAME, ret, reg, len);
 220                 ret = -EREMOTEIO;
 221         }
 222         return ret;
 223 }
 224
 225 /* write multiple registers */
 226 static int rtl2832_wr_regs(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val,
 227         int len)
 228 {
 229         int ret;
 230
 231         /* switch bank if needed */
 232         if (page != priv->page) {
 233                 ret = rtl2832_wr(priv, 0x00, &page, 1);
 234                 if (ret)
 235                         return ret;
 236
 237                 priv->page = page;
 238 }
 239
 240 return rtl2832_wr(priv, reg, val, len);
 241 }
 242
 243 /* read multiple registers */
 244 static int rtl2832_rd_regs(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val,
 245         int len)
 246 {
 247         int ret;
 248
 249         /* switch bank if needed */
 250         if (page != priv->page) {
 251                 ret = rtl2832_wr(priv, 0x00, &page, 1);
 252                 if (ret)
 253                         return ret;
 254
 255                 priv->page = page;
 256         }
 257
 258         return rtl2832_rd(priv, reg, val, len);
 259 }
 260
 261 #if 0 /* currently not used */
 262 /* write single register */
 263 static int rtl2832_wr_reg(struct rtl2832_priv *priv, u8 reg, u8 page, u8 val)
 264 {
 265         return rtl2832_wr_regs(priv, reg, page, &val, 1);
 266 }
 267 #endif
 268
 269 /* read single register */
 270 static int rtl2832_rd_reg(struct rtl2832_priv *priv, u8 reg, u8 page, u8 *val)
 271 {
 272         return rtl2832_rd_regs(priv, reg, page, val, 1);
 273 }
 274
 275 static int rtl2832_rd_demod_reg(struct rtl2832_priv *priv, int reg, u32 *val)
 276 {
 277         int ret;
 278
 279         u8 reg_start_addr;
 280         u8 msb, lsb;
 281         u8 page;
 282         u8 reading[4];
 283         u32 reading_tmp;
 284         int i;
 285
 286         u8 len;
 287         u32 mask;
 288
 289         reg_start_addr = registers[reg].start_address;
 290         msb = registers[reg].msb;
 291         lsb = registers[reg].lsb;
 292         page = registers[reg].page;
 293
 294         len = (msb >> 3) + 1;
 295         mask = REG_MASK(msb - lsb);
 296
 297         ret = rtl2832_rd_regs(priv, reg_start_addr, page, &reading[0], len);
 298         if (ret)
 299                 goto err;
 300
 301         reading_tmp = 0;
 302         for (i = 0; i < len; i++)
 303                 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
 304
 305         *val = (reading_tmp >> lsb) & mask;
 306
 307         return ret;
 308
 309 err:
 310         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 311         return ret;
 312
 313 }
 314
 315 static int rtl2832_wr_demod_reg(struct rtl2832_priv *priv, int reg, u32 val)
 316 {
 317         int ret, i;
 318         u8 len;
 319         u8 reg_start_addr;
 320         u8 msb, lsb;
 321         u8 page;
 322         u32 mask;
 323
 324
 325         u8 reading[4];
 326         u8 writing[4];
 327         u32 reading_tmp;
 328         u32 writing_tmp;
 329
 330
 331         reg_start_addr = registers[reg].start_address;
 332         msb = registers[reg].msb;
 333         lsb = registers[reg].lsb;
 334         page = registers[reg].page;
 335
 336         len = (msb >> 3) + 1;
 337         mask = REG_MASK(msb - lsb);
 338
 339
 340         ret = rtl2832_rd_regs(priv, reg_start_addr, page, &reading[0], len);
 341         if (ret)
 342                 goto err;
 343
 344         reading_tmp = 0;
 345         for (i = 0; i < len; i++)
 346                 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
 347
 348         writing_tmp = reading_tmp & ~(mask << lsb);
 349         writing_tmp |= ((val & mask) << lsb);
 350
 351
 352         for (i = 0; i < len; i++)
 353                 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
 354
 355         ret = rtl2832_wr_regs(priv, reg_start_addr, page, &writing[0], len);
 356         if (ret)
 357                 goto err;
 358
 359         return ret;
 360
 361 err:
 362         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 363         return ret;
 364
 365 }
 366
 367 static int rtl2832_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 368 {
 369         int ret;
 370         struct rtl2832_priv *priv = fe->demodulator_priv;
 371
 372         dev_dbg(&priv->i2c->dev, "%s: enable=%d\n", __func__, enable);
 373
 374         /* gate already open or close */
 375         if (priv->i2c_gate_state == enable)
 376                 return 0;
 377
 378         ret = rtl2832_wr_demod_reg(priv, DVBT_IIC_REPEAT, (enable ? 0x1 : 0x0));
 379         if (ret)
 380                 goto err;
 381
 382         priv->i2c_gate_state = enable;
 383
 384         return ret;
 385 err:
 386         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 387         return ret;
 388 }
 389
 390
 391 static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
 392 {
 393         struct rtl2832_priv *priv = fe->demodulator_priv;
 394         int ret;
 395         u64 pset_iffreq;
 396         u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
 397
 398         /*
 399         * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
 400         *               / CrystalFreqHz)
 401         */
 402
 403         pset_iffreq = if_freq % priv->cfg.xtal;
 404         pset_iffreq *= 0x400000;
 405         pset_iffreq = div_u64(pset_iffreq, priv->cfg.xtal);
 406         pset_iffreq = -pset_iffreq;
 407         pset_iffreq = pset_iffreq & 0x3fffff;
 408         dev_dbg(&priv->i2c->dev, "%s: if_frequency=%d pset_iffreq=%08x\n",
 409                         __func__, if_freq, (unsigned)pset_iffreq);
 410
 411         ret = rtl2832_wr_demod_reg(priv, DVBT_EN_BBIN, en_bbin);
 412         if (ret)
 413                 return ret;
 414
 415         ret = rtl2832_wr_demod_reg(priv, DVBT_PSET_IFFREQ, pset_iffreq);
 416
 417         return ret;
 418 }
 419
 420 static int rtl2832_init(struct dvb_frontend *fe)
 421 {
 422         struct rtl2832_priv *priv = fe->demodulator_priv;
 423         const struct rtl2832_reg_value *init;
 424         int i, ret, len;
 425
 426         /* initialization values for the demodulator registers */
 427         struct rtl2832_reg_value rtl2832_initial_regs[] = {
 428                 {DVBT_AD_EN_REG,                0x1},
 429                 {DVBT_AD_EN_REG1,               0x1},
 430                 {DVBT_RSD_BER_FAIL_VAL,         0x2800},
 431                 {DVBT_MGD_THD0,                 0x10},
 432                 {DVBT_MGD_THD1,                 0x20},
 433                 {DVBT_MGD_THD2,                 0x20},
 434                 {DVBT_MGD_THD3,                 0x40},
 435                 {DVBT_MGD_THD4,                 0x22},
 436                 {DVBT_MGD_THD5,                 0x32},
 437                 {DVBT_MGD_THD6,                 0x37},
 438                 {DVBT_MGD_THD7,                 0x39},
 439                 {DVBT_EN_BK_TRK,                0x0},
 440                 {DVBT_EN_CACQ_NOTCH,            0x0},
 441                 {DVBT_AD_AV_REF,                0x2a},
 442                 {DVBT_REG_PI,                   0x6},
 443                 {DVBT_PIP_ON,                   0x0},
 444                 {DVBT_CDIV_PH0,                 0x8},
 445                 {DVBT_CDIV_PH1,                 0x8},
 446                 {DVBT_SCALE1_B92,               0x4},
 447                 {DVBT_SCALE1_B93,               0xb0},
 448                 {DVBT_SCALE1_BA7,               0x78},
 449                 {DVBT_SCALE1_BA9,               0x28},
 450                 {DVBT_SCALE1_BAA,               0x59},
 451                 {DVBT_SCALE1_BAB,               0x83},
 452                 {DVBT_SCALE1_BAC,               0xd4},
 453                 {DVBT_SCALE1_BB0,               0x65},
 454                 {DVBT_SCALE1_BB1,               0x43},
 455                 {DVBT_KB_P1,                    0x1},
 456                 {DVBT_KB_P2,                    0x4},
 457                 {DVBT_KB_P3,                    0x7},
 458                 {DVBT_K1_CR_STEP12,             0xa},
 459                 {DVBT_REG_GPE,                  0x1},
 460                 {DVBT_SERIAL,                   0x0},
 461                 {DVBT_CDIV_PH0,                 0x9},
 462                 {DVBT_CDIV_PH1,                 0x9},
 463                 {DVBT_MPEG_IO_OPT_2_2,          0x0},
 464                 {DVBT_MPEG_IO_OPT_1_0,          0x0},
 465                 {DVBT_TRK_KS_P2,                0x4},
 466                 {DVBT_TRK_KS_I2,                0x7},
 467                 {DVBT_TR_THD_SET2,              0x6},
 468                 {DVBT_TRK_KC_I2,                0x5},
 469                 {DVBT_CR_THD_SET2,              0x1},
 470         };
 471
 472         dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
 473
 474         for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
 475                 ret = rtl2832_wr_demod_reg(priv, rtl2832_initial_regs[i].reg,
 476                         rtl2832_initial_regs[i].value);
 477                 if (ret)
 478                         goto err;
 479         }
 480
 481         /* load tuner specific settings */
 482         dev_dbg(&priv->i2c->dev, "%s: load settings for tuner=%02x\n",
 483                         __func__, priv->cfg.tuner);
 484         switch (priv->cfg.tuner) {
 485         case RTL2832_TUNER_FC0012:
 486         case RTL2832_TUNER_FC0013:
 487                 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
 488                 init = rtl2832_tuner_init_fc0012;
 489                 break;
 490         case RTL2832_TUNER_TUA9001:
 491                 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
 492                 init = rtl2832_tuner_init_tua9001;
 493                 break;
 494         case RTL2832_TUNER_E4000:
 495                 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
 496                 init = rtl2832_tuner_init_e4000;
 497                 break;
 498         case RTL2832_TUNER_R820T:
 499         case RTL2832_TUNER_R828D:
 500                 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
 501                 init = rtl2832_tuner_init_r820t;
 502                 break;
 503         default:
 504                 ret = -EINVAL;
 505                 goto err;
 506         }
 507
 508         for (i = 0; i < len; i++) {
 509                 ret = rtl2832_wr_demod_reg(priv, init[i].reg, init[i].value);
 510                 if (ret)
 511                         goto err;
 512         }
 513
 514         /*
 515          * r820t NIM code does a software reset here at the demod -
 516          * may not be needed, as there's already a software reset at
 517          * set_params()
 518          */
 519 #if 1
 520         /* soft reset */
 521         ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x1);
 522         if (ret)
 523                 goto err;
 524
 525         ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x0);
 526         if (ret)
 527                 goto err;
 528 #endif
 529
 530         priv->sleeping = false;
 531
 532         return ret;
 533
 534 err:
 535         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 536         return ret;
 537 }
 538
 539 static int rtl2832_sleep(struct dvb_frontend *fe)
 540 {
 541         struct rtl2832_priv *priv = fe->demodulator_priv;
 542
 543         dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
 544         priv->sleeping = true;
 545         return 0;
 546 }
 547
 548 static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
 549         struct dvb_frontend_tune_settings *s)
 550 {
 551         struct rtl2832_priv *priv = fe->demodulator_priv;
 552
 553         dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
 554         s->min_delay_ms = 1000;
 555         s->step_size = fe->ops.info.frequency_stepsize * 2;
 556         s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
 557         return 0;
 558 }
 559
 560 static int rtl2832_set_frontend(struct dvb_frontend *fe)
 561 {
 562         struct rtl2832_priv *priv = fe->demodulator_priv;
 563         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 564         int ret, i, j;
 565         u64 bw_mode, num, num2;
 566         u32 resamp_ratio, cfreq_off_ratio;
 567         static u8 bw_params[3][32] = {
 568         /* 6 MHz bandwidth */
 569                 {
 570                 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
 571                 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
 572                 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
 573                 0x19, 0xe0,
 574                 },
 575
 576         /*  7 MHz bandwidth */
 577                 {
 578                 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
 579                 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
 580                 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
 581                 0x19, 0x10,
 582                 },
 583
 584         /*  8 MHz bandwidth */
 585                 {
 586                 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
 587                 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
 588                 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
 589                 0x19, 0xe0,
 590                 },
 591         };
 592
 593
 594         dev_dbg(&priv->i2c->dev,
 595                         "%s: frequency=%d bandwidth_hz=%d inversion=%d\n",
 596                         __func__, c->frequency, c->bandwidth_hz, c->inversion);
 597
 598         /* program tuner */
 599         if (fe->ops.tuner_ops.set_params)
 600                 fe->ops.tuner_ops.set_params(fe);
 601
 602         /* If the frontend has get_if_frequency(), use it */
 603         if (fe->ops.tuner_ops.get_if_frequency) {
 604                 u32 if_freq;
 605
 606                 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
 607                 if (ret)
 608                         goto err;
 609
 610                 ret = rtl2832_set_if(fe, if_freq);
 611                 if (ret)
 612                         goto err;
 613         }
 614
 615         switch (c->bandwidth_hz) {
 616         case 6000000:
 617                 i = 0;
 618                 bw_mode = 48000000;
 619                 break;
 620         case 7000000:
 621                 i = 1;
 622                 bw_mode = 56000000;
 623                 break;
 624         case 8000000:
 625                 i = 2;
 626                 bw_mode = 64000000;
 627                 break;
 628         default:
 629                 dev_dbg(&priv->i2c->dev, "%s: invalid bandwidth\n", __func__);
 630                 return -EINVAL;
 631         }
 632
 633         for (j = 0; j < sizeof(bw_params[0]); j++) {
 634                 ret = rtl2832_wr_regs(priv, 0x1c+j, 1, &bw_params[i][j], 1);
 635                 if (ret)
 636                         goto err;
 637         }
 638
 639         /* calculate and set resample ratio
 640         * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
 641         *       / ConstWithBandwidthMode)
 642         */
 643         num = priv->cfg.xtal * 7;
 644         num *= 0x400000;
 645         num = div_u64(num, bw_mode);
 646         resamp_ratio =  num & 0x3ffffff;
 647         ret = rtl2832_wr_demod_reg(priv, DVBT_RSAMP_RATIO, resamp_ratio);
 648         if (ret)
 649                 goto err;
 650
 651         /* calculate and set cfreq off ratio
 652         * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
 653         *       / (CrystalFreqHz * 7))
 654         */
 655         num = bw_mode << 20;
 656         num2 = priv->cfg.xtal * 7;
 657         num = div_u64(num, num2);
 658         num = -num;
 659         cfreq_off_ratio = num & 0xfffff;
 660         ret = rtl2832_wr_demod_reg(priv, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
 661         if (ret)
 662                 goto err;
 663
 664
 665         /* soft reset */
 666         ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x1);
 667         if (ret)
 668                 goto err;
 669
 670         ret = rtl2832_wr_demod_reg(priv, DVBT_SOFT_RST, 0x0);
 671         if (ret)
 672                 goto err;
 673
 674         return ret;
 675 err:
 676         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 677         return ret;
 678 }
 679
 680 static int rtl2832_get_frontend(struct dvb_frontend *fe)
 681 {
 682         struct rtl2832_priv *priv = fe->demodulator_priv;
 683         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 684         int ret;
 685         u8 buf[3];
 686
 687         if (priv->sleeping)
 688                 return 0;
 689
 690         ret = rtl2832_rd_regs(priv, 0x3c, 3, buf, 2);
 691         if (ret)
 692                 goto err;
 693
 694         ret = rtl2832_rd_reg(priv, 0x51, 3, &buf[2]);
 695         if (ret)
 696                 goto err;
 697
 698         dev_dbg(&priv->i2c->dev, "%s: TPS=%*ph\n", __func__, 3, buf);
 699
 700         switch ((buf[0] >> 2) & 3) {
 701         case 0:
 702                 c->modulation = QPSK;
 703                 break;
 704         case 1:
 705                 c->modulation = QAM_16;
 706                 break;
 707         case 2:
 708                 c->modulation = QAM_64;
 709                 break;
 710         }
 711
 712         switch ((buf[2] >> 2) & 1) {
 713         case 0:
 714                 c->transmission_mode = TRANSMISSION_MODE_2K;
 715                 break;
 716         case 1:
 717                 c->transmission_mode = TRANSMISSION_MODE_8K;
 718         }
 719
 720         switch ((buf[2] >> 0) & 3) {
 721         case 0:
 722                 c->guard_interval = GUARD_INTERVAL_1_32;
 723                 break;
 724         case 1:
 725                 c->guard_interval = GUARD_INTERVAL_1_16;
 726                 break;
 727         case 2:
 728                 c->guard_interval = GUARD_INTERVAL_1_8;
 729                 break;
 730         case 3:
 731                 c->guard_interval = GUARD_INTERVAL_1_4;
 732                 break;
 733         }
 734
 735         switch ((buf[0] >> 4) & 7) {
 736         case 0:
 737                 c->hierarchy = HIERARCHY_NONE;
 738                 break;
 739         case 1:
 740                 c->hierarchy = HIERARCHY_1;
 741                 break;
 742         case 2:
 743                 c->hierarchy = HIERARCHY_2;
 744                 break;
 745         case 3:
 746                 c->hierarchy = HIERARCHY_4;
 747                 break;
 748         }
 749
 750         switch ((buf[1] >> 3) & 7) {
 751         case 0:
 752                 c->code_rate_HP = FEC_1_2;
 753                 break;
 754         case 1:
 755                 c->code_rate_HP = FEC_2_3;
 756                 break;
 757         case 2:
 758                 c->code_rate_HP = FEC_3_4;
 759                 break;
 760         case 3:
 761                 c->code_rate_HP = FEC_5_6;
 762                 break;
 763         case 4:
 764                 c->code_rate_HP = FEC_7_8;
 765                 break;
 766         }
 767
 768         switch ((buf[1] >> 0) & 7) {
 769         case 0:
 770                 c->code_rate_LP = FEC_1_2;
 771                 break;
 772         case 1:
 773                 c->code_rate_LP = FEC_2_3;
 774                 break;
 775         case 2:
 776                 c->code_rate_LP = FEC_3_4;
 777                 break;
 778         case 3:
 779                 c->code_rate_LP = FEC_5_6;
 780                 break;
 781         case 4:
 782                 c->code_rate_LP = FEC_7_8;
 783                 break;
 784         }
 785
 786         return 0;
 787 err:
 788         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 789         return ret;
 790 }
 791
 792 static int rtl2832_read_status(struct dvb_frontend *fe, fe_status_t *status)
 793 {
 794         struct rtl2832_priv *priv = fe->demodulator_priv;
 795         int ret;
 796         u32 tmp;
 797         *status = 0;
 798
 799         dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
 800         if (priv->sleeping)
 801                 return 0;
 802
 803         ret = rtl2832_rd_demod_reg(priv, DVBT_FSM_STAGE, &tmp);
 804         if (ret)
 805                 goto err;
 806
 807         if (tmp == 11) {
 808                 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
 809                                 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
 810         }
 811         /* TODO find out if this is also true for rtl2832? */
 812         /*else if (tmp == 10) {
 813                 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
 814                                 FE_HAS_VITERBI;
 815         }*/
 816
 817         return ret;
 818 err:
 819         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 820         return ret;
 821 }
 822
 823 static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
 824 {
 825         struct rtl2832_priv *priv = fe->demodulator_priv;
 826         int ret, hierarchy, constellation;
 827         u8 buf[2], tmp;
 828         u16 tmp16;
 829 #define CONSTELLATION_NUM 3
 830 #define HIERARCHY_NUM 4
 831         static const u32 snr_constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
 832                 { 85387325, 85387325, 85387325, 85387325 },
 833                 { 86676178, 86676178, 87167949, 87795660 },
 834                 { 87659938, 87659938, 87885178, 88241743 },
 835         };
 836
 837         /* reports SNR in resolution of 0.1 dB */
 838
 839         ret = rtl2832_rd_reg(priv, 0x3c, 3, &tmp);
 840         if (ret)
 841                 goto err;
 842
 843         constellation = (tmp >> 2) & 0x03; /* [3:2] */
 844         if (constellation > CONSTELLATION_NUM - 1)
 845                 goto err;
 846
 847         hierarchy = (tmp >> 4) & 0x07; /* [6:4] */
 848         if (hierarchy > HIERARCHY_NUM - 1)
 849                 goto err;
 850
 851         ret = rtl2832_rd_regs(priv, 0x0c, 4, buf, 2);
 852         if (ret)
 853                 goto err;
 854
 855         tmp16 = buf[0] << 8 | buf[1];
 856
 857         if (tmp16)
 858                 *snr = (snr_constant[constellation][hierarchy] -
 859                                 intlog10(tmp16)) / ((1 << 24) / 100);
 860         else
 861                 *snr = 0;
 862
 863         return 0;
 864 err:
 865         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 866         return ret;
 867 }
 868
 869 static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
 870 {
 871         struct rtl2832_priv *priv = fe->demodulator_priv;
 872         int ret;
 873         u8 buf[2];
 874
 875         ret = rtl2832_rd_regs(priv, 0x4e, 3, buf, 2);
 876         if (ret)
 877                 goto err;
 878
 879         *ber = buf[0] << 8 | buf[1];
 880
 881         return 0;
 882 err:
 883         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 884         return ret;
 885 }
 886
 887 static struct dvb_frontend_ops rtl2832_ops;
 888
 889 static void rtl2832_release(struct dvb_frontend *fe)
 890 {
 891         struct rtl2832_priv *priv = fe->demodulator_priv;
 892
 893         dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
 894         i2c_del_mux_adapter(priv->i2c_adapter);
 895         kfree(priv);
 896 }
 897
 898 static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
 899 {
 900         struct rtl2832_priv *priv = mux_priv;
 901         return rtl2832_i2c_gate_ctrl(&priv->fe, 1);
 902 }
 903
 904 static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv, u32 chan)
 905 {
 906         struct rtl2832_priv *priv = mux_priv;
 907         return rtl2832_i2c_gate_ctrl(&priv->fe, 0);
 908 }
 909
 910 struct i2c_adapter *rtl2832_get_i2c_adapter(struct dvb_frontend *fe)
 911 {
 912         struct rtl2832_priv *priv = fe->demodulator_priv;
 913         return priv->i2c_adapter;
 914 }
 915 EXPORT_SYMBOL(rtl2832_get_i2c_adapter);
 916
 917 struct dvb_frontend *rtl2832_attach(const struct rtl2832_config *cfg,
 918         struct i2c_adapter *i2c)
 919 {
 920         struct rtl2832_priv *priv = NULL;
 921         int ret = 0;
 922         u8 tmp;
 923
 924         dev_dbg(&i2c->dev, "%s:\n", __func__);
 925
 926         /* allocate memory for the internal state */
 927         priv = kzalloc(sizeof(struct rtl2832_priv), GFP_KERNEL);
 928         if (priv == NULL)
 929                 goto err;
 930
 931         /* setup the priv */
 932         priv->i2c = i2c;
 933         priv->tuner = cfg->tuner;
 934         memcpy(&priv->cfg, cfg, sizeof(struct rtl2832_config));
 935
 936         /* check if the demod is there */
 937         ret = rtl2832_rd_reg(priv, 0x00, 0x0, &tmp);
 938         if (ret)
 939                 goto err;
 940
 941         /* create muxed i2c adapter */
 942         priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0,
 943                         rtl2832_select, rtl2832_deselect);
 944         if (priv->i2c_adapter == NULL)
 945                 goto err;
 946
 947         /* create dvb_frontend */
 948         memcpy(&priv->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
 949         priv->fe.demodulator_priv = priv;
 950
 951         /* TODO implement sleep mode */
 952         priv->sleeping = true;
 953
 954         return &priv->fe;
 955 err:
 956         dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
 957         kfree(priv);
 958         return NULL;
 959 }
 960 EXPORT_SYMBOL(rtl2832_attach);
 961
 962 static struct dvb_frontend_ops rtl2832_ops = {
 963         .delsys = { SYS_DVBT },
 964         .info = {
 965                 .name = "Realtek RTL2832 (DVB-T)",
 966                 .frequency_min    = 174000000,
 967                 .frequency_max    = 862000000,
 968                 .frequency_stepsize = 166667,
 969                 .caps = FE_CAN_FEC_1_2 |
 970                         FE_CAN_FEC_2_3 |
 971                         FE_CAN_FEC_3_4 |
 972                         FE_CAN_FEC_5_6 |
 973                         FE_CAN_FEC_7_8 |
 974                         FE_CAN_FEC_AUTO |
 975                         FE_CAN_QPSK |
 976                         FE_CAN_QAM_16 |
 977                         FE_CAN_QAM_64 |
 978                         FE_CAN_QAM_AUTO |
 979                         FE_CAN_TRANSMISSION_MODE_AUTO |
 980                         FE_CAN_GUARD_INTERVAL_AUTO |
 981                         FE_CAN_HIERARCHY_AUTO |
 982                         FE_CAN_RECOVER |
 983                         FE_CAN_MUTE_TS
 984          },
 985
 986         .release = rtl2832_release,
 987
 988         .init = rtl2832_init,
 989         .sleep = rtl2832_sleep,
 990
 991         .get_tune_settings = rtl2832_get_tune_settings,
 992
 993         .set_frontend = rtl2832_set_frontend,
 994         .get_frontend = rtl2832_get_frontend,
 995
 996         .read_status = rtl2832_read_status,
 997         .read_snr = rtl2832_read_snr,
 998         .read_ber = rtl2832_read_ber,
 999
1000         .i2c_gate_ctrl = rtl2832_i2c_gate_ctrl,
1001 };
1002
1003 MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
1004 MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1005 MODULE_LICENSE("GPL");
1006 MODULE_VERSION("0.5");