2 * adv7604 - Analog Devices ADV7604 video decoder driver
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/i2c.h>
35 #include <linux/delay.h>
36 #include <linux/videodev2.h>
37 #include <linux/workqueue.h>
38 #include <linux/v4l2-dv-timings.h>
39 #include <media/v4l2-device.h>
40 #include <media/v4l2-ctrls.h>
41 #include <media/v4l2-dv-timings.h>
42 #include <media/adv7604.h>
45 module_param(debug
, int, 0644);
46 MODULE_PARM_DESC(debug
, "debug level (0-2)");
48 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
49 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
50 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
51 MODULE_LICENSE("GPL");
53 /* ADV7604 system clock frequency */
54 #define ADV7604_fsc (28636360)
57 **********************************************************************
59 * Arrays with configuration parameters for the ADV7604
61 **********************************************************************
63 struct adv7604_state
{
64 struct adv7604_platform_data pdata
;
65 struct v4l2_subdev sd
;
67 struct v4l2_ctrl_handler hdl
;
68 enum adv7604_input_port selected_input
;
69 struct v4l2_dv_timings timings
;
76 struct v4l2_fract aspect_ratio
;
77 u32 rgb_quantization_range
;
78 struct workqueue_struct
*work_queues
;
79 struct delayed_work delayed_work_enable_hotplug
;
80 bool restart_stdi_once
;
83 struct i2c_client
*i2c_avlink
;
84 struct i2c_client
*i2c_cec
;
85 struct i2c_client
*i2c_infoframe
;
86 struct i2c_client
*i2c_esdp
;
87 struct i2c_client
*i2c_dpp
;
88 struct i2c_client
*i2c_afe
;
89 struct i2c_client
*i2c_repeater
;
90 struct i2c_client
*i2c_edid
;
91 struct i2c_client
*i2c_hdmi
;
92 struct i2c_client
*i2c_test
;
93 struct i2c_client
*i2c_cp
;
94 struct i2c_client
*i2c_vdp
;
97 struct v4l2_ctrl
*detect_tx_5v_ctrl
;
98 struct v4l2_ctrl
*analog_sampling_phase_ctrl
;
99 struct v4l2_ctrl
*free_run_color_manual_ctrl
;
100 struct v4l2_ctrl
*free_run_color_ctrl
;
101 struct v4l2_ctrl
*rgb_quantization_range_ctrl
;
104 /* Supported CEA and DMT timings */
105 static const struct v4l2_dv_timings adv7604_timings
[] = {
106 V4L2_DV_BT_CEA_720X480P59_94
,
107 V4L2_DV_BT_CEA_720X576P50
,
108 V4L2_DV_BT_CEA_1280X720P24
,
109 V4L2_DV_BT_CEA_1280X720P25
,
110 V4L2_DV_BT_CEA_1280X720P50
,
111 V4L2_DV_BT_CEA_1280X720P60
,
112 V4L2_DV_BT_CEA_1920X1080P24
,
113 V4L2_DV_BT_CEA_1920X1080P25
,
114 V4L2_DV_BT_CEA_1920X1080P30
,
115 V4L2_DV_BT_CEA_1920X1080P50
,
116 V4L2_DV_BT_CEA_1920X1080P60
,
118 /* sorted by DMT ID */
119 V4L2_DV_BT_DMT_640X350P85
,
120 V4L2_DV_BT_DMT_640X400P85
,
121 V4L2_DV_BT_DMT_720X400P85
,
122 V4L2_DV_BT_DMT_640X480P60
,
123 V4L2_DV_BT_DMT_640X480P72
,
124 V4L2_DV_BT_DMT_640X480P75
,
125 V4L2_DV_BT_DMT_640X480P85
,
126 V4L2_DV_BT_DMT_800X600P56
,
127 V4L2_DV_BT_DMT_800X600P60
,
128 V4L2_DV_BT_DMT_800X600P72
,
129 V4L2_DV_BT_DMT_800X600P75
,
130 V4L2_DV_BT_DMT_800X600P85
,
131 V4L2_DV_BT_DMT_848X480P60
,
132 V4L2_DV_BT_DMT_1024X768P60
,
133 V4L2_DV_BT_DMT_1024X768P70
,
134 V4L2_DV_BT_DMT_1024X768P75
,
135 V4L2_DV_BT_DMT_1024X768P85
,
136 V4L2_DV_BT_DMT_1152X864P75
,
137 V4L2_DV_BT_DMT_1280X768P60_RB
,
138 V4L2_DV_BT_DMT_1280X768P60
,
139 V4L2_DV_BT_DMT_1280X768P75
,
140 V4L2_DV_BT_DMT_1280X768P85
,
141 V4L2_DV_BT_DMT_1280X800P60_RB
,
142 V4L2_DV_BT_DMT_1280X800P60
,
143 V4L2_DV_BT_DMT_1280X800P75
,
144 V4L2_DV_BT_DMT_1280X800P85
,
145 V4L2_DV_BT_DMT_1280X960P60
,
146 V4L2_DV_BT_DMT_1280X960P85
,
147 V4L2_DV_BT_DMT_1280X1024P60
,
148 V4L2_DV_BT_DMT_1280X1024P75
,
149 V4L2_DV_BT_DMT_1280X1024P85
,
150 V4L2_DV_BT_DMT_1360X768P60
,
151 V4L2_DV_BT_DMT_1400X1050P60_RB
,
152 V4L2_DV_BT_DMT_1400X1050P60
,
153 V4L2_DV_BT_DMT_1400X1050P75
,
154 V4L2_DV_BT_DMT_1400X1050P85
,
155 V4L2_DV_BT_DMT_1440X900P60_RB
,
156 V4L2_DV_BT_DMT_1440X900P60
,
157 V4L2_DV_BT_DMT_1600X1200P60
,
158 V4L2_DV_BT_DMT_1680X1050P60_RB
,
159 V4L2_DV_BT_DMT_1680X1050P60
,
160 V4L2_DV_BT_DMT_1792X1344P60
,
161 V4L2_DV_BT_DMT_1856X1392P60
,
162 V4L2_DV_BT_DMT_1920X1200P60_RB
,
163 V4L2_DV_BT_DMT_1366X768P60_RB
,
164 V4L2_DV_BT_DMT_1366X768P60
,
165 V4L2_DV_BT_DMT_1920X1080P60
,
169 struct adv7604_video_standards
{
170 struct v4l2_dv_timings timings
;
175 /* sorted by number of lines */
176 static const struct adv7604_video_standards adv7604_prim_mode_comp
[] = {
177 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
178 { V4L2_DV_BT_CEA_720X576P50
, 0x0b, 0x00 },
179 { V4L2_DV_BT_CEA_1280X720P50
, 0x19, 0x01 },
180 { V4L2_DV_BT_CEA_1280X720P60
, 0x19, 0x00 },
181 { V4L2_DV_BT_CEA_1920X1080P24
, 0x1e, 0x04 },
182 { V4L2_DV_BT_CEA_1920X1080P25
, 0x1e, 0x03 },
183 { V4L2_DV_BT_CEA_1920X1080P30
, 0x1e, 0x02 },
184 { V4L2_DV_BT_CEA_1920X1080P50
, 0x1e, 0x01 },
185 { V4L2_DV_BT_CEA_1920X1080P60
, 0x1e, 0x00 },
186 /* TODO add 1920x1080P60_RB (CVT timing) */
190 /* sorted by number of lines */
191 static const struct adv7604_video_standards adv7604_prim_mode_gr
[] = {
192 { V4L2_DV_BT_DMT_640X480P60
, 0x08, 0x00 },
193 { V4L2_DV_BT_DMT_640X480P72
, 0x09, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P75
, 0x0a, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P85
, 0x0b, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P56
, 0x00, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P60
, 0x01, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P72
, 0x02, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P75
, 0x03, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P85
, 0x04, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P60
, 0x0c, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P70
, 0x0d, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P75
, 0x0e, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P85
, 0x0f, 0x00 },
205 { V4L2_DV_BT_DMT_1280X1024P60
, 0x05, 0x00 },
206 { V4L2_DV_BT_DMT_1280X1024P75
, 0x06, 0x00 },
207 { V4L2_DV_BT_DMT_1360X768P60
, 0x12, 0x00 },
208 { V4L2_DV_BT_DMT_1366X768P60
, 0x13, 0x00 },
209 { V4L2_DV_BT_DMT_1400X1050P60
, 0x14, 0x00 },
210 { V4L2_DV_BT_DMT_1400X1050P75
, 0x15, 0x00 },
211 { V4L2_DV_BT_DMT_1600X1200P60
, 0x16, 0x00 }, /* TODO not tested */
212 /* TODO add 1600X1200P60_RB (not a DMT timing) */
213 { V4L2_DV_BT_DMT_1680X1050P60
, 0x18, 0x00 },
214 { V4L2_DV_BT_DMT_1920X1200P60_RB
, 0x19, 0x00 }, /* TODO not tested */
218 /* sorted by number of lines */
219 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp
[] = {
220 { V4L2_DV_BT_CEA_720X480P59_94
, 0x0a, 0x00 },
221 { V4L2_DV_BT_CEA_720X576P50
, 0x0b, 0x00 },
222 { V4L2_DV_BT_CEA_1280X720P50
, 0x13, 0x01 },
223 { V4L2_DV_BT_CEA_1280X720P60
, 0x13, 0x00 },
224 { V4L2_DV_BT_CEA_1920X1080P24
, 0x1e, 0x04 },
225 { V4L2_DV_BT_CEA_1920X1080P25
, 0x1e, 0x03 },
226 { V4L2_DV_BT_CEA_1920X1080P30
, 0x1e, 0x02 },
227 { V4L2_DV_BT_CEA_1920X1080P50
, 0x1e, 0x01 },
228 { V4L2_DV_BT_CEA_1920X1080P60
, 0x1e, 0x00 },
232 /* sorted by number of lines */
233 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr
[] = {
234 { V4L2_DV_BT_DMT_640X480P60
, 0x08, 0x00 },
235 { V4L2_DV_BT_DMT_640X480P72
, 0x09, 0x00 },
236 { V4L2_DV_BT_DMT_640X480P75
, 0x0a, 0x00 },
237 { V4L2_DV_BT_DMT_640X480P85
, 0x0b, 0x00 },
238 { V4L2_DV_BT_DMT_800X600P56
, 0x00, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P60
, 0x01, 0x00 },
240 { V4L2_DV_BT_DMT_800X600P72
, 0x02, 0x00 },
241 { V4L2_DV_BT_DMT_800X600P75
, 0x03, 0x00 },
242 { V4L2_DV_BT_DMT_800X600P85
, 0x04, 0x00 },
243 { V4L2_DV_BT_DMT_1024X768P60
, 0x0c, 0x00 },
244 { V4L2_DV_BT_DMT_1024X768P70
, 0x0d, 0x00 },
245 { V4L2_DV_BT_DMT_1024X768P75
, 0x0e, 0x00 },
246 { V4L2_DV_BT_DMT_1024X768P85
, 0x0f, 0x00 },
247 { V4L2_DV_BT_DMT_1280X1024P60
, 0x05, 0x00 },
248 { V4L2_DV_BT_DMT_1280X1024P75
, 0x06, 0x00 },
252 /* ----------------------------------------------------------------------- */
254 static inline struct adv7604_state
*to_state(struct v4l2_subdev
*sd
)
256 return container_of(sd
, struct adv7604_state
, sd
);
259 static inline struct v4l2_subdev
*to_sd(struct v4l2_ctrl
*ctrl
)
261 return &container_of(ctrl
->handler
, struct adv7604_state
, hdl
)->sd
;
264 static inline unsigned hblanking(const struct v4l2_bt_timings
*t
)
266 return V4L2_DV_BT_BLANKING_WIDTH(t
);
269 static inline unsigned htotal(const struct v4l2_bt_timings
*t
)
271 return V4L2_DV_BT_FRAME_WIDTH(t
);
274 static inline unsigned vblanking(const struct v4l2_bt_timings
*t
)
276 return V4L2_DV_BT_BLANKING_HEIGHT(t
);
279 static inline unsigned vtotal(const struct v4l2_bt_timings
*t
)
281 return V4L2_DV_BT_FRAME_HEIGHT(t
);
284 /* ----------------------------------------------------------------------- */
286 static s32
adv_smbus_read_byte_data_check(struct i2c_client
*client
,
287 u8 command
, bool check
)
289 union i2c_smbus_data data
;
291 if (!i2c_smbus_xfer(client
->adapter
, client
->addr
, client
->flags
,
292 I2C_SMBUS_READ
, command
,
293 I2C_SMBUS_BYTE_DATA
, &data
))
296 v4l_err(client
, "error reading %02x, %02x\n",
297 client
->addr
, command
);
301 static s32
adv_smbus_read_byte_data(struct i2c_client
*client
, u8 command
)
303 return adv_smbus_read_byte_data_check(client
, command
, true);
306 static s32
adv_smbus_write_byte_data(struct i2c_client
*client
,
307 u8 command
, u8 value
)
309 union i2c_smbus_data data
;
314 for (i
= 0; i
< 3; i
++) {
315 err
= i2c_smbus_xfer(client
->adapter
, client
->addr
,
317 I2C_SMBUS_WRITE
, command
,
318 I2C_SMBUS_BYTE_DATA
, &data
);
323 v4l_err(client
, "error writing %02x, %02x, %02x\n",
324 client
->addr
, command
, value
);
328 static s32
adv_smbus_write_i2c_block_data(struct i2c_client
*client
,
329 u8 command
, unsigned length
, const u8
*values
)
331 union i2c_smbus_data data
;
333 if (length
> I2C_SMBUS_BLOCK_MAX
)
334 length
= I2C_SMBUS_BLOCK_MAX
;
335 data
.block
[0] = length
;
336 memcpy(data
.block
+ 1, values
, length
);
337 return i2c_smbus_xfer(client
->adapter
, client
->addr
, client
->flags
,
338 I2C_SMBUS_WRITE
, command
,
339 I2C_SMBUS_I2C_BLOCK_DATA
, &data
);
342 /* ----------------------------------------------------------------------- */
344 static inline int io_read(struct v4l2_subdev
*sd
, u8 reg
)
346 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
348 return adv_smbus_read_byte_data(client
, reg
);
351 static inline int io_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
353 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
355 return adv_smbus_write_byte_data(client
, reg
, val
);
358 static inline int io_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
360 return io_write(sd
, reg
, (io_read(sd
, reg
) & mask
) | val
);
363 static inline int avlink_read(struct v4l2_subdev
*sd
, u8 reg
)
365 struct adv7604_state
*state
= to_state(sd
);
367 return adv_smbus_read_byte_data(state
->i2c_avlink
, reg
);
370 static inline int avlink_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
372 struct adv7604_state
*state
= to_state(sd
);
374 return adv_smbus_write_byte_data(state
->i2c_avlink
, reg
, val
);
377 static inline int cec_read(struct v4l2_subdev
*sd
, u8 reg
)
379 struct adv7604_state
*state
= to_state(sd
);
381 return adv_smbus_read_byte_data(state
->i2c_cec
, reg
);
384 static inline int cec_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
386 struct adv7604_state
*state
= to_state(sd
);
388 return adv_smbus_write_byte_data(state
->i2c_cec
, reg
, val
);
391 static inline int cec_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
393 return cec_write(sd
, reg
, (cec_read(sd
, reg
) & mask
) | val
);
396 static inline int infoframe_read(struct v4l2_subdev
*sd
, u8 reg
)
398 struct adv7604_state
*state
= to_state(sd
);
400 return adv_smbus_read_byte_data(state
->i2c_infoframe
, reg
);
403 static inline int infoframe_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
405 struct adv7604_state
*state
= to_state(sd
);
407 return adv_smbus_write_byte_data(state
->i2c_infoframe
, reg
, val
);
410 static inline int esdp_read(struct v4l2_subdev
*sd
, u8 reg
)
412 struct adv7604_state
*state
= to_state(sd
);
414 return adv_smbus_read_byte_data(state
->i2c_esdp
, reg
);
417 static inline int esdp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
419 struct adv7604_state
*state
= to_state(sd
);
421 return adv_smbus_write_byte_data(state
->i2c_esdp
, reg
, val
);
424 static inline int dpp_read(struct v4l2_subdev
*sd
, u8 reg
)
426 struct adv7604_state
*state
= to_state(sd
);
428 return adv_smbus_read_byte_data(state
->i2c_dpp
, reg
);
431 static inline int dpp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
433 struct adv7604_state
*state
= to_state(sd
);
435 return adv_smbus_write_byte_data(state
->i2c_dpp
, reg
, val
);
438 static inline int afe_read(struct v4l2_subdev
*sd
, u8 reg
)
440 struct adv7604_state
*state
= to_state(sd
);
442 return adv_smbus_read_byte_data(state
->i2c_afe
, reg
);
445 static inline int afe_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
447 struct adv7604_state
*state
= to_state(sd
);
449 return adv_smbus_write_byte_data(state
->i2c_afe
, reg
, val
);
452 static inline int rep_read(struct v4l2_subdev
*sd
, u8 reg
)
454 struct adv7604_state
*state
= to_state(sd
);
456 return adv_smbus_read_byte_data(state
->i2c_repeater
, reg
);
459 static inline int rep_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
461 struct adv7604_state
*state
= to_state(sd
);
463 return adv_smbus_write_byte_data(state
->i2c_repeater
, reg
, val
);
466 static inline int rep_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
468 return rep_write(sd
, reg
, (rep_read(sd
, reg
) & mask
) | val
);
471 static inline int edid_read(struct v4l2_subdev
*sd
, u8 reg
)
473 struct adv7604_state
*state
= to_state(sd
);
475 return adv_smbus_read_byte_data(state
->i2c_edid
, reg
);
478 static inline int edid_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
480 struct adv7604_state
*state
= to_state(sd
);
482 return adv_smbus_write_byte_data(state
->i2c_edid
, reg
, val
);
485 static inline int edid_read_block(struct v4l2_subdev
*sd
, unsigned len
, u8
*val
)
487 struct adv7604_state
*state
= to_state(sd
);
488 struct i2c_client
*client
= state
->i2c_edid
;
489 u8 msgbuf0
[1] = { 0 };
491 struct i2c_msg msg
[2] = {
493 .addr
= client
->addr
,
498 .addr
= client
->addr
,
505 if (i2c_transfer(client
->adapter
, msg
, 2) < 0)
507 memcpy(val
, msgbuf1
, len
);
511 static inline int edid_write_block(struct v4l2_subdev
*sd
,
512 unsigned len
, const u8
*val
)
514 struct adv7604_state
*state
= to_state(sd
);
518 v4l2_dbg(2, debug
, sd
, "%s: write EDID block (%d byte)\n", __func__
, len
);
520 for (i
= 0; !err
&& i
< len
; i
+= I2C_SMBUS_BLOCK_MAX
)
521 err
= adv_smbus_write_i2c_block_data(state
->i2c_edid
, i
,
522 I2C_SMBUS_BLOCK_MAX
, val
+ i
);
526 static void adv7604_delayed_work_enable_hotplug(struct work_struct
*work
)
528 struct delayed_work
*dwork
= to_delayed_work(work
);
529 struct adv7604_state
*state
= container_of(dwork
, struct adv7604_state
,
530 delayed_work_enable_hotplug
);
531 struct v4l2_subdev
*sd
= &state
->sd
;
533 v4l2_dbg(2, debug
, sd
, "%s: enable hotplug\n", __func__
);
535 v4l2_subdev_notify(sd
, ADV7604_HOTPLUG
, (void *)&state
->edid
.present
);
538 static inline int hdmi_read(struct v4l2_subdev
*sd
, u8 reg
)
540 struct adv7604_state
*state
= to_state(sd
);
542 return adv_smbus_read_byte_data(state
->i2c_hdmi
, reg
);
545 static inline int hdmi_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
547 struct adv7604_state
*state
= to_state(sd
);
549 return adv_smbus_write_byte_data(state
->i2c_hdmi
, reg
, val
);
552 static inline int hdmi_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
554 return hdmi_write(sd
, reg
, (hdmi_read(sd
, reg
) & mask
) | val
);
557 static inline int test_read(struct v4l2_subdev
*sd
, u8 reg
)
559 struct adv7604_state
*state
= to_state(sd
);
561 return adv_smbus_read_byte_data(state
->i2c_test
, reg
);
564 static inline int test_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
566 struct adv7604_state
*state
= to_state(sd
);
568 return adv_smbus_write_byte_data(state
->i2c_test
, reg
, val
);
571 static inline int cp_read(struct v4l2_subdev
*sd
, u8 reg
)
573 struct adv7604_state
*state
= to_state(sd
);
575 return adv_smbus_read_byte_data(state
->i2c_cp
, reg
);
578 static inline int cp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
580 struct adv7604_state
*state
= to_state(sd
);
582 return adv_smbus_write_byte_data(state
->i2c_cp
, reg
, val
);
585 static inline int cp_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
587 return cp_write(sd
, reg
, (cp_read(sd
, reg
) & mask
) | val
);
590 static inline int vdp_read(struct v4l2_subdev
*sd
, u8 reg
)
592 struct adv7604_state
*state
= to_state(sd
);
594 return adv_smbus_read_byte_data(state
->i2c_vdp
, reg
);
597 static inline int vdp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
599 struct adv7604_state
*state
= to_state(sd
);
601 return adv_smbus_write_byte_data(state
->i2c_vdp
, reg
, val
);
604 /* ----------------------------------------------------------------------- */
606 static inline bool is_analog_input(struct v4l2_subdev
*sd
)
608 struct adv7604_state
*state
= to_state(sd
);
610 return state
->selected_input
== ADV7604_INPUT_VGA_RGB
||
611 state
->selected_input
== ADV7604_INPUT_VGA_COMP
;
614 static inline bool is_digital_input(struct v4l2_subdev
*sd
)
616 struct adv7604_state
*state
= to_state(sd
);
618 return state
->selected_input
== ADV7604_INPUT_HDMI_PORT_A
||
619 state
->selected_input
== ADV7604_INPUT_HDMI_PORT_B
||
620 state
->selected_input
== ADV7604_INPUT_HDMI_PORT_C
||
621 state
->selected_input
== ADV7604_INPUT_HDMI_PORT_D
;
624 /* ----------------------------------------------------------------------- */
626 #ifdef CONFIG_VIDEO_ADV_DEBUG
627 static void adv7604_inv_register(struct v4l2_subdev
*sd
)
629 v4l2_info(sd
, "0x000-0x0ff: IO Map\n");
630 v4l2_info(sd
, "0x100-0x1ff: AVLink Map\n");
631 v4l2_info(sd
, "0x200-0x2ff: CEC Map\n");
632 v4l2_info(sd
, "0x300-0x3ff: InfoFrame Map\n");
633 v4l2_info(sd
, "0x400-0x4ff: ESDP Map\n");
634 v4l2_info(sd
, "0x500-0x5ff: DPP Map\n");
635 v4l2_info(sd
, "0x600-0x6ff: AFE Map\n");
636 v4l2_info(sd
, "0x700-0x7ff: Repeater Map\n");
637 v4l2_info(sd
, "0x800-0x8ff: EDID Map\n");
638 v4l2_info(sd
, "0x900-0x9ff: HDMI Map\n");
639 v4l2_info(sd
, "0xa00-0xaff: Test Map\n");
640 v4l2_info(sd
, "0xb00-0xbff: CP Map\n");
641 v4l2_info(sd
, "0xc00-0xcff: VDP Map\n");
644 static int adv7604_g_register(struct v4l2_subdev
*sd
,
645 struct v4l2_dbg_register
*reg
)
648 switch (reg
->reg
>> 8) {
650 reg
->val
= io_read(sd
, reg
->reg
& 0xff);
653 reg
->val
= avlink_read(sd
, reg
->reg
& 0xff);
656 reg
->val
= cec_read(sd
, reg
->reg
& 0xff);
659 reg
->val
= infoframe_read(sd
, reg
->reg
& 0xff);
662 reg
->val
= esdp_read(sd
, reg
->reg
& 0xff);
665 reg
->val
= dpp_read(sd
, reg
->reg
& 0xff);
668 reg
->val
= afe_read(sd
, reg
->reg
& 0xff);
671 reg
->val
= rep_read(sd
, reg
->reg
& 0xff);
674 reg
->val
= edid_read(sd
, reg
->reg
& 0xff);
677 reg
->val
= hdmi_read(sd
, reg
->reg
& 0xff);
680 reg
->val
= test_read(sd
, reg
->reg
& 0xff);
683 reg
->val
= cp_read(sd
, reg
->reg
& 0xff);
686 reg
->val
= vdp_read(sd
, reg
->reg
& 0xff);
689 v4l2_info(sd
, "Register %03llx not supported\n", reg
->reg
);
690 adv7604_inv_register(sd
);
696 static int adv7604_s_register(struct v4l2_subdev
*sd
,
697 const struct v4l2_dbg_register
*reg
)
699 u8 val
= reg
->val
& 0xff;
701 switch (reg
->reg
>> 8) {
703 io_write(sd
, reg
->reg
& 0xff, val
);
706 avlink_write(sd
, reg
->reg
& 0xff, val
);
709 cec_write(sd
, reg
->reg
& 0xff, val
);
712 infoframe_write(sd
, reg
->reg
& 0xff, val
);
715 esdp_write(sd
, reg
->reg
& 0xff, val
);
718 dpp_write(sd
, reg
->reg
& 0xff, val
);
721 afe_write(sd
, reg
->reg
& 0xff, val
);
724 rep_write(sd
, reg
->reg
& 0xff, val
);
727 edid_write(sd
, reg
->reg
& 0xff, val
);
730 hdmi_write(sd
, reg
->reg
& 0xff, val
);
733 test_write(sd
, reg
->reg
& 0xff, val
);
736 cp_write(sd
, reg
->reg
& 0xff, val
);
739 vdp_write(sd
, reg
->reg
& 0xff, val
);
742 v4l2_info(sd
, "Register %03llx not supported\n", reg
->reg
);
743 adv7604_inv_register(sd
);
750 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev
*sd
)
752 struct adv7604_state
*state
= to_state(sd
);
753 u8 reg_io_6f
= io_read(sd
, 0x6f);
755 return v4l2_ctrl_s_ctrl(state
->detect_tx_5v_ctrl
,
756 ((reg_io_6f
& 0x10) >> 4) |
757 ((reg_io_6f
& 0x08) >> 2) |
759 ((reg_io_6f
& 0x02) << 2));
762 static int find_and_set_predefined_video_timings(struct v4l2_subdev
*sd
,
764 const struct adv7604_video_standards
*predef_vid_timings
,
765 const struct v4l2_dv_timings
*timings
)
769 for (i
= 0; predef_vid_timings
[i
].timings
.bt
.width
; i
++) {
770 if (!v4l2_match_dv_timings(timings
, &predef_vid_timings
[i
].timings
,
771 is_digital_input(sd
) ? 250000 : 1000000))
773 io_write(sd
, 0x00, predef_vid_timings
[i
].vid_std
); /* video std */
774 io_write(sd
, 0x01, (predef_vid_timings
[i
].v_freq
<< 4) +
775 prim_mode
); /* v_freq and prim mode */
782 static int configure_predefined_video_timings(struct v4l2_subdev
*sd
,
783 struct v4l2_dv_timings
*timings
)
785 struct adv7604_state
*state
= to_state(sd
);
788 v4l2_dbg(1, debug
, sd
, "%s", __func__
);
790 /* reset to default values */
791 io_write(sd
, 0x16, 0x43);
792 io_write(sd
, 0x17, 0x5a);
793 /* disable embedded syncs for auto graphics mode */
794 cp_write_and_or(sd
, 0x81, 0xef, 0x00);
795 cp_write(sd
, 0x8f, 0x00);
796 cp_write(sd
, 0x90, 0x00);
797 cp_write(sd
, 0xa2, 0x00);
798 cp_write(sd
, 0xa3, 0x00);
799 cp_write(sd
, 0xa4, 0x00);
800 cp_write(sd
, 0xa5, 0x00);
801 cp_write(sd
, 0xa6, 0x00);
802 cp_write(sd
, 0xa7, 0x00);
803 cp_write(sd
, 0xab, 0x00);
804 cp_write(sd
, 0xac, 0x00);
806 if (is_analog_input(sd
)) {
807 err
= find_and_set_predefined_video_timings(sd
,
808 0x01, adv7604_prim_mode_comp
, timings
);
810 err
= find_and_set_predefined_video_timings(sd
,
811 0x02, adv7604_prim_mode_gr
, timings
);
812 } else if (is_digital_input(sd
)) {
813 err
= find_and_set_predefined_video_timings(sd
,
814 0x05, adv7604_prim_mode_hdmi_comp
, timings
);
816 err
= find_and_set_predefined_video_timings(sd
,
817 0x06, adv7604_prim_mode_hdmi_gr
, timings
);
819 v4l2_dbg(2, debug
, sd
, "%s: Unknown port %d selected\n",
820 __func__
, state
->selected_input
);
828 static void configure_custom_video_timings(struct v4l2_subdev
*sd
,
829 const struct v4l2_bt_timings
*bt
)
831 struct adv7604_state
*state
= to_state(sd
);
832 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
833 u32 width
= htotal(bt
);
834 u32 height
= vtotal(bt
);
835 u16 cp_start_sav
= bt
->hsync
+ bt
->hbackporch
- 4;
836 u16 cp_start_eav
= width
- bt
->hfrontporch
;
837 u16 cp_start_vbi
= height
- bt
->vfrontporch
;
838 u16 cp_end_vbi
= bt
->vsync
+ bt
->vbackporch
;
839 u16 ch1_fr_ll
= (((u32
)bt
->pixelclock
/ 100) > 0) ?
840 ((width
* (ADV7604_fsc
/ 100)) / ((u32
)bt
->pixelclock
/ 100)) : 0;
842 0xc0 | ((width
>> 8) & 0x1f),
846 v4l2_dbg(2, debug
, sd
, "%s\n", __func__
);
848 if (is_analog_input(sd
)) {
850 io_write(sd
, 0x00, 0x07); /* video std */
851 io_write(sd
, 0x01, 0x02); /* prim mode */
852 /* enable embedded syncs for auto graphics mode */
853 cp_write_and_or(sd
, 0x81, 0xef, 0x10);
855 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
856 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
857 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
858 if (adv_smbus_write_i2c_block_data(client
, 0x16, 2, pll
))
859 v4l2_err(sd
, "writing to reg 0x16 and 0x17 failed\n");
861 /* active video - horizontal timing */
862 cp_write(sd
, 0xa2, (cp_start_sav
>> 4) & 0xff);
863 cp_write(sd
, 0xa3, ((cp_start_sav
& 0x0f) << 4) |
864 ((cp_start_eav
>> 8) & 0x0f));
865 cp_write(sd
, 0xa4, cp_start_eav
& 0xff);
867 /* active video - vertical timing */
868 cp_write(sd
, 0xa5, (cp_start_vbi
>> 4) & 0xff);
869 cp_write(sd
, 0xa6, ((cp_start_vbi
& 0xf) << 4) |
870 ((cp_end_vbi
>> 8) & 0xf));
871 cp_write(sd
, 0xa7, cp_end_vbi
& 0xff);
872 } else if (is_digital_input(sd
)) {
873 /* set default prim_mode/vid_std for HDMI
874 according to [REF_03, c. 4.2] */
875 io_write(sd
, 0x00, 0x02); /* video std */
876 io_write(sd
, 0x01, 0x06); /* prim mode */
878 v4l2_dbg(2, debug
, sd
, "%s: Unknown port %d selected\n",
879 __func__
, state
->selected_input
);
882 cp_write(sd
, 0x8f, (ch1_fr_ll
>> 8) & 0x7);
883 cp_write(sd
, 0x90, ch1_fr_ll
& 0xff);
884 cp_write(sd
, 0xab, (height
>> 4) & 0xff);
885 cp_write(sd
, 0xac, (height
& 0x0f) << 4);
888 static void set_rgb_quantization_range(struct v4l2_subdev
*sd
)
890 struct adv7604_state
*state
= to_state(sd
);
892 v4l2_dbg(2, debug
, sd
, "%s: rgb_quantization_range = %d\n",
893 __func__
, state
->rgb_quantization_range
);
895 switch (state
->rgb_quantization_range
) {
896 case V4L2_DV_RGB_RANGE_AUTO
:
897 if (state
->selected_input
== ADV7604_INPUT_VGA_RGB
) {
898 /* Receiving analog RGB signal
899 * Set RGB full range (0-255) */
900 io_write_and_or(sd
, 0x02, 0x0f, 0x10);
904 if (state
->selected_input
== ADV7604_INPUT_VGA_COMP
) {
905 /* Receiving analog YPbPr signal
907 io_write_and_or(sd
, 0x02, 0x0f, 0xf0);
911 if (hdmi_read(sd
, 0x05) & 0x80) {
912 /* Receiving HDMI signal
914 io_write_and_or(sd
, 0x02, 0x0f, 0xf0);
918 /* Receiving DVI-D signal
919 * ADV7604 selects RGB limited range regardless of
920 * input format (CE/IT) in automatic mode */
921 if (state
->timings
.bt
.standards
& V4L2_DV_BT_STD_CEA861
) {
922 /* RGB limited range (16-235) */
923 io_write_and_or(sd
, 0x02, 0x0f, 0x00);
925 /* RGB full range (0-255) */
926 io_write_and_or(sd
, 0x02, 0x0f, 0x10);
929 case V4L2_DV_RGB_RANGE_LIMITED
:
930 if (state
->selected_input
== ADV7604_INPUT_VGA_COMP
) {
931 /* YCrCb limited range (16-235) */
932 io_write_and_or(sd
, 0x02, 0x0f, 0x20);
934 /* RGB limited range (16-235) */
935 io_write_and_or(sd
, 0x02, 0x0f, 0x00);
938 case V4L2_DV_RGB_RANGE_FULL
:
939 if (state
->selected_input
== ADV7604_INPUT_VGA_COMP
) {
940 /* YCrCb full range (0-255) */
941 io_write_and_or(sd
, 0x02, 0x0f, 0x60);
943 /* RGB full range (0-255) */
944 io_write_and_or(sd
, 0x02, 0x0f, 0x10);
950 static int adv7604_s_ctrl(struct v4l2_ctrl
*ctrl
)
952 struct v4l2_subdev
*sd
= to_sd(ctrl
);
953 struct adv7604_state
*state
= to_state(sd
);
956 case V4L2_CID_BRIGHTNESS
:
957 cp_write(sd
, 0x3c, ctrl
->val
);
959 case V4L2_CID_CONTRAST
:
960 cp_write(sd
, 0x3a, ctrl
->val
);
962 case V4L2_CID_SATURATION
:
963 cp_write(sd
, 0x3b, ctrl
->val
);
966 cp_write(sd
, 0x3d, ctrl
->val
);
968 case V4L2_CID_DV_RX_RGB_RANGE
:
969 state
->rgb_quantization_range
= ctrl
->val
;
970 set_rgb_quantization_range(sd
);
972 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE
:
973 /* Set the analog sampling phase. This is needed to find the
974 best sampling phase for analog video: an application or
975 driver has to try a number of phases and analyze the picture
976 quality before settling on the best performing phase. */
977 afe_write(sd
, 0xc8, ctrl
->val
);
979 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL
:
980 /* Use the default blue color for free running mode,
981 or supply your own. */
982 cp_write_and_or(sd
, 0xbf, ~0x04, (ctrl
->val
<< 2));
984 case V4L2_CID_ADV_RX_FREE_RUN_COLOR
:
985 cp_write(sd
, 0xc0, (ctrl
->val
& 0xff0000) >> 16);
986 cp_write(sd
, 0xc1, (ctrl
->val
& 0x00ff00) >> 8);
987 cp_write(sd
, 0xc2, (u8
)(ctrl
->val
& 0x0000ff));
993 /* ----------------------------------------------------------------------- */
995 static inline bool no_power(struct v4l2_subdev
*sd
)
997 /* Entire chip or CP powered off */
998 return io_read(sd
, 0x0c) & 0x24;
1001 static inline bool no_signal_tmds(struct v4l2_subdev
*sd
)
1003 struct adv7604_state
*state
= to_state(sd
);
1005 return !(io_read(sd
, 0x6a) & (0x10 >> state
->selected_input
));
1008 static inline bool no_lock_tmds(struct v4l2_subdev
*sd
)
1010 return (io_read(sd
, 0x6a) & 0xe0) != 0xe0;
1013 static inline bool is_hdmi(struct v4l2_subdev
*sd
)
1015 return hdmi_read(sd
, 0x05) & 0x80;
1018 static inline bool no_lock_sspd(struct v4l2_subdev
*sd
)
1020 /* TODO channel 2 */
1021 return ((cp_read(sd
, 0xb5) & 0xd0) != 0xd0);
1024 static inline bool no_lock_stdi(struct v4l2_subdev
*sd
)
1026 /* TODO channel 2 */
1027 return !(cp_read(sd
, 0xb1) & 0x80);
1030 static inline bool no_signal(struct v4l2_subdev
*sd
)
1036 ret
|= no_lock_stdi(sd
);
1037 ret
|= no_lock_sspd(sd
);
1039 if (is_digital_input(sd
)) {
1040 ret
|= no_lock_tmds(sd
);
1041 ret
|= no_signal_tmds(sd
);
1047 static inline bool no_lock_cp(struct v4l2_subdev
*sd
)
1049 /* CP has detected a non standard number of lines on the incoming
1050 video compared to what it is configured to receive by s_dv_timings */
1051 return io_read(sd
, 0x12) & 0x01;
1054 static int adv7604_g_input_status(struct v4l2_subdev
*sd
, u32
*status
)
1057 *status
|= no_power(sd
) ? V4L2_IN_ST_NO_POWER
: 0;
1058 *status
|= no_signal(sd
) ? V4L2_IN_ST_NO_SIGNAL
: 0;
1060 *status
|= is_digital_input(sd
) ? V4L2_IN_ST_NO_SYNC
: V4L2_IN_ST_NO_H_LOCK
;
1062 v4l2_dbg(1, debug
, sd
, "%s: status = 0x%x\n", __func__
, *status
);
1067 /* ----------------------------------------------------------------------- */
1069 struct stdi_readback
{
1075 static int stdi2dv_timings(struct v4l2_subdev
*sd
,
1076 struct stdi_readback
*stdi
,
1077 struct v4l2_dv_timings
*timings
)
1079 struct adv7604_state
*state
= to_state(sd
);
1080 u32 hfreq
= (ADV7604_fsc
* 8) / stdi
->bl
;
1084 for (i
= 0; adv7604_timings
[i
].bt
.height
; i
++) {
1085 if (vtotal(&adv7604_timings
[i
].bt
) != stdi
->lcf
+ 1)
1087 if (adv7604_timings
[i
].bt
.vsync
!= stdi
->lcvs
)
1090 pix_clk
= hfreq
* htotal(&adv7604_timings
[i
].bt
);
1092 if ((pix_clk
< adv7604_timings
[i
].bt
.pixelclock
+ 1000000) &&
1093 (pix_clk
> adv7604_timings
[i
].bt
.pixelclock
- 1000000)) {
1094 *timings
= adv7604_timings
[i
];
1099 if (v4l2_detect_cvt(stdi
->lcf
+ 1, hfreq
, stdi
->lcvs
,
1100 (stdi
->hs_pol
== '+' ? V4L2_DV_HSYNC_POS_POL
: 0) |
1101 (stdi
->vs_pol
== '+' ? V4L2_DV_VSYNC_POS_POL
: 0),
1104 if (v4l2_detect_gtf(stdi
->lcf
+ 1, hfreq
, stdi
->lcvs
,
1105 (stdi
->hs_pol
== '+' ? V4L2_DV_HSYNC_POS_POL
: 0) |
1106 (stdi
->vs_pol
== '+' ? V4L2_DV_VSYNC_POS_POL
: 0),
1107 state
->aspect_ratio
, timings
))
1110 v4l2_dbg(2, debug
, sd
,
1111 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1112 __func__
, stdi
->lcvs
, stdi
->lcf
, stdi
->bl
,
1113 stdi
->hs_pol
, stdi
->vs_pol
);
1117 static int read_stdi(struct v4l2_subdev
*sd
, struct stdi_readback
*stdi
)
1119 if (no_lock_stdi(sd
) || no_lock_sspd(sd
)) {
1120 v4l2_dbg(2, debug
, sd
, "%s: STDI and/or SSPD not locked\n", __func__
);
1125 stdi
->bl
= ((cp_read(sd
, 0xb1) & 0x3f) << 8) | cp_read(sd
, 0xb2);
1126 stdi
->lcf
= ((cp_read(sd
, 0xb3) & 0x7) << 8) | cp_read(sd
, 0xb4);
1127 stdi
->lcvs
= cp_read(sd
, 0xb3) >> 3;
1128 stdi
->interlaced
= io_read(sd
, 0x12) & 0x10;
1131 if ((cp_read(sd
, 0xb5) & 0x03) == 0x01) {
1132 stdi
->hs_pol
= ((cp_read(sd
, 0xb5) & 0x10) ?
1133 ((cp_read(sd
, 0xb5) & 0x08) ? '+' : '-') : 'x');
1134 stdi
->vs_pol
= ((cp_read(sd
, 0xb5) & 0x40) ?
1135 ((cp_read(sd
, 0xb5) & 0x20) ? '+' : '-') : 'x');
1141 if (no_lock_stdi(sd
) || no_lock_sspd(sd
)) {
1142 v4l2_dbg(2, debug
, sd
,
1143 "%s: signal lost during readout of STDI/SSPD\n", __func__
);
1147 if (stdi
->lcf
< 239 || stdi
->bl
< 8 || stdi
->bl
== 0x3fff) {
1148 v4l2_dbg(2, debug
, sd
, "%s: invalid signal\n", __func__
);
1149 memset(stdi
, 0, sizeof(struct stdi_readback
));
1153 v4l2_dbg(2, debug
, sd
,
1154 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1155 __func__
, stdi
->lcf
, stdi
->bl
, stdi
->lcvs
,
1156 stdi
->hs_pol
, stdi
->vs_pol
,
1157 stdi
->interlaced
? "interlaced" : "progressive");
1162 static int adv7604_enum_dv_timings(struct v4l2_subdev
*sd
,
1163 struct v4l2_enum_dv_timings
*timings
)
1165 if (timings
->index
>= ARRAY_SIZE(adv7604_timings
) - 1)
1167 memset(timings
->reserved
, 0, sizeof(timings
->reserved
));
1168 timings
->timings
= adv7604_timings
[timings
->index
];
1172 static int adv7604_dv_timings_cap(struct v4l2_subdev
*sd
,
1173 struct v4l2_dv_timings_cap
*cap
)
1175 cap
->type
= V4L2_DV_BT_656_1120
;
1176 cap
->bt
.max_width
= 1920;
1177 cap
->bt
.max_height
= 1200;
1178 cap
->bt
.min_pixelclock
= 25000000;
1179 if (is_digital_input(sd
))
1180 cap
->bt
.max_pixelclock
= 225000000;
1182 cap
->bt
.max_pixelclock
= 170000000;
1183 cap
->bt
.standards
= V4L2_DV_BT_STD_CEA861
| V4L2_DV_BT_STD_DMT
|
1184 V4L2_DV_BT_STD_GTF
| V4L2_DV_BT_STD_CVT
;
1185 cap
->bt
.capabilities
= V4L2_DV_BT_CAP_PROGRESSIVE
|
1186 V4L2_DV_BT_CAP_REDUCED_BLANKING
| V4L2_DV_BT_CAP_CUSTOM
;
1190 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1191 if the format is listed in adv7604_timings[] */
1192 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev
*sd
,
1193 struct v4l2_dv_timings
*timings
)
1197 for (i
= 0; adv7604_timings
[i
].bt
.width
; i
++) {
1198 if (v4l2_match_dv_timings(timings
, &adv7604_timings
[i
],
1199 is_digital_input(sd
) ? 250000 : 1000000)) {
1200 *timings
= adv7604_timings
[i
];
1206 static int adv7604_query_dv_timings(struct v4l2_subdev
*sd
,
1207 struct v4l2_dv_timings
*timings
)
1209 struct adv7604_state
*state
= to_state(sd
);
1210 struct v4l2_bt_timings
*bt
= &timings
->bt
;
1211 struct stdi_readback stdi
;
1216 memset(timings
, 0, sizeof(struct v4l2_dv_timings
));
1218 if (no_signal(sd
)) {
1219 v4l2_dbg(1, debug
, sd
, "%s: no valid signal\n", __func__
);
1224 if (read_stdi(sd
, &stdi
)) {
1225 v4l2_dbg(1, debug
, sd
, "%s: STDI/SSPD not locked\n", __func__
);
1228 bt
->interlaced
= stdi
.interlaced
?
1229 V4L2_DV_INTERLACED
: V4L2_DV_PROGRESSIVE
;
1231 if (is_digital_input(sd
)) {
1234 timings
->type
= V4L2_DV_BT_656_1120
;
1236 bt
->width
= (hdmi_read(sd
, 0x07) & 0x0f) * 256 + hdmi_read(sd
, 0x08);
1237 bt
->height
= (hdmi_read(sd
, 0x09) & 0x0f) * 256 + hdmi_read(sd
, 0x0a);
1238 freq
= (hdmi_read(sd
, 0x06) * 1000000) +
1239 ((hdmi_read(sd
, 0x3b) & 0x30) >> 4) * 250000;
1241 /* adjust for deep color mode */
1242 unsigned bits_per_channel
= ((hdmi_read(sd
, 0x0b) & 0x60) >> 4) + 8;
1244 freq
= freq
* 8 / bits_per_channel
;
1246 bt
->pixelclock
= freq
;
1247 bt
->hfrontporch
= (hdmi_read(sd
, 0x20) & 0x03) * 256 +
1248 hdmi_read(sd
, 0x21);
1249 bt
->hsync
= (hdmi_read(sd
, 0x22) & 0x03) * 256 +
1250 hdmi_read(sd
, 0x23);
1251 bt
->hbackporch
= (hdmi_read(sd
, 0x24) & 0x03) * 256 +
1252 hdmi_read(sd
, 0x25);
1253 bt
->vfrontporch
= ((hdmi_read(sd
, 0x2a) & 0x1f) * 256 +
1254 hdmi_read(sd
, 0x2b)) / 2;
1255 bt
->vsync
= ((hdmi_read(sd
, 0x2e) & 0x1f) * 256 +
1256 hdmi_read(sd
, 0x2f)) / 2;
1257 bt
->vbackporch
= ((hdmi_read(sd
, 0x32) & 0x1f) * 256 +
1258 hdmi_read(sd
, 0x33)) / 2;
1259 bt
->polarities
= ((hdmi_read(sd
, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL
: 0) |
1260 ((hdmi_read(sd
, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL
: 0);
1261 if (bt
->interlaced
== V4L2_DV_INTERLACED
) {
1262 bt
->height
+= (hdmi_read(sd
, 0x0b) & 0x0f) * 256 +
1263 hdmi_read(sd
, 0x0c);
1264 bt
->il_vfrontporch
= ((hdmi_read(sd
, 0x2c) & 0x1f) * 256 +
1265 hdmi_read(sd
, 0x2d)) / 2;
1266 bt
->il_vsync
= ((hdmi_read(sd
, 0x30) & 0x1f) * 256 +
1267 hdmi_read(sd
, 0x31)) / 2;
1268 bt
->vbackporch
= ((hdmi_read(sd
, 0x34) & 0x1f) * 256 +
1269 hdmi_read(sd
, 0x35)) / 2;
1271 adv7604_fill_optional_dv_timings_fields(sd
, timings
);
1274 * Since LCVS values are inaccurate [REF_03, p. 275-276],
1275 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1277 if (!stdi2dv_timings(sd
, &stdi
, timings
))
1280 v4l2_dbg(1, debug
, sd
, "%s: lcvs + 1 = %d\n", __func__
, stdi
.lcvs
);
1281 if (!stdi2dv_timings(sd
, &stdi
, timings
))
1284 v4l2_dbg(1, debug
, sd
, "%s: lcvs - 1 = %d\n", __func__
, stdi
.lcvs
);
1285 if (stdi2dv_timings(sd
, &stdi
, timings
)) {
1287 * The STDI block may measure wrong values, especially
1288 * for lcvs and lcf. If the driver can not find any
1289 * valid timing, the STDI block is restarted to measure
1290 * the video timings again. The function will return an
1291 * error, but the restart of STDI will generate a new
1292 * STDI interrupt and the format detection process will
1295 if (state
->restart_stdi_once
) {
1296 v4l2_dbg(1, debug
, sd
, "%s: restart STDI\n", __func__
);
1297 /* TODO restart STDI for Sync Channel 2 */
1298 /* enter one-shot mode */
1299 cp_write_and_or(sd
, 0x86, 0xf9, 0x00);
1300 /* trigger STDI restart */
1301 cp_write_and_or(sd
, 0x86, 0xf9, 0x04);
1302 /* reset to continuous mode */
1303 cp_write_and_or(sd
, 0x86, 0xf9, 0x02);
1304 state
->restart_stdi_once
= false;
1307 v4l2_dbg(1, debug
, sd
, "%s: format not supported\n", __func__
);
1310 state
->restart_stdi_once
= true;
1314 if (no_signal(sd
)) {
1315 v4l2_dbg(1, debug
, sd
, "%s: signal lost during readout\n", __func__
);
1316 memset(timings
, 0, sizeof(struct v4l2_dv_timings
));
1320 if ((is_analog_input(sd
) && bt
->pixelclock
> 170000000) ||
1321 (is_digital_input(sd
) && bt
->pixelclock
> 225000000)) {
1322 v4l2_dbg(1, debug
, sd
, "%s: pixelclock out of range %d\n",
1323 __func__
, (u32
)bt
->pixelclock
);
1328 v4l2_print_dv_timings(sd
->name
, "adv7604_query_dv_timings: ",
1334 static int adv7604_s_dv_timings(struct v4l2_subdev
*sd
,
1335 struct v4l2_dv_timings
*timings
)
1337 struct adv7604_state
*state
= to_state(sd
);
1338 struct v4l2_bt_timings
*bt
;
1346 if ((is_analog_input(sd
) && bt
->pixelclock
> 170000000) ||
1347 (is_digital_input(sd
) && bt
->pixelclock
> 225000000)) {
1348 v4l2_dbg(1, debug
, sd
, "%s: pixelclock out of range %d\n",
1349 __func__
, (u32
)bt
->pixelclock
);
1353 adv7604_fill_optional_dv_timings_fields(sd
, timings
);
1355 state
->timings
= *timings
;
1357 cp_write(sd
, 0x91, bt
->interlaced
? 0x50 : 0x10);
1359 /* Use prim_mode and vid_std when available */
1360 err
= configure_predefined_video_timings(sd
, timings
);
1362 /* custom settings when the video format
1363 does not have prim_mode/vid_std */
1364 configure_custom_video_timings(sd
, bt
);
1367 set_rgb_quantization_range(sd
);
1371 v4l2_print_dv_timings(sd
->name
, "adv7604_s_dv_timings: ",
1376 static int adv7604_g_dv_timings(struct v4l2_subdev
*sd
,
1377 struct v4l2_dv_timings
*timings
)
1379 struct adv7604_state
*state
= to_state(sd
);
1381 *timings
= state
->timings
;
1385 static void enable_input(struct v4l2_subdev
*sd
)
1387 struct adv7604_state
*state
= to_state(sd
);
1389 if (is_analog_input(sd
)) {
1390 io_write(sd
, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1391 } else if (is_digital_input(sd
)) {
1392 hdmi_write_and_or(sd
, 0x00, 0xfc, state
->selected_input
);
1393 hdmi_write(sd
, 0x01, 0x00); /* Enable HDMI clock terminators */
1394 io_write(sd
, 0x15, 0xa0); /* Disable Tristate of Pins */
1395 hdmi_write_and_or(sd
, 0x1a, 0xef, 0x00); /* Unmute audio */
1397 v4l2_dbg(2, debug
, sd
, "%s: Unknown port %d selected\n",
1398 __func__
, state
->selected_input
);
1402 static void disable_input(struct v4l2_subdev
*sd
)
1404 hdmi_write_and_or(sd
, 0x1a, 0xef, 0x10); /* Mute audio */
1405 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1406 io_write(sd
, 0x15, 0xbe); /* Tristate all outputs from video core */
1407 hdmi_write(sd
, 0x01, 0x78); /* Disable HDMI clock terminators */
1410 static void select_input(struct v4l2_subdev
*sd
)
1412 struct adv7604_state
*state
= to_state(sd
);
1414 if (is_analog_input(sd
)) {
1415 /* reset ADI recommended settings for HDMI: */
1416 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1417 hdmi_write(sd
, 0x0d, 0x04); /* HDMI filter optimization */
1418 hdmi_write(sd
, 0x3d, 0x00); /* DDC bus active pull-up control */
1419 hdmi_write(sd
, 0x3e, 0x74); /* TMDS PLL optimization */
1420 hdmi_write(sd
, 0x4e, 0x3b); /* TMDS PLL optimization */
1421 hdmi_write(sd
, 0x57, 0x74); /* TMDS PLL optimization */
1422 hdmi_write(sd
, 0x58, 0x63); /* TMDS PLL optimization */
1423 hdmi_write(sd
, 0x8d, 0x18); /* equaliser */
1424 hdmi_write(sd
, 0x8e, 0x34); /* equaliser */
1425 hdmi_write(sd
, 0x93, 0x88); /* equaliser */
1426 hdmi_write(sd
, 0x94, 0x2e); /* equaliser */
1427 hdmi_write(sd
, 0x96, 0x00); /* enable automatic EQ changing */
1429 afe_write(sd
, 0x00, 0x08); /* power up ADC */
1430 afe_write(sd
, 0x01, 0x06); /* power up Analog Front End */
1431 afe_write(sd
, 0xc8, 0x00); /* phase control */
1433 /* set ADI recommended settings for digitizer */
1434 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1435 afe_write(sd
, 0x12, 0x7b); /* ADC noise shaping filter controls */
1436 afe_write(sd
, 0x0c, 0x1f); /* CP core gain controls */
1437 cp_write(sd
, 0x3e, 0x04); /* CP core pre-gain control */
1438 cp_write(sd
, 0xc3, 0x39); /* CP coast control. Graphics mode */
1439 cp_write(sd
, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1440 } else if (is_digital_input(sd
)) {
1441 hdmi_write(sd
, 0x00, state
->selected_input
& 0x03);
1443 /* set ADI recommended settings for HDMI: */
1444 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1445 hdmi_write(sd
, 0x0d, 0x84); /* HDMI filter optimization */
1446 hdmi_write(sd
, 0x3d, 0x10); /* DDC bus active pull-up control */
1447 hdmi_write(sd
, 0x3e, 0x39); /* TMDS PLL optimization */
1448 hdmi_write(sd
, 0x4e, 0x3b); /* TMDS PLL optimization */
1449 hdmi_write(sd
, 0x57, 0xb6); /* TMDS PLL optimization */
1450 hdmi_write(sd
, 0x58, 0x03); /* TMDS PLL optimization */
1451 hdmi_write(sd
, 0x8d, 0x18); /* equaliser */
1452 hdmi_write(sd
, 0x8e, 0x34); /* equaliser */
1453 hdmi_write(sd
, 0x93, 0x8b); /* equaliser */
1454 hdmi_write(sd
, 0x94, 0x2d); /* equaliser */
1455 hdmi_write(sd
, 0x96, 0x01); /* enable automatic EQ changing */
1457 afe_write(sd
, 0x00, 0xff); /* power down ADC */
1458 afe_write(sd
, 0x01, 0xfe); /* power down Analog Front End */
1459 afe_write(sd
, 0xc8, 0x40); /* phase control */
1461 /* reset ADI recommended settings for digitizer */
1462 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1463 afe_write(sd
, 0x12, 0xfb); /* ADC noise shaping filter controls */
1464 afe_write(sd
, 0x0c, 0x0d); /* CP core gain controls */
1465 cp_write(sd
, 0x3e, 0x00); /* CP core pre-gain control */
1466 cp_write(sd
, 0xc3, 0x39); /* CP coast control. Graphics mode */
1467 cp_write(sd
, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1469 v4l2_dbg(2, debug
, sd
, "%s: Unknown port %d selected\n",
1470 __func__
, state
->selected_input
);
1474 static int adv7604_s_routing(struct v4l2_subdev
*sd
,
1475 u32 input
, u32 output
, u32 config
)
1477 struct adv7604_state
*state
= to_state(sd
);
1479 v4l2_dbg(2, debug
, sd
, "%s: input %d, selected input %d",
1480 __func__
, input
, state
->selected_input
);
1482 if (input
== state
->selected_input
)
1485 state
->selected_input
= input
;
1496 static int adv7604_enum_mbus_fmt(struct v4l2_subdev
*sd
, unsigned int index
,
1497 enum v4l2_mbus_pixelcode
*code
)
1501 /* Good enough for now */
1502 *code
= V4L2_MBUS_FMT_FIXED
;
1506 static int adv7604_g_mbus_fmt(struct v4l2_subdev
*sd
,
1507 struct v4l2_mbus_framefmt
*fmt
)
1509 struct adv7604_state
*state
= to_state(sd
);
1511 fmt
->width
= state
->timings
.bt
.width
;
1512 fmt
->height
= state
->timings
.bt
.height
;
1513 fmt
->code
= V4L2_MBUS_FMT_FIXED
;
1514 fmt
->field
= V4L2_FIELD_NONE
;
1515 if (state
->timings
.bt
.standards
& V4L2_DV_BT_STD_CEA861
) {
1516 fmt
->colorspace
= (state
->timings
.bt
.height
<= 576) ?
1517 V4L2_COLORSPACE_SMPTE170M
: V4L2_COLORSPACE_REC709
;
1522 static int adv7604_isr(struct v4l2_subdev
*sd
, u32 status
, bool *handled
)
1524 u8 fmt_change
, fmt_change_digital
, tx_5v
;
1526 v4l2_dbg(2, debug
, sd
, "%s: ", __func__
);
1529 fmt_change
= io_read(sd
, 0x43) & 0x98;
1531 io_write(sd
, 0x44, fmt_change
);
1533 fmt_change_digital
= is_digital_input(sd
) ? (io_read(sd
, 0x6b) & 0xc0) : 0;
1534 if (fmt_change_digital
)
1535 io_write(sd
, 0x6c, fmt_change_digital
);
1537 if (fmt_change
|| fmt_change_digital
) {
1538 v4l2_dbg(1, debug
, sd
,
1539 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1540 __func__
, fmt_change
, fmt_change_digital
);
1542 v4l2_subdev_notify(sd
, ADV7604_FMT_CHANGE
, NULL
);
1548 tx_5v
= io_read(sd
, 0x70) & 0x1e;
1550 v4l2_dbg(1, debug
, sd
, "%s: tx_5v: 0x%x\n", __func__
, tx_5v
);
1551 io_write(sd
, 0x71, tx_5v
);
1552 adv7604_s_detect_tx_5v_ctrl(sd
);
1559 static int adv7604_get_edid(struct v4l2_subdev
*sd
, struct v4l2_subdev_edid
*edid
)
1561 struct adv7604_state
*state
= to_state(sd
);
1564 if (edid
->pad
> ADV7604_EDID_PORT_D
)
1566 if (edid
->blocks
== 0)
1568 if (edid
->blocks
> 2)
1570 if (edid
->start_block
> 1)
1572 if (edid
->start_block
== 1)
1577 if (edid
->blocks
> state
->edid
.blocks
)
1578 edid
->blocks
= state
->edid
.blocks
;
1580 switch (edid
->pad
) {
1581 case ADV7604_EDID_PORT_A
:
1582 case ADV7604_EDID_PORT_B
:
1583 case ADV7604_EDID_PORT_C
:
1584 case ADV7604_EDID_PORT_D
:
1585 if (state
->edid
.present
& (1 << edid
->pad
))
1586 data
= state
->edid
.edid
;
1596 data
+ edid
->start_block
* 128,
1597 edid
->blocks
* 128);
1601 static int get_edid_spa_location(const u8
*edid
)
1605 if ((edid
[0x7e] != 1) ||
1606 (edid
[0x80] != 0x02) ||
1607 (edid
[0x81] != 0x03)) {
1611 /* search Vendor Specific Data Block (tag 3) */
1612 d
= edid
[0x82] & 0x7f;
1618 u8 tag
= edid
[i
] >> 5;
1619 u8 len
= edid
[i
] & 0x1f;
1621 if ((tag
== 3) && (len
>= 5))
1629 static int adv7604_set_edid(struct v4l2_subdev
*sd
, struct v4l2_subdev_edid
*edid
)
1631 struct adv7604_state
*state
= to_state(sd
);
1637 if (edid
->pad
> ADV7604_EDID_PORT_D
)
1639 if (edid
->start_block
!= 0)
1641 if (edid
->blocks
== 0) {
1642 /* Disable hotplug and I2C access to EDID RAM from DDC port */
1643 state
->edid
.present
&= ~(1 << edid
->pad
);
1644 v4l2_subdev_notify(sd
, ADV7604_HOTPLUG
, (void *)&state
->edid
.present
);
1645 rep_write_and_or(sd
, 0x77, 0xf0, state
->edid
.present
);
1647 /* Fall back to a 16:9 aspect ratio */
1648 state
->aspect_ratio
.numerator
= 16;
1649 state
->aspect_ratio
.denominator
= 9;
1651 if (!state
->edid
.present
)
1652 state
->edid
.blocks
= 0;
1654 v4l2_dbg(2, debug
, sd
, "%s: clear EDID pad %d, edid.present = 0x%x\n",
1655 __func__
, edid
->pad
, state
->edid
.present
);
1658 if (edid
->blocks
> 2) {
1665 v4l2_dbg(2, debug
, sd
, "%s: write EDID pad %d, edid.present = 0x%x\n",
1666 __func__
, edid
->pad
, state
->edid
.present
);
1668 /* Disable hotplug and I2C access to EDID RAM from DDC port */
1669 cancel_delayed_work_sync(&state
->delayed_work_enable_hotplug
);
1670 v4l2_subdev_notify(sd
, ADV7604_HOTPLUG
, (void *)&tmp
);
1671 rep_write_and_or(sd
, 0x77, 0xf0, 0x00);
1673 spa_loc
= get_edid_spa_location(edid
->edid
);
1675 spa_loc
= 0xc0; /* Default value [REF_02, p. 116] */
1677 switch (edid
->pad
) {
1678 case ADV7604_EDID_PORT_A
:
1679 state
->spa_port_a
[0] = edid
->edid
[spa_loc
];
1680 state
->spa_port_a
[1] = edid
->edid
[spa_loc
+ 1];
1682 case ADV7604_EDID_PORT_B
:
1683 rep_write(sd
, 0x70, edid
->edid
[spa_loc
]);
1684 rep_write(sd
, 0x71, edid
->edid
[spa_loc
+ 1]);
1686 case ADV7604_EDID_PORT_C
:
1687 rep_write(sd
, 0x72, edid
->edid
[spa_loc
]);
1688 rep_write(sd
, 0x73, edid
->edid
[spa_loc
+ 1]);
1690 case ADV7604_EDID_PORT_D
:
1691 rep_write(sd
, 0x74, edid
->edid
[spa_loc
]);
1692 rep_write(sd
, 0x75, edid
->edid
[spa_loc
+ 1]);
1697 rep_write(sd
, 0x76, spa_loc
& 0xff);
1698 rep_write_and_or(sd
, 0x77, 0xbf, (spa_loc
>> 2) & 0x40);
1700 edid
->edid
[spa_loc
] = state
->spa_port_a
[0];
1701 edid
->edid
[spa_loc
+ 1] = state
->spa_port_a
[1];
1703 memcpy(state
->edid
.edid
, edid
->edid
, 128 * edid
->blocks
);
1704 state
->edid
.blocks
= edid
->blocks
;
1705 state
->aspect_ratio
= v4l2_calc_aspect_ratio(edid
->edid
[0x15],
1707 state
->edid
.present
|= 1 << edid
->pad
;
1709 err
= edid_write_block(sd
, 128 * edid
->blocks
, state
->edid
.edid
);
1711 v4l2_err(sd
, "error %d writing edid pad %d\n", err
, edid
->pad
);
1715 /* adv7604 calculates the checksums and enables I2C access to internal
1716 EDID RAM from DDC port. */
1717 rep_write_and_or(sd
, 0x77, 0xf0, state
->edid
.present
);
1719 for (i
= 0; i
< 1000; i
++) {
1720 if (rep_read(sd
, 0x7d) & state
->edid
.present
)
1725 v4l2_err(sd
, "error enabling edid (0x%x)\n", state
->edid
.present
);
1730 /* enable hotplug after 100 ms */
1731 queue_delayed_work(state
->work_queues
,
1732 &state
->delayed_work_enable_hotplug
, HZ
/ 10);
1736 /*********** avi info frame CEA-861-E **************/
1738 static void print_avi_infoframe(struct v4l2_subdev
*sd
)
1746 v4l2_info(sd
, "receive DVI-D signal (AVI infoframe not supported)\n");
1749 if (!(io_read(sd
, 0x60) & 0x01)) {
1750 v4l2_info(sd
, "AVI infoframe not received\n");
1754 if (io_read(sd
, 0x83) & 0x01) {
1755 v4l2_info(sd
, "AVI infoframe checksum error has occurred earlier\n");
1756 io_write(sd
, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1757 if (io_read(sd
, 0x83) & 0x01) {
1758 v4l2_info(sd
, "AVI infoframe checksum error still present\n");
1759 io_write(sd
, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1763 avi_len
= infoframe_read(sd
, 0xe2);
1764 avi_ver
= infoframe_read(sd
, 0xe1);
1765 v4l2_info(sd
, "AVI infoframe version %d (%d byte)\n",
1768 if (avi_ver
!= 0x02)
1771 for (i
= 0; i
< 14; i
++)
1772 buf
[i
] = infoframe_read(sd
, i
);
1775 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1776 buf
[0], buf
[1], buf
[2], buf
[3], buf
[4], buf
[5], buf
[6], buf
[7],
1777 buf
[8], buf
[9], buf
[10], buf
[11], buf
[12], buf
[13]);
1780 static int adv7604_log_status(struct v4l2_subdev
*sd
)
1782 struct adv7604_state
*state
= to_state(sd
);
1783 struct v4l2_dv_timings timings
;
1784 struct stdi_readback stdi
;
1785 u8 reg_io_0x02
= io_read(sd
, 0x02);
1787 char *csc_coeff_sel_rb
[16] = {
1788 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1789 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1790 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1791 "reserved", "reserved", "reserved", "reserved", "manual"
1793 char *input_color_space_txt
[16] = {
1794 "RGB limited range (16-235)", "RGB full range (0-255)",
1795 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1796 "xvYCC Bt.601", "xvYCC Bt.709",
1797 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1798 "invalid", "invalid", "invalid", "invalid", "invalid",
1799 "invalid", "invalid", "automatic"
1801 char *rgb_quantization_range_txt
[] = {
1803 "RGB limited range (16-235)",
1804 "RGB full range (0-255)",
1806 char *deep_color_mode_txt
[4] = {
1807 "8-bits per channel",
1808 "10-bits per channel",
1809 "12-bits per channel",
1810 "16-bits per channel (not supported)"
1813 v4l2_info(sd
, "-----Chip status-----\n");
1814 v4l2_info(sd
, "Chip power: %s\n", no_power(sd
) ? "off" : "on");
1815 v4l2_info(sd
, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
1816 ((rep_read(sd
, 0x7d) & 0x01) ? "Yes" : "No"),
1817 ((rep_read(sd
, 0x7d) & 0x02) ? "Yes" : "No"),
1818 ((rep_read(sd
, 0x7d) & 0x04) ? "Yes" : "No"),
1819 ((rep_read(sd
, 0x7d) & 0x08) ? "Yes" : "No"));
1820 v4l2_info(sd
, "CEC: %s\n", !!(cec_read(sd
, 0x2a) & 0x01) ?
1821 "enabled" : "disabled");
1823 v4l2_info(sd
, "-----Signal status-----\n");
1824 v4l2_info(sd
, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
1825 ((io_read(sd
, 0x6f) & 0x10) ? "Yes" : "No"),
1826 ((io_read(sd
, 0x6f) & 0x08) ? "Yes" : "No"),
1827 ((io_read(sd
, 0x6f) & 0x04) ? "Yes" : "No"),
1828 ((io_read(sd
, 0x6f) & 0x02) ? "Yes" : "No"));
1829 v4l2_info(sd
, "TMDS signal detected: %s\n",
1830 no_signal_tmds(sd
) ? "false" : "true");
1831 v4l2_info(sd
, "TMDS signal locked: %s\n",
1832 no_lock_tmds(sd
) ? "false" : "true");
1833 v4l2_info(sd
, "SSPD locked: %s\n", no_lock_sspd(sd
) ? "false" : "true");
1834 v4l2_info(sd
, "STDI locked: %s\n", no_lock_stdi(sd
) ? "false" : "true");
1835 v4l2_info(sd
, "CP locked: %s\n", no_lock_cp(sd
) ? "false" : "true");
1836 v4l2_info(sd
, "CP free run: %s\n",
1837 (!!(cp_read(sd
, 0xff) & 0x10) ? "on" : "off"));
1838 v4l2_info(sd
, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1839 io_read(sd
, 0x01) & 0x0f, io_read(sd
, 0x00) & 0x3f,
1840 (io_read(sd
, 0x01) & 0x70) >> 4);
1842 v4l2_info(sd
, "-----Video Timings-----\n");
1843 if (read_stdi(sd
, &stdi
))
1844 v4l2_info(sd
, "STDI: not locked\n");
1846 v4l2_info(sd
, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1847 stdi
.lcf
, stdi
.bl
, stdi
.lcvs
,
1848 stdi
.interlaced
? "interlaced" : "progressive",
1849 stdi
.hs_pol
, stdi
.vs_pol
);
1850 if (adv7604_query_dv_timings(sd
, &timings
))
1851 v4l2_info(sd
, "No video detected\n");
1853 v4l2_print_dv_timings(sd
->name
, "Detected format: ",
1855 v4l2_print_dv_timings(sd
->name
, "Configured format: ",
1856 &state
->timings
, true);
1861 v4l2_info(sd
, "-----Color space-----\n");
1862 v4l2_info(sd
, "RGB quantization range ctrl: %s\n",
1863 rgb_quantization_range_txt
[state
->rgb_quantization_range
]);
1864 v4l2_info(sd
, "Input color space: %s\n",
1865 input_color_space_txt
[reg_io_0x02
>> 4]);
1866 v4l2_info(sd
, "Output color space: %s %s, saturator %s\n",
1867 (reg_io_0x02
& 0x02) ? "RGB" : "YCbCr",
1868 (reg_io_0x02
& 0x04) ? "(16-235)" : "(0-255)",
1869 ((reg_io_0x02
& 0x04) ^ (reg_io_0x02
& 0x01)) ?
1870 "enabled" : "disabled");
1871 v4l2_info(sd
, "Color space conversion: %s\n",
1872 csc_coeff_sel_rb
[cp_read(sd
, 0xfc) >> 4]);
1874 if (!is_digital_input(sd
))
1877 v4l2_info(sd
, "-----%s status-----\n", is_hdmi(sd
) ? "HDMI" : "DVI-D");
1878 v4l2_info(sd
, "Digital video port selected: %c\n",
1879 (hdmi_read(sd
, 0x00) & 0x03) + 'A');
1880 v4l2_info(sd
, "HDCP encrypted content: %s\n",
1881 (hdmi_read(sd
, 0x05) & 0x40) ? "true" : "false");
1882 v4l2_info(sd
, "HDCP keys read: %s%s\n",
1883 (hdmi_read(sd
, 0x04) & 0x20) ? "yes" : "no",
1884 (hdmi_read(sd
, 0x04) & 0x10) ? "ERROR" : "");
1886 bool audio_pll_locked
= hdmi_read(sd
, 0x04) & 0x01;
1887 bool audio_sample_packet_detect
= hdmi_read(sd
, 0x18) & 0x01;
1888 bool audio_mute
= io_read(sd
, 0x65) & 0x40;
1890 v4l2_info(sd
, "Audio: pll %s, samples %s, %s\n",
1891 audio_pll_locked
? "locked" : "not locked",
1892 audio_sample_packet_detect
? "detected" : "not detected",
1893 audio_mute
? "muted" : "enabled");
1894 if (audio_pll_locked
&& audio_sample_packet_detect
) {
1895 v4l2_info(sd
, "Audio format: %s\n",
1896 (hdmi_read(sd
, 0x07) & 0x20) ? "multi-channel" : "stereo");
1898 v4l2_info(sd
, "Audio CTS: %u\n", (hdmi_read(sd
, 0x5b) << 12) +
1899 (hdmi_read(sd
, 0x5c) << 8) +
1900 (hdmi_read(sd
, 0x5d) & 0xf0));
1901 v4l2_info(sd
, "Audio N: %u\n", ((hdmi_read(sd
, 0x5d) & 0x0f) << 16) +
1902 (hdmi_read(sd
, 0x5e) << 8) +
1903 hdmi_read(sd
, 0x5f));
1904 v4l2_info(sd
, "AV Mute: %s\n", (hdmi_read(sd
, 0x04) & 0x40) ? "on" : "off");
1906 v4l2_info(sd
, "Deep color mode: %s\n", deep_color_mode_txt
[(hdmi_read(sd
, 0x0b) & 0x60) >> 5]);
1908 print_avi_infoframe(sd
);
1914 /* ----------------------------------------------------------------------- */
1916 static const struct v4l2_ctrl_ops adv7604_ctrl_ops
= {
1917 .s_ctrl
= adv7604_s_ctrl
,
1920 static const struct v4l2_subdev_core_ops adv7604_core_ops
= {
1921 .log_status
= adv7604_log_status
,
1922 .g_ext_ctrls
= v4l2_subdev_g_ext_ctrls
,
1923 .try_ext_ctrls
= v4l2_subdev_try_ext_ctrls
,
1924 .s_ext_ctrls
= v4l2_subdev_s_ext_ctrls
,
1925 .g_ctrl
= v4l2_subdev_g_ctrl
,
1926 .s_ctrl
= v4l2_subdev_s_ctrl
,
1927 .queryctrl
= v4l2_subdev_queryctrl
,
1928 .querymenu
= v4l2_subdev_querymenu
,
1929 .interrupt_service_routine
= adv7604_isr
,
1930 #ifdef CONFIG_VIDEO_ADV_DEBUG
1931 .g_register
= adv7604_g_register
,
1932 .s_register
= adv7604_s_register
,
1936 static const struct v4l2_subdev_video_ops adv7604_video_ops
= {
1937 .s_routing
= adv7604_s_routing
,
1938 .g_input_status
= adv7604_g_input_status
,
1939 .s_dv_timings
= adv7604_s_dv_timings
,
1940 .g_dv_timings
= adv7604_g_dv_timings
,
1941 .query_dv_timings
= adv7604_query_dv_timings
,
1942 .enum_dv_timings
= adv7604_enum_dv_timings
,
1943 .dv_timings_cap
= adv7604_dv_timings_cap
,
1944 .enum_mbus_fmt
= adv7604_enum_mbus_fmt
,
1945 .g_mbus_fmt
= adv7604_g_mbus_fmt
,
1946 .try_mbus_fmt
= adv7604_g_mbus_fmt
,
1947 .s_mbus_fmt
= adv7604_g_mbus_fmt
,
1950 static const struct v4l2_subdev_pad_ops adv7604_pad_ops
= {
1951 .get_edid
= adv7604_get_edid
,
1952 .set_edid
= adv7604_set_edid
,
1955 static const struct v4l2_subdev_ops adv7604_ops
= {
1956 .core
= &adv7604_core_ops
,
1957 .video
= &adv7604_video_ops
,
1958 .pad
= &adv7604_pad_ops
,
1961 /* -------------------------- custom ctrls ---------------------------------- */
1963 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase
= {
1964 .ops
= &adv7604_ctrl_ops
,
1965 .id
= V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE
,
1966 .name
= "Analog Sampling Phase",
1967 .type
= V4L2_CTRL_TYPE_INTEGER
,
1974 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual
= {
1975 .ops
= &adv7604_ctrl_ops
,
1976 .id
= V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL
,
1977 .name
= "Free Running Color, Manual",
1978 .type
= V4L2_CTRL_TYPE_BOOLEAN
,
1985 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color
= {
1986 .ops
= &adv7604_ctrl_ops
,
1987 .id
= V4L2_CID_ADV_RX_FREE_RUN_COLOR
,
1988 .name
= "Free Running Color",
1989 .type
= V4L2_CTRL_TYPE_INTEGER
,
1996 /* ----------------------------------------------------------------------- */
1998 static int adv7604_core_init(struct v4l2_subdev
*sd
)
2000 struct adv7604_state
*state
= to_state(sd
);
2001 struct adv7604_platform_data
*pdata
= &state
->pdata
;
2003 hdmi_write(sd
, 0x48,
2004 (pdata
->disable_pwrdnb
? 0x80 : 0) |
2005 (pdata
->disable_cable_det_rst
? 0x40 : 0));
2010 io_write(sd
, 0x0c, 0x42); /* Power up part and power down VDP */
2011 io_write(sd
, 0x0b, 0x44); /* Power down ESDP block */
2012 cp_write(sd
, 0xcf, 0x01); /* Power down macrovision */
2015 io_write_and_or(sd
, 0x02, 0xf0,
2016 pdata
->alt_gamma
<< 3 |
2017 pdata
->op_656_range
<< 2 |
2018 pdata
->rgb_out
<< 1 |
2019 pdata
->alt_data_sat
<< 0);
2020 io_write(sd
, 0x03, pdata
->op_format_sel
);
2021 io_write_and_or(sd
, 0x04, 0x1f, pdata
->op_ch_sel
<< 5);
2022 io_write_and_or(sd
, 0x05, 0xf0, pdata
->blank_data
<< 3 |
2023 pdata
->insert_av_codes
<< 2 |
2024 pdata
->replicate_av_codes
<< 1 |
2025 pdata
->invert_cbcr
<< 0);
2027 /* TODO from platform data */
2028 cp_write(sd
, 0x69, 0x30); /* Enable CP CSC */
2029 io_write(sd
, 0x06, 0xa6); /* positive VS and HS */
2031 /* Adjust drive strength */
2032 io_write(sd
, 0x14, 0x40 | pdata
->dr_str_data
<< 4 |
2033 pdata
->dr_str_clk
<< 2 |
2034 pdata
->dr_str_sync
);
2036 cp_write(sd
, 0xba, (pdata
->hdmi_free_run_mode
<< 1) | 0x01); /* HDMI free run */
2037 cp_write(sd
, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2038 cp_write(sd
, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
2039 ADI recommended setting [REF_01, c. 2.3.3] */
2040 cp_write(sd
, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
2041 ADI recommended setting [REF_01, c. 2.3.3] */
2042 cp_write(sd
, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2043 for digital formats */
2046 hdmi_write_and_or(sd
, 0x15, 0xfc, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2047 hdmi_write_and_or(sd
, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2048 hdmi_write_and_or(sd
, 0x68, 0xf9, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2050 /* TODO from platform data */
2051 afe_write(sd
, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2053 afe_write(sd
, 0x02, pdata
->ain_sel
); /* Select analog input muxing mode */
2054 io_write_and_or(sd
, 0x30, ~(1 << 4), pdata
->output_bus_lsb_to_msb
<< 4);
2057 io_write(sd
, 0x40, 0xc2); /* Configure INT1 */
2058 io_write(sd
, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2059 io_write(sd
, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2060 io_write(sd
, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2061 io_write(sd
, 0x73, 0x1e); /* Enable CABLE_DET_A_ST (+5v) interrupts */
2063 return v4l2_ctrl_handler_setup(sd
->ctrl_handler
);
2066 static void adv7604_unregister_clients(struct adv7604_state
*state
)
2068 if (state
->i2c_avlink
)
2069 i2c_unregister_device(state
->i2c_avlink
);
2071 i2c_unregister_device(state
->i2c_cec
);
2072 if (state
->i2c_infoframe
)
2073 i2c_unregister_device(state
->i2c_infoframe
);
2074 if (state
->i2c_esdp
)
2075 i2c_unregister_device(state
->i2c_esdp
);
2077 i2c_unregister_device(state
->i2c_dpp
);
2079 i2c_unregister_device(state
->i2c_afe
);
2080 if (state
->i2c_repeater
)
2081 i2c_unregister_device(state
->i2c_repeater
);
2082 if (state
->i2c_edid
)
2083 i2c_unregister_device(state
->i2c_edid
);
2084 if (state
->i2c_hdmi
)
2085 i2c_unregister_device(state
->i2c_hdmi
);
2086 if (state
->i2c_test
)
2087 i2c_unregister_device(state
->i2c_test
);
2089 i2c_unregister_device(state
->i2c_cp
);
2091 i2c_unregister_device(state
->i2c_vdp
);
2094 static struct i2c_client
*adv7604_dummy_client(struct v4l2_subdev
*sd
,
2097 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
2100 io_write(sd
, io_reg
, addr
<< 1);
2101 return i2c_new_dummy(client
->adapter
, io_read(sd
, io_reg
) >> 1);
2104 static int adv7604_probe(struct i2c_client
*client
,
2105 const struct i2c_device_id
*id
)
2107 struct adv7604_state
*state
;
2108 struct adv7604_platform_data
*pdata
= client
->dev
.platform_data
;
2109 struct v4l2_ctrl_handler
*hdl
;
2110 struct v4l2_subdev
*sd
;
2113 /* Check if the adapter supports the needed features */
2114 if (!i2c_check_functionality(client
->adapter
, I2C_FUNC_SMBUS_BYTE_DATA
))
2116 v4l_dbg(1, debug
, client
, "detecting adv7604 client on address 0x%x\n",
2119 state
= devm_kzalloc(&client
->dev
, sizeof(*state
), GFP_KERNEL
);
2121 v4l_err(client
, "Could not allocate adv7604_state memory!\n");
2125 /* initialize variables */
2126 state
->restart_stdi_once
= true;
2127 state
->selected_input
= ~0;
2131 v4l_err(client
, "No platform data!\n");
2134 memcpy(&state
->pdata
, pdata
, sizeof(state
->pdata
));
2137 v4l2_i2c_subdev_init(sd
, client
, &adv7604_ops
);
2138 sd
->flags
|= V4L2_SUBDEV_FL_HAS_DEVNODE
;
2140 /* i2c access to adv7604? */
2141 if (adv_smbus_read_byte_data_check(client
, 0xfb, false) != 0x68) {
2142 v4l2_info(sd
, "not an adv7604 on address 0x%x\n",
2147 /* control handlers */
2149 v4l2_ctrl_handler_init(hdl
, 9);
2151 v4l2_ctrl_new_std(hdl
, &adv7604_ctrl_ops
,
2152 V4L2_CID_BRIGHTNESS
, -128, 127, 1, 0);
2153 v4l2_ctrl_new_std(hdl
, &adv7604_ctrl_ops
,
2154 V4L2_CID_CONTRAST
, 0, 255, 1, 128);
2155 v4l2_ctrl_new_std(hdl
, &adv7604_ctrl_ops
,
2156 V4L2_CID_SATURATION
, 0, 255, 1, 128);
2157 v4l2_ctrl_new_std(hdl
, &adv7604_ctrl_ops
,
2158 V4L2_CID_HUE
, 0, 128, 1, 0);
2160 /* private controls */
2161 state
->detect_tx_5v_ctrl
= v4l2_ctrl_new_std(hdl
, NULL
,
2162 V4L2_CID_DV_RX_POWER_PRESENT
, 0, 0x0f, 0, 0);
2163 state
->rgb_quantization_range_ctrl
=
2164 v4l2_ctrl_new_std_menu(hdl
, &adv7604_ctrl_ops
,
2165 V4L2_CID_DV_RX_RGB_RANGE
, V4L2_DV_RGB_RANGE_FULL
,
2166 0, V4L2_DV_RGB_RANGE_AUTO
);
2168 /* custom controls */
2169 state
->analog_sampling_phase_ctrl
=
2170 v4l2_ctrl_new_custom(hdl
, &adv7604_ctrl_analog_sampling_phase
, NULL
);
2171 state
->free_run_color_manual_ctrl
=
2172 v4l2_ctrl_new_custom(hdl
, &adv7604_ctrl_free_run_color_manual
, NULL
);
2173 state
->free_run_color_ctrl
=
2174 v4l2_ctrl_new_custom(hdl
, &adv7604_ctrl_free_run_color
, NULL
);
2176 sd
->ctrl_handler
= hdl
;
2181 state
->detect_tx_5v_ctrl
->is_private
= true;
2182 state
->rgb_quantization_range_ctrl
->is_private
= true;
2183 state
->analog_sampling_phase_ctrl
->is_private
= true;
2184 state
->free_run_color_manual_ctrl
->is_private
= true;
2185 state
->free_run_color_ctrl
->is_private
= true;
2187 if (adv7604_s_detect_tx_5v_ctrl(sd
)) {
2192 state
->i2c_avlink
= adv7604_dummy_client(sd
, pdata
->i2c_avlink
, 0xf3);
2193 state
->i2c_cec
= adv7604_dummy_client(sd
, pdata
->i2c_cec
, 0xf4);
2194 state
->i2c_infoframe
= adv7604_dummy_client(sd
, pdata
->i2c_infoframe
, 0xf5);
2195 state
->i2c_esdp
= adv7604_dummy_client(sd
, pdata
->i2c_esdp
, 0xf6);
2196 state
->i2c_dpp
= adv7604_dummy_client(sd
, pdata
->i2c_dpp
, 0xf7);
2197 state
->i2c_afe
= adv7604_dummy_client(sd
, pdata
->i2c_afe
, 0xf8);
2198 state
->i2c_repeater
= adv7604_dummy_client(sd
, pdata
->i2c_repeater
, 0xf9);
2199 state
->i2c_edid
= adv7604_dummy_client(sd
, pdata
->i2c_edid
, 0xfa);
2200 state
->i2c_hdmi
= adv7604_dummy_client(sd
, pdata
->i2c_hdmi
, 0xfb);
2201 state
->i2c_test
= adv7604_dummy_client(sd
, pdata
->i2c_test
, 0xfc);
2202 state
->i2c_cp
= adv7604_dummy_client(sd
, pdata
->i2c_cp
, 0xfd);
2203 state
->i2c_vdp
= adv7604_dummy_client(sd
, pdata
->i2c_vdp
, 0xfe);
2204 if (!state
->i2c_avlink
|| !state
->i2c_cec
|| !state
->i2c_infoframe
||
2205 !state
->i2c_esdp
|| !state
->i2c_dpp
|| !state
->i2c_afe
||
2206 !state
->i2c_repeater
|| !state
->i2c_edid
|| !state
->i2c_hdmi
||
2207 !state
->i2c_test
|| !state
->i2c_cp
|| !state
->i2c_vdp
) {
2209 v4l2_err(sd
, "failed to create all i2c clients\n");
2214 state
->work_queues
= create_singlethread_workqueue(client
->name
);
2215 if (!state
->work_queues
) {
2216 v4l2_err(sd
, "Could not create work queue\n");
2221 INIT_DELAYED_WORK(&state
->delayed_work_enable_hotplug
,
2222 adv7604_delayed_work_enable_hotplug
);
2224 state
->pad
.flags
= MEDIA_PAD_FL_SOURCE
;
2225 err
= media_entity_init(&sd
->entity
, 1, &state
->pad
, 0);
2227 goto err_work_queues
;
2229 err
= adv7604_core_init(sd
);
2232 v4l2_info(sd
, "%s found @ 0x%x (%s)\n", client
->name
,
2233 client
->addr
<< 1, client
->adapter
->name
);
2237 media_entity_cleanup(&sd
->entity
);
2239 cancel_delayed_work(&state
->delayed_work_enable_hotplug
);
2240 destroy_workqueue(state
->work_queues
);
2242 adv7604_unregister_clients(state
);
2244 v4l2_ctrl_handler_free(hdl
);
2248 /* ----------------------------------------------------------------------- */
2250 static int adv7604_remove(struct i2c_client
*client
)
2252 struct v4l2_subdev
*sd
= i2c_get_clientdata(client
);
2253 struct adv7604_state
*state
= to_state(sd
);
2255 cancel_delayed_work(&state
->delayed_work_enable_hotplug
);
2256 destroy_workqueue(state
->work_queues
);
2257 v4l2_device_unregister_subdev(sd
);
2258 media_entity_cleanup(&sd
->entity
);
2259 adv7604_unregister_clients(to_state(sd
));
2260 v4l2_ctrl_handler_free(sd
->ctrl_handler
);
2264 /* ----------------------------------------------------------------------- */
2266 static struct i2c_device_id adv7604_id
[] = {
2270 MODULE_DEVICE_TABLE(i2c
, adv7604_id
);
2272 static struct i2c_driver adv7604_driver
= {
2274 .owner
= THIS_MODULE
,
2277 .probe
= adv7604_probe
,
2278 .remove
= adv7604_remove
,
2279 .id_table
= adv7604_id
,
2282 module_i2c_driver(adv7604_driver
);