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[media] media: i2c: remove duplicate checks for EPERM in dbg_g/s_register
[deliverable/linux.git] / drivers / media / i2c / adv7604.c
1 /*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21 /*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
30
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/i2c.h>
35 #include <linux/delay.h>
36 #include <linux/videodev2.h>
37 #include <linux/workqueue.h>
38 #include <linux/v4l2-dv-timings.h>
39 #include <media/v4l2-device.h>
40 #include <media/v4l2-ctrls.h>
41 #include <media/v4l2-chip-ident.h>
42 #include <media/adv7604.h>
43
44 static int debug;
45 module_param(debug, int, 0644);
46 MODULE_PARM_DESC(debug, "debug level (0-2)");
47
48 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
49 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
50 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
51 MODULE_LICENSE("GPL");
52
53 /* ADV7604 system clock frequency */
54 #define ADV7604_fsc (28636360)
55
56 #define DIGITAL_INPUT (state->mode == ADV7604_MODE_HDMI)
57
58 /*
59 **********************************************************************
60 *
61 * Arrays with configuration parameters for the ADV7604
62 *
63 **********************************************************************
64 */
65 struct adv7604_state {
66 struct adv7604_platform_data pdata;
67 struct v4l2_subdev sd;
68 struct media_pad pad;
69 struct v4l2_ctrl_handler hdl;
70 enum adv7604_mode mode;
71 struct v4l2_dv_timings timings;
72 u8 edid[256];
73 unsigned edid_blocks;
74 struct v4l2_fract aspect_ratio;
75 u32 rgb_quantization_range;
76 struct workqueue_struct *work_queues;
77 struct delayed_work delayed_work_enable_hotplug;
78 bool connector_hdmi;
79 bool restart_stdi_once;
80
81 /* i2c clients */
82 struct i2c_client *i2c_avlink;
83 struct i2c_client *i2c_cec;
84 struct i2c_client *i2c_infoframe;
85 struct i2c_client *i2c_esdp;
86 struct i2c_client *i2c_dpp;
87 struct i2c_client *i2c_afe;
88 struct i2c_client *i2c_repeater;
89 struct i2c_client *i2c_edid;
90 struct i2c_client *i2c_hdmi;
91 struct i2c_client *i2c_test;
92 struct i2c_client *i2c_cp;
93 struct i2c_client *i2c_vdp;
94
95 /* controls */
96 struct v4l2_ctrl *detect_tx_5v_ctrl;
97 struct v4l2_ctrl *analog_sampling_phase_ctrl;
98 struct v4l2_ctrl *free_run_color_manual_ctrl;
99 struct v4l2_ctrl *free_run_color_ctrl;
100 struct v4l2_ctrl *rgb_quantization_range_ctrl;
101 };
102
103 /* Supported CEA and DMT timings */
104 static const struct v4l2_dv_timings adv7604_timings[] = {
105 V4L2_DV_BT_CEA_720X480P59_94,
106 V4L2_DV_BT_CEA_720X576P50,
107 V4L2_DV_BT_CEA_1280X720P24,
108 V4L2_DV_BT_CEA_1280X720P25,
109 V4L2_DV_BT_CEA_1280X720P50,
110 V4L2_DV_BT_CEA_1280X720P60,
111 V4L2_DV_BT_CEA_1920X1080P24,
112 V4L2_DV_BT_CEA_1920X1080P25,
113 V4L2_DV_BT_CEA_1920X1080P30,
114 V4L2_DV_BT_CEA_1920X1080P50,
115 V4L2_DV_BT_CEA_1920X1080P60,
116
117 /* sorted by DMT ID */
118 V4L2_DV_BT_DMT_640X350P85,
119 V4L2_DV_BT_DMT_640X400P85,
120 V4L2_DV_BT_DMT_720X400P85,
121 V4L2_DV_BT_DMT_640X480P60,
122 V4L2_DV_BT_DMT_640X480P72,
123 V4L2_DV_BT_DMT_640X480P75,
124 V4L2_DV_BT_DMT_640X480P85,
125 V4L2_DV_BT_DMT_800X600P56,
126 V4L2_DV_BT_DMT_800X600P60,
127 V4L2_DV_BT_DMT_800X600P72,
128 V4L2_DV_BT_DMT_800X600P75,
129 V4L2_DV_BT_DMT_800X600P85,
130 V4L2_DV_BT_DMT_848X480P60,
131 V4L2_DV_BT_DMT_1024X768P60,
132 V4L2_DV_BT_DMT_1024X768P70,
133 V4L2_DV_BT_DMT_1024X768P75,
134 V4L2_DV_BT_DMT_1024X768P85,
135 V4L2_DV_BT_DMT_1152X864P75,
136 V4L2_DV_BT_DMT_1280X768P60_RB,
137 V4L2_DV_BT_DMT_1280X768P60,
138 V4L2_DV_BT_DMT_1280X768P75,
139 V4L2_DV_BT_DMT_1280X768P85,
140 V4L2_DV_BT_DMT_1280X800P60_RB,
141 V4L2_DV_BT_DMT_1280X800P60,
142 V4L2_DV_BT_DMT_1280X800P75,
143 V4L2_DV_BT_DMT_1280X800P85,
144 V4L2_DV_BT_DMT_1280X960P60,
145 V4L2_DV_BT_DMT_1280X960P85,
146 V4L2_DV_BT_DMT_1280X1024P60,
147 V4L2_DV_BT_DMT_1280X1024P75,
148 V4L2_DV_BT_DMT_1280X1024P85,
149 V4L2_DV_BT_DMT_1360X768P60,
150 V4L2_DV_BT_DMT_1400X1050P60_RB,
151 V4L2_DV_BT_DMT_1400X1050P60,
152 V4L2_DV_BT_DMT_1400X1050P75,
153 V4L2_DV_BT_DMT_1400X1050P85,
154 V4L2_DV_BT_DMT_1440X900P60_RB,
155 V4L2_DV_BT_DMT_1440X900P60,
156 V4L2_DV_BT_DMT_1600X1200P60,
157 V4L2_DV_BT_DMT_1680X1050P60_RB,
158 V4L2_DV_BT_DMT_1680X1050P60,
159 V4L2_DV_BT_DMT_1792X1344P60,
160 V4L2_DV_BT_DMT_1856X1392P60,
161 V4L2_DV_BT_DMT_1920X1200P60_RB,
162 V4L2_DV_BT_DMT_1366X768P60,
163 V4L2_DV_BT_DMT_1920X1080P60,
164 { },
165 };
166
167 struct adv7604_video_standards {
168 struct v4l2_dv_timings timings;
169 u8 vid_std;
170 u8 v_freq;
171 };
172
173 /* sorted by number of lines */
174 static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
175 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
176 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
177 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
178 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
179 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
180 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
181 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
182 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
183 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
184 /* TODO add 1920x1080P60_RB (CVT timing) */
185 { },
186 };
187
188 /* sorted by number of lines */
189 static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
190 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
191 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
192 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
193 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
194 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
195 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
199 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
200 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
203 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
204 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
205 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
206 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
207 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
208 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
209 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
210 /* TODO add 1600X1200P60_RB (not a DMT timing) */
211 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
212 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
213 { },
214 };
215
216 /* sorted by number of lines */
217 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
218 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
219 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
220 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
221 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
222 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
223 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
224 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
225 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
226 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
227 { },
228 };
229
230 /* sorted by number of lines */
231 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
232 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
233 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
234 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
235 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
236 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
237 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
238 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
240 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
241 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
242 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
243 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
244 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
245 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
246 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
247 { },
248 };
249
250 /* ----------------------------------------------------------------------- */
251
252 static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
253 {
254 return container_of(sd, struct adv7604_state, sd);
255 }
256
257 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
258 {
259 return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
260 }
261
262 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
263 {
264 return t->hfrontporch + t->hsync + t->hbackporch;
265 }
266
267 static inline unsigned htotal(const struct v4l2_bt_timings *t)
268 {
269 return t->width + t->hfrontporch + t->hsync + t->hbackporch;
270 }
271
272 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
273 {
274 return t->vfrontporch + t->vsync + t->vbackporch;
275 }
276
277 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
278 {
279 return t->height + t->vfrontporch + t->vsync + t->vbackporch;
280 }
281
282 /* ----------------------------------------------------------------------- */
283
284 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
285 u8 command, bool check)
286 {
287 union i2c_smbus_data data;
288
289 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
290 I2C_SMBUS_READ, command,
291 I2C_SMBUS_BYTE_DATA, &data))
292 return data.byte;
293 if (check)
294 v4l_err(client, "error reading %02x, %02x\n",
295 client->addr, command);
296 return -EIO;
297 }
298
299 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
300 {
301 return adv_smbus_read_byte_data_check(client, command, true);
302 }
303
304 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
305 u8 command, u8 value)
306 {
307 union i2c_smbus_data data;
308 int err;
309 int i;
310
311 data.byte = value;
312 for (i = 0; i < 3; i++) {
313 err = i2c_smbus_xfer(client->adapter, client->addr,
314 client->flags,
315 I2C_SMBUS_WRITE, command,
316 I2C_SMBUS_BYTE_DATA, &data);
317 if (!err)
318 break;
319 }
320 if (err < 0)
321 v4l_err(client, "error writing %02x, %02x, %02x\n",
322 client->addr, command, value);
323 return err;
324 }
325
326 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
327 u8 command, unsigned length, const u8 *values)
328 {
329 union i2c_smbus_data data;
330
331 if (length > I2C_SMBUS_BLOCK_MAX)
332 length = I2C_SMBUS_BLOCK_MAX;
333 data.block[0] = length;
334 memcpy(data.block + 1, values, length);
335 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
336 I2C_SMBUS_WRITE, command,
337 I2C_SMBUS_I2C_BLOCK_DATA, &data);
338 }
339
340 /* ----------------------------------------------------------------------- */
341
342 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
343 {
344 struct i2c_client *client = v4l2_get_subdevdata(sd);
345
346 return adv_smbus_read_byte_data(client, reg);
347 }
348
349 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
350 {
351 struct i2c_client *client = v4l2_get_subdevdata(sd);
352
353 return adv_smbus_write_byte_data(client, reg, val);
354 }
355
356 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
357 {
358 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
359 }
360
361 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
362 {
363 struct adv7604_state *state = to_state(sd);
364
365 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
366 }
367
368 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
369 {
370 struct adv7604_state *state = to_state(sd);
371
372 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
373 }
374
375 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
376 {
377 struct adv7604_state *state = to_state(sd);
378
379 return adv_smbus_read_byte_data(state->i2c_cec, reg);
380 }
381
382 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
383 {
384 struct adv7604_state *state = to_state(sd);
385
386 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
387 }
388
389 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
390 {
391 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
392 }
393
394 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
395 {
396 struct adv7604_state *state = to_state(sd);
397
398 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
399 }
400
401 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
402 {
403 struct adv7604_state *state = to_state(sd);
404
405 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
406 }
407
408 static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
409 {
410 struct adv7604_state *state = to_state(sd);
411
412 return adv_smbus_read_byte_data(state->i2c_esdp, reg);
413 }
414
415 static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
416 {
417 struct adv7604_state *state = to_state(sd);
418
419 return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
420 }
421
422 static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
423 {
424 struct adv7604_state *state = to_state(sd);
425
426 return adv_smbus_read_byte_data(state->i2c_dpp, reg);
427 }
428
429 static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
430 {
431 struct adv7604_state *state = to_state(sd);
432
433 return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
434 }
435
436 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
437 {
438 struct adv7604_state *state = to_state(sd);
439
440 return adv_smbus_read_byte_data(state->i2c_afe, reg);
441 }
442
443 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
444 {
445 struct adv7604_state *state = to_state(sd);
446
447 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
448 }
449
450 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
451 {
452 struct adv7604_state *state = to_state(sd);
453
454 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
455 }
456
457 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
458 {
459 struct adv7604_state *state = to_state(sd);
460
461 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
462 }
463
464 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
465 {
466 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
467 }
468
469 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
470 {
471 struct adv7604_state *state = to_state(sd);
472
473 return adv_smbus_read_byte_data(state->i2c_edid, reg);
474 }
475
476 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
477 {
478 struct adv7604_state *state = to_state(sd);
479
480 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
481 }
482
483 static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
484 {
485 struct adv7604_state *state = to_state(sd);
486 struct i2c_client *client = state->i2c_edid;
487 u8 msgbuf0[1] = { 0 };
488 u8 msgbuf1[256];
489 struct i2c_msg msg[2] = {
490 {
491 .addr = client->addr,
492 .len = 1,
493 .buf = msgbuf0
494 },
495 {
496 .addr = client->addr,
497 .flags = I2C_M_RD,
498 .len = len,
499 .buf = msgbuf1
500 },
501 };
502
503 if (i2c_transfer(client->adapter, msg, 2) < 0)
504 return -EIO;
505 memcpy(val, msgbuf1, len);
506 return 0;
507 }
508
509 static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
510 {
511 struct delayed_work *dwork = to_delayed_work(work);
512 struct adv7604_state *state = container_of(dwork, struct adv7604_state,
513 delayed_work_enable_hotplug);
514 struct v4l2_subdev *sd = &state->sd;
515
516 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
517
518 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)1);
519 }
520
521 static inline int edid_write_block(struct v4l2_subdev *sd,
522 unsigned len, const u8 *val)
523 {
524 struct i2c_client *client = v4l2_get_subdevdata(sd);
525 struct adv7604_state *state = to_state(sd);
526 int err = 0;
527 int i;
528
529 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
530
531 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
532
533 /* Disables I2C access to internal EDID ram from DDC port */
534 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
535
536 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
537 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
538 I2C_SMBUS_BLOCK_MAX, val + i);
539 if (err)
540 return err;
541
542 /* adv7604 calculates the checksums and enables I2C access to internal
543 EDID ram from DDC port. */
544 rep_write_and_or(sd, 0x77, 0xf0, 0x1);
545
546 for (i = 0; i < 1000; i++) {
547 if (rep_read(sd, 0x7d) & 1)
548 break;
549 mdelay(1);
550 }
551 if (i == 1000) {
552 v4l_err(client, "error enabling edid\n");
553 return -EIO;
554 }
555
556 /* enable hotplug after 100 ms */
557 queue_delayed_work(state->work_queues,
558 &state->delayed_work_enable_hotplug, HZ / 10);
559 return 0;
560 }
561
562 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
563 {
564 struct adv7604_state *state = to_state(sd);
565
566 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
567 }
568
569 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
570 {
571 struct adv7604_state *state = to_state(sd);
572
573 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
574 }
575
576 static inline int test_read(struct v4l2_subdev *sd, u8 reg)
577 {
578 struct adv7604_state *state = to_state(sd);
579
580 return adv_smbus_read_byte_data(state->i2c_test, reg);
581 }
582
583 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
584 {
585 struct adv7604_state *state = to_state(sd);
586
587 return adv_smbus_write_byte_data(state->i2c_test, reg, val);
588 }
589
590 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
591 {
592 struct adv7604_state *state = to_state(sd);
593
594 return adv_smbus_read_byte_data(state->i2c_cp, reg);
595 }
596
597 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
598 {
599 struct adv7604_state *state = to_state(sd);
600
601 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
602 }
603
604 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
605 {
606 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
607 }
608
609 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
610 {
611 struct adv7604_state *state = to_state(sd);
612
613 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
614 }
615
616 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
617 {
618 struct adv7604_state *state = to_state(sd);
619
620 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
621 }
622
623 /* ----------------------------------------------------------------------- */
624
625 #ifdef CONFIG_VIDEO_ADV_DEBUG
626 static void adv7604_inv_register(struct v4l2_subdev *sd)
627 {
628 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
629 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
630 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
631 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
632 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
633 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
634 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
635 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
636 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
637 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
638 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
639 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
640 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
641 }
642
643 static int adv7604_g_register(struct v4l2_subdev *sd,
644 struct v4l2_dbg_register *reg)
645 {
646 struct i2c_client *client = v4l2_get_subdevdata(sd);
647
648 if (!v4l2_chip_match_i2c_client(client, &reg->match))
649 return -EINVAL;
650 reg->size = 1;
651 switch (reg->reg >> 8) {
652 case 0:
653 reg->val = io_read(sd, reg->reg & 0xff);
654 break;
655 case 1:
656 reg->val = avlink_read(sd, reg->reg & 0xff);
657 break;
658 case 2:
659 reg->val = cec_read(sd, reg->reg & 0xff);
660 break;
661 case 3:
662 reg->val = infoframe_read(sd, reg->reg & 0xff);
663 break;
664 case 4:
665 reg->val = esdp_read(sd, reg->reg & 0xff);
666 break;
667 case 5:
668 reg->val = dpp_read(sd, reg->reg & 0xff);
669 break;
670 case 6:
671 reg->val = afe_read(sd, reg->reg & 0xff);
672 break;
673 case 7:
674 reg->val = rep_read(sd, reg->reg & 0xff);
675 break;
676 case 8:
677 reg->val = edid_read(sd, reg->reg & 0xff);
678 break;
679 case 9:
680 reg->val = hdmi_read(sd, reg->reg & 0xff);
681 break;
682 case 0xa:
683 reg->val = test_read(sd, reg->reg & 0xff);
684 break;
685 case 0xb:
686 reg->val = cp_read(sd, reg->reg & 0xff);
687 break;
688 case 0xc:
689 reg->val = vdp_read(sd, reg->reg & 0xff);
690 break;
691 default:
692 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
693 adv7604_inv_register(sd);
694 break;
695 }
696 return 0;
697 }
698
699 static int adv7604_s_register(struct v4l2_subdev *sd,
700 const struct v4l2_dbg_register *reg)
701 {
702 struct i2c_client *client = v4l2_get_subdevdata(sd);
703
704 if (!v4l2_chip_match_i2c_client(client, &reg->match))
705 return -EINVAL;
706 switch (reg->reg >> 8) {
707 case 0:
708 io_write(sd, reg->reg & 0xff, reg->val & 0xff);
709 break;
710 case 1:
711 avlink_write(sd, reg->reg & 0xff, reg->val & 0xff);
712 break;
713 case 2:
714 cec_write(sd, reg->reg & 0xff, reg->val & 0xff);
715 break;
716 case 3:
717 infoframe_write(sd, reg->reg & 0xff, reg->val & 0xff);
718 break;
719 case 4:
720 esdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
721 break;
722 case 5:
723 dpp_write(sd, reg->reg & 0xff, reg->val & 0xff);
724 break;
725 case 6:
726 afe_write(sd, reg->reg & 0xff, reg->val & 0xff);
727 break;
728 case 7:
729 rep_write(sd, reg->reg & 0xff, reg->val & 0xff);
730 break;
731 case 8:
732 edid_write(sd, reg->reg & 0xff, reg->val & 0xff);
733 break;
734 case 9:
735 hdmi_write(sd, reg->reg & 0xff, reg->val & 0xff);
736 break;
737 case 0xa:
738 test_write(sd, reg->reg & 0xff, reg->val & 0xff);
739 break;
740 case 0xb:
741 cp_write(sd, reg->reg & 0xff, reg->val & 0xff);
742 break;
743 case 0xc:
744 vdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
745 break;
746 default:
747 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
748 adv7604_inv_register(sd);
749 break;
750 }
751 return 0;
752 }
753 #endif
754
755 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
756 {
757 struct adv7604_state *state = to_state(sd);
758
759 /* port A only */
760 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
761 ((io_read(sd, 0x6f) & 0x10) >> 4));
762 }
763
764 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
765 u8 prim_mode,
766 const struct adv7604_video_standards *predef_vid_timings,
767 const struct v4l2_dv_timings *timings)
768 {
769 struct adv7604_state *state = to_state(sd);
770 int i;
771
772 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
773 if (!v4l_match_dv_timings(timings, &predef_vid_timings[i].timings,
774 DIGITAL_INPUT ? 250000 : 1000000))
775 continue;
776 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
777 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
778 prim_mode); /* v_freq and prim mode */
779 return 0;
780 }
781
782 return -1;
783 }
784
785 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
786 struct v4l2_dv_timings *timings)
787 {
788 struct adv7604_state *state = to_state(sd);
789 int err;
790
791 v4l2_dbg(1, debug, sd, "%s", __func__);
792
793 /* reset to default values */
794 io_write(sd, 0x16, 0x43);
795 io_write(sd, 0x17, 0x5a);
796 /* disable embedded syncs for auto graphics mode */
797 cp_write_and_or(sd, 0x81, 0xef, 0x00);
798 cp_write(sd, 0x8f, 0x00);
799 cp_write(sd, 0x90, 0x00);
800 cp_write(sd, 0xa2, 0x00);
801 cp_write(sd, 0xa3, 0x00);
802 cp_write(sd, 0xa4, 0x00);
803 cp_write(sd, 0xa5, 0x00);
804 cp_write(sd, 0xa6, 0x00);
805 cp_write(sd, 0xa7, 0x00);
806 cp_write(sd, 0xab, 0x00);
807 cp_write(sd, 0xac, 0x00);
808
809 switch (state->mode) {
810 case ADV7604_MODE_COMP:
811 case ADV7604_MODE_GR:
812 err = find_and_set_predefined_video_timings(sd,
813 0x01, adv7604_prim_mode_comp, timings);
814 if (err)
815 err = find_and_set_predefined_video_timings(sd,
816 0x02, adv7604_prim_mode_gr, timings);
817 break;
818 case ADV7604_MODE_HDMI:
819 err = find_and_set_predefined_video_timings(sd,
820 0x05, adv7604_prim_mode_hdmi_comp, timings);
821 if (err)
822 err = find_and_set_predefined_video_timings(sd,
823 0x06, adv7604_prim_mode_hdmi_gr, timings);
824 break;
825 default:
826 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
827 __func__, state->mode);
828 err = -1;
829 break;
830 }
831
832
833 return err;
834 }
835
836 static void configure_custom_video_timings(struct v4l2_subdev *sd,
837 const struct v4l2_bt_timings *bt)
838 {
839 struct adv7604_state *state = to_state(sd);
840 struct i2c_client *client = v4l2_get_subdevdata(sd);
841 u32 width = htotal(bt);
842 u32 height = vtotal(bt);
843 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
844 u16 cp_start_eav = width - bt->hfrontporch;
845 u16 cp_start_vbi = height - bt->vfrontporch;
846 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
847 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
848 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
849 const u8 pll[2] = {
850 0xc0 | ((width >> 8) & 0x1f),
851 width & 0xff
852 };
853
854 v4l2_dbg(2, debug, sd, "%s\n", __func__);
855
856 switch (state->mode) {
857 case ADV7604_MODE_COMP:
858 case ADV7604_MODE_GR:
859 /* auto graphics */
860 io_write(sd, 0x00, 0x07); /* video std */
861 io_write(sd, 0x01, 0x02); /* prim mode */
862 /* enable embedded syncs for auto graphics mode */
863 cp_write_and_or(sd, 0x81, 0xef, 0x10);
864
865 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
866 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
867 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
868 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
869 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
870 break;
871 }
872
873 /* active video - horizontal timing */
874 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
875 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
876 ((cp_start_eav >> 8) & 0x0f));
877 cp_write(sd, 0xa4, cp_start_eav & 0xff);
878
879 /* active video - vertical timing */
880 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
881 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
882 ((cp_end_vbi >> 8) & 0xf));
883 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
884 break;
885 case ADV7604_MODE_HDMI:
886 /* set default prim_mode/vid_std for HDMI
887 accoring to [REF_03, c. 4.2] */
888 io_write(sd, 0x00, 0x02); /* video std */
889 io_write(sd, 0x01, 0x06); /* prim mode */
890 break;
891 default:
892 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
893 __func__, state->mode);
894 break;
895 }
896
897 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
898 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
899 cp_write(sd, 0xab, (height >> 4) & 0xff);
900 cp_write(sd, 0xac, (height & 0x0f) << 4);
901 }
902
903 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
904 {
905 struct adv7604_state *state = to_state(sd);
906
907 switch (state->rgb_quantization_range) {
908 case V4L2_DV_RGB_RANGE_AUTO:
909 /* automatic */
910 if (DIGITAL_INPUT && !(hdmi_read(sd, 0x05) & 0x80)) {
911 /* receiving DVI-D signal */
912
913 /* ADV7604 selects RGB limited range regardless of
914 input format (CE/IT) in automatic mode */
915 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
916 /* RGB limited range (16-235) */
917 io_write_and_or(sd, 0x02, 0x0f, 0x00);
918
919 } else {
920 /* RGB full range (0-255) */
921 io_write_and_or(sd, 0x02, 0x0f, 0x10);
922 }
923 } else {
924 /* receiving HDMI or analog signal, set automode */
925 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
926 }
927 break;
928 case V4L2_DV_RGB_RANGE_LIMITED:
929 /* RGB limited range (16-235) */
930 io_write_and_or(sd, 0x02, 0x0f, 0x00);
931 break;
932 case V4L2_DV_RGB_RANGE_FULL:
933 /* RGB full range (0-255) */
934 io_write_and_or(sd, 0x02, 0x0f, 0x10);
935 break;
936 }
937 }
938
939
940 static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
941 {
942 struct v4l2_subdev *sd = to_sd(ctrl);
943 struct adv7604_state *state = to_state(sd);
944
945 switch (ctrl->id) {
946 case V4L2_CID_BRIGHTNESS:
947 cp_write(sd, 0x3c, ctrl->val);
948 return 0;
949 case V4L2_CID_CONTRAST:
950 cp_write(sd, 0x3a, ctrl->val);
951 return 0;
952 case V4L2_CID_SATURATION:
953 cp_write(sd, 0x3b, ctrl->val);
954 return 0;
955 case V4L2_CID_HUE:
956 cp_write(sd, 0x3d, ctrl->val);
957 return 0;
958 case V4L2_CID_DV_RX_RGB_RANGE:
959 state->rgb_quantization_range = ctrl->val;
960 set_rgb_quantization_range(sd);
961 return 0;
962 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
963 /* Set the analog sampling phase. This is needed to find the
964 best sampling phase for analog video: an application or
965 driver has to try a number of phases and analyze the picture
966 quality before settling on the best performing phase. */
967 afe_write(sd, 0xc8, ctrl->val);
968 return 0;
969 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
970 /* Use the default blue color for free running mode,
971 or supply your own. */
972 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
973 return 0;
974 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
975 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
976 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
977 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
978 return 0;
979 }
980 return -EINVAL;
981 }
982
983 static int adv7604_g_chip_ident(struct v4l2_subdev *sd,
984 struct v4l2_dbg_chip_ident *chip)
985 {
986 struct i2c_client *client = v4l2_get_subdevdata(sd);
987
988 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_ADV7604, 0);
989 }
990
991 /* ----------------------------------------------------------------------- */
992
993 static inline bool no_power(struct v4l2_subdev *sd)
994 {
995 /* Entire chip or CP powered off */
996 return io_read(sd, 0x0c) & 0x24;
997 }
998
999 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1000 {
1001 /* TODO port B, C and D */
1002 return !(io_read(sd, 0x6a) & 0x10);
1003 }
1004
1005 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1006 {
1007 return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
1008 }
1009
1010 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1011 {
1012 /* TODO channel 2 */
1013 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1014 }
1015
1016 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1017 {
1018 /* TODO channel 2 */
1019 return !(cp_read(sd, 0xb1) & 0x80);
1020 }
1021
1022 static inline bool no_signal(struct v4l2_subdev *sd)
1023 {
1024 struct adv7604_state *state = to_state(sd);
1025 bool ret;
1026
1027 ret = no_power(sd);
1028
1029 ret |= no_lock_stdi(sd);
1030 ret |= no_lock_sspd(sd);
1031
1032 if (DIGITAL_INPUT) {
1033 ret |= no_lock_tmds(sd);
1034 ret |= no_signal_tmds(sd);
1035 }
1036
1037 return ret;
1038 }
1039
1040 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1041 {
1042 /* CP has detected a non standard number of lines on the incoming
1043 video compared to what it is configured to receive by s_dv_timings */
1044 return io_read(sd, 0x12) & 0x01;
1045 }
1046
1047 static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1048 {
1049 struct adv7604_state *state = to_state(sd);
1050
1051 *status = 0;
1052 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1053 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1054 if (no_lock_cp(sd))
1055 *status |= DIGITAL_INPUT ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1056
1057 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1058
1059 return 0;
1060 }
1061
1062 /* ----------------------------------------------------------------------- */
1063
1064 static void adv7604_print_timings(struct v4l2_subdev *sd,
1065 struct v4l2_dv_timings *timings, const char *txt, bool detailed)
1066 {
1067 struct v4l2_bt_timings *bt = &timings->bt;
1068 u32 htot, vtot;
1069
1070 if (timings->type != V4L2_DV_BT_656_1120)
1071 return;
1072
1073 htot = htotal(bt);
1074 vtot = vtotal(bt);
1075
1076 v4l2_info(sd, "%s %dx%d%s%d (%dx%d)",
1077 txt, bt->width, bt->height, bt->interlaced ? "i" : "p",
1078 (htot * vtot) > 0 ? ((u32)bt->pixelclock /
1079 (htot * vtot)) : 0,
1080 htot, vtot);
1081
1082 if (detailed) {
1083 v4l2_info(sd, " horizontal: fp = %d, %ssync = %d, bp = %d\n",
1084 bt->hfrontporch,
1085 (bt->polarities & V4L2_DV_HSYNC_POS_POL) ? "+" : "-",
1086 bt->hsync, bt->hbackporch);
1087 v4l2_info(sd, " vertical: fp = %d, %ssync = %d, bp = %d\n",
1088 bt->vfrontporch,
1089 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-",
1090 bt->vsync, bt->vbackporch);
1091 v4l2_info(sd, " pixelclock: %lld, flags: 0x%x, standards: 0x%x\n",
1092 bt->pixelclock, bt->flags, bt->standards);
1093 }
1094 }
1095
1096 struct stdi_readback {
1097 u16 bl, lcf, lcvs;
1098 u8 hs_pol, vs_pol;
1099 bool interlaced;
1100 };
1101
1102 static int stdi2dv_timings(struct v4l2_subdev *sd,
1103 struct stdi_readback *stdi,
1104 struct v4l2_dv_timings *timings)
1105 {
1106 struct adv7604_state *state = to_state(sd);
1107 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1108 u32 pix_clk;
1109 int i;
1110
1111 for (i = 0; adv7604_timings[i].bt.height; i++) {
1112 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1113 continue;
1114 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1115 continue;
1116
1117 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1118
1119 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1120 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1121 *timings = adv7604_timings[i];
1122 return 0;
1123 }
1124 }
1125
1126 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1127 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1128 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1129 timings))
1130 return 0;
1131 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1132 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1133 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1134 state->aspect_ratio, timings))
1135 return 0;
1136
1137 v4l2_dbg(2, debug, sd,
1138 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1139 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1140 stdi->hs_pol, stdi->vs_pol);
1141 return -1;
1142 }
1143
1144 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1145 {
1146 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1147 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1148 return -1;
1149 }
1150
1151 /* read STDI */
1152 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1153 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1154 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1155 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1156
1157 /* read SSPD */
1158 if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1159 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1160 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1161 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1162 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1163 } else {
1164 stdi->hs_pol = 'x';
1165 stdi->vs_pol = 'x';
1166 }
1167
1168 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1169 v4l2_dbg(2, debug, sd,
1170 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1171 return -1;
1172 }
1173
1174 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1175 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1176 memset(stdi, 0, sizeof(struct stdi_readback));
1177 return -1;
1178 }
1179
1180 v4l2_dbg(2, debug, sd,
1181 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1182 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1183 stdi->hs_pol, stdi->vs_pol,
1184 stdi->interlaced ? "interlaced" : "progressive");
1185
1186 return 0;
1187 }
1188
1189 static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1190 struct v4l2_enum_dv_timings *timings)
1191 {
1192 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1193 return -EINVAL;
1194 memset(timings->reserved, 0, sizeof(timings->reserved));
1195 timings->timings = adv7604_timings[timings->index];
1196 return 0;
1197 }
1198
1199 static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1200 struct v4l2_dv_timings_cap *cap)
1201 {
1202 struct adv7604_state *state = to_state(sd);
1203
1204 cap->type = V4L2_DV_BT_656_1120;
1205 cap->bt.max_width = 1920;
1206 cap->bt.max_height = 1200;
1207 cap->bt.min_pixelclock = 27000000;
1208 if (DIGITAL_INPUT)
1209 cap->bt.max_pixelclock = 225000000;
1210 else
1211 cap->bt.max_pixelclock = 170000000;
1212 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1213 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1214 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1215 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1216 return 0;
1217 }
1218
1219 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1220 if the format is listed in adv7604_timings[] */
1221 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1222 struct v4l2_dv_timings *timings)
1223 {
1224 struct adv7604_state *state = to_state(sd);
1225 int i;
1226
1227 for (i = 0; adv7604_timings[i].bt.width; i++) {
1228 if (v4l_match_dv_timings(timings, &adv7604_timings[i],
1229 DIGITAL_INPUT ? 250000 : 1000000)) {
1230 *timings = adv7604_timings[i];
1231 break;
1232 }
1233 }
1234 }
1235
1236 static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1237 struct v4l2_dv_timings *timings)
1238 {
1239 struct adv7604_state *state = to_state(sd);
1240 struct v4l2_bt_timings *bt = &timings->bt;
1241 struct stdi_readback stdi;
1242
1243 if (!timings)
1244 return -EINVAL;
1245
1246 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1247
1248 if (no_signal(sd)) {
1249 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1250 return -ENOLINK;
1251 }
1252
1253 /* read STDI */
1254 if (read_stdi(sd, &stdi)) {
1255 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1256 return -ENOLINK;
1257 }
1258 bt->interlaced = stdi.interlaced ?
1259 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1260
1261 if (DIGITAL_INPUT) {
1262 timings->type = V4L2_DV_BT_656_1120;
1263
1264 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1265 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1266 bt->pixelclock = (hdmi_read(sd, 0x06) * 1000000) +
1267 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1268 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1269 hdmi_read(sd, 0x21);
1270 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1271 hdmi_read(sd, 0x23);
1272 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1273 hdmi_read(sd, 0x25);
1274 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1275 hdmi_read(sd, 0x2b)) / 2;
1276 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1277 hdmi_read(sd, 0x2f)) / 2;
1278 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1279 hdmi_read(sd, 0x33)) / 2;
1280 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1281 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1282 if (bt->interlaced == V4L2_DV_INTERLACED) {
1283 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1284 hdmi_read(sd, 0x0c);
1285 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1286 hdmi_read(sd, 0x2d)) / 2;
1287 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1288 hdmi_read(sd, 0x31)) / 2;
1289 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1290 hdmi_read(sd, 0x35)) / 2;
1291 }
1292 adv7604_fill_optional_dv_timings_fields(sd, timings);
1293 } else {
1294 /* find format
1295 * Since LCVS values are inaccurate [REF_03, p. 275-276],
1296 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1297 */
1298 if (!stdi2dv_timings(sd, &stdi, timings))
1299 goto found;
1300 stdi.lcvs += 1;
1301 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1302 if (!stdi2dv_timings(sd, &stdi, timings))
1303 goto found;
1304 stdi.lcvs -= 2;
1305 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1306 if (stdi2dv_timings(sd, &stdi, timings)) {
1307 /*
1308 * The STDI block may measure wrong values, especially
1309 * for lcvs and lcf. If the driver can not find any
1310 * valid timing, the STDI block is restarted to measure
1311 * the video timings again. The function will return an
1312 * error, but the restart of STDI will generate a new
1313 * STDI interrupt and the format detection process will
1314 * restart.
1315 */
1316 if (state->restart_stdi_once) {
1317 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1318 /* TODO restart STDI for Sync Channel 2 */
1319 /* enter one-shot mode */
1320 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1321 /* trigger STDI restart */
1322 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1323 /* reset to continuous mode */
1324 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1325 state->restart_stdi_once = false;
1326 return -ENOLINK;
1327 }
1328 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1329 return -ERANGE;
1330 }
1331 state->restart_stdi_once = true;
1332 }
1333 found:
1334
1335 if (no_signal(sd)) {
1336 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1337 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1338 return -ENOLINK;
1339 }
1340
1341 if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1342 (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1343 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1344 __func__, (u32)bt->pixelclock);
1345 return -ERANGE;
1346 }
1347
1348 if (debug > 1)
1349 adv7604_print_timings(sd, timings,
1350 "adv7604_query_dv_timings:", true);
1351
1352 return 0;
1353 }
1354
1355 static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1356 struct v4l2_dv_timings *timings)
1357 {
1358 struct adv7604_state *state = to_state(sd);
1359 struct v4l2_bt_timings *bt;
1360 int err;
1361
1362 if (!timings)
1363 return -EINVAL;
1364
1365 bt = &timings->bt;
1366
1367 if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1368 (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1369 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1370 __func__, (u32)bt->pixelclock);
1371 return -ERANGE;
1372 }
1373
1374 adv7604_fill_optional_dv_timings_fields(sd, timings);
1375
1376 state->timings = *timings;
1377
1378 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1379
1380 /* Use prim_mode and vid_std when available */
1381 err = configure_predefined_video_timings(sd, timings);
1382 if (err) {
1383 /* custom settings when the video format
1384 does not have prim_mode/vid_std */
1385 configure_custom_video_timings(sd, bt);
1386 }
1387
1388 set_rgb_quantization_range(sd);
1389
1390
1391 if (debug > 1)
1392 adv7604_print_timings(sd, timings,
1393 "adv7604_s_dv_timings:", true);
1394 return 0;
1395 }
1396
1397 static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1398 struct v4l2_dv_timings *timings)
1399 {
1400 struct adv7604_state *state = to_state(sd);
1401
1402 *timings = state->timings;
1403 return 0;
1404 }
1405
1406 static void enable_input(struct v4l2_subdev *sd)
1407 {
1408 struct adv7604_state *state = to_state(sd);
1409
1410 switch (state->mode) {
1411 case ADV7604_MODE_COMP:
1412 case ADV7604_MODE_GR:
1413 /* enable */
1414 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1415 break;
1416 case ADV7604_MODE_HDMI:
1417 /* enable */
1418 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1419 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1420 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1421 break;
1422 default:
1423 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1424 __func__, state->mode);
1425 break;
1426 }
1427 }
1428
1429 static void disable_input(struct v4l2_subdev *sd)
1430 {
1431 /* disable */
1432 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1433 hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1434 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1435 }
1436
1437 static void select_input(struct v4l2_subdev *sd)
1438 {
1439 struct adv7604_state *state = to_state(sd);
1440
1441 switch (state->mode) {
1442 case ADV7604_MODE_COMP:
1443 case ADV7604_MODE_GR:
1444 /* reset ADI recommended settings for HDMI: */
1445 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1446 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1447 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1448 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1449 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1450 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1451 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1452 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1453 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1454 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1455 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1456 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1457
1458 afe_write(sd, 0x00, 0x08); /* power up ADC */
1459 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1460 afe_write(sd, 0xc8, 0x00); /* phase control */
1461
1462 /* set ADI recommended settings for digitizer */
1463 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1464 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1465 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1466 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1467 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1468 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1469 break;
1470
1471 case ADV7604_MODE_HDMI:
1472 /* set ADI recommended settings for HDMI: */
1473 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1474 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1475 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1476 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1477 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1478 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1479 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1480 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1481 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1482 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1483 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1484 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1485
1486 afe_write(sd, 0x00, 0xff); /* power down ADC */
1487 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1488 afe_write(sd, 0xc8, 0x40); /* phase control */
1489
1490 /* reset ADI recommended settings for digitizer */
1491 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1492 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1493 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1494 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1495 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1496 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1497
1498 break;
1499 default:
1500 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1501 __func__, state->mode);
1502 break;
1503 }
1504 }
1505
1506 static int adv7604_s_routing(struct v4l2_subdev *sd,
1507 u32 input, u32 output, u32 config)
1508 {
1509 struct adv7604_state *state = to_state(sd);
1510
1511 v4l2_dbg(2, debug, sd, "%s: input %d", __func__, input);
1512
1513 state->mode = input;
1514
1515 disable_input(sd);
1516
1517 select_input(sd);
1518
1519 enable_input(sd);
1520
1521 return 0;
1522 }
1523
1524 static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1525 enum v4l2_mbus_pixelcode *code)
1526 {
1527 if (index)
1528 return -EINVAL;
1529 /* Good enough for now */
1530 *code = V4L2_MBUS_FMT_FIXED;
1531 return 0;
1532 }
1533
1534 static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1535 struct v4l2_mbus_framefmt *fmt)
1536 {
1537 struct adv7604_state *state = to_state(sd);
1538
1539 fmt->width = state->timings.bt.width;
1540 fmt->height = state->timings.bt.height;
1541 fmt->code = V4L2_MBUS_FMT_FIXED;
1542 fmt->field = V4L2_FIELD_NONE;
1543 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1544 fmt->colorspace = (state->timings.bt.height <= 576) ?
1545 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1546 }
1547 return 0;
1548 }
1549
1550 static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1551 {
1552 struct adv7604_state *state = to_state(sd);
1553 u8 fmt_change, fmt_change_digital, tx_5v;
1554
1555 /* format change */
1556 fmt_change = io_read(sd, 0x43) & 0x98;
1557 if (fmt_change)
1558 io_write(sd, 0x44, fmt_change);
1559 fmt_change_digital = DIGITAL_INPUT ? (io_read(sd, 0x6b) & 0xc0) : 0;
1560 if (fmt_change_digital)
1561 io_write(sd, 0x6c, fmt_change_digital);
1562 if (fmt_change || fmt_change_digital) {
1563 v4l2_dbg(1, debug, sd,
1564 "%s: ADV7604_FMT_CHANGE, fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1565 __func__, fmt_change, fmt_change_digital);
1566 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1567 if (handled)
1568 *handled = true;
1569 }
1570 /* tx 5v detect */
1571 tx_5v = io_read(sd, 0x70) & 0x10;
1572 if (tx_5v) {
1573 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1574 io_write(sd, 0x71, tx_5v);
1575 adv7604_s_detect_tx_5v_ctrl(sd);
1576 if (handled)
1577 *handled = true;
1578 }
1579 return 0;
1580 }
1581
1582 static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1583 {
1584 struct adv7604_state *state = to_state(sd);
1585
1586 if (edid->pad != 0)
1587 return -EINVAL;
1588 if (edid->blocks == 0)
1589 return -EINVAL;
1590 if (edid->start_block >= state->edid_blocks)
1591 return -EINVAL;
1592 if (edid->start_block + edid->blocks > state->edid_blocks)
1593 edid->blocks = state->edid_blocks - edid->start_block;
1594 if (!edid->edid)
1595 return -EINVAL;
1596 memcpy(edid->edid + edid->start_block * 128,
1597 state->edid + edid->start_block * 128,
1598 edid->blocks * 128);
1599 return 0;
1600 }
1601
1602 static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1603 {
1604 struct adv7604_state *state = to_state(sd);
1605 int err;
1606
1607 if (edid->pad != 0)
1608 return -EINVAL;
1609 if (edid->start_block != 0)
1610 return -EINVAL;
1611 if (edid->blocks == 0) {
1612 /* Pull down the hotplug pin */
1613 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
1614 /* Disables I2C access to internal EDID ram from DDC port */
1615 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
1616 state->edid_blocks = 0;
1617 /* Fall back to a 16:9 aspect ratio */
1618 state->aspect_ratio.numerator = 16;
1619 state->aspect_ratio.denominator = 9;
1620 return 0;
1621 }
1622 if (edid->blocks > 2)
1623 return -E2BIG;
1624 if (!edid->edid)
1625 return -EINVAL;
1626 memcpy(state->edid, edid->edid, 128 * edid->blocks);
1627 state->edid_blocks = edid->blocks;
1628 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1629 edid->edid[0x16]);
1630 err = edid_write_block(sd, 128 * edid->blocks, state->edid);
1631 if (err < 0)
1632 v4l2_err(sd, "error %d writing edid\n", err);
1633 return err;
1634 }
1635
1636 /*********** avi info frame CEA-861-E **************/
1637
1638 static void print_avi_infoframe(struct v4l2_subdev *sd)
1639 {
1640 int i;
1641 u8 buf[14];
1642 u8 avi_len;
1643 u8 avi_ver;
1644
1645 if (!(hdmi_read(sd, 0x05) & 0x80)) {
1646 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1647 return;
1648 }
1649 if (!(io_read(sd, 0x60) & 0x01)) {
1650 v4l2_info(sd, "AVI infoframe not received\n");
1651 return;
1652 }
1653
1654 if (io_read(sd, 0x83) & 0x01) {
1655 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1656 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1657 if (io_read(sd, 0x83) & 0x01) {
1658 v4l2_info(sd, "AVI infoframe checksum error still present\n");
1659 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1660 }
1661 }
1662
1663 avi_len = infoframe_read(sd, 0xe2);
1664 avi_ver = infoframe_read(sd, 0xe1);
1665 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1666 avi_ver, avi_len);
1667
1668 if (avi_ver != 0x02)
1669 return;
1670
1671 for (i = 0; i < 14; i++)
1672 buf[i] = infoframe_read(sd, i);
1673
1674 v4l2_info(sd,
1675 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1676 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1677 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1678 }
1679
1680 static int adv7604_log_status(struct v4l2_subdev *sd)
1681 {
1682 struct adv7604_state *state = to_state(sd);
1683 struct v4l2_dv_timings timings;
1684 struct stdi_readback stdi;
1685 u8 reg_io_0x02 = io_read(sd, 0x02);
1686
1687 char *csc_coeff_sel_rb[16] = {
1688 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1689 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1690 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1691 "reserved", "reserved", "reserved", "reserved", "manual"
1692 };
1693 char *input_color_space_txt[16] = {
1694 "RGB limited range (16-235)", "RGB full range (0-255)",
1695 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1696 "XvYCC Bt.601", "XvYCC Bt.709",
1697 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1698 "invalid", "invalid", "invalid", "invalid", "invalid",
1699 "invalid", "invalid", "automatic"
1700 };
1701 char *rgb_quantization_range_txt[] = {
1702 "Automatic",
1703 "RGB limited range (16-235)",
1704 "RGB full range (0-255)",
1705 };
1706
1707 v4l2_info(sd, "-----Chip status-----\n");
1708 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
1709 v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ?
1710 "HDMI" : (DIGITAL_INPUT ? "DVI-D" : "DVI-A"));
1711 v4l2_info(sd, "EDID: %s\n", ((rep_read(sd, 0x7d) & 0x01) &&
1712 (rep_read(sd, 0x77) & 0x01)) ? "enabled" : "disabled ");
1713 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1714 "enabled" : "disabled");
1715
1716 v4l2_info(sd, "-----Signal status-----\n");
1717 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1718 (io_read(sd, 0x6f) & 0x10) ? "true" : "false");
1719 v4l2_info(sd, "TMDS signal detected: %s\n",
1720 no_signal_tmds(sd) ? "false" : "true");
1721 v4l2_info(sd, "TMDS signal locked: %s\n",
1722 no_lock_tmds(sd) ? "false" : "true");
1723 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1724 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1725 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1726 v4l2_info(sd, "CP free run: %s\n",
1727 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
1728 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1729 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1730 (io_read(sd, 0x01) & 0x70) >> 4);
1731
1732 v4l2_info(sd, "-----Video Timings-----\n");
1733 if (read_stdi(sd, &stdi))
1734 v4l2_info(sd, "STDI: not locked\n");
1735 else
1736 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1737 stdi.lcf, stdi.bl, stdi.lcvs,
1738 stdi.interlaced ? "interlaced" : "progressive",
1739 stdi.hs_pol, stdi.vs_pol);
1740 if (adv7604_query_dv_timings(sd, &timings))
1741 v4l2_info(sd, "No video detected\n");
1742 else
1743 adv7604_print_timings(sd, &timings, "Detected format:", true);
1744 adv7604_print_timings(sd, &state->timings, "Configured format:", true);
1745
1746 v4l2_info(sd, "-----Color space-----\n");
1747 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1748 rgb_quantization_range_txt[state->rgb_quantization_range]);
1749 v4l2_info(sd, "Input color space: %s\n",
1750 input_color_space_txt[reg_io_0x02 >> 4]);
1751 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1752 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1753 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1754 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
1755 "enabled" : "disabled");
1756 v4l2_info(sd, "Color space conversion: %s\n",
1757 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1758
1759 /* Digital video */
1760 if (DIGITAL_INPUT) {
1761 v4l2_info(sd, "-----HDMI status-----\n");
1762 v4l2_info(sd, "HDCP encrypted content: %s\n",
1763 hdmi_read(sd, 0x05) & 0x40 ? "true" : "false");
1764
1765 print_avi_infoframe(sd);
1766 }
1767
1768 return 0;
1769 }
1770
1771 /* ----------------------------------------------------------------------- */
1772
1773 static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1774 .s_ctrl = adv7604_s_ctrl,
1775 };
1776
1777 static const struct v4l2_subdev_core_ops adv7604_core_ops = {
1778 .log_status = adv7604_log_status,
1779 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1780 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1781 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1782 .g_ctrl = v4l2_subdev_g_ctrl,
1783 .s_ctrl = v4l2_subdev_s_ctrl,
1784 .queryctrl = v4l2_subdev_queryctrl,
1785 .querymenu = v4l2_subdev_querymenu,
1786 .g_chip_ident = adv7604_g_chip_ident,
1787 .interrupt_service_routine = adv7604_isr,
1788 #ifdef CONFIG_VIDEO_ADV_DEBUG
1789 .g_register = adv7604_g_register,
1790 .s_register = adv7604_s_register,
1791 #endif
1792 };
1793
1794 static const struct v4l2_subdev_video_ops adv7604_video_ops = {
1795 .s_routing = adv7604_s_routing,
1796 .g_input_status = adv7604_g_input_status,
1797 .s_dv_timings = adv7604_s_dv_timings,
1798 .g_dv_timings = adv7604_g_dv_timings,
1799 .query_dv_timings = adv7604_query_dv_timings,
1800 .enum_dv_timings = adv7604_enum_dv_timings,
1801 .dv_timings_cap = adv7604_dv_timings_cap,
1802 .enum_mbus_fmt = adv7604_enum_mbus_fmt,
1803 .g_mbus_fmt = adv7604_g_mbus_fmt,
1804 .try_mbus_fmt = adv7604_g_mbus_fmt,
1805 .s_mbus_fmt = adv7604_g_mbus_fmt,
1806 };
1807
1808 static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
1809 .get_edid = adv7604_get_edid,
1810 .set_edid = adv7604_set_edid,
1811 };
1812
1813 static const struct v4l2_subdev_ops adv7604_ops = {
1814 .core = &adv7604_core_ops,
1815 .video = &adv7604_video_ops,
1816 .pad = &adv7604_pad_ops,
1817 };
1818
1819 /* -------------------------- custom ctrls ---------------------------------- */
1820
1821 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
1822 .ops = &adv7604_ctrl_ops,
1823 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
1824 .name = "Analog Sampling Phase",
1825 .type = V4L2_CTRL_TYPE_INTEGER,
1826 .min = 0,
1827 .max = 0x1f,
1828 .step = 1,
1829 .def = 0,
1830 };
1831
1832 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
1833 .ops = &adv7604_ctrl_ops,
1834 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
1835 .name = "Free Running Color, Manual",
1836 .type = V4L2_CTRL_TYPE_BOOLEAN,
1837 .min = false,
1838 .max = true,
1839 .step = 1,
1840 .def = false,
1841 };
1842
1843 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
1844 .ops = &adv7604_ctrl_ops,
1845 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
1846 .name = "Free Running Color",
1847 .type = V4L2_CTRL_TYPE_INTEGER,
1848 .min = 0x0,
1849 .max = 0xffffff,
1850 .step = 0x1,
1851 .def = 0x0,
1852 };
1853
1854 /* ----------------------------------------------------------------------- */
1855
1856 static int adv7604_core_init(struct v4l2_subdev *sd)
1857 {
1858 struct adv7604_state *state = to_state(sd);
1859 struct adv7604_platform_data *pdata = &state->pdata;
1860
1861 hdmi_write(sd, 0x48,
1862 (pdata->disable_pwrdnb ? 0x80 : 0) |
1863 (pdata->disable_cable_det_rst ? 0x40 : 0));
1864
1865 disable_input(sd);
1866
1867 /* power */
1868 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
1869 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
1870 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
1871
1872 /* video format */
1873 io_write_and_or(sd, 0x02, 0xf0,
1874 pdata->alt_gamma << 3 |
1875 pdata->op_656_range << 2 |
1876 pdata->rgb_out << 1 |
1877 pdata->alt_data_sat << 0);
1878 io_write(sd, 0x03, pdata->op_format_sel);
1879 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
1880 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
1881 pdata->insert_av_codes << 2 |
1882 pdata->replicate_av_codes << 1 |
1883 pdata->invert_cbcr << 0);
1884
1885 /* TODO from platform data */
1886 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
1887 io_write(sd, 0x06, 0xa6); /* positive VS and HS */
1888 io_write(sd, 0x14, 0x7f); /* Drive strength adjusted to max */
1889 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
1890 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
1891 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
1892 ADI recommended setting [REF_01, c. 2.3.3] */
1893 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
1894 ADI recommended setting [REF_01, c. 2.3.3] */
1895 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
1896 for digital formats */
1897
1898 /* TODO from platform data */
1899 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
1900
1901 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
1902 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
1903
1904 /* interrupts */
1905 io_write(sd, 0x40, 0xc2); /* Configure INT1 */
1906 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
1907 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
1908 io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1909 io_write(sd, 0x73, 0x10); /* Enable CABLE_DET_A_ST (+5v) interrupt */
1910
1911 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
1912 }
1913
1914 static void adv7604_unregister_clients(struct adv7604_state *state)
1915 {
1916 if (state->i2c_avlink)
1917 i2c_unregister_device(state->i2c_avlink);
1918 if (state->i2c_cec)
1919 i2c_unregister_device(state->i2c_cec);
1920 if (state->i2c_infoframe)
1921 i2c_unregister_device(state->i2c_infoframe);
1922 if (state->i2c_esdp)
1923 i2c_unregister_device(state->i2c_esdp);
1924 if (state->i2c_dpp)
1925 i2c_unregister_device(state->i2c_dpp);
1926 if (state->i2c_afe)
1927 i2c_unregister_device(state->i2c_afe);
1928 if (state->i2c_repeater)
1929 i2c_unregister_device(state->i2c_repeater);
1930 if (state->i2c_edid)
1931 i2c_unregister_device(state->i2c_edid);
1932 if (state->i2c_hdmi)
1933 i2c_unregister_device(state->i2c_hdmi);
1934 if (state->i2c_test)
1935 i2c_unregister_device(state->i2c_test);
1936 if (state->i2c_cp)
1937 i2c_unregister_device(state->i2c_cp);
1938 if (state->i2c_vdp)
1939 i2c_unregister_device(state->i2c_vdp);
1940 }
1941
1942 static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
1943 u8 addr, u8 io_reg)
1944 {
1945 struct i2c_client *client = v4l2_get_subdevdata(sd);
1946
1947 if (addr)
1948 io_write(sd, io_reg, addr << 1);
1949 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
1950 }
1951
1952 static int adv7604_probe(struct i2c_client *client,
1953 const struct i2c_device_id *id)
1954 {
1955 struct adv7604_state *state;
1956 struct adv7604_platform_data *pdata = client->dev.platform_data;
1957 struct v4l2_ctrl_handler *hdl;
1958 struct v4l2_subdev *sd;
1959 int err;
1960
1961 /* Check if the adapter supports the needed features */
1962 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1963 return -EIO;
1964 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
1965 client->addr << 1);
1966
1967 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1968 if (!state) {
1969 v4l_err(client, "Could not allocate adv7604_state memory!\n");
1970 return -ENOMEM;
1971 }
1972
1973 /* platform data */
1974 if (!pdata) {
1975 v4l_err(client, "No platform data!\n");
1976 return -ENODEV;
1977 }
1978 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1979
1980 sd = &state->sd;
1981 v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
1982 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1983 state->connector_hdmi = pdata->connector_hdmi;
1984
1985 /* i2c access to adv7604? */
1986 if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
1987 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
1988 client->addr << 1);
1989 return -ENODEV;
1990 }
1991
1992 /* control handlers */
1993 hdl = &state->hdl;
1994 v4l2_ctrl_handler_init(hdl, 9);
1995
1996 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1997 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
1998 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1999 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2000 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2001 V4L2_CID_SATURATION, 0, 255, 1, 128);
2002 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2003 V4L2_CID_HUE, 0, 128, 1, 0);
2004
2005 /* private controls */
2006 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2007 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
2008 state->detect_tx_5v_ctrl->is_private = true;
2009 state->rgb_quantization_range_ctrl =
2010 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2011 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2012 0, V4L2_DV_RGB_RANGE_AUTO);
2013 state->rgb_quantization_range_ctrl->is_private = true;
2014
2015 /* custom controls */
2016 state->analog_sampling_phase_ctrl =
2017 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2018 state->analog_sampling_phase_ctrl->is_private = true;
2019 state->free_run_color_manual_ctrl =
2020 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
2021 state->free_run_color_manual_ctrl->is_private = true;
2022 state->free_run_color_ctrl =
2023 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
2024 state->free_run_color_ctrl->is_private = true;
2025
2026 sd->ctrl_handler = hdl;
2027 if (hdl->error) {
2028 err = hdl->error;
2029 goto err_hdl;
2030 }
2031 if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2032 err = -ENODEV;
2033 goto err_hdl;
2034 }
2035
2036 state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2037 state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2038 state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2039 state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2040 state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2041 state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2042 state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2043 state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2044 state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2045 state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2046 state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2047 state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2048 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2049 !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2050 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2051 !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2052 err = -ENOMEM;
2053 v4l2_err(sd, "failed to create all i2c clients\n");
2054 goto err_i2c;
2055 }
2056 state->restart_stdi_once = true;
2057
2058 /* work queues */
2059 state->work_queues = create_singlethread_workqueue(client->name);
2060 if (!state->work_queues) {
2061 v4l2_err(sd, "Could not create work queue\n");
2062 err = -ENOMEM;
2063 goto err_i2c;
2064 }
2065
2066 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2067 adv7604_delayed_work_enable_hotplug);
2068
2069 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2070 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2071 if (err)
2072 goto err_work_queues;
2073
2074 err = adv7604_core_init(sd);
2075 if (err)
2076 goto err_entity;
2077 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2078 client->addr << 1, client->adapter->name);
2079 return 0;
2080
2081 err_entity:
2082 media_entity_cleanup(&sd->entity);
2083 err_work_queues:
2084 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2085 destroy_workqueue(state->work_queues);
2086 err_i2c:
2087 adv7604_unregister_clients(state);
2088 err_hdl:
2089 v4l2_ctrl_handler_free(hdl);
2090 return err;
2091 }
2092
2093 /* ----------------------------------------------------------------------- */
2094
2095 static int adv7604_remove(struct i2c_client *client)
2096 {
2097 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2098 struct adv7604_state *state = to_state(sd);
2099
2100 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2101 destroy_workqueue(state->work_queues);
2102 v4l2_device_unregister_subdev(sd);
2103 media_entity_cleanup(&sd->entity);
2104 adv7604_unregister_clients(to_state(sd));
2105 v4l2_ctrl_handler_free(sd->ctrl_handler);
2106 return 0;
2107 }
2108
2109 /* ----------------------------------------------------------------------- */
2110
2111 static struct i2c_device_id adv7604_id[] = {
2112 { "adv7604", 0 },
2113 { }
2114 };
2115 MODULE_DEVICE_TABLE(i2c, adv7604_id);
2116
2117 static struct i2c_driver adv7604_driver = {
2118 .driver = {
2119 .owner = THIS_MODULE,
2120 .name = "adv7604",
2121 },
2122 .probe = adv7604_probe,
2123 .remove = adv7604_remove,
2124 .id_table = adv7604_id,
2125 };
2126
2127 module_i2c_driver(adv7604_driver);
Linux kernel - Deliverables
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