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[deliverable/linux.git] / drivers / media / i2c / adv7842.c
1 /*
2 * adv7842 - Analog Devices ADV7842 video decoder driver
3 *
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21 /*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7842,
24 * Register Settings Recommendations, Rev. 1.9, April 2011
25 * REF_02 - Analog devices, Software User Guide, UG-206,
26 * ADV7842 I2C Register Maps, Rev. 0, November 2010
27 * REF_03 - Analog devices, Hardware User Guide, UG-214,
28 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
29 * Decoder and Digitizer , Rev. 0, January 2011
30 */
31
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/i2c.h>
37 #include <linux/delay.h>
38 #include <linux/videodev2.h>
39 #include <linux/workqueue.h>
40 #include <linux/v4l2-dv-timings.h>
41 #include <linux/hdmi.h>
42 #include <media/v4l2-device.h>
43 #include <media/v4l2-ctrls.h>
44 #include <media/v4l2-dv-timings.h>
45 #include <media/adv7842.h>
46
47 static int debug;
48 module_param(debug, int, 0644);
49 MODULE_PARM_DESC(debug, "debug level (0-2)");
50
51 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
52 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
53 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
54 MODULE_LICENSE("GPL");
55
56 /* ADV7842 system clock frequency */
57 #define ADV7842_fsc (28636360)
58
59 /*
60 **********************************************************************
61 *
62 * Arrays with configuration parameters for the ADV7842
63 *
64 **********************************************************************
65 */
66
67 struct adv7842_state {
68 struct adv7842_platform_data pdata;
69 struct v4l2_subdev sd;
70 struct media_pad pad;
71 struct v4l2_ctrl_handler hdl;
72 enum adv7842_mode mode;
73 struct v4l2_dv_timings timings;
74 enum adv7842_vid_std_select vid_std_select;
75 v4l2_std_id norm;
76 struct {
77 u8 edid[256];
78 u32 present;
79 } hdmi_edid;
80 struct {
81 u8 edid[256];
82 u32 present;
83 } vga_edid;
84 struct v4l2_fract aspect_ratio;
85 u32 rgb_quantization_range;
86 bool is_cea_format;
87 struct workqueue_struct *work_queues;
88 struct delayed_work delayed_work_enable_hotplug;
89 bool restart_stdi_once;
90 bool hdmi_port_a;
91
92 /* i2c clients */
93 struct i2c_client *i2c_sdp_io;
94 struct i2c_client *i2c_sdp;
95 struct i2c_client *i2c_cp;
96 struct i2c_client *i2c_vdp;
97 struct i2c_client *i2c_afe;
98 struct i2c_client *i2c_hdmi;
99 struct i2c_client *i2c_repeater;
100 struct i2c_client *i2c_edid;
101 struct i2c_client *i2c_infoframe;
102 struct i2c_client *i2c_cec;
103 struct i2c_client *i2c_avlink;
104
105 /* controls */
106 struct v4l2_ctrl *detect_tx_5v_ctrl;
107 struct v4l2_ctrl *analog_sampling_phase_ctrl;
108 struct v4l2_ctrl *free_run_color_ctrl_manual;
109 struct v4l2_ctrl *free_run_color_ctrl;
110 struct v4l2_ctrl *rgb_quantization_range_ctrl;
111 };
112
113 /* Unsupported timings. This device cannot support 720p30. */
114 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
115 V4L2_DV_BT_CEA_1280X720P30,
116 { }
117 };
118
119 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
120 {
121 int i;
122
123 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
124 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0))
125 return false;
126 return true;
127 }
128
129 struct adv7842_video_standards {
130 struct v4l2_dv_timings timings;
131 u8 vid_std;
132 u8 v_freq;
133 };
134
135 /* sorted by number of lines */
136 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
137 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
138 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
139 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
140 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
141 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
142 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
143 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
144 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
145 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
146 /* TODO add 1920x1080P60_RB (CVT timing) */
147 { },
148 };
149
150 /* sorted by number of lines */
151 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
152 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
153 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
154 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
155 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
156 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
157 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
158 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
159 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
160 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
161 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
162 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
163 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
164 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
165 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
166 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
167 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
168 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
169 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
170 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
171 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
172 /* TODO add 1600X1200P60_RB (not a DMT timing) */
173 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
174 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
175 { },
176 };
177
178 /* sorted by number of lines */
179 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
180 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
181 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
182 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
183 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
184 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
185 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
186 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
187 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
188 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
189 { },
190 };
191
192 /* sorted by number of lines */
193 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
194 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
196 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
197 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
201 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
202 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
205 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
206 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
207 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
208 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
209 { },
210 };
211
212 /* ----------------------------------------------------------------------- */
213
214 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
215 {
216 return container_of(sd, struct adv7842_state, sd);
217 }
218
219 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
220 {
221 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
222 }
223
224 static inline unsigned htotal(const struct v4l2_bt_timings *t)
225 {
226 return V4L2_DV_BT_FRAME_WIDTH(t);
227 }
228
229 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
230 {
231 return V4L2_DV_BT_FRAME_HEIGHT(t);
232 }
233
234
235 /* ----------------------------------------------------------------------- */
236
237 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
238 u8 command, bool check)
239 {
240 union i2c_smbus_data data;
241
242 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
243 I2C_SMBUS_READ, command,
244 I2C_SMBUS_BYTE_DATA, &data))
245 return data.byte;
246 if (check)
247 v4l_err(client, "error reading %02x, %02x\n",
248 client->addr, command);
249 return -EIO;
250 }
251
252 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
253 {
254 int i;
255
256 for (i = 0; i < 3; i++) {
257 int ret = adv_smbus_read_byte_data_check(client, command, true);
258
259 if (ret >= 0) {
260 if (i)
261 v4l_err(client, "read ok after %d retries\n", i);
262 return ret;
263 }
264 }
265 v4l_err(client, "read failed\n");
266 return -EIO;
267 }
268
269 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
270 u8 command, u8 value)
271 {
272 union i2c_smbus_data data;
273 int err;
274 int i;
275
276 data.byte = value;
277 for (i = 0; i < 3; i++) {
278 err = i2c_smbus_xfer(client->adapter, client->addr,
279 client->flags,
280 I2C_SMBUS_WRITE, command,
281 I2C_SMBUS_BYTE_DATA, &data);
282 if (!err)
283 break;
284 }
285 if (err < 0)
286 v4l_err(client, "error writing %02x, %02x, %02x\n",
287 client->addr, command, value);
288 return err;
289 }
290
291 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
292 u8 command, u8 value)
293 {
294 union i2c_smbus_data data;
295 data.byte = value;
296
297 i2c_smbus_xfer(client->adapter, client->addr,
298 client->flags,
299 I2C_SMBUS_WRITE, command,
300 I2C_SMBUS_BYTE_DATA, &data);
301 }
302
303 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
304 u8 command, unsigned length, const u8 *values)
305 {
306 union i2c_smbus_data data;
307
308 if (length > I2C_SMBUS_BLOCK_MAX)
309 length = I2C_SMBUS_BLOCK_MAX;
310 data.block[0] = length;
311 memcpy(data.block + 1, values, length);
312 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
313 I2C_SMBUS_WRITE, command,
314 I2C_SMBUS_I2C_BLOCK_DATA, &data);
315 }
316
317 /* ----------------------------------------------------------------------- */
318
319 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
320 {
321 struct i2c_client *client = v4l2_get_subdevdata(sd);
322
323 return adv_smbus_read_byte_data(client, reg);
324 }
325
326 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
327 {
328 struct i2c_client *client = v4l2_get_subdevdata(sd);
329
330 return adv_smbus_write_byte_data(client, reg, val);
331 }
332
333 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
334 {
335 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
336 }
337
338 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
339 {
340 struct adv7842_state *state = to_state(sd);
341
342 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
343 }
344
345 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
346 {
347 struct adv7842_state *state = to_state(sd);
348
349 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
350 }
351
352 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
353 {
354 struct adv7842_state *state = to_state(sd);
355
356 return adv_smbus_read_byte_data(state->i2c_cec, reg);
357 }
358
359 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
360 {
361 struct adv7842_state *state = to_state(sd);
362
363 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
364 }
365
366 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
367 {
368 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
369 }
370
371 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
372 {
373 struct adv7842_state *state = to_state(sd);
374
375 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
376 }
377
378 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
379 {
380 struct adv7842_state *state = to_state(sd);
381
382 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
383 }
384
385 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
386 {
387 struct adv7842_state *state = to_state(sd);
388
389 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
390 }
391
392 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
393 {
394 struct adv7842_state *state = to_state(sd);
395
396 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
397 }
398
399 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
400 {
401 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
402 }
403
404 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
405 {
406 struct adv7842_state *state = to_state(sd);
407
408 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
409 }
410
411 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
412 {
413 struct adv7842_state *state = to_state(sd);
414
415 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
416 }
417
418 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
419 {
420 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
421 }
422
423 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
424 {
425 struct adv7842_state *state = to_state(sd);
426
427 return adv_smbus_read_byte_data(state->i2c_afe, reg);
428 }
429
430 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
431 {
432 struct adv7842_state *state = to_state(sd);
433
434 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
435 }
436
437 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
438 {
439 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
440 }
441
442 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
443 {
444 struct adv7842_state *state = to_state(sd);
445
446 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
447 }
448
449 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
450 {
451 struct adv7842_state *state = to_state(sd);
452
453 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
454 }
455
456 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
457 {
458 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
459 }
460
461 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
462 {
463 struct adv7842_state *state = to_state(sd);
464
465 return adv_smbus_read_byte_data(state->i2c_edid, reg);
466 }
467
468 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
469 {
470 struct adv7842_state *state = to_state(sd);
471
472 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
473 }
474
475 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
476 {
477 struct adv7842_state *state = to_state(sd);
478
479 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
480 }
481
482 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
483 {
484 struct adv7842_state *state = to_state(sd);
485
486 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
487 }
488
489 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
490 {
491 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
492 }
493
494 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
495 {
496 struct adv7842_state *state = to_state(sd);
497
498 return adv_smbus_read_byte_data(state->i2c_cp, reg);
499 }
500
501 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
502 {
503 struct adv7842_state *state = to_state(sd);
504
505 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
506 }
507
508 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
509 {
510 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
511 }
512
513 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
514 {
515 struct adv7842_state *state = to_state(sd);
516
517 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
518 }
519
520 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
521 {
522 struct adv7842_state *state = to_state(sd);
523
524 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
525 }
526
527 static void main_reset(struct v4l2_subdev *sd)
528 {
529 struct i2c_client *client = v4l2_get_subdevdata(sd);
530
531 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
532
533 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
534
535 mdelay(5);
536 }
537
538 /* ----------------------------------------------------------------------- */
539
540 static inline bool is_analog_input(struct v4l2_subdev *sd)
541 {
542 struct adv7842_state *state = to_state(sd);
543
544 return ((state->mode == ADV7842_MODE_RGB) ||
545 (state->mode == ADV7842_MODE_COMP));
546 }
547
548 static inline bool is_digital_input(struct v4l2_subdev *sd)
549 {
550 struct adv7842_state *state = to_state(sd);
551
552 return state->mode == ADV7842_MODE_HDMI;
553 }
554
555 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
556 .type = V4L2_DV_BT_656_1120,
557 /* keep this initialization for compatibility with GCC < 4.4.6 */
558 .reserved = { 0 },
559 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
560 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
561 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
562 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
563 V4L2_DV_BT_CAP_CUSTOM)
564 };
565
566 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
567 .type = V4L2_DV_BT_656_1120,
568 /* keep this initialization for compatibility with GCC < 4.4.6 */
569 .reserved = { 0 },
570 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
571 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
572 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
573 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
574 V4L2_DV_BT_CAP_CUSTOM)
575 };
576
577 static inline const struct v4l2_dv_timings_cap *
578 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
579 {
580 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
581 &adv7842_timings_cap_analog;
582 }
583
584 /* ----------------------------------------------------------------------- */
585
586 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
587 {
588 struct delayed_work *dwork = to_delayed_work(work);
589 struct adv7842_state *state = container_of(dwork,
590 struct adv7842_state, delayed_work_enable_hotplug);
591 struct v4l2_subdev *sd = &state->sd;
592 int present = state->hdmi_edid.present;
593 u8 mask = 0;
594
595 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
596 __func__, present);
597
598 if (present & (0x04 << ADV7842_EDID_PORT_A))
599 mask |= 0x20;
600 if (present & (0x04 << ADV7842_EDID_PORT_B))
601 mask |= 0x10;
602 io_write_and_or(sd, 0x20, 0xcf, mask);
603 }
604
605 static int edid_write_vga_segment(struct v4l2_subdev *sd)
606 {
607 struct i2c_client *client = v4l2_get_subdevdata(sd);
608 struct adv7842_state *state = to_state(sd);
609 const u8 *val = state->vga_edid.edid;
610 int err = 0;
611 int i;
612
613 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
614
615 /* HPA disable on port A and B */
616 io_write_and_or(sd, 0x20, 0xcf, 0x00);
617
618 /* Disable I2C access to internal EDID ram from VGA DDC port */
619 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
620
621 /* edid segment pointer '1' for VGA port */
622 rep_write_and_or(sd, 0x77, 0xef, 0x10);
623
624 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
625 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
626 I2C_SMBUS_BLOCK_MAX, val + i);
627 if (err)
628 return err;
629
630 /* Calculates the checksums and enables I2C access
631 * to internal EDID ram from VGA DDC port.
632 */
633 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
634
635 for (i = 0; i < 1000; i++) {
636 if (rep_read(sd, 0x79) & 0x20)
637 break;
638 mdelay(1);
639 }
640 if (i == 1000) {
641 v4l_err(client, "error enabling edid on VGA port\n");
642 return -EIO;
643 }
644
645 /* enable hotplug after 200 ms */
646 queue_delayed_work(state->work_queues,
647 &state->delayed_work_enable_hotplug, HZ / 5);
648
649 return 0;
650 }
651
652 static int edid_spa_location(const u8 *edid)
653 {
654 u8 d;
655
656 /*
657 * TODO, improve and update for other CEA extensions
658 * currently only for 1 segment (256 bytes),
659 * i.e. 1 extension block and CEA revision 3.
660 */
661 if ((edid[0x7e] != 1) ||
662 (edid[0x80] != 0x02) ||
663 (edid[0x81] != 0x03)) {
664 return -EINVAL;
665 }
666 /*
667 * search Vendor Specific Data Block (tag 3)
668 */
669 d = edid[0x82] & 0x7f;
670 if (d > 4) {
671 int i = 0x84;
672 int end = 0x80 + d;
673 do {
674 u8 tag = edid[i]>>5;
675 u8 len = edid[i] & 0x1f;
676
677 if ((tag == 3) && (len >= 5))
678 return i + 4;
679 i += len + 1;
680 } while (i < end);
681 }
682 return -EINVAL;
683 }
684
685 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
686 {
687 struct i2c_client *client = v4l2_get_subdevdata(sd);
688 struct adv7842_state *state = to_state(sd);
689 const u8 *val = state->hdmi_edid.edid;
690 int spa_loc = edid_spa_location(val);
691 int err = 0;
692 int i;
693
694 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c (spa at 0x%x)\n",
695 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B', spa_loc);
696
697 /* HPA disable on port A and B */
698 io_write_and_or(sd, 0x20, 0xcf, 0x00);
699
700 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
701 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
702
703 if (!state->hdmi_edid.present)
704 return 0;
705
706 /* edid segment pointer '0' for HDMI ports */
707 rep_write_and_or(sd, 0x77, 0xef, 0x00);
708
709 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
710 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
711 I2C_SMBUS_BLOCK_MAX, val + i);
712 if (err)
713 return err;
714
715 if (spa_loc < 0)
716 spa_loc = 0xc0; /* Default value [REF_02, p. 199] */
717
718 if (port == ADV7842_EDID_PORT_A) {
719 rep_write(sd, 0x72, val[spa_loc]);
720 rep_write(sd, 0x73, val[spa_loc + 1]);
721 } else {
722 rep_write(sd, 0x74, val[spa_loc]);
723 rep_write(sd, 0x75, val[spa_loc + 1]);
724 }
725 rep_write(sd, 0x76, spa_loc & 0xff);
726 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
727
728 /* Calculates the checksums and enables I2C access to internal
729 * EDID ram from HDMI DDC ports
730 */
731 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
732
733 for (i = 0; i < 1000; i++) {
734 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
735 break;
736 mdelay(1);
737 }
738 if (i == 1000) {
739 v4l_err(client, "error enabling edid on port %c\n",
740 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
741 return -EIO;
742 }
743
744 /* enable hotplug after 200 ms */
745 queue_delayed_work(state->work_queues,
746 &state->delayed_work_enable_hotplug, HZ / 5);
747
748 return 0;
749 }
750
751 /* ----------------------------------------------------------------------- */
752
753 #ifdef CONFIG_VIDEO_ADV_DEBUG
754 static void adv7842_inv_register(struct v4l2_subdev *sd)
755 {
756 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
757 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
758 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
759 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
760 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
761 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
762 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
763 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
764 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
765 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
766 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
767 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
768 }
769
770 static int adv7842_g_register(struct v4l2_subdev *sd,
771 struct v4l2_dbg_register *reg)
772 {
773 reg->size = 1;
774 switch (reg->reg >> 8) {
775 case 0:
776 reg->val = io_read(sd, reg->reg & 0xff);
777 break;
778 case 1:
779 reg->val = avlink_read(sd, reg->reg & 0xff);
780 break;
781 case 2:
782 reg->val = cec_read(sd, reg->reg & 0xff);
783 break;
784 case 3:
785 reg->val = infoframe_read(sd, reg->reg & 0xff);
786 break;
787 case 4:
788 reg->val = sdp_io_read(sd, reg->reg & 0xff);
789 break;
790 case 5:
791 reg->val = sdp_read(sd, reg->reg & 0xff);
792 break;
793 case 6:
794 reg->val = afe_read(sd, reg->reg & 0xff);
795 break;
796 case 7:
797 reg->val = rep_read(sd, reg->reg & 0xff);
798 break;
799 case 8:
800 reg->val = edid_read(sd, reg->reg & 0xff);
801 break;
802 case 9:
803 reg->val = hdmi_read(sd, reg->reg & 0xff);
804 break;
805 case 0xa:
806 reg->val = cp_read(sd, reg->reg & 0xff);
807 break;
808 case 0xb:
809 reg->val = vdp_read(sd, reg->reg & 0xff);
810 break;
811 default:
812 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
813 adv7842_inv_register(sd);
814 break;
815 }
816 return 0;
817 }
818
819 static int adv7842_s_register(struct v4l2_subdev *sd,
820 const struct v4l2_dbg_register *reg)
821 {
822 u8 val = reg->val & 0xff;
823
824 switch (reg->reg >> 8) {
825 case 0:
826 io_write(sd, reg->reg & 0xff, val);
827 break;
828 case 1:
829 avlink_write(sd, reg->reg & 0xff, val);
830 break;
831 case 2:
832 cec_write(sd, reg->reg & 0xff, val);
833 break;
834 case 3:
835 infoframe_write(sd, reg->reg & 0xff, val);
836 break;
837 case 4:
838 sdp_io_write(sd, reg->reg & 0xff, val);
839 break;
840 case 5:
841 sdp_write(sd, reg->reg & 0xff, val);
842 break;
843 case 6:
844 afe_write(sd, reg->reg & 0xff, val);
845 break;
846 case 7:
847 rep_write(sd, reg->reg & 0xff, val);
848 break;
849 case 8:
850 edid_write(sd, reg->reg & 0xff, val);
851 break;
852 case 9:
853 hdmi_write(sd, reg->reg & 0xff, val);
854 break;
855 case 0xa:
856 cp_write(sd, reg->reg & 0xff, val);
857 break;
858 case 0xb:
859 vdp_write(sd, reg->reg & 0xff, val);
860 break;
861 default:
862 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
863 adv7842_inv_register(sd);
864 break;
865 }
866 return 0;
867 }
868 #endif
869
870 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
871 {
872 struct adv7842_state *state = to_state(sd);
873 int prev = v4l2_ctrl_g_ctrl(state->detect_tx_5v_ctrl);
874 u8 reg_io_6f = io_read(sd, 0x6f);
875 int val = 0;
876
877 if (reg_io_6f & 0x02)
878 val |= 1; /* port A */
879 if (reg_io_6f & 0x01)
880 val |= 2; /* port B */
881
882 v4l2_dbg(1, debug, sd, "%s: 0x%x -> 0x%x\n", __func__, prev, val);
883
884 if (val != prev)
885 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, val);
886 return 0;
887 }
888
889 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
890 u8 prim_mode,
891 const struct adv7842_video_standards *predef_vid_timings,
892 const struct v4l2_dv_timings *timings)
893 {
894 int i;
895
896 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
897 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
898 is_digital_input(sd) ? 250000 : 1000000))
899 continue;
900 /* video std */
901 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
902 /* v_freq and prim mode */
903 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
904 return 0;
905 }
906
907 return -1;
908 }
909
910 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
911 struct v4l2_dv_timings *timings)
912 {
913 struct adv7842_state *state = to_state(sd);
914 int err;
915
916 v4l2_dbg(1, debug, sd, "%s\n", __func__);
917
918 /* reset to default values */
919 io_write(sd, 0x16, 0x43);
920 io_write(sd, 0x17, 0x5a);
921 /* disable embedded syncs for auto graphics mode */
922 cp_write_and_or(sd, 0x81, 0xef, 0x00);
923 cp_write(sd, 0x26, 0x00);
924 cp_write(sd, 0x27, 0x00);
925 cp_write(sd, 0x28, 0x00);
926 cp_write(sd, 0x29, 0x00);
927 cp_write(sd, 0x8f, 0x40);
928 cp_write(sd, 0x90, 0x00);
929 cp_write(sd, 0xa5, 0x00);
930 cp_write(sd, 0xa6, 0x00);
931 cp_write(sd, 0xa7, 0x00);
932 cp_write(sd, 0xab, 0x00);
933 cp_write(sd, 0xac, 0x00);
934
935 switch (state->mode) {
936 case ADV7842_MODE_COMP:
937 case ADV7842_MODE_RGB:
938 err = find_and_set_predefined_video_timings(sd,
939 0x01, adv7842_prim_mode_comp, timings);
940 if (err)
941 err = find_and_set_predefined_video_timings(sd,
942 0x02, adv7842_prim_mode_gr, timings);
943 break;
944 case ADV7842_MODE_HDMI:
945 err = find_and_set_predefined_video_timings(sd,
946 0x05, adv7842_prim_mode_hdmi_comp, timings);
947 if (err)
948 err = find_and_set_predefined_video_timings(sd,
949 0x06, adv7842_prim_mode_hdmi_gr, timings);
950 break;
951 default:
952 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
953 __func__, state->mode);
954 err = -1;
955 break;
956 }
957
958
959 return err;
960 }
961
962 static void configure_custom_video_timings(struct v4l2_subdev *sd,
963 const struct v4l2_bt_timings *bt)
964 {
965 struct adv7842_state *state = to_state(sd);
966 struct i2c_client *client = v4l2_get_subdevdata(sd);
967 u32 width = htotal(bt);
968 u32 height = vtotal(bt);
969 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
970 u16 cp_start_eav = width - bt->hfrontporch;
971 u16 cp_start_vbi = height - bt->vfrontporch + 1;
972 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
973 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
974 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
975 const u8 pll[2] = {
976 0xc0 | ((width >> 8) & 0x1f),
977 width & 0xff
978 };
979
980 v4l2_dbg(2, debug, sd, "%s\n", __func__);
981
982 switch (state->mode) {
983 case ADV7842_MODE_COMP:
984 case ADV7842_MODE_RGB:
985 /* auto graphics */
986 io_write(sd, 0x00, 0x07); /* video std */
987 io_write(sd, 0x01, 0x02); /* prim mode */
988 /* enable embedded syncs for auto graphics mode */
989 cp_write_and_or(sd, 0x81, 0xef, 0x10);
990
991 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
992 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
993 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
994 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
995 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
996 break;
997 }
998
999 /* active video - horizontal timing */
1000 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1001 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1002 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1003 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1004
1005 /* active video - vertical timing */
1006 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1007 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1008 ((cp_end_vbi >> 8) & 0xf));
1009 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1010 break;
1011 case ADV7842_MODE_HDMI:
1012 /* set default prim_mode/vid_std for HDMI
1013 according to [REF_03, c. 4.2] */
1014 io_write(sd, 0x00, 0x02); /* video std */
1015 io_write(sd, 0x01, 0x06); /* prim mode */
1016 break;
1017 default:
1018 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1019 __func__, state->mode);
1020 break;
1021 }
1022
1023 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1024 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1025 cp_write(sd, 0xab, (height >> 4) & 0xff);
1026 cp_write(sd, 0xac, (height & 0x0f) << 4);
1027 }
1028
1029 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1030 {
1031 struct adv7842_state *state = to_state(sd);
1032 u8 offset_buf[4];
1033
1034 if (auto_offset) {
1035 offset_a = 0x3ff;
1036 offset_b = 0x3ff;
1037 offset_c = 0x3ff;
1038 }
1039
1040 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1041 __func__, auto_offset ? "Auto" : "Manual",
1042 offset_a, offset_b, offset_c);
1043
1044 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1045 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1046 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1047 offset_buf[3] = offset_c & 0x0ff;
1048
1049 /* Registers must be written in this order with no i2c access in between */
1050 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
1051 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1052 }
1053
1054 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1055 {
1056 struct adv7842_state *state = to_state(sd);
1057 u8 gain_buf[4];
1058 u8 gain_man = 1;
1059 u8 agc_mode_man = 1;
1060
1061 if (auto_gain) {
1062 gain_man = 0;
1063 agc_mode_man = 0;
1064 gain_a = 0x100;
1065 gain_b = 0x100;
1066 gain_c = 0x100;
1067 }
1068
1069 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1070 __func__, auto_gain ? "Auto" : "Manual",
1071 gain_a, gain_b, gain_c);
1072
1073 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1074 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1075 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1076 gain_buf[3] = ((gain_c & 0x0ff));
1077
1078 /* Registers must be written in this order with no i2c access in between */
1079 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
1080 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1081 }
1082
1083 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1084 {
1085 struct adv7842_state *state = to_state(sd);
1086 bool rgb_output = io_read(sd, 0x02) & 0x02;
1087 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1088
1089 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1090 __func__, state->rgb_quantization_range,
1091 rgb_output, hdmi_signal);
1092
1093 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
1094 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
1095
1096 switch (state->rgb_quantization_range) {
1097 case V4L2_DV_RGB_RANGE_AUTO:
1098 if (state->mode == ADV7842_MODE_RGB) {
1099 /* Receiving analog RGB signal
1100 * Set RGB full range (0-255) */
1101 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1102 break;
1103 }
1104
1105 if (state->mode == ADV7842_MODE_COMP) {
1106 /* Receiving analog YPbPr signal
1107 * Set automode */
1108 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1109 break;
1110 }
1111
1112 if (hdmi_signal) {
1113 /* Receiving HDMI signal
1114 * Set automode */
1115 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1116 break;
1117 }
1118
1119 /* Receiving DVI-D signal
1120 * ADV7842 selects RGB limited range regardless of
1121 * input format (CE/IT) in automatic mode */
1122 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1123 /* RGB limited range (16-235) */
1124 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1125 } else {
1126 /* RGB full range (0-255) */
1127 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1128
1129 if (is_digital_input(sd) && rgb_output) {
1130 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1131 } else {
1132 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1133 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1134 }
1135 }
1136 break;
1137 case V4L2_DV_RGB_RANGE_LIMITED:
1138 if (state->mode == ADV7842_MODE_COMP) {
1139 /* YCrCb limited range (16-235) */
1140 io_write_and_or(sd, 0x02, 0x0f, 0x20);
1141 break;
1142 }
1143
1144 /* RGB limited range (16-235) */
1145 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1146
1147 break;
1148 case V4L2_DV_RGB_RANGE_FULL:
1149 if (state->mode == ADV7842_MODE_COMP) {
1150 /* YCrCb full range (0-255) */
1151 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1152 break;
1153 }
1154
1155 /* RGB full range (0-255) */
1156 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1157
1158 if (is_analog_input(sd) || hdmi_signal)
1159 break;
1160
1161 /* Adjust gain/offset for DVI-D signals only */
1162 if (rgb_output) {
1163 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1164 } else {
1165 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1166 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1167 }
1168 break;
1169 }
1170 }
1171
1172 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1173 {
1174 struct v4l2_subdev *sd = to_sd(ctrl);
1175 struct adv7842_state *state = to_state(sd);
1176
1177 /* TODO SDP ctrls
1178 contrast/brightness/hue/free run is acting a bit strange,
1179 not sure if sdp csc is correct.
1180 */
1181 switch (ctrl->id) {
1182 /* standard ctrls */
1183 case V4L2_CID_BRIGHTNESS:
1184 cp_write(sd, 0x3c, ctrl->val);
1185 sdp_write(sd, 0x14, ctrl->val);
1186 /* ignore lsb sdp 0x17[3:2] */
1187 return 0;
1188 case V4L2_CID_CONTRAST:
1189 cp_write(sd, 0x3a, ctrl->val);
1190 sdp_write(sd, 0x13, ctrl->val);
1191 /* ignore lsb sdp 0x17[1:0] */
1192 return 0;
1193 case V4L2_CID_SATURATION:
1194 cp_write(sd, 0x3b, ctrl->val);
1195 sdp_write(sd, 0x15, ctrl->val);
1196 /* ignore lsb sdp 0x17[5:4] */
1197 return 0;
1198 case V4L2_CID_HUE:
1199 cp_write(sd, 0x3d, ctrl->val);
1200 sdp_write(sd, 0x16, ctrl->val);
1201 /* ignore lsb sdp 0x17[7:6] */
1202 return 0;
1203 /* custom ctrls */
1204 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1205 afe_write(sd, 0xc8, ctrl->val);
1206 return 0;
1207 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1208 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1209 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1210 return 0;
1211 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1212 u8 R = (ctrl->val & 0xff0000) >> 16;
1213 u8 G = (ctrl->val & 0x00ff00) >> 8;
1214 u8 B = (ctrl->val & 0x0000ff);
1215 /* RGB -> YUV, numerical approximation */
1216 int Y = 66 * R + 129 * G + 25 * B;
1217 int U = -38 * R - 74 * G + 112 * B;
1218 int V = 112 * R - 94 * G - 18 * B;
1219
1220 /* Scale down to 8 bits with rounding */
1221 Y = (Y + 128) >> 8;
1222 U = (U + 128) >> 8;
1223 V = (V + 128) >> 8;
1224 /* make U,V positive */
1225 Y += 16;
1226 U += 128;
1227 V += 128;
1228
1229 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1230 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1231
1232 /* CP */
1233 cp_write(sd, 0xc1, R);
1234 cp_write(sd, 0xc0, G);
1235 cp_write(sd, 0xc2, B);
1236 /* SDP */
1237 sdp_write(sd, 0xde, Y);
1238 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1239 return 0;
1240 }
1241 case V4L2_CID_DV_RX_RGB_RANGE:
1242 state->rgb_quantization_range = ctrl->val;
1243 set_rgb_quantization_range(sd);
1244 return 0;
1245 }
1246 return -EINVAL;
1247 }
1248
1249 static inline bool no_power(struct v4l2_subdev *sd)
1250 {
1251 return io_read(sd, 0x0c) & 0x24;
1252 }
1253
1254 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1255 {
1256 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1257 }
1258
1259 static inline bool is_hdmi(struct v4l2_subdev *sd)
1260 {
1261 return hdmi_read(sd, 0x05) & 0x80;
1262 }
1263
1264 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1265 {
1266 struct adv7842_state *state = to_state(sd);
1267
1268 *status = 0;
1269
1270 if (io_read(sd, 0x0c) & 0x24)
1271 *status |= V4L2_IN_ST_NO_POWER;
1272
1273 if (state->mode == ADV7842_MODE_SDP) {
1274 /* status from SDP block */
1275 if (!(sdp_read(sd, 0x5A) & 0x01))
1276 *status |= V4L2_IN_ST_NO_SIGNAL;
1277
1278 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1279 __func__, *status);
1280 return 0;
1281 }
1282 /* status from CP block */
1283 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1284 !(cp_read(sd, 0xb1) & 0x80))
1285 /* TODO channel 2 */
1286 *status |= V4L2_IN_ST_NO_SIGNAL;
1287
1288 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1289 *status |= V4L2_IN_ST_NO_SIGNAL;
1290
1291 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1292 __func__, *status);
1293
1294 return 0;
1295 }
1296
1297 struct stdi_readback {
1298 u16 bl, lcf, lcvs;
1299 u8 hs_pol, vs_pol;
1300 bool interlaced;
1301 };
1302
1303 static int stdi2dv_timings(struct v4l2_subdev *sd,
1304 struct stdi_readback *stdi,
1305 struct v4l2_dv_timings *timings)
1306 {
1307 struct adv7842_state *state = to_state(sd);
1308 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1309 u32 pix_clk;
1310 int i;
1311
1312 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1313 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1314
1315 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1316 adv7842_get_dv_timings_cap(sd),
1317 adv7842_check_dv_timings, NULL))
1318 continue;
1319 if (vtotal(bt) != stdi->lcf + 1)
1320 continue;
1321 if (bt->vsync != stdi->lcvs)
1322 continue;
1323
1324 pix_clk = hfreq * htotal(bt);
1325
1326 if ((pix_clk < bt->pixelclock + 1000000) &&
1327 (pix_clk > bt->pixelclock - 1000000)) {
1328 *timings = v4l2_dv_timings_presets[i];
1329 return 0;
1330 }
1331 }
1332
1333 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1334 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1335 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1336 timings))
1337 return 0;
1338 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1339 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1340 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1341 state->aspect_ratio, timings))
1342 return 0;
1343
1344 v4l2_dbg(2, debug, sd,
1345 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1346 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1347 stdi->hs_pol, stdi->vs_pol);
1348 return -1;
1349 }
1350
1351 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1352 {
1353 u32 status;
1354
1355 adv7842_g_input_status(sd, &status);
1356 if (status & V4L2_IN_ST_NO_SIGNAL) {
1357 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1358 return -ENOLINK;
1359 }
1360
1361 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1362 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1363 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1364
1365 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1366 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1367 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1368 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1369 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1370 } else {
1371 stdi->hs_pol = 'x';
1372 stdi->vs_pol = 'x';
1373 }
1374 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1375
1376 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1377 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1378 return -ENOLINK;
1379 }
1380
1381 v4l2_dbg(2, debug, sd,
1382 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1383 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1384 stdi->hs_pol, stdi->vs_pol,
1385 stdi->interlaced ? "interlaced" : "progressive");
1386
1387 return 0;
1388 }
1389
1390 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1391 struct v4l2_enum_dv_timings *timings)
1392 {
1393 if (timings->pad != 0)
1394 return -EINVAL;
1395
1396 return v4l2_enum_dv_timings_cap(timings,
1397 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1398 }
1399
1400 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1401 struct v4l2_dv_timings_cap *cap)
1402 {
1403 if (cap->pad != 0)
1404 return -EINVAL;
1405
1406 *cap = *adv7842_get_dv_timings_cap(sd);
1407 return 0;
1408 }
1409
1410 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1411 if the format is listed in adv7842_timings[] */
1412 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1413 struct v4l2_dv_timings *timings)
1414 {
1415 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1416 is_digital_input(sd) ? 250000 : 1000000,
1417 adv7842_check_dv_timings, NULL);
1418 }
1419
1420 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1421 struct v4l2_dv_timings *timings)
1422 {
1423 struct adv7842_state *state = to_state(sd);
1424 struct v4l2_bt_timings *bt = &timings->bt;
1425 struct stdi_readback stdi = { 0 };
1426
1427 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1428
1429 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1430
1431 /* SDP block */
1432 if (state->mode == ADV7842_MODE_SDP)
1433 return -ENODATA;
1434
1435 /* read STDI */
1436 if (read_stdi(sd, &stdi)) {
1437 state->restart_stdi_once = true;
1438 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1439 return -ENOLINK;
1440 }
1441 bt->interlaced = stdi.interlaced ?
1442 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1443
1444 if (is_digital_input(sd)) {
1445 uint32_t freq;
1446
1447 timings->type = V4L2_DV_BT_656_1120;
1448
1449 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1450 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1451 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
1452 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
1453 if (is_hdmi(sd)) {
1454 /* adjust for deep color mode */
1455 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
1456 }
1457 bt->pixelclock = freq;
1458 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1459 hdmi_read(sd, 0x21);
1460 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1461 hdmi_read(sd, 0x23);
1462 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1463 hdmi_read(sd, 0x25);
1464 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1465 hdmi_read(sd, 0x2b)) / 2;
1466 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1467 hdmi_read(sd, 0x2f)) / 2;
1468 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1469 hdmi_read(sd, 0x33)) / 2;
1470 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1471 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1472 if (bt->interlaced == V4L2_DV_INTERLACED) {
1473 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1474 hdmi_read(sd, 0x0c);
1475 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1476 hdmi_read(sd, 0x2d)) / 2;
1477 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1478 hdmi_read(sd, 0x31)) / 2;
1479 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1480 hdmi_read(sd, 0x35)) / 2;
1481 }
1482 adv7842_fill_optional_dv_timings_fields(sd, timings);
1483 } else {
1484 /* find format
1485 * Since LCVS values are inaccurate [REF_03, p. 339-340],
1486 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1487 */
1488 if (!stdi2dv_timings(sd, &stdi, timings))
1489 goto found;
1490 stdi.lcvs += 1;
1491 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1492 if (!stdi2dv_timings(sd, &stdi, timings))
1493 goto found;
1494 stdi.lcvs -= 2;
1495 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1496 if (stdi2dv_timings(sd, &stdi, timings)) {
1497 /*
1498 * The STDI block may measure wrong values, especially
1499 * for lcvs and lcf. If the driver can not find any
1500 * valid timing, the STDI block is restarted to measure
1501 * the video timings again. The function will return an
1502 * error, but the restart of STDI will generate a new
1503 * STDI interrupt and the format detection process will
1504 * restart.
1505 */
1506 if (state->restart_stdi_once) {
1507 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1508 /* TODO restart STDI for Sync Channel 2 */
1509 /* enter one-shot mode */
1510 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1511 /* trigger STDI restart */
1512 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1513 /* reset to continuous mode */
1514 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1515 state->restart_stdi_once = false;
1516 return -ENOLINK;
1517 }
1518 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1519 return -ERANGE;
1520 }
1521 state->restart_stdi_once = true;
1522 }
1523 found:
1524
1525 if (debug > 1)
1526 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1527 timings, true);
1528 return 0;
1529 }
1530
1531 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1532 struct v4l2_dv_timings *timings)
1533 {
1534 struct adv7842_state *state = to_state(sd);
1535 struct v4l2_bt_timings *bt;
1536 int err;
1537
1538 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1539
1540 if (state->mode == ADV7842_MODE_SDP)
1541 return -ENODATA;
1542
1543 if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1544 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1545 return 0;
1546 }
1547
1548 bt = &timings->bt;
1549
1550 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1551 adv7842_check_dv_timings, NULL))
1552 return -ERANGE;
1553
1554 adv7842_fill_optional_dv_timings_fields(sd, timings);
1555
1556 state->timings = *timings;
1557
1558 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1559
1560 /* Use prim_mode and vid_std when available */
1561 err = configure_predefined_video_timings(sd, timings);
1562 if (err) {
1563 /* custom settings when the video format
1564 does not have prim_mode/vid_std */
1565 configure_custom_video_timings(sd, bt);
1566 }
1567
1568 set_rgb_quantization_range(sd);
1569
1570
1571 if (debug > 1)
1572 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1573 timings, true);
1574 return 0;
1575 }
1576
1577 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1578 struct v4l2_dv_timings *timings)
1579 {
1580 struct adv7842_state *state = to_state(sd);
1581
1582 if (state->mode == ADV7842_MODE_SDP)
1583 return -ENODATA;
1584 *timings = state->timings;
1585 return 0;
1586 }
1587
1588 static void enable_input(struct v4l2_subdev *sd)
1589 {
1590 struct adv7842_state *state = to_state(sd);
1591
1592 set_rgb_quantization_range(sd);
1593 switch (state->mode) {
1594 case ADV7842_MODE_SDP:
1595 case ADV7842_MODE_COMP:
1596 case ADV7842_MODE_RGB:
1597 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1598 break;
1599 case ADV7842_MODE_HDMI:
1600 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1601 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1602 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1603 break;
1604 default:
1605 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1606 __func__, state->mode);
1607 break;
1608 }
1609 }
1610
1611 static void disable_input(struct v4l2_subdev *sd)
1612 {
1613 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1614 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
1615 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1616 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1617 }
1618
1619 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1620 const struct adv7842_sdp_csc_coeff *c)
1621 {
1622 /* csc auto/manual */
1623 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1624
1625 if (!c->manual)
1626 return;
1627
1628 /* csc scaling */
1629 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1630
1631 /* A coeff */
1632 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1633 sdp_io_write(sd, 0xe1, c->A1);
1634 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1635 sdp_io_write(sd, 0xe3, c->A2);
1636 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1637 sdp_io_write(sd, 0xe5, c->A3);
1638
1639 /* A scale */
1640 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1641 sdp_io_write(sd, 0xe7, c->A4);
1642
1643 /* B coeff */
1644 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1645 sdp_io_write(sd, 0xe9, c->B1);
1646 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1647 sdp_io_write(sd, 0xeb, c->B2);
1648 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1649 sdp_io_write(sd, 0xed, c->B3);
1650
1651 /* B scale */
1652 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1653 sdp_io_write(sd, 0xef, c->B4);
1654
1655 /* C coeff */
1656 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1657 sdp_io_write(sd, 0xf1, c->C1);
1658 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1659 sdp_io_write(sd, 0xf3, c->C2);
1660 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1661 sdp_io_write(sd, 0xf5, c->C3);
1662
1663 /* C scale */
1664 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1665 sdp_io_write(sd, 0xf7, c->C4);
1666 }
1667
1668 static void select_input(struct v4l2_subdev *sd,
1669 enum adv7842_vid_std_select vid_std_select)
1670 {
1671 struct adv7842_state *state = to_state(sd);
1672
1673 switch (state->mode) {
1674 case ADV7842_MODE_SDP:
1675 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1676 io_write(sd, 0x01, 0); /* prim mode */
1677 /* enable embedded syncs for auto graphics mode */
1678 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1679
1680 afe_write(sd, 0x00, 0x00); /* power up ADC */
1681 afe_write(sd, 0xc8, 0x00); /* phase control */
1682
1683 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1684 /* script says register 0xde, which don't exist in manual */
1685
1686 /* Manual analog input muxing mode, CVBS (6.4)*/
1687 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1688 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1689 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1690 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1691 } else {
1692 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1693 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1694 }
1695 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1696 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1697
1698 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1699 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1700
1701 /* SDP recommended settings */
1702 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1703 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1704
1705 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1706 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1707 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1708 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1709 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1710 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1711 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1712
1713 /* deinterlacer enabled and 3D comb */
1714 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1715
1716 break;
1717
1718 case ADV7842_MODE_COMP:
1719 case ADV7842_MODE_RGB:
1720 /* Automatic analog input muxing mode */
1721 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1722 /* set mode and select free run resolution */
1723 io_write(sd, 0x00, vid_std_select); /* video std */
1724 io_write(sd, 0x01, 0x02); /* prim mode */
1725 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1726 for auto graphics mode */
1727
1728 afe_write(sd, 0x00, 0x00); /* power up ADC */
1729 afe_write(sd, 0xc8, 0x00); /* phase control */
1730 if (state->mode == ADV7842_MODE_COMP) {
1731 /* force to YCrCb */
1732 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1733 } else {
1734 /* force to RGB */
1735 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1736 }
1737
1738 /* set ADI recommended settings for digitizer */
1739 /* "ADV7842 Register Settings Recommendations
1740 * (rev. 1.8, November 2010)" p. 9. */
1741 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1742 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1743
1744 /* set to default gain for RGB */
1745 cp_write(sd, 0x73, 0x10);
1746 cp_write(sd, 0x74, 0x04);
1747 cp_write(sd, 0x75, 0x01);
1748 cp_write(sd, 0x76, 0x00);
1749
1750 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1751 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1752 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1753 break;
1754
1755 case ADV7842_MODE_HDMI:
1756 /* Automatic analog input muxing mode */
1757 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1758 /* set mode and select free run resolution */
1759 if (state->hdmi_port_a)
1760 hdmi_write(sd, 0x00, 0x02); /* select port A */
1761 else
1762 hdmi_write(sd, 0x00, 0x03); /* select port B */
1763 io_write(sd, 0x00, vid_std_select); /* video std */
1764 io_write(sd, 0x01, 5); /* prim mode */
1765 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1766 for auto graphics mode */
1767
1768 /* set ADI recommended settings for HDMI: */
1769 /* "ADV7842 Register Settings Recommendations
1770 * (rev. 1.8, November 2010)" p. 3. */
1771 hdmi_write(sd, 0xc0, 0x00);
1772 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1773 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1774 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1775 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1776 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1777 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1778 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1779 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1780 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1781 Improve robustness */
1782 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1783 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1784 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1785 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1786 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1787 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1788 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1789 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1790 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1791 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1792
1793 afe_write(sd, 0x00, 0xff); /* power down ADC */
1794 afe_write(sd, 0xc8, 0x40); /* phase control */
1795
1796 /* set to default gain for HDMI */
1797 cp_write(sd, 0x73, 0x10);
1798 cp_write(sd, 0x74, 0x04);
1799 cp_write(sd, 0x75, 0x01);
1800 cp_write(sd, 0x76, 0x00);
1801
1802 /* reset ADI recommended settings for digitizer */
1803 /* "ADV7842 Register Settings Recommendations
1804 * (rev. 2.5, June 2010)" p. 17. */
1805 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1806 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1807 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1808
1809 /* CP coast control */
1810 cp_write(sd, 0xc3, 0x33); /* Component mode */
1811
1812 /* color space conversion, autodetect color space */
1813 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1814 break;
1815
1816 default:
1817 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1818 __func__, state->mode);
1819 break;
1820 }
1821 }
1822
1823 static int adv7842_s_routing(struct v4l2_subdev *sd,
1824 u32 input, u32 output, u32 config)
1825 {
1826 struct adv7842_state *state = to_state(sd);
1827
1828 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1829
1830 switch (input) {
1831 case ADV7842_SELECT_HDMI_PORT_A:
1832 state->mode = ADV7842_MODE_HDMI;
1833 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1834 state->hdmi_port_a = true;
1835 break;
1836 case ADV7842_SELECT_HDMI_PORT_B:
1837 state->mode = ADV7842_MODE_HDMI;
1838 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1839 state->hdmi_port_a = false;
1840 break;
1841 case ADV7842_SELECT_VGA_COMP:
1842 state->mode = ADV7842_MODE_COMP;
1843 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1844 break;
1845 case ADV7842_SELECT_VGA_RGB:
1846 state->mode = ADV7842_MODE_RGB;
1847 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1848 break;
1849 case ADV7842_SELECT_SDP_CVBS:
1850 state->mode = ADV7842_MODE_SDP;
1851 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1852 break;
1853 case ADV7842_SELECT_SDP_YC:
1854 state->mode = ADV7842_MODE_SDP;
1855 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1856 break;
1857 default:
1858 return -EINVAL;
1859 }
1860
1861 disable_input(sd);
1862 select_input(sd, state->vid_std_select);
1863 enable_input(sd);
1864
1865 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1866
1867 return 0;
1868 }
1869
1870 static int adv7842_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1871 u32 *code)
1872 {
1873 if (index)
1874 return -EINVAL;
1875 /* Good enough for now */
1876 *code = MEDIA_BUS_FMT_FIXED;
1877 return 0;
1878 }
1879
1880 static int adv7842_g_mbus_fmt(struct v4l2_subdev *sd,
1881 struct v4l2_mbus_framefmt *fmt)
1882 {
1883 struct adv7842_state *state = to_state(sd);
1884
1885 fmt->width = state->timings.bt.width;
1886 fmt->height = state->timings.bt.height;
1887 fmt->code = MEDIA_BUS_FMT_FIXED;
1888 fmt->field = V4L2_FIELD_NONE;
1889
1890 if (state->mode == ADV7842_MODE_SDP) {
1891 /* SPD block */
1892 if (!(sdp_read(sd, 0x5A) & 0x01))
1893 return -EINVAL;
1894 fmt->width = 720;
1895 /* valid signal */
1896 if (state->norm & V4L2_STD_525_60)
1897 fmt->height = 480;
1898 else
1899 fmt->height = 576;
1900 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1901 return 0;
1902 }
1903
1904 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1905 fmt->colorspace = (state->timings.bt.height <= 576) ?
1906 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1907 }
1908 return 0;
1909 }
1910
1911 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
1912 {
1913 if (enable) {
1914 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
1915 io_write(sd, 0x46, 0x9c);
1916 /* ESDP_50HZ_DET interrupt */
1917 io_write(sd, 0x5a, 0x10);
1918 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
1919 io_write(sd, 0x73, 0x03);
1920 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1921 io_write(sd, 0x78, 0x03);
1922 /* Enable SDP Standard Detection Change and SDP Video Detected */
1923 io_write(sd, 0xa0, 0x09);
1924 /* Enable HDMI_MODE interrupt */
1925 io_write(sd, 0x69, 0x08);
1926 } else {
1927 io_write(sd, 0x46, 0x0);
1928 io_write(sd, 0x5a, 0x0);
1929 io_write(sd, 0x73, 0x0);
1930 io_write(sd, 0x78, 0x0);
1931 io_write(sd, 0xa0, 0x0);
1932 io_write(sd, 0x69, 0x0);
1933 }
1934 }
1935
1936 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1937 {
1938 struct adv7842_state *state = to_state(sd);
1939 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
1940 u8 irq_status[6];
1941
1942 adv7842_irq_enable(sd, false);
1943
1944 /* read status */
1945 irq_status[0] = io_read(sd, 0x43);
1946 irq_status[1] = io_read(sd, 0x57);
1947 irq_status[2] = io_read(sd, 0x70);
1948 irq_status[3] = io_read(sd, 0x75);
1949 irq_status[4] = io_read(sd, 0x9d);
1950 irq_status[5] = io_read(sd, 0x66);
1951
1952 /* and clear */
1953 if (irq_status[0])
1954 io_write(sd, 0x44, irq_status[0]);
1955 if (irq_status[1])
1956 io_write(sd, 0x58, irq_status[1]);
1957 if (irq_status[2])
1958 io_write(sd, 0x71, irq_status[2]);
1959 if (irq_status[3])
1960 io_write(sd, 0x76, irq_status[3]);
1961 if (irq_status[4])
1962 io_write(sd, 0x9e, irq_status[4]);
1963 if (irq_status[5])
1964 io_write(sd, 0x67, irq_status[5]);
1965
1966 adv7842_irq_enable(sd, true);
1967
1968 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
1969 irq_status[0], irq_status[1], irq_status[2],
1970 irq_status[3], irq_status[4], irq_status[5]);
1971
1972 /* format change CP */
1973 fmt_change_cp = irq_status[0] & 0x9c;
1974
1975 /* format change SDP */
1976 if (state->mode == ADV7842_MODE_SDP)
1977 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
1978 else
1979 fmt_change_sdp = 0;
1980
1981 /* digital format CP */
1982 if (is_digital_input(sd))
1983 fmt_change_digital = irq_status[3] & 0x03;
1984 else
1985 fmt_change_digital = 0;
1986
1987 /* format change */
1988 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
1989 v4l2_dbg(1, debug, sd,
1990 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
1991 __func__, fmt_change_cp, fmt_change_digital,
1992 fmt_change_sdp);
1993 v4l2_subdev_notify(sd, ADV7842_FMT_CHANGE, NULL);
1994 if (handled)
1995 *handled = true;
1996 }
1997
1998 /* HDMI/DVI mode */
1999 if (irq_status[5] & 0x08) {
2000 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2001 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
2002 set_rgb_quantization_range(sd);
2003 if (handled)
2004 *handled = true;
2005 }
2006
2007 /* tx 5v detect */
2008 if (irq_status[2] & 0x3) {
2009 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
2010 adv7842_s_detect_tx_5v_ctrl(sd);
2011 if (handled)
2012 *handled = true;
2013 }
2014 return 0;
2015 }
2016
2017 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2018 {
2019 struct adv7842_state *state = to_state(sd);
2020 u8 *data = NULL;
2021
2022 memset(edid->reserved, 0, sizeof(edid->reserved));
2023
2024 switch (edid->pad) {
2025 case ADV7842_EDID_PORT_A:
2026 case ADV7842_EDID_PORT_B:
2027 if (state->hdmi_edid.present & (0x04 << edid->pad))
2028 data = state->hdmi_edid.edid;
2029 break;
2030 case ADV7842_EDID_PORT_VGA:
2031 if (state->vga_edid.present)
2032 data = state->vga_edid.edid;
2033 break;
2034 default:
2035 return -EINVAL;
2036 }
2037
2038 if (edid->start_block == 0 && edid->blocks == 0) {
2039 edid->blocks = data ? 2 : 0;
2040 return 0;
2041 }
2042
2043 if (!data)
2044 return -ENODATA;
2045
2046 if (edid->start_block >= 2)
2047 return -EINVAL;
2048
2049 if (edid->start_block + edid->blocks > 2)
2050 edid->blocks = 2 - edid->start_block;
2051
2052 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2053
2054 return 0;
2055 }
2056
2057 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
2058 {
2059 struct adv7842_state *state = to_state(sd);
2060 int err = 0;
2061
2062 memset(e->reserved, 0, sizeof(e->reserved));
2063
2064 if (e->pad > ADV7842_EDID_PORT_VGA)
2065 return -EINVAL;
2066 if (e->start_block != 0)
2067 return -EINVAL;
2068 if (e->blocks > 2) {
2069 e->blocks = 2;
2070 return -E2BIG;
2071 }
2072
2073 /* todo, per edid */
2074 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
2075 e->edid[0x16]);
2076
2077 switch (e->pad) {
2078 case ADV7842_EDID_PORT_VGA:
2079 memset(&state->vga_edid.edid, 0, 256);
2080 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
2081 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
2082 err = edid_write_vga_segment(sd);
2083 break;
2084 case ADV7842_EDID_PORT_A:
2085 case ADV7842_EDID_PORT_B:
2086 memset(&state->hdmi_edid.edid, 0, 256);
2087 if (e->blocks)
2088 state->hdmi_edid.present |= 0x04 << e->pad;
2089 else
2090 state->hdmi_edid.present &= ~(0x04 << e->pad);
2091 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
2092 err = edid_write_hdmi_segment(sd, e->pad);
2093 break;
2094 default:
2095 return -EINVAL;
2096 }
2097 if (err < 0)
2098 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2099 return err;
2100 }
2101
2102 struct adv7842_cfg_read_infoframe {
2103 const char *desc;
2104 u8 present_mask;
2105 u8 head_addr;
2106 u8 payload_addr;
2107 };
2108
2109 static void log_infoframe(struct v4l2_subdev *sd, struct adv7842_cfg_read_infoframe *cri)
2110 {
2111 int i;
2112 uint8_t buffer[32];
2113 union hdmi_infoframe frame;
2114 u8 len;
2115 struct i2c_client *client = v4l2_get_subdevdata(sd);
2116 struct device *dev = &client->dev;
2117
2118 if (!(io_read(sd, 0x60) & cri->present_mask)) {
2119 v4l2_info(sd, "%s infoframe not received\n", cri->desc);
2120 return;
2121 }
2122
2123 for (i = 0; i < 3; i++)
2124 buffer[i] = infoframe_read(sd, cri->head_addr + i);
2125
2126 len = buffer[2] + 1;
2127
2128 if (len + 3 > sizeof(buffer)) {
2129 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
2130 return;
2131 }
2132
2133 for (i = 0; i < len; i++)
2134 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);
2135
2136 if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
2137 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
2138 return;
2139 }
2140
2141 hdmi_infoframe_log(KERN_INFO, dev, &frame);
2142 }
2143
2144 static void adv7842_log_infoframes(struct v4l2_subdev *sd)
2145 {
2146 int i;
2147 struct adv7842_cfg_read_infoframe cri[] = {
2148 { "AVI", 0x01, 0xe0, 0x00 },
2149 { "Audio", 0x02, 0xe3, 0x1c },
2150 { "SDP", 0x04, 0xe6, 0x2a },
2151 { "Vendor", 0x10, 0xec, 0x54 }
2152 };
2153
2154 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2155 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2156 return;
2157 }
2158
2159 for (i = 0; i < ARRAY_SIZE(cri); i++)
2160 log_infoframe(sd, &cri[i]);
2161 }
2162
2163 static const char * const prim_mode_txt[] = {
2164 "SDP",
2165 "Component",
2166 "Graphics",
2167 "Reserved",
2168 "CVBS & HDMI AUDIO",
2169 "HDMI-Comp",
2170 "HDMI-GR",
2171 "Reserved",
2172 "Reserved",
2173 "Reserved",
2174 "Reserved",
2175 "Reserved",
2176 "Reserved",
2177 "Reserved",
2178 "Reserved",
2179 "Reserved",
2180 };
2181
2182 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2183 {
2184 /* SDP (Standard definition processor) block */
2185 uint8_t sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2186
2187 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2188 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2189 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2190
2191 v4l2_info(sd, "SDP: free run: %s\n",
2192 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2193 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2194 "valid SD/PR signal detected" : "invalid/no signal");
2195 if (sdp_signal_detected) {
2196 static const char * const sdp_std_txt[] = {
2197 "NTSC-M/J",
2198 "1?",
2199 "NTSC-443",
2200 "60HzSECAM",
2201 "PAL-M",
2202 "5?",
2203 "PAL-60",
2204 "7?", "8?", "9?", "a?", "b?",
2205 "PAL-CombN",
2206 "d?",
2207 "PAL-BGHID",
2208 "SECAM"
2209 };
2210 v4l2_info(sd, "SDP: standard %s\n",
2211 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2212 v4l2_info(sd, "SDP: %s\n",
2213 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2214 v4l2_info(sd, "SDP: %s\n",
2215 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2216 v4l2_info(sd, "SDP: deinterlacer %s\n",
2217 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2218 v4l2_info(sd, "SDP: csc %s mode\n",
2219 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2220 }
2221 return 0;
2222 }
2223
2224 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2225 {
2226 /* CP block */
2227 struct adv7842_state *state = to_state(sd);
2228 struct v4l2_dv_timings timings;
2229 uint8_t reg_io_0x02 = io_read(sd, 0x02);
2230 uint8_t reg_io_0x21 = io_read(sd, 0x21);
2231 uint8_t reg_rep_0x77 = rep_read(sd, 0x77);
2232 uint8_t reg_rep_0x7d = rep_read(sd, 0x7d);
2233 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2234 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2235 bool audio_mute = io_read(sd, 0x65) & 0x40;
2236
2237 static const char * const csc_coeff_sel_rb[16] = {
2238 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2239 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2240 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2241 "reserved", "reserved", "reserved", "reserved", "manual"
2242 };
2243 static const char * const input_color_space_txt[16] = {
2244 "RGB limited range (16-235)", "RGB full range (0-255)",
2245 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2246 "xvYCC Bt.601", "xvYCC Bt.709",
2247 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2248 "invalid", "invalid", "invalid", "invalid", "invalid",
2249 "invalid", "invalid", "automatic"
2250 };
2251 static const char * const rgb_quantization_range_txt[] = {
2252 "Automatic",
2253 "RGB limited range (16-235)",
2254 "RGB full range (0-255)",
2255 };
2256 static const char * const deep_color_mode_txt[4] = {
2257 "8-bits per channel",
2258 "10-bits per channel",
2259 "12-bits per channel",
2260 "16-bits per channel (not supported)"
2261 };
2262
2263 v4l2_info(sd, "-----Chip status-----\n");
2264 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2265 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2266 state->hdmi_port_a ? "A" : "B");
2267 v4l2_info(sd, "EDID A %s, B %s\n",
2268 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2269 "enabled" : "disabled",
2270 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2271 "enabled" : "disabled");
2272 v4l2_info(sd, "HPD A %s, B %s\n",
2273 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2274 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2275 v4l2_info(sd, "CEC %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2276 "enabled" : "disabled");
2277
2278 v4l2_info(sd, "-----Signal status-----\n");
2279 if (state->hdmi_port_a) {
2280 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2281 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2282 v4l2_info(sd, "TMDS signal detected: %s\n",
2283 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2284 v4l2_info(sd, "TMDS signal locked: %s\n",
2285 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2286 } else {
2287 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2288 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2289 v4l2_info(sd, "TMDS signal detected: %s\n",
2290 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2291 v4l2_info(sd, "TMDS signal locked: %s\n",
2292 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2293 }
2294 v4l2_info(sd, "CP free run: %s\n",
2295 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2296 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2297 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2298 (io_read(sd, 0x01) & 0x70) >> 4);
2299
2300 v4l2_info(sd, "-----Video Timings-----\n");
2301 if (no_cp_signal(sd)) {
2302 v4l2_info(sd, "STDI: not locked\n");
2303 } else {
2304 uint32_t bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2305 uint32_t lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2306 uint32_t lcvs = cp_read(sd, 0xb3) >> 3;
2307 uint32_t fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2308 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2309 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2310 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2311 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2312 v4l2_info(sd,
2313 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2314 lcf, bl, lcvs, fcl,
2315 (cp_read(sd, 0xb1) & 0x40) ?
2316 "interlaced" : "progressive",
2317 hs_pol, vs_pol);
2318 }
2319 if (adv7842_query_dv_timings(sd, &timings))
2320 v4l2_info(sd, "No video detected\n");
2321 else
2322 v4l2_print_dv_timings(sd->name, "Detected format: ",
2323 &timings, true);
2324 v4l2_print_dv_timings(sd->name, "Configured format: ",
2325 &state->timings, true);
2326
2327 if (no_cp_signal(sd))
2328 return 0;
2329
2330 v4l2_info(sd, "-----Color space-----\n");
2331 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2332 rgb_quantization_range_txt[state->rgb_quantization_range]);
2333 v4l2_info(sd, "Input color space: %s\n",
2334 input_color_space_txt[reg_io_0x02 >> 4]);
2335 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2336 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2337 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2338 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2339 "enabled" : "disabled");
2340 v4l2_info(sd, "Color space conversion: %s\n",
2341 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2342
2343 if (!is_digital_input(sd))
2344 return 0;
2345
2346 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2347 v4l2_info(sd, "HDCP encrypted content: %s\n",
2348 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2349 v4l2_info(sd, "HDCP keys read: %s%s\n",
2350 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2351 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2352 if (!is_hdmi(sd))
2353 return 0;
2354
2355 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2356 audio_pll_locked ? "locked" : "not locked",
2357 audio_sample_packet_detect ? "detected" : "not detected",
2358 audio_mute ? "muted" : "enabled");
2359 if (audio_pll_locked && audio_sample_packet_detect) {
2360 v4l2_info(sd, "Audio format: %s\n",
2361 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2362 }
2363 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2364 (hdmi_read(sd, 0x5c) << 8) +
2365 (hdmi_read(sd, 0x5d) & 0xf0));
2366 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2367 (hdmi_read(sd, 0x5e) << 8) +
2368 hdmi_read(sd, 0x5f));
2369 v4l2_info(sd, "AV Mute: %s\n",
2370 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2371 v4l2_info(sd, "Deep color mode: %s\n",
2372 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2373
2374 adv7842_log_infoframes(sd);
2375
2376 return 0;
2377 }
2378
2379 static int adv7842_log_status(struct v4l2_subdev *sd)
2380 {
2381 struct adv7842_state *state = to_state(sd);
2382
2383 if (state->mode == ADV7842_MODE_SDP)
2384 return adv7842_sdp_log_status(sd);
2385 return adv7842_cp_log_status(sd);
2386 }
2387
2388 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2389 {
2390 struct adv7842_state *state = to_state(sd);
2391
2392 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2393
2394 if (state->mode != ADV7842_MODE_SDP)
2395 return -ENODATA;
2396
2397 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2398 *std = 0;
2399 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2400 return 0;
2401 }
2402
2403 switch (sdp_read(sd, 0x52) & 0x0f) {
2404 case 0:
2405 /* NTSC-M/J */
2406 *std &= V4L2_STD_NTSC;
2407 break;
2408 case 2:
2409 /* NTSC-443 */
2410 *std &= V4L2_STD_NTSC_443;
2411 break;
2412 case 3:
2413 /* 60HzSECAM */
2414 *std &= V4L2_STD_SECAM;
2415 break;
2416 case 4:
2417 /* PAL-M */
2418 *std &= V4L2_STD_PAL_M;
2419 break;
2420 case 6:
2421 /* PAL-60 */
2422 *std &= V4L2_STD_PAL_60;
2423 break;
2424 case 0xc:
2425 /* PAL-CombN */
2426 *std &= V4L2_STD_PAL_Nc;
2427 break;
2428 case 0xe:
2429 /* PAL-BGHID */
2430 *std &= V4L2_STD_PAL;
2431 break;
2432 case 0xf:
2433 /* SECAM */
2434 *std &= V4L2_STD_SECAM;
2435 break;
2436 default:
2437 *std &= V4L2_STD_ALL;
2438 break;
2439 }
2440 return 0;
2441 }
2442
2443 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2444 {
2445 if (s && s->adjust) {
2446 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2447 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2448 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2449 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2450 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2451 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2452 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2453 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2454 sdp_io_write(sd, 0xa8, s->vs_beg_o);
2455 sdp_io_write(sd, 0xa9, s->vs_beg_e);
2456 sdp_io_write(sd, 0xaa, s->vs_end_o);
2457 sdp_io_write(sd, 0xab, s->vs_end_e);
2458 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2459 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2460 sdp_io_write(sd, 0xae, s->de_v_end_o);
2461 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2462 } else {
2463 /* set to default */
2464 sdp_io_write(sd, 0x94, 0x00);
2465 sdp_io_write(sd, 0x95, 0x00);
2466 sdp_io_write(sd, 0x96, 0x00);
2467 sdp_io_write(sd, 0x97, 0x20);
2468 sdp_io_write(sd, 0x98, 0x00);
2469 sdp_io_write(sd, 0x99, 0x00);
2470 sdp_io_write(sd, 0x9a, 0x00);
2471 sdp_io_write(sd, 0x9b, 0x00);
2472 sdp_io_write(sd, 0xa8, 0x04);
2473 sdp_io_write(sd, 0xa9, 0x04);
2474 sdp_io_write(sd, 0xaa, 0x04);
2475 sdp_io_write(sd, 0xab, 0x04);
2476 sdp_io_write(sd, 0xac, 0x04);
2477 sdp_io_write(sd, 0xad, 0x04);
2478 sdp_io_write(sd, 0xae, 0x04);
2479 sdp_io_write(sd, 0xaf, 0x04);
2480 }
2481 }
2482
2483 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2484 {
2485 struct adv7842_state *state = to_state(sd);
2486 struct adv7842_platform_data *pdata = &state->pdata;
2487
2488 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2489
2490 if (state->mode != ADV7842_MODE_SDP)
2491 return -ENODATA;
2492
2493 if (norm & V4L2_STD_625_50)
2494 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2495 else if (norm & V4L2_STD_525_60)
2496 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2497 else
2498 adv7842_s_sdp_io(sd, NULL);
2499
2500 if (norm & V4L2_STD_ALL) {
2501 state->norm = norm;
2502 return 0;
2503 }
2504 return -EINVAL;
2505 }
2506
2507 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2508 {
2509 struct adv7842_state *state = to_state(sd);
2510
2511 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2512
2513 if (state->mode != ADV7842_MODE_SDP)
2514 return -ENODATA;
2515
2516 *norm = state->norm;
2517 return 0;
2518 }
2519
2520 /* ----------------------------------------------------------------------- */
2521
2522 static int adv7842_core_init(struct v4l2_subdev *sd)
2523 {
2524 struct adv7842_state *state = to_state(sd);
2525 struct adv7842_platform_data *pdata = &state->pdata;
2526 hdmi_write(sd, 0x48,
2527 (pdata->disable_pwrdnb ? 0x80 : 0) |
2528 (pdata->disable_cable_det_rst ? 0x40 : 0));
2529
2530 disable_input(sd);
2531
2532 /*
2533 * Disable I2C access to internal EDID ram from HDMI DDC ports
2534 * Disable auto edid enable when leaving powerdown mode
2535 */
2536 rep_write_and_or(sd, 0x77, 0xd3, 0x20);
2537
2538 /* power */
2539 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2540 io_write(sd, 0x15, 0x80); /* Power up pads */
2541
2542 /* video format */
2543 io_write(sd, 0x02,
2544 0xf0 |
2545 pdata->alt_gamma << 3 |
2546 pdata->op_656_range << 2 |
2547 pdata->rgb_out << 1 |
2548 pdata->alt_data_sat << 0);
2549 io_write(sd, 0x03, pdata->op_format_sel);
2550 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2551 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2552 pdata->insert_av_codes << 2 |
2553 pdata->replicate_av_codes << 1 |
2554 pdata->invert_cbcr << 0);
2555
2556 /* HDMI audio */
2557 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2558
2559 /* Drive strength */
2560 io_write_and_or(sd, 0x14, 0xc0,
2561 pdata->dr_str_data << 4 |
2562 pdata->dr_str_clk << 2 |
2563 pdata->dr_str_sync);
2564
2565 /* HDMI free run */
2566 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
2567 (pdata->hdmi_free_run_mode << 1));
2568
2569 /* SPD free run */
2570 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
2571 (pdata->sdp_free_run_cbar_en << 1) |
2572 (pdata->sdp_free_run_man_col_en << 2) |
2573 (pdata->sdp_free_run_auto << 3));
2574
2575 /* TODO from platform data */
2576 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
2577 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
2578 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2579 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2580
2581 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2582 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2583
2584 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
2585
2586 /* todo, improve settings for sdram */
2587 if (pdata->sd_ram_size >= 128) {
2588 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2589 if (pdata->sd_ram_ddr) {
2590 /* SDP setup for the AD eval board */
2591 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
2592 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
2593 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2594 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2595 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2596 } else {
2597 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
2598 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
2599 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
2600 depends on memory */
2601 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
2602 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
2603 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
2604 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
2605 }
2606 } else {
2607 /*
2608 * Manual UG-214, rev 0 is bit confusing on this bit
2609 * but a '1' disables any signal if the Ram is active.
2610 */
2611 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
2612 }
2613
2614 select_input(sd, pdata->vid_std_select);
2615
2616 enable_input(sd);
2617
2618 if (pdata->hpa_auto) {
2619 /* HPA auto, HPA 0.5s after Edid set and Cable detect */
2620 hdmi_write(sd, 0x69, 0x5c);
2621 } else {
2622 /* HPA manual */
2623 hdmi_write(sd, 0x69, 0xa3);
2624 /* HPA disable on port A and B */
2625 io_write_and_or(sd, 0x20, 0xcf, 0x00);
2626 }
2627
2628 /* LLC */
2629 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
2630 io_write(sd, 0x33, 0x40);
2631
2632 /* interrupts */
2633 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
2634
2635 adv7842_irq_enable(sd, true);
2636
2637 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2638 }
2639
2640 /* ----------------------------------------------------------------------- */
2641
2642 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
2643 {
2644 /*
2645 * From ADV784x external Memory test.pdf
2646 *
2647 * Reset must just been performed before running test.
2648 * Recommended to reset after test.
2649 */
2650 int i;
2651 int pass = 0;
2652 int fail = 0;
2653 int complete = 0;
2654
2655 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
2656 io_write(sd, 0x01, 0x00); /* Program SDP mode */
2657 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
2658 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2659 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2660 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2661 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2662 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
2663 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
2664 io_write(sd, 0x15, 0xBA); /* Enable outputs */
2665 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2666 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
2667
2668 mdelay(5);
2669
2670 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
2671 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
2672 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
2673 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
2674 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
2675 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
2676 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
2677 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
2678 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
2679 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
2680 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
2681
2682 mdelay(5);
2683
2684 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
2685 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2686
2687 mdelay(20);
2688
2689 for (i = 0; i < 10; i++) {
2690 u8 result = sdp_io_read(sd, 0xdb);
2691 if (result & 0x10) {
2692 complete++;
2693 if (result & 0x20)
2694 fail++;
2695 else
2696 pass++;
2697 }
2698 mdelay(20);
2699 }
2700
2701 v4l2_dbg(1, debug, sd,
2702 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2703 complete, i, pass, fail);
2704
2705 if (!complete || fail)
2706 return -EIO;
2707 return 0;
2708 }
2709
2710 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
2711 struct adv7842_platform_data *pdata)
2712 {
2713 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
2714 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
2715 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
2716 io_write(sd, 0xf4, pdata->i2c_cec << 1);
2717 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
2718
2719 io_write(sd, 0xf8, pdata->i2c_afe << 1);
2720 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
2721 io_write(sd, 0xfa, pdata->i2c_edid << 1);
2722 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
2723
2724 io_write(sd, 0xfd, pdata->i2c_cp << 1);
2725 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
2726 }
2727
2728 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
2729 {
2730 struct i2c_client *client = v4l2_get_subdevdata(sd);
2731 struct adv7842_state *state = to_state(sd);
2732 struct adv7842_platform_data *pdata = client->dev.platform_data;
2733 struct v4l2_dv_timings timings;
2734 int ret = 0;
2735
2736 if (!pdata)
2737 return -ENODEV;
2738
2739 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
2740 v4l2_info(sd, "no sdram or no ddr sdram\n");
2741 return -EINVAL;
2742 }
2743
2744 main_reset(sd);
2745
2746 adv7842_rewrite_i2c_addresses(sd, pdata);
2747
2748 /* run ram test */
2749 ret = adv7842_ddr_ram_test(sd);
2750
2751 main_reset(sd);
2752
2753 adv7842_rewrite_i2c_addresses(sd, pdata);
2754
2755 /* and re-init chip and state */
2756 adv7842_core_init(sd);
2757
2758 disable_input(sd);
2759
2760 select_input(sd, state->vid_std_select);
2761
2762 enable_input(sd);
2763
2764 edid_write_vga_segment(sd);
2765 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
2766 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
2767
2768 timings = state->timings;
2769
2770 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
2771
2772 adv7842_s_dv_timings(sd, &timings);
2773
2774 return ret;
2775 }
2776
2777 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2778 {
2779 switch (cmd) {
2780 case ADV7842_CMD_RAM_TEST:
2781 return adv7842_command_ram_test(sd);
2782 }
2783 return -ENOTTY;
2784 }
2785
2786 /* ----------------------------------------------------------------------- */
2787
2788 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
2789 .s_ctrl = adv7842_s_ctrl,
2790 };
2791
2792 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
2793 .log_status = adv7842_log_status,
2794 .ioctl = adv7842_ioctl,
2795 .interrupt_service_routine = adv7842_isr,
2796 #ifdef CONFIG_VIDEO_ADV_DEBUG
2797 .g_register = adv7842_g_register,
2798 .s_register = adv7842_s_register,
2799 #endif
2800 };
2801
2802 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
2803 .g_std = adv7842_g_std,
2804 .s_std = adv7842_s_std,
2805 .s_routing = adv7842_s_routing,
2806 .querystd = adv7842_querystd,
2807 .g_input_status = adv7842_g_input_status,
2808 .s_dv_timings = adv7842_s_dv_timings,
2809 .g_dv_timings = adv7842_g_dv_timings,
2810 .query_dv_timings = adv7842_query_dv_timings,
2811 .enum_mbus_fmt = adv7842_enum_mbus_fmt,
2812 .g_mbus_fmt = adv7842_g_mbus_fmt,
2813 .try_mbus_fmt = adv7842_g_mbus_fmt,
2814 .s_mbus_fmt = adv7842_g_mbus_fmt,
2815 };
2816
2817 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
2818 .get_edid = adv7842_get_edid,
2819 .set_edid = adv7842_set_edid,
2820 .enum_dv_timings = adv7842_enum_dv_timings,
2821 .dv_timings_cap = adv7842_dv_timings_cap,
2822 };
2823
2824 static const struct v4l2_subdev_ops adv7842_ops = {
2825 .core = &adv7842_core_ops,
2826 .video = &adv7842_video_ops,
2827 .pad = &adv7842_pad_ops,
2828 };
2829
2830 /* -------------------------- custom ctrls ---------------------------------- */
2831
2832 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
2833 .ops = &adv7842_ctrl_ops,
2834 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2835 .name = "Analog Sampling Phase",
2836 .type = V4L2_CTRL_TYPE_INTEGER,
2837 .min = 0,
2838 .max = 0x1f,
2839 .step = 1,
2840 .def = 0,
2841 };
2842
2843 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
2844 .ops = &adv7842_ctrl_ops,
2845 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2846 .name = "Free Running Color, Manual",
2847 .type = V4L2_CTRL_TYPE_BOOLEAN,
2848 .max = 1,
2849 .step = 1,
2850 .def = 1,
2851 };
2852
2853 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
2854 .ops = &adv7842_ctrl_ops,
2855 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2856 .name = "Free Running Color",
2857 .type = V4L2_CTRL_TYPE_INTEGER,
2858 .max = 0xffffff,
2859 .step = 0x1,
2860 };
2861
2862
2863 static void adv7842_unregister_clients(struct v4l2_subdev *sd)
2864 {
2865 struct adv7842_state *state = to_state(sd);
2866 if (state->i2c_avlink)
2867 i2c_unregister_device(state->i2c_avlink);
2868 if (state->i2c_cec)
2869 i2c_unregister_device(state->i2c_cec);
2870 if (state->i2c_infoframe)
2871 i2c_unregister_device(state->i2c_infoframe);
2872 if (state->i2c_sdp_io)
2873 i2c_unregister_device(state->i2c_sdp_io);
2874 if (state->i2c_sdp)
2875 i2c_unregister_device(state->i2c_sdp);
2876 if (state->i2c_afe)
2877 i2c_unregister_device(state->i2c_afe);
2878 if (state->i2c_repeater)
2879 i2c_unregister_device(state->i2c_repeater);
2880 if (state->i2c_edid)
2881 i2c_unregister_device(state->i2c_edid);
2882 if (state->i2c_hdmi)
2883 i2c_unregister_device(state->i2c_hdmi);
2884 if (state->i2c_cp)
2885 i2c_unregister_device(state->i2c_cp);
2886 if (state->i2c_vdp)
2887 i2c_unregister_device(state->i2c_vdp);
2888
2889 state->i2c_avlink = NULL;
2890 state->i2c_cec = NULL;
2891 state->i2c_infoframe = NULL;
2892 state->i2c_sdp_io = NULL;
2893 state->i2c_sdp = NULL;
2894 state->i2c_afe = NULL;
2895 state->i2c_repeater = NULL;
2896 state->i2c_edid = NULL;
2897 state->i2c_hdmi = NULL;
2898 state->i2c_cp = NULL;
2899 state->i2c_vdp = NULL;
2900 }
2901
2902 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
2903 u8 addr, u8 io_reg)
2904 {
2905 struct i2c_client *client = v4l2_get_subdevdata(sd);
2906 struct i2c_client *cp;
2907
2908 io_write(sd, io_reg, addr << 1);
2909
2910 if (addr == 0) {
2911 v4l2_err(sd, "no %s i2c addr configured\n", desc);
2912 return NULL;
2913 }
2914
2915 cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2916 if (!cp)
2917 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr);
2918
2919 return cp;
2920 }
2921
2922 static int adv7842_register_clients(struct v4l2_subdev *sd)
2923 {
2924 struct adv7842_state *state = to_state(sd);
2925 struct adv7842_platform_data *pdata = &state->pdata;
2926
2927 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
2928 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
2929 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
2930 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
2931 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
2932 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
2933 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
2934 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
2935 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
2936 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
2937 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
2938
2939 if (!state->i2c_avlink ||
2940 !state->i2c_cec ||
2941 !state->i2c_infoframe ||
2942 !state->i2c_sdp_io ||
2943 !state->i2c_sdp ||
2944 !state->i2c_afe ||
2945 !state->i2c_repeater ||
2946 !state->i2c_edid ||
2947 !state->i2c_hdmi ||
2948 !state->i2c_cp ||
2949 !state->i2c_vdp)
2950 return -1;
2951
2952 return 0;
2953 }
2954
2955 static int adv7842_probe(struct i2c_client *client,
2956 const struct i2c_device_id *id)
2957 {
2958 struct adv7842_state *state;
2959 static const struct v4l2_dv_timings cea640x480 =
2960 V4L2_DV_BT_CEA_640X480P59_94;
2961 struct adv7842_platform_data *pdata = client->dev.platform_data;
2962 struct v4l2_ctrl_handler *hdl;
2963 struct v4l2_subdev *sd;
2964 u16 rev;
2965 int err;
2966
2967 /* Check if the adapter supports the needed features */
2968 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2969 return -EIO;
2970
2971 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
2972 client->addr << 1);
2973
2974 if (!pdata) {
2975 v4l_err(client, "No platform data!\n");
2976 return -ENODEV;
2977 }
2978
2979 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
2980 if (!state) {
2981 v4l_err(client, "Could not allocate adv7842_state memory!\n");
2982 return -ENOMEM;
2983 }
2984
2985 /* platform data */
2986 state->pdata = *pdata;
2987 state->timings = cea640x480;
2988
2989 sd = &state->sd;
2990 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
2991 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2992 state->mode = pdata->mode;
2993
2994 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
2995 state->restart_stdi_once = true;
2996
2997 /* i2c access to adv7842? */
2998 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
2999 adv_smbus_read_byte_data_check(client, 0xeb, false);
3000 if (rev != 0x2012) {
3001 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
3002 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3003 adv_smbus_read_byte_data_check(client, 0xeb, false);
3004 }
3005 if (rev != 0x2012) {
3006 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3007 client->addr << 1, rev);
3008 return -ENODEV;
3009 }
3010
3011 if (pdata->chip_reset)
3012 main_reset(sd);
3013
3014 /* control handlers */
3015 hdl = &state->hdl;
3016 v4l2_ctrl_handler_init(hdl, 6);
3017
3018 /* add in ascending ID order */
3019 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3020 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3021 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3022 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3023 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3024 V4L2_CID_SATURATION, 0, 255, 1, 128);
3025 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3026 V4L2_CID_HUE, 0, 128, 1, 0);
3027
3028 /* custom controls */
3029 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3030 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
3031 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
3032 &adv7842_ctrl_analog_sampling_phase, NULL);
3033 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
3034 &adv7842_ctrl_free_run_color_manual, NULL);
3035 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
3036 &adv7842_ctrl_free_run_color, NULL);
3037 state->rgb_quantization_range_ctrl =
3038 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3039 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3040 0, V4L2_DV_RGB_RANGE_AUTO);
3041 sd->ctrl_handler = hdl;
3042 if (hdl->error) {
3043 err = hdl->error;
3044 goto err_hdl;
3045 }
3046 state->detect_tx_5v_ctrl->is_private = true;
3047 state->rgb_quantization_range_ctrl->is_private = true;
3048 state->analog_sampling_phase_ctrl->is_private = true;
3049 state->free_run_color_ctrl_manual->is_private = true;
3050 state->free_run_color_ctrl->is_private = true;
3051
3052 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3053 err = -ENODEV;
3054 goto err_hdl;
3055 }
3056
3057 if (adv7842_register_clients(sd) < 0) {
3058 err = -ENOMEM;
3059 v4l2_err(sd, "failed to create all i2c clients\n");
3060 goto err_i2c;
3061 }
3062
3063 /* work queues */
3064 state->work_queues = create_singlethread_workqueue(client->name);
3065 if (!state->work_queues) {
3066 v4l2_err(sd, "Could not create work queue\n");
3067 err = -ENOMEM;
3068 goto err_i2c;
3069 }
3070
3071 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3072 adv7842_delayed_work_enable_hotplug);
3073
3074 state->pad.flags = MEDIA_PAD_FL_SOURCE;
3075 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
3076 if (err)
3077 goto err_work_queues;
3078
3079 err = adv7842_core_init(sd);
3080 if (err)
3081 goto err_entity;
3082
3083 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3084 client->addr << 1, client->adapter->name);
3085 return 0;
3086
3087 err_entity:
3088 media_entity_cleanup(&sd->entity);
3089 err_work_queues:
3090 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3091 destroy_workqueue(state->work_queues);
3092 err_i2c:
3093 adv7842_unregister_clients(sd);
3094 err_hdl:
3095 v4l2_ctrl_handler_free(hdl);
3096 return err;
3097 }
3098
3099 /* ----------------------------------------------------------------------- */
3100
3101 static int adv7842_remove(struct i2c_client *client)
3102 {
3103 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3104 struct adv7842_state *state = to_state(sd);
3105
3106 adv7842_irq_enable(sd, false);
3107
3108 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3109 destroy_workqueue(state->work_queues);
3110 v4l2_device_unregister_subdev(sd);
3111 media_entity_cleanup(&sd->entity);
3112 adv7842_unregister_clients(sd);
3113 v4l2_ctrl_handler_free(sd->ctrl_handler);
3114 return 0;
3115 }
3116
3117 /* ----------------------------------------------------------------------- */
3118
3119 static struct i2c_device_id adv7842_id[] = {
3120 { "adv7842", 0 },
3121 { }
3122 };
3123 MODULE_DEVICE_TABLE(i2c, adv7842_id);
3124
3125 /* ----------------------------------------------------------------------- */
3126
3127 static struct i2c_driver adv7842_driver = {
3128 .driver = {
3129 .owner = THIS_MODULE,
3130 .name = "adv7842",
3131 },
3132 .probe = adv7842_probe,
3133 .remove = adv7842_remove,
3134 .id_table = adv7842_id,
3135 };
3136
3137 module_i2c_driver(adv7842_driver);
Linux kernel - Deliverables
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