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[deliverable/linux.git] / drivers / media / i2c / mt9p031.c
1 /*
2 * Driver for MT9P031 CMOS Image Sensor from Aptina
3 *
4 * Copyright (C) 2011, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
5 * Copyright (C) 2011, Javier Martin <javier.martin@vista-silicon.com>
6 * Copyright (C) 2011, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7 *
8 * Based on the MT9V032 driver and Bastian Hecht's code.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <linux/gpio.h>
18 #include <linux/module.h>
19 #include <linux/i2c.h>
20 #include <linux/log2.h>
21 #include <linux/pm.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/videodev2.h>
25
26 #include <media/mt9p031.h>
27 #include <media/v4l2-chip-ident.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-subdev.h>
31
32 #include "aptina-pll.h"
33
34 #define MT9P031_PIXEL_ARRAY_WIDTH 2752
35 #define MT9P031_PIXEL_ARRAY_HEIGHT 2004
36
37 #define MT9P031_CHIP_VERSION 0x00
38 #define MT9P031_CHIP_VERSION_VALUE 0x1801
39 #define MT9P031_ROW_START 0x01
40 #define MT9P031_ROW_START_MIN 0
41 #define MT9P031_ROW_START_MAX 2004
42 #define MT9P031_ROW_START_DEF 54
43 #define MT9P031_COLUMN_START 0x02
44 #define MT9P031_COLUMN_START_MIN 0
45 #define MT9P031_COLUMN_START_MAX 2750
46 #define MT9P031_COLUMN_START_DEF 16
47 #define MT9P031_WINDOW_HEIGHT 0x03
48 #define MT9P031_WINDOW_HEIGHT_MIN 2
49 #define MT9P031_WINDOW_HEIGHT_MAX 2006
50 #define MT9P031_WINDOW_HEIGHT_DEF 1944
51 #define MT9P031_WINDOW_WIDTH 0x04
52 #define MT9P031_WINDOW_WIDTH_MIN 2
53 #define MT9P031_WINDOW_WIDTH_MAX 2752
54 #define MT9P031_WINDOW_WIDTH_DEF 2592
55 #define MT9P031_HORIZONTAL_BLANK 0x05
56 #define MT9P031_HORIZONTAL_BLANK_MIN 0
57 #define MT9P031_HORIZONTAL_BLANK_MAX 4095
58 #define MT9P031_VERTICAL_BLANK 0x06
59 #define MT9P031_VERTICAL_BLANK_MIN 1
60 #define MT9P031_VERTICAL_BLANK_MAX 4096
61 #define MT9P031_VERTICAL_BLANK_DEF 26
62 #define MT9P031_OUTPUT_CONTROL 0x07
63 #define MT9P031_OUTPUT_CONTROL_CEN 2
64 #define MT9P031_OUTPUT_CONTROL_SYN 1
65 #define MT9P031_OUTPUT_CONTROL_DEF 0x1f82
66 #define MT9P031_SHUTTER_WIDTH_UPPER 0x08
67 #define MT9P031_SHUTTER_WIDTH_LOWER 0x09
68 #define MT9P031_SHUTTER_WIDTH_MIN 1
69 #define MT9P031_SHUTTER_WIDTH_MAX 1048575
70 #define MT9P031_SHUTTER_WIDTH_DEF 1943
71 #define MT9P031_PLL_CONTROL 0x10
72 #define MT9P031_PLL_CONTROL_PWROFF 0x0050
73 #define MT9P031_PLL_CONTROL_PWRON 0x0051
74 #define MT9P031_PLL_CONTROL_USEPLL 0x0052
75 #define MT9P031_PLL_CONFIG_1 0x11
76 #define MT9P031_PLL_CONFIG_2 0x12
77 #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a
78 #define MT9P031_FRAME_RESTART 0x0b
79 #define MT9P031_SHUTTER_DELAY 0x0c
80 #define MT9P031_RST 0x0d
81 #define MT9P031_RST_ENABLE 1
82 #define MT9P031_RST_DISABLE 0
83 #define MT9P031_READ_MODE_1 0x1e
84 #define MT9P031_READ_MODE_2 0x20
85 #define MT9P031_READ_MODE_2_ROW_MIR (1 << 15)
86 #define MT9P031_READ_MODE_2_COL_MIR (1 << 14)
87 #define MT9P031_READ_MODE_2_ROW_BLC (1 << 6)
88 #define MT9P031_ROW_ADDRESS_MODE 0x22
89 #define MT9P031_COLUMN_ADDRESS_MODE 0x23
90 #define MT9P031_GLOBAL_GAIN 0x35
91 #define MT9P031_GLOBAL_GAIN_MIN 8
92 #define MT9P031_GLOBAL_GAIN_MAX 1024
93 #define MT9P031_GLOBAL_GAIN_DEF 8
94 #define MT9P031_GLOBAL_GAIN_MULT (1 << 6)
95 #define MT9P031_ROW_BLACK_TARGET 0x49
96 #define MT9P031_ROW_BLACK_DEF_OFFSET 0x4b
97 #define MT9P031_GREEN1_OFFSET 0x60
98 #define MT9P031_GREEN2_OFFSET 0x61
99 #define MT9P031_BLACK_LEVEL_CALIBRATION 0x62
100 #define MT9P031_BLC_MANUAL_BLC (1 << 0)
101 #define MT9P031_RED_OFFSET 0x63
102 #define MT9P031_BLUE_OFFSET 0x64
103 #define MT9P031_TEST_PATTERN 0xa0
104 #define MT9P031_TEST_PATTERN_SHIFT 3
105 #define MT9P031_TEST_PATTERN_ENABLE (1 << 0)
106 #define MT9P031_TEST_PATTERN_DISABLE (0 << 0)
107 #define MT9P031_TEST_PATTERN_GREEN 0xa1
108 #define MT9P031_TEST_PATTERN_RED 0xa2
109 #define MT9P031_TEST_PATTERN_BLUE 0xa3
110
111 enum mt9p031_model {
112 MT9P031_MODEL_COLOR,
113 MT9P031_MODEL_MONOCHROME,
114 };
115
116 struct mt9p031 {
117 struct v4l2_subdev subdev;
118 struct media_pad pad;
119 struct v4l2_rect crop; /* Sensor window */
120 struct v4l2_mbus_framefmt format;
121 struct mt9p031_platform_data *pdata;
122 struct mutex power_lock; /* lock to protect power_count */
123 int power_count;
124
125 struct regulator *vaa;
126 struct regulator *vdd;
127 struct regulator *vdd_io;
128
129 enum mt9p031_model model;
130 struct aptina_pll pll;
131 int reset;
132
133 struct v4l2_ctrl_handler ctrls;
134 struct v4l2_ctrl *blc_auto;
135 struct v4l2_ctrl *blc_offset;
136
137 /* Registers cache */
138 u16 output_control;
139 u16 mode2;
140 };
141
142 static struct mt9p031 *to_mt9p031(struct v4l2_subdev *sd)
143 {
144 return container_of(sd, struct mt9p031, subdev);
145 }
146
147 static int mt9p031_read(struct i2c_client *client, u8 reg)
148 {
149 return i2c_smbus_read_word_swapped(client, reg);
150 }
151
152 static int mt9p031_write(struct i2c_client *client, u8 reg, u16 data)
153 {
154 return i2c_smbus_write_word_swapped(client, reg, data);
155 }
156
157 static int mt9p031_set_output_control(struct mt9p031 *mt9p031, u16 clear,
158 u16 set)
159 {
160 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
161 u16 value = (mt9p031->output_control & ~clear) | set;
162 int ret;
163
164 ret = mt9p031_write(client, MT9P031_OUTPUT_CONTROL, value);
165 if (ret < 0)
166 return ret;
167
168 mt9p031->output_control = value;
169 return 0;
170 }
171
172 static int mt9p031_set_mode2(struct mt9p031 *mt9p031, u16 clear, u16 set)
173 {
174 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
175 u16 value = (mt9p031->mode2 & ~clear) | set;
176 int ret;
177
178 ret = mt9p031_write(client, MT9P031_READ_MODE_2, value);
179 if (ret < 0)
180 return ret;
181
182 mt9p031->mode2 = value;
183 return 0;
184 }
185
186 static int mt9p031_reset(struct mt9p031 *mt9p031)
187 {
188 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
189 int ret;
190
191 /* Disable chip output, synchronous option update */
192 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_ENABLE);
193 if (ret < 0)
194 return ret;
195 ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_DISABLE);
196 if (ret < 0)
197 return ret;
198
199 return mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN,
200 0);
201 }
202
203 static int mt9p031_pll_setup(struct mt9p031 *mt9p031)
204 {
205 static const struct aptina_pll_limits limits = {
206 .ext_clock_min = 6000000,
207 .ext_clock_max = 27000000,
208 .int_clock_min = 2000000,
209 .int_clock_max = 13500000,
210 .out_clock_min = 180000000,
211 .out_clock_max = 360000000,
212 .pix_clock_max = 96000000,
213 .n_min = 1,
214 .n_max = 64,
215 .m_min = 16,
216 .m_max = 255,
217 .p1_min = 1,
218 .p1_max = 128,
219 };
220
221 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
222 struct mt9p031_platform_data *pdata = mt9p031->pdata;
223
224 mt9p031->pll.ext_clock = pdata->ext_freq;
225 mt9p031->pll.pix_clock = pdata->target_freq;
226
227 return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll);
228 }
229
230 static int mt9p031_pll_enable(struct mt9p031 *mt9p031)
231 {
232 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
233 int ret;
234
235 ret = mt9p031_write(client, MT9P031_PLL_CONTROL,
236 MT9P031_PLL_CONTROL_PWRON);
237 if (ret < 0)
238 return ret;
239
240 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_1,
241 (mt9p031->pll.m << 8) | (mt9p031->pll.n - 1));
242 if (ret < 0)
243 return ret;
244
245 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_2, mt9p031->pll.p1 - 1);
246 if (ret < 0)
247 return ret;
248
249 usleep_range(1000, 2000);
250 ret = mt9p031_write(client, MT9P031_PLL_CONTROL,
251 MT9P031_PLL_CONTROL_PWRON |
252 MT9P031_PLL_CONTROL_USEPLL);
253 return ret;
254 }
255
256 static inline int mt9p031_pll_disable(struct mt9p031 *mt9p031)
257 {
258 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
259
260 return mt9p031_write(client, MT9P031_PLL_CONTROL,
261 MT9P031_PLL_CONTROL_PWROFF);
262 }
263
264 static int mt9p031_power_on(struct mt9p031 *mt9p031)
265 {
266 /* Ensure RESET_BAR is low */
267 if (mt9p031->reset != -1) {
268 gpio_set_value(mt9p031->reset, 0);
269 usleep_range(1000, 2000);
270 }
271
272 /* Bring up the supplies */
273 regulator_enable(mt9p031->vdd);
274 regulator_enable(mt9p031->vdd_io);
275 regulator_enable(mt9p031->vaa);
276
277 /* Emable clock */
278 if (mt9p031->pdata->set_xclk)
279 mt9p031->pdata->set_xclk(&mt9p031->subdev,
280 mt9p031->pdata->ext_freq);
281
282 /* Now RESET_BAR must be high */
283 if (mt9p031->reset != -1) {
284 gpio_set_value(mt9p031->reset, 1);
285 usleep_range(1000, 2000);
286 }
287
288 return 0;
289 }
290
291 static void mt9p031_power_off(struct mt9p031 *mt9p031)
292 {
293 if (mt9p031->reset != -1) {
294 gpio_set_value(mt9p031->reset, 0);
295 usleep_range(1000, 2000);
296 }
297
298 regulator_disable(mt9p031->vaa);
299 regulator_disable(mt9p031->vdd_io);
300 regulator_disable(mt9p031->vdd);
301
302 if (mt9p031->pdata->set_xclk)
303 mt9p031->pdata->set_xclk(&mt9p031->subdev, 0);
304 }
305
306 static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on)
307 {
308 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
309 int ret;
310
311 if (!on) {
312 mt9p031_power_off(mt9p031);
313 return 0;
314 }
315
316 ret = mt9p031_power_on(mt9p031);
317 if (ret < 0)
318 return ret;
319
320 ret = mt9p031_reset(mt9p031);
321 if (ret < 0) {
322 dev_err(&client->dev, "Failed to reset the camera\n");
323 return ret;
324 }
325
326 return v4l2_ctrl_handler_setup(&mt9p031->ctrls);
327 }
328
329 /* -----------------------------------------------------------------------------
330 * V4L2 subdev video operations
331 */
332
333 static int mt9p031_set_params(struct mt9p031 *mt9p031)
334 {
335 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
336 struct v4l2_mbus_framefmt *format = &mt9p031->format;
337 const struct v4l2_rect *crop = &mt9p031->crop;
338 unsigned int hblank;
339 unsigned int vblank;
340 unsigned int xskip;
341 unsigned int yskip;
342 unsigned int xbin;
343 unsigned int ybin;
344 int ret;
345
346 /* Windows position and size.
347 *
348 * TODO: Make sure the start coordinates and window size match the
349 * skipping, binning and mirroring (see description of registers 2 and 4
350 * in table 13, and Binning section on page 41).
351 */
352 ret = mt9p031_write(client, MT9P031_COLUMN_START, crop->left);
353 if (ret < 0)
354 return ret;
355 ret = mt9p031_write(client, MT9P031_ROW_START, crop->top);
356 if (ret < 0)
357 return ret;
358 ret = mt9p031_write(client, MT9P031_WINDOW_WIDTH, crop->width - 1);
359 if (ret < 0)
360 return ret;
361 ret = mt9p031_write(client, MT9P031_WINDOW_HEIGHT, crop->height - 1);
362 if (ret < 0)
363 return ret;
364
365 /* Row and column binning and skipping. Use the maximum binning value
366 * compatible with the skipping settings.
367 */
368 xskip = DIV_ROUND_CLOSEST(crop->width, format->width);
369 yskip = DIV_ROUND_CLOSEST(crop->height, format->height);
370 xbin = 1 << (ffs(xskip) - 1);
371 ybin = 1 << (ffs(yskip) - 1);
372
373 ret = mt9p031_write(client, MT9P031_COLUMN_ADDRESS_MODE,
374 ((xbin - 1) << 4) | (xskip - 1));
375 if (ret < 0)
376 return ret;
377 ret = mt9p031_write(client, MT9P031_ROW_ADDRESS_MODE,
378 ((ybin - 1) << 4) | (yskip - 1));
379 if (ret < 0)
380 return ret;
381
382 /* Blanking - use minimum value for horizontal blanking and default
383 * value for vertical blanking.
384 */
385 hblank = 346 * ybin + 64 + (80 >> min_t(unsigned int, xbin, 3));
386 vblank = MT9P031_VERTICAL_BLANK_DEF;
387
388 ret = mt9p031_write(client, MT9P031_HORIZONTAL_BLANK, hblank - 1);
389 if (ret < 0)
390 return ret;
391 ret = mt9p031_write(client, MT9P031_VERTICAL_BLANK, vblank - 1);
392 if (ret < 0)
393 return ret;
394
395 return ret;
396 }
397
398 static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable)
399 {
400 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
401 int ret;
402
403 if (!enable) {
404 /* Stop sensor readout */
405 ret = mt9p031_set_output_control(mt9p031,
406 MT9P031_OUTPUT_CONTROL_CEN, 0);
407 if (ret < 0)
408 return ret;
409
410 return mt9p031_pll_disable(mt9p031);
411 }
412
413 ret = mt9p031_set_params(mt9p031);
414 if (ret < 0)
415 return ret;
416
417 /* Switch to master "normal" mode */
418 ret = mt9p031_set_output_control(mt9p031, 0,
419 MT9P031_OUTPUT_CONTROL_CEN);
420 if (ret < 0)
421 return ret;
422
423 return mt9p031_pll_enable(mt9p031);
424 }
425
426 static int mt9p031_enum_mbus_code(struct v4l2_subdev *subdev,
427 struct v4l2_subdev_fh *fh,
428 struct v4l2_subdev_mbus_code_enum *code)
429 {
430 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
431
432 if (code->pad || code->index)
433 return -EINVAL;
434
435 code->code = mt9p031->format.code;
436 return 0;
437 }
438
439 static int mt9p031_enum_frame_size(struct v4l2_subdev *subdev,
440 struct v4l2_subdev_fh *fh,
441 struct v4l2_subdev_frame_size_enum *fse)
442 {
443 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
444
445 if (fse->index >= 8 || fse->code != mt9p031->format.code)
446 return -EINVAL;
447
448 fse->min_width = MT9P031_WINDOW_WIDTH_DEF
449 / min_t(unsigned int, 7, fse->index + 1);
450 fse->max_width = fse->min_width;
451 fse->min_height = MT9P031_WINDOW_HEIGHT_DEF / (fse->index + 1);
452 fse->max_height = fse->min_height;
453
454 return 0;
455 }
456
457 static struct v4l2_mbus_framefmt *
458 __mt9p031_get_pad_format(struct mt9p031 *mt9p031, struct v4l2_subdev_fh *fh,
459 unsigned int pad, u32 which)
460 {
461 switch (which) {
462 case V4L2_SUBDEV_FORMAT_TRY:
463 return v4l2_subdev_get_try_format(fh, pad);
464 case V4L2_SUBDEV_FORMAT_ACTIVE:
465 return &mt9p031->format;
466 default:
467 return NULL;
468 }
469 }
470
471 static struct v4l2_rect *
472 __mt9p031_get_pad_crop(struct mt9p031 *mt9p031, struct v4l2_subdev_fh *fh,
473 unsigned int pad, u32 which)
474 {
475 switch (which) {
476 case V4L2_SUBDEV_FORMAT_TRY:
477 return v4l2_subdev_get_try_crop(fh, pad);
478 case V4L2_SUBDEV_FORMAT_ACTIVE:
479 return &mt9p031->crop;
480 default:
481 return NULL;
482 }
483 }
484
485 static int mt9p031_get_format(struct v4l2_subdev *subdev,
486 struct v4l2_subdev_fh *fh,
487 struct v4l2_subdev_format *fmt)
488 {
489 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
490
491 fmt->format = *__mt9p031_get_pad_format(mt9p031, fh, fmt->pad,
492 fmt->which);
493 return 0;
494 }
495
496 static int mt9p031_set_format(struct v4l2_subdev *subdev,
497 struct v4l2_subdev_fh *fh,
498 struct v4l2_subdev_format *format)
499 {
500 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
501 struct v4l2_mbus_framefmt *__format;
502 struct v4l2_rect *__crop;
503 unsigned int width;
504 unsigned int height;
505 unsigned int hratio;
506 unsigned int vratio;
507
508 __crop = __mt9p031_get_pad_crop(mt9p031, fh, format->pad,
509 format->which);
510
511 /* Clamp the width and height to avoid dividing by zero. */
512 width = clamp_t(unsigned int, ALIGN(format->format.width, 2),
513 max(__crop->width / 7, MT9P031_WINDOW_WIDTH_MIN),
514 __crop->width);
515 height = clamp_t(unsigned int, ALIGN(format->format.height, 2),
516 max(__crop->height / 8, MT9P031_WINDOW_HEIGHT_MIN),
517 __crop->height);
518
519 hratio = DIV_ROUND_CLOSEST(__crop->width, width);
520 vratio = DIV_ROUND_CLOSEST(__crop->height, height);
521
522 __format = __mt9p031_get_pad_format(mt9p031, fh, format->pad,
523 format->which);
524 __format->width = __crop->width / hratio;
525 __format->height = __crop->height / vratio;
526
527 format->format = *__format;
528
529 return 0;
530 }
531
532 static int mt9p031_get_crop(struct v4l2_subdev *subdev,
533 struct v4l2_subdev_fh *fh,
534 struct v4l2_subdev_crop *crop)
535 {
536 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
537
538 crop->rect = *__mt9p031_get_pad_crop(mt9p031, fh, crop->pad,
539 crop->which);
540 return 0;
541 }
542
543 static int mt9p031_set_crop(struct v4l2_subdev *subdev,
544 struct v4l2_subdev_fh *fh,
545 struct v4l2_subdev_crop *crop)
546 {
547 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
548 struct v4l2_mbus_framefmt *__format;
549 struct v4l2_rect *__crop;
550 struct v4l2_rect rect;
551
552 /* Clamp the crop rectangle boundaries and align them to a multiple of 2
553 * pixels to ensure a GRBG Bayer pattern.
554 */
555 rect.left = clamp(ALIGN(crop->rect.left, 2), MT9P031_COLUMN_START_MIN,
556 MT9P031_COLUMN_START_MAX);
557 rect.top = clamp(ALIGN(crop->rect.top, 2), MT9P031_ROW_START_MIN,
558 MT9P031_ROW_START_MAX);
559 rect.width = clamp(ALIGN(crop->rect.width, 2),
560 MT9P031_WINDOW_WIDTH_MIN,
561 MT9P031_WINDOW_WIDTH_MAX);
562 rect.height = clamp(ALIGN(crop->rect.height, 2),
563 MT9P031_WINDOW_HEIGHT_MIN,
564 MT9P031_WINDOW_HEIGHT_MAX);
565
566 rect.width = min(rect.width, MT9P031_PIXEL_ARRAY_WIDTH - rect.left);
567 rect.height = min(rect.height, MT9P031_PIXEL_ARRAY_HEIGHT - rect.top);
568
569 __crop = __mt9p031_get_pad_crop(mt9p031, fh, crop->pad, crop->which);
570
571 if (rect.width != __crop->width || rect.height != __crop->height) {
572 /* Reset the output image size if the crop rectangle size has
573 * been modified.
574 */
575 __format = __mt9p031_get_pad_format(mt9p031, fh, crop->pad,
576 crop->which);
577 __format->width = rect.width;
578 __format->height = rect.height;
579 }
580
581 *__crop = rect;
582 crop->rect = rect;
583
584 return 0;
585 }
586
587 /* -----------------------------------------------------------------------------
588 * V4L2 subdev control operations
589 */
590
591 #define V4L2_CID_BLC_AUTO (V4L2_CID_USER_BASE | 0x1002)
592 #define V4L2_CID_BLC_TARGET_LEVEL (V4L2_CID_USER_BASE | 0x1003)
593 #define V4L2_CID_BLC_ANALOG_OFFSET (V4L2_CID_USER_BASE | 0x1004)
594 #define V4L2_CID_BLC_DIGITAL_OFFSET (V4L2_CID_USER_BASE | 0x1005)
595
596 static int mt9p031_s_ctrl(struct v4l2_ctrl *ctrl)
597 {
598 struct mt9p031 *mt9p031 =
599 container_of(ctrl->handler, struct mt9p031, ctrls);
600 struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
601 u16 data;
602 int ret;
603
604 switch (ctrl->id) {
605 case V4L2_CID_EXPOSURE:
606 ret = mt9p031_write(client, MT9P031_SHUTTER_WIDTH_UPPER,
607 (ctrl->val >> 16) & 0xffff);
608 if (ret < 0)
609 return ret;
610
611 return mt9p031_write(client, MT9P031_SHUTTER_WIDTH_LOWER,
612 ctrl->val & 0xffff);
613
614 case V4L2_CID_GAIN:
615 /* Gain is controlled by 2 analog stages and a digital stage.
616 * Valid values for the 3 stages are
617 *
618 * Stage Min Max Step
619 * ------------------------------------------
620 * First analog stage x1 x2 1
621 * Second analog stage x1 x4 0.125
622 * Digital stage x1 x16 0.125
623 *
624 * To minimize noise, the gain stages should be used in the
625 * second analog stage, first analog stage, digital stage order.
626 * Gain from a previous stage should be pushed to its maximum
627 * value before the next stage is used.
628 */
629 if (ctrl->val <= 32) {
630 data = ctrl->val;
631 } else if (ctrl->val <= 64) {
632 ctrl->val &= ~1;
633 data = (1 << 6) | (ctrl->val >> 1);
634 } else {
635 ctrl->val &= ~7;
636 data = ((ctrl->val - 64) << 5) | (1 << 6) | 32;
637 }
638
639 return mt9p031_write(client, MT9P031_GLOBAL_GAIN, data);
640
641 case V4L2_CID_HFLIP:
642 if (ctrl->val)
643 return mt9p031_set_mode2(mt9p031,
644 0, MT9P031_READ_MODE_2_COL_MIR);
645 else
646 return mt9p031_set_mode2(mt9p031,
647 MT9P031_READ_MODE_2_COL_MIR, 0);
648
649 case V4L2_CID_VFLIP:
650 if (ctrl->val)
651 return mt9p031_set_mode2(mt9p031,
652 0, MT9P031_READ_MODE_2_ROW_MIR);
653 else
654 return mt9p031_set_mode2(mt9p031,
655 MT9P031_READ_MODE_2_ROW_MIR, 0);
656
657 case V4L2_CID_TEST_PATTERN:
658 if (!ctrl->val) {
659 /* Restore the black level compensation settings. */
660 if (mt9p031->blc_auto->cur.val != 0) {
661 ret = mt9p031_s_ctrl(mt9p031->blc_auto);
662 if (ret < 0)
663 return ret;
664 }
665 if (mt9p031->blc_offset->cur.val != 0) {
666 ret = mt9p031_s_ctrl(mt9p031->blc_offset);
667 if (ret < 0)
668 return ret;
669 }
670 return mt9p031_write(client, MT9P031_TEST_PATTERN,
671 MT9P031_TEST_PATTERN_DISABLE);
672 }
673
674 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_GREEN, 0x05a0);
675 if (ret < 0)
676 return ret;
677 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_RED, 0x0a50);
678 if (ret < 0)
679 return ret;
680 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_BLUE, 0x0aa0);
681 if (ret < 0)
682 return ret;
683
684 /* Disable digital black level compensation when using a test
685 * pattern.
686 */
687 ret = mt9p031_set_mode2(mt9p031, MT9P031_READ_MODE_2_ROW_BLC,
688 0);
689 if (ret < 0)
690 return ret;
691
692 ret = mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 0);
693 if (ret < 0)
694 return ret;
695
696 return mt9p031_write(client, MT9P031_TEST_PATTERN,
697 ((ctrl->val - 1) << MT9P031_TEST_PATTERN_SHIFT)
698 | MT9P031_TEST_PATTERN_ENABLE);
699
700 case V4L2_CID_BLC_AUTO:
701 ret = mt9p031_set_mode2(mt9p031,
702 ctrl->val ? 0 : MT9P031_READ_MODE_2_ROW_BLC,
703 ctrl->val ? MT9P031_READ_MODE_2_ROW_BLC : 0);
704 if (ret < 0)
705 return ret;
706
707 return mt9p031_write(client, MT9P031_BLACK_LEVEL_CALIBRATION,
708 ctrl->val ? 0 : MT9P031_BLC_MANUAL_BLC);
709
710 case V4L2_CID_BLC_TARGET_LEVEL:
711 return mt9p031_write(client, MT9P031_ROW_BLACK_TARGET,
712 ctrl->val);
713
714 case V4L2_CID_BLC_ANALOG_OFFSET:
715 data = ctrl->val & ((1 << 9) - 1);
716
717 ret = mt9p031_write(client, MT9P031_GREEN1_OFFSET, data);
718 if (ret < 0)
719 return ret;
720 ret = mt9p031_write(client, MT9P031_GREEN2_OFFSET, data);
721 if (ret < 0)
722 return ret;
723 ret = mt9p031_write(client, MT9P031_RED_OFFSET, data);
724 if (ret < 0)
725 return ret;
726 return mt9p031_write(client, MT9P031_BLUE_OFFSET, data);
727
728 case V4L2_CID_BLC_DIGITAL_OFFSET:
729 return mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET,
730 ctrl->val & ((1 << 12) - 1));
731 }
732
733 return 0;
734 }
735
736 static struct v4l2_ctrl_ops mt9p031_ctrl_ops = {
737 .s_ctrl = mt9p031_s_ctrl,
738 };
739
740 static const char * const mt9p031_test_pattern_menu[] = {
741 "Disabled",
742 "Color Field",
743 "Horizontal Gradient",
744 "Vertical Gradient",
745 "Diagonal Gradient",
746 "Classic Test Pattern",
747 "Walking 1s",
748 "Monochrome Horizontal Bars",
749 "Monochrome Vertical Bars",
750 "Vertical Color Bars",
751 };
752
753 static const struct v4l2_ctrl_config mt9p031_ctrls[] = {
754 {
755 .ops = &mt9p031_ctrl_ops,
756 .id = V4L2_CID_BLC_AUTO,
757 .type = V4L2_CTRL_TYPE_BOOLEAN,
758 .name = "BLC, Auto",
759 .min = 0,
760 .max = 1,
761 .step = 1,
762 .def = 1,
763 .flags = 0,
764 }, {
765 .ops = &mt9p031_ctrl_ops,
766 .id = V4L2_CID_BLC_TARGET_LEVEL,
767 .type = V4L2_CTRL_TYPE_INTEGER,
768 .name = "BLC Target Level",
769 .min = 0,
770 .max = 4095,
771 .step = 1,
772 .def = 168,
773 .flags = 0,
774 }, {
775 .ops = &mt9p031_ctrl_ops,
776 .id = V4L2_CID_BLC_ANALOG_OFFSET,
777 .type = V4L2_CTRL_TYPE_INTEGER,
778 .name = "BLC Analog Offset",
779 .min = -255,
780 .max = 255,
781 .step = 1,
782 .def = 32,
783 .flags = 0,
784 }, {
785 .ops = &mt9p031_ctrl_ops,
786 .id = V4L2_CID_BLC_DIGITAL_OFFSET,
787 .type = V4L2_CTRL_TYPE_INTEGER,
788 .name = "BLC Digital Offset",
789 .min = -2048,
790 .max = 2047,
791 .step = 1,
792 .def = 40,
793 .flags = 0,
794 }
795 };
796
797 /* -----------------------------------------------------------------------------
798 * V4L2 subdev core operations
799 */
800
801 static int mt9p031_set_power(struct v4l2_subdev *subdev, int on)
802 {
803 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
804 int ret = 0;
805
806 mutex_lock(&mt9p031->power_lock);
807
808 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
809 * update the power state.
810 */
811 if (mt9p031->power_count == !on) {
812 ret = __mt9p031_set_power(mt9p031, !!on);
813 if (ret < 0)
814 goto out;
815 }
816
817 /* Update the power count. */
818 mt9p031->power_count += on ? 1 : -1;
819 WARN_ON(mt9p031->power_count < 0);
820
821 out:
822 mutex_unlock(&mt9p031->power_lock);
823 return ret;
824 }
825
826 /* -----------------------------------------------------------------------------
827 * V4L2 subdev internal operations
828 */
829
830 static int mt9p031_registered(struct v4l2_subdev *subdev)
831 {
832 struct i2c_client *client = v4l2_get_subdevdata(subdev);
833 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
834 s32 data;
835 int ret;
836
837 ret = mt9p031_power_on(mt9p031);
838 if (ret < 0) {
839 dev_err(&client->dev, "MT9P031 power up failed\n");
840 return ret;
841 }
842
843 /* Read out the chip version register */
844 data = mt9p031_read(client, MT9P031_CHIP_VERSION);
845 if (data != MT9P031_CHIP_VERSION_VALUE) {
846 dev_err(&client->dev, "MT9P031 not detected, wrong version "
847 "0x%04x\n", data);
848 return -ENODEV;
849 }
850
851 mt9p031_power_off(mt9p031);
852
853 dev_info(&client->dev, "MT9P031 detected at address 0x%02x\n",
854 client->addr);
855
856 return ret;
857 }
858
859 static int mt9p031_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
860 {
861 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
862 struct v4l2_mbus_framefmt *format;
863 struct v4l2_rect *crop;
864
865 crop = v4l2_subdev_get_try_crop(fh, 0);
866 crop->left = MT9P031_COLUMN_START_DEF;
867 crop->top = MT9P031_ROW_START_DEF;
868 crop->width = MT9P031_WINDOW_WIDTH_DEF;
869 crop->height = MT9P031_WINDOW_HEIGHT_DEF;
870
871 format = v4l2_subdev_get_try_format(fh, 0);
872
873 if (mt9p031->model == MT9P031_MODEL_MONOCHROME)
874 format->code = V4L2_MBUS_FMT_Y12_1X12;
875 else
876 format->code = V4L2_MBUS_FMT_SGRBG12_1X12;
877
878 format->width = MT9P031_WINDOW_WIDTH_DEF;
879 format->height = MT9P031_WINDOW_HEIGHT_DEF;
880 format->field = V4L2_FIELD_NONE;
881 format->colorspace = V4L2_COLORSPACE_SRGB;
882
883 return mt9p031_set_power(subdev, 1);
884 }
885
886 static int mt9p031_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
887 {
888 return mt9p031_set_power(subdev, 0);
889 }
890
891 static struct v4l2_subdev_core_ops mt9p031_subdev_core_ops = {
892 .s_power = mt9p031_set_power,
893 };
894
895 static struct v4l2_subdev_video_ops mt9p031_subdev_video_ops = {
896 .s_stream = mt9p031_s_stream,
897 };
898
899 static struct v4l2_subdev_pad_ops mt9p031_subdev_pad_ops = {
900 .enum_mbus_code = mt9p031_enum_mbus_code,
901 .enum_frame_size = mt9p031_enum_frame_size,
902 .get_fmt = mt9p031_get_format,
903 .set_fmt = mt9p031_set_format,
904 .get_crop = mt9p031_get_crop,
905 .set_crop = mt9p031_set_crop,
906 };
907
908 static struct v4l2_subdev_ops mt9p031_subdev_ops = {
909 .core = &mt9p031_subdev_core_ops,
910 .video = &mt9p031_subdev_video_ops,
911 .pad = &mt9p031_subdev_pad_ops,
912 };
913
914 static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = {
915 .registered = mt9p031_registered,
916 .open = mt9p031_open,
917 .close = mt9p031_close,
918 };
919
920 /* -----------------------------------------------------------------------------
921 * Driver initialization and probing
922 */
923
924 static int mt9p031_probe(struct i2c_client *client,
925 const struct i2c_device_id *did)
926 {
927 struct mt9p031_platform_data *pdata = client->dev.platform_data;
928 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
929 struct mt9p031 *mt9p031;
930 unsigned int i;
931 int ret;
932
933 if (pdata == NULL) {
934 dev_err(&client->dev, "No platform data\n");
935 return -EINVAL;
936 }
937
938 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
939 dev_warn(&client->dev,
940 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
941 return -EIO;
942 }
943
944 mt9p031 = devm_kzalloc(&client->dev, sizeof(*mt9p031), GFP_KERNEL);
945 if (mt9p031 == NULL)
946 return -ENOMEM;
947
948 mt9p031->pdata = pdata;
949 mt9p031->output_control = MT9P031_OUTPUT_CONTROL_DEF;
950 mt9p031->mode2 = MT9P031_READ_MODE_2_ROW_BLC;
951 mt9p031->model = did->driver_data;
952 mt9p031->reset = -1;
953
954 mt9p031->vaa = devm_regulator_get(&client->dev, "vaa");
955 mt9p031->vdd = devm_regulator_get(&client->dev, "vdd");
956 mt9p031->vdd_io = devm_regulator_get(&client->dev, "vdd_io");
957
958 if (IS_ERR(mt9p031->vaa) || IS_ERR(mt9p031->vdd) ||
959 IS_ERR(mt9p031->vdd_io)) {
960 dev_err(&client->dev, "Unable to get regulators\n");
961 return -ENODEV;
962 }
963
964 v4l2_ctrl_handler_init(&mt9p031->ctrls, ARRAY_SIZE(mt9p031_ctrls) + 6);
965
966 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
967 V4L2_CID_EXPOSURE, MT9P031_SHUTTER_WIDTH_MIN,
968 MT9P031_SHUTTER_WIDTH_MAX, 1,
969 MT9P031_SHUTTER_WIDTH_DEF);
970 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
971 V4L2_CID_GAIN, MT9P031_GLOBAL_GAIN_MIN,
972 MT9P031_GLOBAL_GAIN_MAX, 1, MT9P031_GLOBAL_GAIN_DEF);
973 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
974 V4L2_CID_HFLIP, 0, 1, 1, 0);
975 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
976 V4L2_CID_VFLIP, 0, 1, 1, 0);
977 v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
978 V4L2_CID_PIXEL_RATE, pdata->target_freq,
979 pdata->target_freq, 1, pdata->target_freq);
980 v4l2_ctrl_new_std_menu_items(&mt9p031->ctrls, &mt9p031_ctrl_ops,
981 V4L2_CID_TEST_PATTERN,
982 ARRAY_SIZE(mt9p031_test_pattern_menu) - 1, 0,
983 0, mt9p031_test_pattern_menu);
984
985 for (i = 0; i < ARRAY_SIZE(mt9p031_ctrls); ++i)
986 v4l2_ctrl_new_custom(&mt9p031->ctrls, &mt9p031_ctrls[i], NULL);
987
988 mt9p031->subdev.ctrl_handler = &mt9p031->ctrls;
989
990 if (mt9p031->ctrls.error) {
991 printk(KERN_INFO "%s: control initialization error %d\n",
992 __func__, mt9p031->ctrls.error);
993 ret = mt9p031->ctrls.error;
994 goto done;
995 }
996
997 mt9p031->blc_auto = v4l2_ctrl_find(&mt9p031->ctrls, V4L2_CID_BLC_AUTO);
998 mt9p031->blc_offset = v4l2_ctrl_find(&mt9p031->ctrls,
999 V4L2_CID_BLC_DIGITAL_OFFSET);
1000
1001 mutex_init(&mt9p031->power_lock);
1002 v4l2_i2c_subdev_init(&mt9p031->subdev, client, &mt9p031_subdev_ops);
1003 mt9p031->subdev.internal_ops = &mt9p031_subdev_internal_ops;
1004
1005 mt9p031->pad.flags = MEDIA_PAD_FL_SOURCE;
1006 ret = media_entity_init(&mt9p031->subdev.entity, 1, &mt9p031->pad, 0);
1007 if (ret < 0)
1008 goto done;
1009
1010 mt9p031->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1011
1012 mt9p031->crop.width = MT9P031_WINDOW_WIDTH_DEF;
1013 mt9p031->crop.height = MT9P031_WINDOW_HEIGHT_DEF;
1014 mt9p031->crop.left = MT9P031_COLUMN_START_DEF;
1015 mt9p031->crop.top = MT9P031_ROW_START_DEF;
1016
1017 if (mt9p031->model == MT9P031_MODEL_MONOCHROME)
1018 mt9p031->format.code = V4L2_MBUS_FMT_Y12_1X12;
1019 else
1020 mt9p031->format.code = V4L2_MBUS_FMT_SGRBG12_1X12;
1021
1022 mt9p031->format.width = MT9P031_WINDOW_WIDTH_DEF;
1023 mt9p031->format.height = MT9P031_WINDOW_HEIGHT_DEF;
1024 mt9p031->format.field = V4L2_FIELD_NONE;
1025 mt9p031->format.colorspace = V4L2_COLORSPACE_SRGB;
1026
1027 if (pdata->reset != -1) {
1028 ret = devm_gpio_request_one(&client->dev, pdata->reset,
1029 GPIOF_OUT_INIT_LOW, "mt9p031_rst");
1030 if (ret < 0)
1031 goto done;
1032
1033 mt9p031->reset = pdata->reset;
1034 }
1035
1036 ret = mt9p031_pll_setup(mt9p031);
1037
1038 done:
1039 if (ret < 0) {
1040 v4l2_ctrl_handler_free(&mt9p031->ctrls);
1041 media_entity_cleanup(&mt9p031->subdev.entity);
1042 }
1043
1044 return ret;
1045 }
1046
1047 static int mt9p031_remove(struct i2c_client *client)
1048 {
1049 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1050 struct mt9p031 *mt9p031 = to_mt9p031(subdev);
1051
1052 v4l2_ctrl_handler_free(&mt9p031->ctrls);
1053 v4l2_device_unregister_subdev(subdev);
1054 media_entity_cleanup(&subdev->entity);
1055
1056 return 0;
1057 }
1058
1059 static const struct i2c_device_id mt9p031_id[] = {
1060 { "mt9p031", MT9P031_MODEL_COLOR },
1061 { "mt9p031m", MT9P031_MODEL_MONOCHROME },
1062 { }
1063 };
1064 MODULE_DEVICE_TABLE(i2c, mt9p031_id);
1065
1066 static struct i2c_driver mt9p031_i2c_driver = {
1067 .driver = {
1068 .name = "mt9p031",
1069 },
1070 .probe = mt9p031_probe,
1071 .remove = mt9p031_remove,
1072 .id_table = mt9p031_id,
1073 };
1074
1075 module_i2c_driver(mt9p031_i2c_driver);
1076
1077 MODULE_DESCRIPTION("Aptina MT9P031 Camera driver");
1078 MODULE_AUTHOR("Bastian Hecht <hechtb@gmail.com>");
1079 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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