2 * Driver for MT9V022, MT9V024, MT9V032, and MT9V034 CMOS Image Sensors
4 * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6 * Based on the MT9M001 driver,
8 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/log2.h>
19 #include <linux/mutex.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22 #include <linux/videodev2.h>
23 #include <linux/v4l2-mediabus.h>
24 #include <linux/module.h>
26 #include <media/mt9v032.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-subdev.h>
31 /* The first four rows are black rows. The active area spans 753x481 pixels. */
32 #define MT9V032_PIXEL_ARRAY_HEIGHT 485
33 #define MT9V032_PIXEL_ARRAY_WIDTH 753
35 #define MT9V032_SYSCLK_FREQ_DEF 26600000
37 #define MT9V032_CHIP_VERSION 0x00
38 #define MT9V032_CHIP_ID_REV1 0x1311
39 #define MT9V032_CHIP_ID_REV3 0x1313
40 #define MT9V034_CHIP_ID_REV1 0X1324
41 #define MT9V032_COLUMN_START 0x01
42 #define MT9V032_COLUMN_START_MIN 1
43 #define MT9V032_COLUMN_START_DEF 1
44 #define MT9V032_COLUMN_START_MAX 752
45 #define MT9V032_ROW_START 0x02
46 #define MT9V032_ROW_START_MIN 4
47 #define MT9V032_ROW_START_DEF 5
48 #define MT9V032_ROW_START_MAX 482
49 #define MT9V032_WINDOW_HEIGHT 0x03
50 #define MT9V032_WINDOW_HEIGHT_MIN 1
51 #define MT9V032_WINDOW_HEIGHT_DEF 480
52 #define MT9V032_WINDOW_HEIGHT_MAX 480
53 #define MT9V032_WINDOW_WIDTH 0x04
54 #define MT9V032_WINDOW_WIDTH_MIN 1
55 #define MT9V032_WINDOW_WIDTH_DEF 752
56 #define MT9V032_WINDOW_WIDTH_MAX 752
57 #define MT9V032_HORIZONTAL_BLANKING 0x05
58 #define MT9V032_HORIZONTAL_BLANKING_MIN 43
59 #define MT9V034_HORIZONTAL_BLANKING_MIN 61
60 #define MT9V032_HORIZONTAL_BLANKING_DEF 94
61 #define MT9V032_HORIZONTAL_BLANKING_MAX 1023
62 #define MT9V032_VERTICAL_BLANKING 0x06
63 #define MT9V032_VERTICAL_BLANKING_MIN 4
64 #define MT9V034_VERTICAL_BLANKING_MIN 2
65 #define MT9V032_VERTICAL_BLANKING_DEF 45
66 #define MT9V032_VERTICAL_BLANKING_MAX 3000
67 #define MT9V034_VERTICAL_BLANKING_MAX 32288
68 #define MT9V032_CHIP_CONTROL 0x07
69 #define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3)
70 #define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7)
71 #define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8)
72 #define MT9V032_SHUTTER_WIDTH1 0x08
73 #define MT9V032_SHUTTER_WIDTH2 0x09
74 #define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a
75 #define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b
76 #define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1
77 #define MT9V034_TOTAL_SHUTTER_WIDTH_MIN 0
78 #define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480
79 #define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767
80 #define MT9V034_TOTAL_SHUTTER_WIDTH_MAX 32765
81 #define MT9V032_RESET 0x0c
82 #define MT9V032_READ_MODE 0x0d
83 #define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0)
84 #define MT9V032_READ_MODE_ROW_BIN_SHIFT 0
85 #define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2)
86 #define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2
87 #define MT9V032_READ_MODE_ROW_FLIP (1 << 4)
88 #define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5)
89 #define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6)
90 #define MT9V032_READ_MODE_DARK_ROWS (1 << 7)
91 #define MT9V032_READ_MODE_RESERVED 0x0300
92 #define MT9V032_PIXEL_OPERATION_MODE 0x0f
93 #define MT9V034_PIXEL_OPERATION_MODE_HDR (1 << 0)
94 #define MT9V034_PIXEL_OPERATION_MODE_COLOR (1 << 1)
95 #define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2)
96 #define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6)
97 #define MT9V032_ANALOG_GAIN 0x35
98 #define MT9V032_ANALOG_GAIN_MIN 16
99 #define MT9V032_ANALOG_GAIN_DEF 16
100 #define MT9V032_ANALOG_GAIN_MAX 64
101 #define MT9V032_MAX_ANALOG_GAIN 0x36
102 #define MT9V032_MAX_ANALOG_GAIN_MAX 127
103 #define MT9V032_FRAME_DARK_AVERAGE 0x42
104 #define MT9V032_DARK_AVG_THRESH 0x46
105 #define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0)
106 #define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0
107 #define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8)
108 #define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8
109 #define MT9V032_ROW_NOISE_CORR_CONTROL 0x70
110 #define MT9V034_ROW_NOISE_CORR_ENABLE (1 << 0)
111 #define MT9V034_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1)
112 #define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5)
113 #define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7)
114 #define MT9V032_PIXEL_CLOCK 0x74
115 #define MT9V034_PIXEL_CLOCK 0x72
116 #define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0)
117 #define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1)
118 #define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2)
119 #define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3)
120 #define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4)
121 #define MT9V032_TEST_PATTERN 0x7f
122 #define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0)
123 #define MT9V032_TEST_PATTERN_DATA_SHIFT 0
124 #define MT9V032_TEST_PATTERN_USE_DATA (1 << 10)
125 #define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11)
126 #define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11)
127 #define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11)
128 #define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11)
129 #define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11)
130 #define MT9V032_TEST_PATTERN_ENABLE (1 << 13)
131 #define MT9V032_TEST_PATTERN_FLIP (1 << 14)
132 #define MT9V032_AEC_AGC_ENABLE 0xaf
133 #define MT9V032_AEC_ENABLE (1 << 0)
134 #define MT9V032_AGC_ENABLE (1 << 1)
135 #define MT9V032_THERMAL_INFO 0xc1
138 MT9V032_MODEL_V022_COLOR
, /* MT9V022IX7ATC */
139 MT9V032_MODEL_V022_MONO
, /* MT9V022IX7ATM */
140 MT9V032_MODEL_V024_COLOR
, /* MT9V024IA7XTC */
141 MT9V032_MODEL_V024_MONO
, /* MT9V024IA7XTM */
142 MT9V032_MODEL_V032_COLOR
, /* MT9V032C12STM */
143 MT9V032_MODEL_V032_MONO
, /* MT9V032C12STC */
144 MT9V032_MODEL_V034_COLOR
,
145 MT9V032_MODEL_V034_MONO
,
148 struct mt9v032_model_version
{
149 unsigned int version
;
153 struct mt9v032_model_data
{
154 unsigned int min_row_time
;
155 unsigned int min_hblank
;
156 unsigned int min_vblank
;
157 unsigned int max_vblank
;
158 unsigned int min_shutter
;
159 unsigned int max_shutter
;
160 unsigned int pclk_reg
;
163 struct mt9v032_model_info
{
164 const struct mt9v032_model_data
*data
;
168 static const struct mt9v032_model_version mt9v032_versions
[] = {
169 { MT9V032_CHIP_ID_REV1
, "MT9V022/MT9V032 rev1/2" },
170 { MT9V032_CHIP_ID_REV3
, "MT9V022/MT9V032 rev3" },
171 { MT9V034_CHIP_ID_REV1
, "MT9V024/MT9V034 rev1" },
174 static const struct mt9v032_model_data mt9v032_model_data
[] = {
176 /* MT9V022, MT9V032 revisions 1/2/3 */
178 .min_hblank
= MT9V032_HORIZONTAL_BLANKING_MIN
,
179 .min_vblank
= MT9V032_VERTICAL_BLANKING_MIN
,
180 .max_vblank
= MT9V032_VERTICAL_BLANKING_MAX
,
181 .min_shutter
= MT9V032_TOTAL_SHUTTER_WIDTH_MIN
,
182 .max_shutter
= MT9V032_TOTAL_SHUTTER_WIDTH_MAX
,
183 .pclk_reg
= MT9V032_PIXEL_CLOCK
,
185 /* MT9V024, MT9V034 */
187 .min_hblank
= MT9V034_HORIZONTAL_BLANKING_MIN
,
188 .min_vblank
= MT9V034_VERTICAL_BLANKING_MIN
,
189 .max_vblank
= MT9V034_VERTICAL_BLANKING_MAX
,
190 .min_shutter
= MT9V034_TOTAL_SHUTTER_WIDTH_MIN
,
191 .max_shutter
= MT9V034_TOTAL_SHUTTER_WIDTH_MAX
,
192 .pclk_reg
= MT9V034_PIXEL_CLOCK
,
196 static const struct mt9v032_model_info mt9v032_models
[] = {
197 [MT9V032_MODEL_V022_COLOR
] = {
198 .data
= &mt9v032_model_data
[0],
201 [MT9V032_MODEL_V022_MONO
] = {
202 .data
= &mt9v032_model_data
[0],
205 [MT9V032_MODEL_V024_COLOR
] = {
206 .data
= &mt9v032_model_data
[1],
209 [MT9V032_MODEL_V024_MONO
] = {
210 .data
= &mt9v032_model_data
[1],
213 [MT9V032_MODEL_V032_COLOR
] = {
214 .data
= &mt9v032_model_data
[0],
217 [MT9V032_MODEL_V032_MONO
] = {
218 .data
= &mt9v032_model_data
[0],
221 [MT9V032_MODEL_V034_COLOR
] = {
222 .data
= &mt9v032_model_data
[1],
225 [MT9V032_MODEL_V034_MONO
] = {
226 .data
= &mt9v032_model_data
[1],
232 struct v4l2_subdev subdev
;
233 struct media_pad pad
;
235 struct v4l2_mbus_framefmt format
;
236 struct v4l2_rect crop
;
240 struct v4l2_ctrl_handler ctrls
;
242 struct v4l2_ctrl
*link_freq
;
243 struct v4l2_ctrl
*pixel_rate
;
246 struct mutex power_lock
;
249 struct regmap
*regmap
;
252 struct mt9v032_platform_data
*pdata
;
253 const struct mt9v032_model_info
*model
;
254 const struct mt9v032_model_version
*version
;
260 struct v4l2_ctrl
*test_pattern
;
261 struct v4l2_ctrl
*test_pattern_color
;
265 static struct mt9v032
*to_mt9v032(struct v4l2_subdev
*sd
)
267 return container_of(sd
, struct mt9v032
, subdev
);
271 mt9v032_update_aec_agc(struct mt9v032
*mt9v032
, u16 which
, int enable
)
273 struct regmap
*map
= mt9v032
->regmap
;
274 u16 value
= mt9v032
->aec_agc
;
282 ret
= regmap_write(map
, MT9V032_AEC_AGC_ENABLE
, value
);
286 mt9v032
->aec_agc
= value
;
291 mt9v032_update_hblank(struct mt9v032
*mt9v032
)
293 struct v4l2_rect
*crop
= &mt9v032
->crop
;
294 unsigned int min_hblank
= mt9v032
->model
->data
->min_hblank
;
297 if (mt9v032
->version
->version
== MT9V034_CHIP_ID_REV1
)
298 min_hblank
+= (mt9v032
->hratio
- 1) * 10;
299 min_hblank
= max_t(int, mt9v032
->model
->data
->min_row_time
- crop
->width
,
301 hblank
= max_t(unsigned int, mt9v032
->hblank
, min_hblank
);
303 return regmap_write(mt9v032
->regmap
, MT9V032_HORIZONTAL_BLANKING
,
307 static int mt9v032_power_on(struct mt9v032
*mt9v032
)
309 struct regmap
*map
= mt9v032
->regmap
;
312 ret
= clk_set_rate(mt9v032
->clk
, mt9v032
->sysclk
);
316 ret
= clk_prepare_enable(mt9v032
->clk
);
322 /* Reset the chip and stop data read out */
323 ret
= regmap_write(map
, MT9V032_RESET
, 1);
327 ret
= regmap_write(map
, MT9V032_RESET
, 0);
331 return regmap_write(map
, MT9V032_CHIP_CONTROL
, 0);
334 static void mt9v032_power_off(struct mt9v032
*mt9v032
)
336 clk_disable_unprepare(mt9v032
->clk
);
339 static int __mt9v032_set_power(struct mt9v032
*mt9v032
, bool on
)
341 struct regmap
*map
= mt9v032
->regmap
;
345 mt9v032_power_off(mt9v032
);
349 ret
= mt9v032_power_on(mt9v032
);
353 /* Configure the pixel clock polarity */
354 if (mt9v032
->pdata
&& mt9v032
->pdata
->clk_pol
) {
355 ret
= regmap_write(map
, mt9v032
->model
->data
->pclk_reg
,
356 MT9V032_PIXEL_CLOCK_INV_PXL_CLK
);
361 /* Disable the noise correction algorithm and restore the controls. */
362 ret
= regmap_write(map
, MT9V032_ROW_NOISE_CORR_CONTROL
, 0);
366 return v4l2_ctrl_handler_setup(&mt9v032
->ctrls
);
369 /* -----------------------------------------------------------------------------
370 * V4L2 subdev video operations
373 static struct v4l2_mbus_framefmt
*
374 __mt9v032_get_pad_format(struct mt9v032
*mt9v032
, struct v4l2_subdev_fh
*fh
,
375 unsigned int pad
, enum v4l2_subdev_format_whence which
)
378 case V4L2_SUBDEV_FORMAT_TRY
:
379 return v4l2_subdev_get_try_format(fh
, pad
);
380 case V4L2_SUBDEV_FORMAT_ACTIVE
:
381 return &mt9v032
->format
;
387 static struct v4l2_rect
*
388 __mt9v032_get_pad_crop(struct mt9v032
*mt9v032
, struct v4l2_subdev_fh
*fh
,
389 unsigned int pad
, enum v4l2_subdev_format_whence which
)
392 case V4L2_SUBDEV_FORMAT_TRY
:
393 return v4l2_subdev_get_try_crop(fh
, pad
);
394 case V4L2_SUBDEV_FORMAT_ACTIVE
:
395 return &mt9v032
->crop
;
401 static int mt9v032_s_stream(struct v4l2_subdev
*subdev
, int enable
)
403 const u16 mode
= MT9V032_CHIP_CONTROL_MASTER_MODE
404 | MT9V032_CHIP_CONTROL_DOUT_ENABLE
405 | MT9V032_CHIP_CONTROL_SEQUENTIAL
;
406 struct mt9v032
*mt9v032
= to_mt9v032(subdev
);
407 struct v4l2_rect
*crop
= &mt9v032
->crop
;
408 struct regmap
*map
= mt9v032
->regmap
;
414 return regmap_update_bits(map
, MT9V032_CHIP_CONTROL
, mode
, 0);
416 /* Configure the window size and row/column bin */
417 hbin
= fls(mt9v032
->hratio
) - 1;
418 vbin
= fls(mt9v032
->vratio
) - 1;
419 ret
= regmap_update_bits(map
, MT9V032_READ_MODE
,
420 ~MT9V032_READ_MODE_RESERVED
,
421 hbin
<< MT9V032_READ_MODE_COLUMN_BIN_SHIFT
|
422 vbin
<< MT9V032_READ_MODE_ROW_BIN_SHIFT
);
426 ret
= regmap_write(map
, MT9V032_COLUMN_START
, crop
->left
);
430 ret
= regmap_write(map
, MT9V032_ROW_START
, crop
->top
);
434 ret
= regmap_write(map
, MT9V032_WINDOW_WIDTH
, crop
->width
);
438 ret
= regmap_write(map
, MT9V032_WINDOW_HEIGHT
, crop
->height
);
442 ret
= mt9v032_update_hblank(mt9v032
);
446 /* Switch to master "normal" mode */
447 return regmap_update_bits(map
, MT9V032_CHIP_CONTROL
, mode
, mode
);
450 static int mt9v032_enum_mbus_code(struct v4l2_subdev
*subdev
,
451 struct v4l2_subdev_fh
*fh
,
452 struct v4l2_subdev_mbus_code_enum
*code
)
457 code
->code
= MEDIA_BUS_FMT_SGRBG10_1X10
;
461 static int mt9v032_enum_frame_size(struct v4l2_subdev
*subdev
,
462 struct v4l2_subdev_fh
*fh
,
463 struct v4l2_subdev_frame_size_enum
*fse
)
465 if (fse
->index
>= 3 || fse
->code
!= MEDIA_BUS_FMT_SGRBG10_1X10
)
468 fse
->min_width
= MT9V032_WINDOW_WIDTH_DEF
/ (1 << fse
->index
);
469 fse
->max_width
= fse
->min_width
;
470 fse
->min_height
= MT9V032_WINDOW_HEIGHT_DEF
/ (1 << fse
->index
);
471 fse
->max_height
= fse
->min_height
;
476 static int mt9v032_get_format(struct v4l2_subdev
*subdev
,
477 struct v4l2_subdev_fh
*fh
,
478 struct v4l2_subdev_format
*format
)
480 struct mt9v032
*mt9v032
= to_mt9v032(subdev
);
482 format
->format
= *__mt9v032_get_pad_format(mt9v032
, fh
, format
->pad
,
487 static void mt9v032_configure_pixel_rate(struct mt9v032
*mt9v032
)
489 struct i2c_client
*client
= v4l2_get_subdevdata(&mt9v032
->subdev
);
492 ret
= v4l2_ctrl_s_ctrl_int64(mt9v032
->pixel_rate
,
493 mt9v032
->sysclk
/ mt9v032
->hratio
);
495 dev_warn(&client
->dev
, "failed to set pixel rate (%d)\n", ret
);
498 static unsigned int mt9v032_calc_ratio(unsigned int input
, unsigned int output
)
500 /* Compute the power-of-two binning factor closest to the input size to
501 * output size ratio. Given that the output size is bounded by input/4
502 * and input, a generic implementation would be an ineffective luxury.
504 if (output
* 3 > input
* 2)
506 if (output
* 3 > input
)
511 static int mt9v032_set_format(struct v4l2_subdev
*subdev
,
512 struct v4l2_subdev_fh
*fh
,
513 struct v4l2_subdev_format
*format
)
515 struct mt9v032
*mt9v032
= to_mt9v032(subdev
);
516 struct v4l2_mbus_framefmt
*__format
;
517 struct v4l2_rect
*__crop
;
523 __crop
= __mt9v032_get_pad_crop(mt9v032
, fh
, format
->pad
,
526 /* Clamp the width and height to avoid dividing by zero. */
527 width
= clamp(ALIGN(format
->format
.width
, 2),
528 max_t(unsigned int, __crop
->width
/ 4,
529 MT9V032_WINDOW_WIDTH_MIN
),
531 height
= clamp(ALIGN(format
->format
.height
, 2),
532 max_t(unsigned int, __crop
->height
/ 4,
533 MT9V032_WINDOW_HEIGHT_MIN
),
536 hratio
= mt9v032_calc_ratio(__crop
->width
, width
);
537 vratio
= mt9v032_calc_ratio(__crop
->height
, height
);
539 __format
= __mt9v032_get_pad_format(mt9v032
, fh
, format
->pad
,
541 __format
->width
= __crop
->width
/ hratio
;
542 __format
->height
= __crop
->height
/ vratio
;
544 if (format
->which
== V4L2_SUBDEV_FORMAT_ACTIVE
) {
545 mt9v032
->hratio
= hratio
;
546 mt9v032
->vratio
= vratio
;
547 mt9v032_configure_pixel_rate(mt9v032
);
550 format
->format
= *__format
;
555 static int mt9v032_get_selection(struct v4l2_subdev
*subdev
,
556 struct v4l2_subdev_fh
*fh
,
557 struct v4l2_subdev_selection
*sel
)
559 struct mt9v032
*mt9v032
= to_mt9v032(subdev
);
561 if (sel
->target
!= V4L2_SEL_TGT_CROP
)
564 sel
->r
= *__mt9v032_get_pad_crop(mt9v032
, fh
, sel
->pad
, sel
->which
);
568 static int mt9v032_set_selection(struct v4l2_subdev
*subdev
,
569 struct v4l2_subdev_fh
*fh
,
570 struct v4l2_subdev_selection
*sel
)
572 struct mt9v032
*mt9v032
= to_mt9v032(subdev
);
573 struct v4l2_mbus_framefmt
*__format
;
574 struct v4l2_rect
*__crop
;
575 struct v4l2_rect rect
;
577 if (sel
->target
!= V4L2_SEL_TGT_CROP
)
580 /* Clamp the crop rectangle boundaries and align them to a non multiple
581 * of 2 pixels to ensure a GRBG Bayer pattern.
583 rect
.left
= clamp(ALIGN(sel
->r
.left
+ 1, 2) - 1,
584 MT9V032_COLUMN_START_MIN
,
585 MT9V032_COLUMN_START_MAX
);
586 rect
.top
= clamp(ALIGN(sel
->r
.top
+ 1, 2) - 1,
587 MT9V032_ROW_START_MIN
,
588 MT9V032_ROW_START_MAX
);
589 rect
.width
= clamp_t(unsigned int, ALIGN(sel
->r
.width
, 2),
590 MT9V032_WINDOW_WIDTH_MIN
,
591 MT9V032_WINDOW_WIDTH_MAX
);
592 rect
.height
= clamp_t(unsigned int, ALIGN(sel
->r
.height
, 2),
593 MT9V032_WINDOW_HEIGHT_MIN
,
594 MT9V032_WINDOW_HEIGHT_MAX
);
596 rect
.width
= min_t(unsigned int,
597 rect
.width
, MT9V032_PIXEL_ARRAY_WIDTH
- rect
.left
);
598 rect
.height
= min_t(unsigned int,
599 rect
.height
, MT9V032_PIXEL_ARRAY_HEIGHT
- rect
.top
);
601 __crop
= __mt9v032_get_pad_crop(mt9v032
, fh
, sel
->pad
, sel
->which
);
603 if (rect
.width
!= __crop
->width
|| rect
.height
!= __crop
->height
) {
604 /* Reset the output image size if the crop rectangle size has
607 __format
= __mt9v032_get_pad_format(mt9v032
, fh
, sel
->pad
,
609 __format
->width
= rect
.width
;
610 __format
->height
= rect
.height
;
611 if (sel
->which
== V4L2_SUBDEV_FORMAT_ACTIVE
) {
614 mt9v032_configure_pixel_rate(mt9v032
);
624 /* -----------------------------------------------------------------------------
625 * V4L2 subdev control operations
628 #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
630 static int mt9v032_s_ctrl(struct v4l2_ctrl
*ctrl
)
632 struct mt9v032
*mt9v032
=
633 container_of(ctrl
->handler
, struct mt9v032
, ctrls
);
634 struct regmap
*map
= mt9v032
->regmap
;
639 case V4L2_CID_AUTOGAIN
:
640 return mt9v032_update_aec_agc(mt9v032
, MT9V032_AGC_ENABLE
,
644 return regmap_write(map
, MT9V032_ANALOG_GAIN
, ctrl
->val
);
646 case V4L2_CID_EXPOSURE_AUTO
:
647 return mt9v032_update_aec_agc(mt9v032
, MT9V032_AEC_ENABLE
,
650 case V4L2_CID_EXPOSURE
:
651 return regmap_write(map
, MT9V032_TOTAL_SHUTTER_WIDTH
,
654 case V4L2_CID_HBLANK
:
655 mt9v032
->hblank
= ctrl
->val
;
656 return mt9v032_update_hblank(mt9v032
);
658 case V4L2_CID_VBLANK
:
659 return regmap_write(map
, MT9V032_VERTICAL_BLANKING
,
662 case V4L2_CID_PIXEL_RATE
:
663 case V4L2_CID_LINK_FREQ
:
664 if (mt9v032
->link_freq
== NULL
)
667 freq
= mt9v032
->pdata
->link_freqs
[mt9v032
->link_freq
->val
];
668 *mt9v032
->pixel_rate
->p_new
.p_s64
= freq
;
669 mt9v032
->sysclk
= freq
;
672 case V4L2_CID_TEST_PATTERN
:
673 switch (mt9v032
->test_pattern
->val
) {
678 data
= MT9V032_TEST_PATTERN_GRAY_VERTICAL
679 | MT9V032_TEST_PATTERN_ENABLE
;
682 data
= MT9V032_TEST_PATTERN_GRAY_HORIZONTAL
683 | MT9V032_TEST_PATTERN_ENABLE
;
686 data
= MT9V032_TEST_PATTERN_GRAY_DIAGONAL
687 | MT9V032_TEST_PATTERN_ENABLE
;
690 data
= (mt9v032
->test_pattern_color
->val
<<
691 MT9V032_TEST_PATTERN_DATA_SHIFT
)
692 | MT9V032_TEST_PATTERN_USE_DATA
693 | MT9V032_TEST_PATTERN_ENABLE
694 | MT9V032_TEST_PATTERN_FLIP
;
697 return regmap_write(map
, MT9V032_TEST_PATTERN
, data
);
703 static struct v4l2_ctrl_ops mt9v032_ctrl_ops
= {
704 .s_ctrl
= mt9v032_s_ctrl
,
707 static const char * const mt9v032_test_pattern_menu
[] = {
709 "Gray Vertical Shade",
710 "Gray Horizontal Shade",
711 "Gray Diagonal Shade",
715 static const struct v4l2_ctrl_config mt9v032_test_pattern_color
= {
716 .ops
= &mt9v032_ctrl_ops
,
717 .id
= V4L2_CID_TEST_PATTERN_COLOR
,
718 .type
= V4L2_CTRL_TYPE_INTEGER
,
719 .name
= "Test Pattern Color",
727 /* -----------------------------------------------------------------------------
728 * V4L2 subdev core operations
731 static int mt9v032_set_power(struct v4l2_subdev
*subdev
, int on
)
733 struct mt9v032
*mt9v032
= to_mt9v032(subdev
);
736 mutex_lock(&mt9v032
->power_lock
);
738 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
739 * update the power state.
741 if (mt9v032
->power_count
== !on
) {
742 ret
= __mt9v032_set_power(mt9v032
, !!on
);
747 /* Update the power count. */
748 mt9v032
->power_count
+= on
? 1 : -1;
749 WARN_ON(mt9v032
->power_count
< 0);
752 mutex_unlock(&mt9v032
->power_lock
);
756 /* -----------------------------------------------------------------------------
757 * V4L2 subdev internal operations
760 static int mt9v032_registered(struct v4l2_subdev
*subdev
)
762 struct i2c_client
*client
= v4l2_get_subdevdata(subdev
);
763 struct mt9v032
*mt9v032
= to_mt9v032(subdev
);
768 dev_info(&client
->dev
, "Probing MT9V032 at address 0x%02x\n",
771 ret
= mt9v032_power_on(mt9v032
);
773 dev_err(&client
->dev
, "MT9V032 power up failed\n");
777 /* Read and check the sensor version */
778 ret
= regmap_read(mt9v032
->regmap
, MT9V032_CHIP_VERSION
, &version
);
780 dev_err(&client
->dev
, "Failed reading chip version\n");
784 for (i
= 0; i
< ARRAY_SIZE(mt9v032_versions
); ++i
) {
785 if (mt9v032_versions
[i
].version
== version
) {
786 mt9v032
->version
= &mt9v032_versions
[i
];
791 if (mt9v032
->version
== NULL
) {
792 dev_err(&client
->dev
, "Unsupported chip version 0x%04x\n",
797 mt9v032_power_off(mt9v032
);
799 dev_info(&client
->dev
, "%s detected at address 0x%02x\n",
800 mt9v032
->version
->name
, client
->addr
);
802 mt9v032_configure_pixel_rate(mt9v032
);
807 static int mt9v032_open(struct v4l2_subdev
*subdev
, struct v4l2_subdev_fh
*fh
)
809 struct mt9v032
*mt9v032
= to_mt9v032(subdev
);
810 struct v4l2_mbus_framefmt
*format
;
811 struct v4l2_rect
*crop
;
813 crop
= v4l2_subdev_get_try_crop(fh
, 0);
814 crop
->left
= MT9V032_COLUMN_START_DEF
;
815 crop
->top
= MT9V032_ROW_START_DEF
;
816 crop
->width
= MT9V032_WINDOW_WIDTH_DEF
;
817 crop
->height
= MT9V032_WINDOW_HEIGHT_DEF
;
819 format
= v4l2_subdev_get_try_format(fh
, 0);
821 if (mt9v032
->model
->color
)
822 format
->code
= MEDIA_BUS_FMT_SGRBG10_1X10
;
824 format
->code
= MEDIA_BUS_FMT_Y10_1X10
;
826 format
->width
= MT9V032_WINDOW_WIDTH_DEF
;
827 format
->height
= MT9V032_WINDOW_HEIGHT_DEF
;
828 format
->field
= V4L2_FIELD_NONE
;
829 format
->colorspace
= V4L2_COLORSPACE_SRGB
;
831 return mt9v032_set_power(subdev
, 1);
834 static int mt9v032_close(struct v4l2_subdev
*subdev
, struct v4l2_subdev_fh
*fh
)
836 return mt9v032_set_power(subdev
, 0);
839 static struct v4l2_subdev_core_ops mt9v032_subdev_core_ops
= {
840 .s_power
= mt9v032_set_power
,
843 static struct v4l2_subdev_video_ops mt9v032_subdev_video_ops
= {
844 .s_stream
= mt9v032_s_stream
,
847 static struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops
= {
848 .enum_mbus_code
= mt9v032_enum_mbus_code
,
849 .enum_frame_size
= mt9v032_enum_frame_size
,
850 .get_fmt
= mt9v032_get_format
,
851 .set_fmt
= mt9v032_set_format
,
852 .get_selection
= mt9v032_get_selection
,
853 .set_selection
= mt9v032_set_selection
,
856 static struct v4l2_subdev_ops mt9v032_subdev_ops
= {
857 .core
= &mt9v032_subdev_core_ops
,
858 .video
= &mt9v032_subdev_video_ops
,
859 .pad
= &mt9v032_subdev_pad_ops
,
862 static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops
= {
863 .registered
= mt9v032_registered
,
864 .open
= mt9v032_open
,
865 .close
= mt9v032_close
,
868 static const struct regmap_config mt9v032_regmap_config
= {
871 .max_register
= 0xff,
872 .cache_type
= REGCACHE_RBTREE
,
875 /* -----------------------------------------------------------------------------
876 * Driver initialization and probing
879 static int mt9v032_probe(struct i2c_client
*client
,
880 const struct i2c_device_id
*did
)
882 struct mt9v032_platform_data
*pdata
= client
->dev
.platform_data
;
883 struct mt9v032
*mt9v032
;
887 if (!i2c_check_functionality(client
->adapter
,
888 I2C_FUNC_SMBUS_WORD_DATA
)) {
889 dev_warn(&client
->adapter
->dev
,
890 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
894 mt9v032
= devm_kzalloc(&client
->dev
, sizeof(*mt9v032
), GFP_KERNEL
);
898 mt9v032
->regmap
= devm_regmap_init_i2c(client
, &mt9v032_regmap_config
);
899 if (IS_ERR(mt9v032
->regmap
))
900 return PTR_ERR(mt9v032
->regmap
);
902 mt9v032
->clk
= devm_clk_get(&client
->dev
, NULL
);
903 if (IS_ERR(mt9v032
->clk
))
904 return PTR_ERR(mt9v032
->clk
);
906 mutex_init(&mt9v032
->power_lock
);
907 mt9v032
->pdata
= pdata
;
908 mt9v032
->model
= (const void *)did
->driver_data
;
910 v4l2_ctrl_handler_init(&mt9v032
->ctrls
, 10);
912 v4l2_ctrl_new_std(&mt9v032
->ctrls
, &mt9v032_ctrl_ops
,
913 V4L2_CID_AUTOGAIN
, 0, 1, 1, 1);
914 v4l2_ctrl_new_std(&mt9v032
->ctrls
, &mt9v032_ctrl_ops
,
915 V4L2_CID_GAIN
, MT9V032_ANALOG_GAIN_MIN
,
916 MT9V032_ANALOG_GAIN_MAX
, 1, MT9V032_ANALOG_GAIN_DEF
);
917 v4l2_ctrl_new_std_menu(&mt9v032
->ctrls
, &mt9v032_ctrl_ops
,
918 V4L2_CID_EXPOSURE_AUTO
, V4L2_EXPOSURE_MANUAL
, 0,
920 v4l2_ctrl_new_std(&mt9v032
->ctrls
, &mt9v032_ctrl_ops
,
921 V4L2_CID_EXPOSURE
, mt9v032
->model
->data
->min_shutter
,
922 mt9v032
->model
->data
->max_shutter
, 1,
923 MT9V032_TOTAL_SHUTTER_WIDTH_DEF
);
924 v4l2_ctrl_new_std(&mt9v032
->ctrls
, &mt9v032_ctrl_ops
,
925 V4L2_CID_HBLANK
, mt9v032
->model
->data
->min_hblank
,
926 MT9V032_HORIZONTAL_BLANKING_MAX
, 1,
927 MT9V032_HORIZONTAL_BLANKING_DEF
);
928 v4l2_ctrl_new_std(&mt9v032
->ctrls
, &mt9v032_ctrl_ops
,
929 V4L2_CID_VBLANK
, mt9v032
->model
->data
->min_vblank
,
930 mt9v032
->model
->data
->max_vblank
, 1,
931 MT9V032_VERTICAL_BLANKING_DEF
);
932 mt9v032
->test_pattern
= v4l2_ctrl_new_std_menu_items(&mt9v032
->ctrls
,
933 &mt9v032_ctrl_ops
, V4L2_CID_TEST_PATTERN
,
934 ARRAY_SIZE(mt9v032_test_pattern_menu
) - 1, 0, 0,
935 mt9v032_test_pattern_menu
);
936 mt9v032
->test_pattern_color
= v4l2_ctrl_new_custom(&mt9v032
->ctrls
,
937 &mt9v032_test_pattern_color
, NULL
);
939 v4l2_ctrl_cluster(2, &mt9v032
->test_pattern
);
941 mt9v032
->pixel_rate
=
942 v4l2_ctrl_new_std(&mt9v032
->ctrls
, &mt9v032_ctrl_ops
,
943 V4L2_CID_PIXEL_RATE
, 1, INT_MAX
, 1, 1);
945 if (pdata
&& pdata
->link_freqs
) {
946 unsigned int def
= 0;
948 for (i
= 0; pdata
->link_freqs
[i
]; ++i
) {
949 if (pdata
->link_freqs
[i
] == pdata
->link_def_freq
)
954 v4l2_ctrl_new_int_menu(&mt9v032
->ctrls
,
956 V4L2_CID_LINK_FREQ
, i
- 1, def
,
958 v4l2_ctrl_cluster(2, &mt9v032
->link_freq
);
962 mt9v032
->subdev
.ctrl_handler
= &mt9v032
->ctrls
;
964 if (mt9v032
->ctrls
.error
)
965 printk(KERN_INFO
"%s: control initialization error %d\n",
966 __func__
, mt9v032
->ctrls
.error
);
968 mt9v032
->crop
.left
= MT9V032_COLUMN_START_DEF
;
969 mt9v032
->crop
.top
= MT9V032_ROW_START_DEF
;
970 mt9v032
->crop
.width
= MT9V032_WINDOW_WIDTH_DEF
;
971 mt9v032
->crop
.height
= MT9V032_WINDOW_HEIGHT_DEF
;
973 if (mt9v032
->model
->color
)
974 mt9v032
->format
.code
= MEDIA_BUS_FMT_SGRBG10_1X10
;
976 mt9v032
->format
.code
= MEDIA_BUS_FMT_Y10_1X10
;
978 mt9v032
->format
.width
= MT9V032_WINDOW_WIDTH_DEF
;
979 mt9v032
->format
.height
= MT9V032_WINDOW_HEIGHT_DEF
;
980 mt9v032
->format
.field
= V4L2_FIELD_NONE
;
981 mt9v032
->format
.colorspace
= V4L2_COLORSPACE_SRGB
;
986 mt9v032
->aec_agc
= MT9V032_AEC_ENABLE
| MT9V032_AGC_ENABLE
;
987 mt9v032
->hblank
= MT9V032_HORIZONTAL_BLANKING_DEF
;
988 mt9v032
->sysclk
= MT9V032_SYSCLK_FREQ_DEF
;
990 v4l2_i2c_subdev_init(&mt9v032
->subdev
, client
, &mt9v032_subdev_ops
);
991 mt9v032
->subdev
.internal_ops
= &mt9v032_subdev_internal_ops
;
992 mt9v032
->subdev
.flags
|= V4L2_SUBDEV_FL_HAS_DEVNODE
;
994 mt9v032
->pad
.flags
= MEDIA_PAD_FL_SOURCE
;
995 ret
= media_entity_init(&mt9v032
->subdev
.entity
, 1, &mt9v032
->pad
, 0);
999 mt9v032
->subdev
.dev
= &client
->dev
;
1000 ret
= v4l2_async_register_subdev(&mt9v032
->subdev
);
1007 media_entity_cleanup(&mt9v032
->subdev
.entity
);
1008 v4l2_ctrl_handler_free(&mt9v032
->ctrls
);
1012 static int mt9v032_remove(struct i2c_client
*client
)
1014 struct v4l2_subdev
*subdev
= i2c_get_clientdata(client
);
1015 struct mt9v032
*mt9v032
= to_mt9v032(subdev
);
1017 v4l2_async_unregister_subdev(subdev
);
1018 v4l2_ctrl_handler_free(&mt9v032
->ctrls
);
1019 v4l2_device_unregister_subdev(subdev
);
1020 media_entity_cleanup(&subdev
->entity
);
1025 static const struct i2c_device_id mt9v032_id
[] = {
1026 { "mt9v022", (kernel_ulong_t
)&mt9v032_models
[MT9V032_MODEL_V022_COLOR
] },
1027 { "mt9v022m", (kernel_ulong_t
)&mt9v032_models
[MT9V032_MODEL_V022_MONO
] },
1028 { "mt9v024", (kernel_ulong_t
)&mt9v032_models
[MT9V032_MODEL_V024_COLOR
] },
1029 { "mt9v024m", (kernel_ulong_t
)&mt9v032_models
[MT9V032_MODEL_V024_MONO
] },
1030 { "mt9v032", (kernel_ulong_t
)&mt9v032_models
[MT9V032_MODEL_V032_COLOR
] },
1031 { "mt9v032m", (kernel_ulong_t
)&mt9v032_models
[MT9V032_MODEL_V032_MONO
] },
1032 { "mt9v034", (kernel_ulong_t
)&mt9v032_models
[MT9V032_MODEL_V034_COLOR
] },
1033 { "mt9v034m", (kernel_ulong_t
)&mt9v032_models
[MT9V032_MODEL_V034_MONO
] },
1036 MODULE_DEVICE_TABLE(i2c
, mt9v032_id
);
1038 static struct i2c_driver mt9v032_driver
= {
1042 .probe
= mt9v032_probe
,
1043 .remove
= mt9v032_remove
,
1044 .id_table
= mt9v032_id
,
1047 module_i2c_driver(mt9v032_driver
);
1049 MODULE_DESCRIPTION("Aptina MT9V032 Camera driver");
1050 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1051 MODULE_LICENSE("GPL");