2 * Driver for Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor
3 * with embedded SoC ISP.
5 * Copyright (C) 2013, Samsung Electronics Co., Ltd.
6 * Andrzej Hajda <a.hajda@samsung.com>
8 * Based on S5K6AA driver authored by Sylwester Nawrocki
9 * Copyright (C) 2013, Samsung Electronics Co., Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/firmware.h>
19 #include <linux/gpio.h>
20 #include <linux/i2c.h>
21 #include <linux/media.h>
22 #include <linux/module.h>
23 #include <linux/of_gpio.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/slab.h>
27 #include <media/media-entity.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-subdev.h>
31 #include <media/v4l2-mediabus.h>
32 #include <media/v4l2-of.h>
35 module_param(debug
, int, 0644);
37 #define S5K5BAF_DRIVER_NAME "s5k5baf"
38 #define S5K5BAF_DEFAULT_MCLK_FREQ 24000000U
39 #define S5K5BAF_CLK_NAME "mclk"
41 #define S5K5BAF_FW_FILENAME "s5k5baf-cfg.bin"
42 #define S5K5BAF_FW_TAG "SF00"
43 #define S5K5BAG_FW_TAG_LEN 2
44 #define S5K5BAG_FW_MAX_COUNT 16
46 #define S5K5BAF_CIS_WIDTH 1600
47 #define S5K5BAF_CIS_HEIGHT 1200
48 #define S5K5BAF_WIN_WIDTH_MIN 8
49 #define S5K5BAF_WIN_HEIGHT_MIN 8
50 #define S5K5BAF_GAIN_RED_DEF 127
51 #define S5K5BAF_GAIN_GREEN_DEF 95
52 #define S5K5BAF_GAIN_BLUE_DEF 180
53 /* Default number of MIPI CSI-2 data lanes used */
54 #define S5K5BAF_DEF_NUM_LANES 1
56 #define AHB_MSB_ADDR_PTR 0xfcfc
59 * Register interface pages (the most significant word of the address)
61 #define PAGE_IF_HW 0xd000
62 #define PAGE_IF_SW 0x7000
65 * H/W register Interface (PAGE_IF_HW)
67 #define REG_SW_LOAD_COMPLETE 0x0014
68 #define REG_CMDWR_PAGE 0x0028
69 #define REG_CMDWR_ADDR 0x002a
70 #define REG_CMDRD_PAGE 0x002c
71 #define REG_CMDRD_ADDR 0x002e
72 #define REG_CMD_BUF 0x0f12
73 #define REG_SET_HOST_INT 0x1000
74 #define REG_CLEAR_HOST_INT 0x1030
75 #define REG_PATTERN_SET 0x3100
76 #define REG_PATTERN_WIDTH 0x3118
77 #define REG_PATTERN_HEIGHT 0x311a
78 #define REG_PATTERN_PARAM 0x311c
81 * S/W register interface (PAGE_IF_SW)
84 /* Firmware revision information */
85 #define REG_FW_APIVER 0x012e
86 #define S5K5BAF_FW_APIVER 0x0001
87 #define REG_FW_REVISION 0x0130
88 #define REG_FW_SENSOR_ID 0x0152
90 /* Initialization parameters */
91 /* Master clock frequency in KHz */
92 #define REG_I_INCLK_FREQ_L 0x01b8
93 #define REG_I_INCLK_FREQ_H 0x01ba
94 #define MIN_MCLK_FREQ_KHZ 6000U
95 #define MAX_MCLK_FREQ_KHZ 48000U
96 #define REG_I_USE_NPVI_CLOCKS 0x01c6
98 #define REG_I_USE_NMIPI_CLOCKS 0x01c8
99 #define NMIPI_CLOCKS 1
100 #define REG_I_BLOCK_INTERNAL_PLL_CALC 0x01ca
102 /* Clock configurations, n = 0..2. REG_I_* frequency unit is 4 kHz. */
103 #define REG_I_OPCLK_4KHZ(n) ((n) * 6 + 0x01cc)
104 #define REG_I_MIN_OUTRATE_4KHZ(n) ((n) * 6 + 0x01ce)
105 #define REG_I_MAX_OUTRATE_4KHZ(n) ((n) * 6 + 0x01d0)
106 #define SCLK_PVI_FREQ 24000
107 #define SCLK_MIPI_FREQ 48000
108 #define PCLK_MIN_FREQ 6000
109 #define PCLK_MAX_FREQ 48000
110 #define REG_I_USE_REGS_API 0x01de
111 #define REG_I_INIT_PARAMS_UPDATED 0x01e0
112 #define REG_I_ERROR_INFO 0x01e2
114 /* General purpose parameters */
115 #define REG_USER_BRIGHTNESS 0x01e4
116 #define REG_USER_CONTRAST 0x01e6
117 #define REG_USER_SATURATION 0x01e8
118 #define REG_USER_SHARPBLUR 0x01ea
120 #define REG_G_SPEC_EFFECTS 0x01ee
121 #define REG_G_ENABLE_PREV 0x01f0
122 #define REG_G_ENABLE_PREV_CHG 0x01f2
123 #define REG_G_NEW_CFG_SYNC 0x01f8
124 #define REG_G_PREVREQ_IN_WIDTH 0x01fa
125 #define REG_G_PREVREQ_IN_HEIGHT 0x01fc
126 #define REG_G_PREVREQ_IN_XOFFS 0x01fe
127 #define REG_G_PREVREQ_IN_YOFFS 0x0200
128 #define REG_G_PREVZOOM_IN_WIDTH 0x020a
129 #define REG_G_PREVZOOM_IN_HEIGHT 0x020c
130 #define REG_G_PREVZOOM_IN_XOFFS 0x020e
131 #define REG_G_PREVZOOM_IN_YOFFS 0x0210
132 #define REG_G_INPUTS_CHANGE_REQ 0x021a
133 #define REG_G_ACTIVE_PREV_CFG 0x021c
134 #define REG_G_PREV_CFG_CHG 0x021e
135 #define REG_G_PREV_OPEN_AFTER_CH 0x0220
136 #define REG_G_PREV_CFG_ERROR 0x0222
137 #define CFG_ERROR_RANGE 0x0b
138 #define REG_G_PREV_CFG_BYPASS_CHANGED 0x022a
139 #define REG_G_ACTUAL_P_FR_TIME 0x023a
140 #define REG_G_ACTUAL_P_OUT_RATE 0x023c
141 #define REG_G_ACTUAL_C_FR_TIME 0x023e
142 #define REG_G_ACTUAL_C_OUT_RATE 0x0240
144 /* Preview control section. n = 0...4. */
145 #define PREG(n, x) ((n) * 0x26 + x)
146 #define REG_P_OUT_WIDTH(n) PREG(n, 0x0242)
147 #define REG_P_OUT_HEIGHT(n) PREG(n, 0x0244)
148 #define REG_P_FMT(n) PREG(n, 0x0246)
149 #define REG_P_MAX_OUT_RATE(n) PREG(n, 0x0248)
150 #define REG_P_MIN_OUT_RATE(n) PREG(n, 0x024a)
151 #define REG_P_PVI_MASK(n) PREG(n, 0x024c)
152 #define PVI_MASK_MIPI 0x52
153 #define REG_P_CLK_INDEX(n) PREG(n, 0x024e)
154 #define CLK_PVI_INDEX 0
155 #define CLK_MIPI_INDEX NPVI_CLOCKS
156 #define REG_P_FR_RATE_TYPE(n) PREG(n, 0x0250)
157 #define FR_RATE_DYNAMIC 0
158 #define FR_RATE_FIXED 1
159 #define FR_RATE_FIXED_ACCURATE 2
160 #define REG_P_FR_RATE_Q_TYPE(n) PREG(n, 0x0252)
161 #define FR_RATE_Q_DYNAMIC 0
162 #define FR_RATE_Q_BEST_FRRATE 1 /* Binning enabled */
163 #define FR_RATE_Q_BEST_QUALITY 2 /* Binning disabled */
164 /* Frame period in 0.1 ms units */
165 #define REG_P_MAX_FR_TIME(n) PREG(n, 0x0254)
166 #define REG_P_MIN_FR_TIME(n) PREG(n, 0x0256)
167 #define S5K5BAF_MIN_FR_TIME 333 /* x100 us */
168 #define S5K5BAF_MAX_FR_TIME 6500 /* x100 us */
169 /* The below 5 registers are for "device correction" values */
170 #define REG_P_SATURATION(n) PREG(n, 0x0258)
171 #define REG_P_SHARP_BLUR(n) PREG(n, 0x025a)
172 #define REG_P_GLAMOUR(n) PREG(n, 0x025c)
173 #define REG_P_COLORTEMP(n) PREG(n, 0x025e)
174 #define REG_P_GAMMA_INDEX(n) PREG(n, 0x0260)
175 #define REG_P_PREV_MIRROR(n) PREG(n, 0x0262)
176 #define REG_P_CAP_MIRROR(n) PREG(n, 0x0264)
177 #define REG_P_CAP_ROTATION(n) PREG(n, 0x0266)
179 /* Extended image property controls */
180 /* Exposure time in 10 us units */
181 #define REG_SF_USR_EXPOSURE_L 0x03bc
182 #define REG_SF_USR_EXPOSURE_H 0x03be
183 #define REG_SF_USR_EXPOSURE_CHG 0x03c0
184 #define REG_SF_USR_TOT_GAIN 0x03c2
185 #define REG_SF_USR_TOT_GAIN_CHG 0x03c4
186 #define REG_SF_RGAIN 0x03c6
187 #define REG_SF_RGAIN_CHG 0x03c8
188 #define REG_SF_GGAIN 0x03ca
189 #define REG_SF_GGAIN_CHG 0x03cc
190 #define REG_SF_BGAIN 0x03ce
191 #define REG_SF_BGAIN_CHG 0x03d0
192 #define REG_SF_WBGAIN_CHG 0x03d2
193 #define REG_SF_FLICKER_QUANT 0x03d4
194 #define REG_SF_FLICKER_QUANT_CHG 0x03d6
196 /* Output interface (parallel/MIPI) setup */
197 #define REG_OIF_EN_MIPI_LANES 0x03f2
198 #define REG_OIF_EN_PACKETS 0x03f4
199 #define EN_PACKETS_CSI2 0xc3
200 #define REG_OIF_CFG_CHG 0x03f6
202 /* Auto-algorithms enable mask */
203 #define REG_DBG_AUTOALG_EN 0x03f8
204 #define AALG_ALL_EN BIT(0)
205 #define AALG_AE_EN BIT(1)
206 #define AALG_DIVLEI_EN BIT(2)
207 #define AALG_WB_EN BIT(3)
208 #define AALG_USE_WB_FOR_ISP BIT(4)
209 #define AALG_FLICKER_EN BIT(5)
210 #define AALG_FIT_EN BIT(6)
211 #define AALG_WRHW_EN BIT(7)
213 /* Pointers to color correction matrices */
214 #define REG_PTR_CCM_HORIZON 0x06d0
215 #define REG_PTR_CCM_INCANDESCENT 0x06d4
216 #define REG_PTR_CCM_WARM_WHITE 0x06d8
217 #define REG_PTR_CCM_COOL_WHITE 0x06dc
218 #define REG_PTR_CCM_DL50 0x06e0
219 #define REG_PTR_CCM_DL65 0x06e4
220 #define REG_PTR_CCM_OUTDOOR 0x06ec
222 #define REG_ARR_CCM(n) (0x2800 + 36 * (n))
224 static const char * const s5k5baf_supply_names
[] = {
225 "vdda", /* Analog power supply 2.8V (2.6V to 3.0V) */
226 "vddreg", /* Regulator input power supply 1.8V (1.7V to 1.9V)
227 or 2.8V (2.6V to 3.0) */
228 "vddio", /* I/O power supply 1.8V (1.65V to 1.95V)
229 or 2.8V (2.5V to 3.1V) */
231 #define S5K5BAF_NUM_SUPPLIES ARRAY_SIZE(s5k5baf_supply_names)
233 struct s5k5baf_gpio
{
238 enum s5k5baf_gpio_id
{
246 #define NUM_CIS_PADS 1
247 #define NUM_ISP_PADS 2
249 struct s5k5baf_pixfmt
{
250 enum v4l2_mbus_pixelcode code
;
252 /* REG_P_FMT(x) register value */
256 struct s5k5baf_ctrls
{
257 struct v4l2_ctrl_handler handler
;
258 struct { /* Auto / manual white balance cluster */
259 struct v4l2_ctrl
*awb
;
260 struct v4l2_ctrl
*gain_red
;
261 struct v4l2_ctrl
*gain_blue
;
263 struct { /* Mirror cluster */
264 struct v4l2_ctrl
*hflip
;
265 struct v4l2_ctrl
*vflip
;
267 struct { /* Auto exposure / manual exposure and gain cluster */
268 struct v4l2_ctrl
*auto_exp
;
269 struct v4l2_ctrl
*exposure
;
270 struct v4l2_ctrl
*gain
;
290 struct s5k5baf_gpio gpios
[NUM_GPIOS
];
291 enum v4l2_mbus_type bus_type
;
293 struct regulator_bulk_data supplies
[S5K5BAF_NUM_SUPPLIES
];
298 struct s5k5baf_fw
*fw
;
300 struct v4l2_subdev cis_sd
;
301 struct media_pad cis_pad
;
303 struct v4l2_subdev sd
;
304 struct media_pad pads
[NUM_ISP_PADS
];
306 /* protects the struct members below */
311 struct v4l2_rect crop_sink
;
312 struct v4l2_rect compose
;
313 struct v4l2_rect crop_source
;
314 /* index to s5k5baf_formats array */
316 /* actual frame interval in 100us */
318 /* requested frame interval in 100us */
320 /* cache for REG_DBG_AUTOALG_EN register */
323 struct s5k5baf_ctrls ctrls
;
325 unsigned int streaming
:1;
326 unsigned int apply_cfg
:1;
327 unsigned int apply_crop
:1;
328 unsigned int valid_auto_alg
:1;
332 static const struct s5k5baf_pixfmt s5k5baf_formats
[] = {
333 { V4L2_MBUS_FMT_VYUY8_2X8
, V4L2_COLORSPACE_JPEG
, 5 },
335 { V4L2_MBUS_FMT_VYUY8_2X8
, V4L2_COLORSPACE_REC709
, 6 },
336 { V4L2_MBUS_FMT_RGB565_2X8_BE
, V4L2_COLORSPACE_JPEG
, 0 },
339 static struct v4l2_rect s5k5baf_cis_rect
= {
340 0, 0, S5K5BAF_CIS_WIDTH
, S5K5BAF_CIS_HEIGHT
343 /* Setfile contains set of I2C command sequences. Each sequence has its ID.
346 * u16 count; number of sequences
348 * u16 id; sequence id
349 * u16 offset; sequence offset in data array
351 * u16 data[*]; array containing sequences
354 static int s5k5baf_fw_parse(struct device
*dev
, struct s5k5baf_fw
**fw
,
355 size_t count
, const u16
*data
)
357 struct s5k5baf_fw
*f
;
361 if (count
< S5K5BAG_FW_TAG_LEN
+ 1) {
362 dev_err(dev
, "firmware file too short (%zu)\n", count
);
366 ret
= memcmp(data
, S5K5BAF_FW_TAG
, S5K5BAG_FW_TAG_LEN
* sizeof(u16
));
368 dev_err(dev
, "invalid firmware magic number\n");
372 data
+= S5K5BAG_FW_TAG_LEN
;
373 count
-= S5K5BAG_FW_TAG_LEN
;
375 d
= devm_kzalloc(dev
, count
* sizeof(u16
), GFP_KERNEL
);
377 for (i
= 0; i
< count
; ++i
)
378 d
[i
] = le16_to_cpu(data
[i
]);
380 f
= (struct s5k5baf_fw
*)d
;
381 if (count
< 1 + 2 * f
->count
) {
382 dev_err(dev
, "invalid firmware header (count=%d size=%zu)\n",
383 f
->count
, 2 * (count
+ S5K5BAG_FW_TAG_LEN
));
387 d
+= 1 + 2 * f
->count
;
389 for (i
= 0; i
< f
->count
; ++i
) {
390 if (f
->seq
[i
].offset
+ d
<= end
)
392 dev_err(dev
, "invalid firmware header (seq=%d)\n", i
);
401 static inline struct v4l2_subdev
*ctrl_to_sd(struct v4l2_ctrl
*ctrl
)
403 return &container_of(ctrl
->handler
, struct s5k5baf
, ctrls
.handler
)->sd
;
406 static inline bool s5k5baf_is_cis_subdev(struct v4l2_subdev
*sd
)
408 return sd
->entity
.type
== MEDIA_ENT_T_V4L2_SUBDEV_SENSOR
;
411 static inline struct s5k5baf
*to_s5k5baf(struct v4l2_subdev
*sd
)
413 if (s5k5baf_is_cis_subdev(sd
))
414 return container_of(sd
, struct s5k5baf
, cis_sd
);
416 return container_of(sd
, struct s5k5baf
, sd
);
419 static u16
s5k5baf_i2c_read(struct s5k5baf
*state
, u16 addr
)
421 struct i2c_client
*c
= v4l2_get_subdevdata(&state
->sd
);
423 struct i2c_msg msg
[] = {
424 { .addr
= c
->addr
, .flags
= 0,
425 .len
= 2, .buf
= (u8
*)&w
},
426 { .addr
= c
->addr
, .flags
= I2C_M_RD
,
427 .len
= 2, .buf
= (u8
*)&r
},
434 w
= cpu_to_be16(addr
);
435 ret
= i2c_transfer(c
->adapter
, msg
, 2);
438 v4l2_dbg(3, debug
, c
, "i2c_read: 0x%04x : 0x%04x\n", addr
, r
);
441 v4l2_err(c
, "i2c_read: error during transfer (%d)\n", ret
);
447 static void s5k5baf_i2c_write(struct s5k5baf
*state
, u16 addr
, u16 val
)
449 u8 buf
[4] = { addr
>> 8, addr
& 0xFF, val
>> 8, val
& 0xFF };
450 struct i2c_client
*c
= v4l2_get_subdevdata(&state
->sd
);
456 ret
= i2c_master_send(c
, buf
, 4);
457 v4l2_dbg(3, debug
, c
, "i2c_write: 0x%04x : 0x%04x\n", addr
, val
);
460 v4l2_err(c
, "i2c_write: error during transfer (%d)\n", ret
);
465 static u16
s5k5baf_read(struct s5k5baf
*state
, u16 addr
)
467 s5k5baf_i2c_write(state
, REG_CMDRD_ADDR
, addr
);
468 return s5k5baf_i2c_read(state
, REG_CMD_BUF
);
471 static void s5k5baf_write(struct s5k5baf
*state
, u16 addr
, u16 val
)
473 s5k5baf_i2c_write(state
, REG_CMDWR_ADDR
, addr
);
474 s5k5baf_i2c_write(state
, REG_CMD_BUF
, val
);
477 static void s5k5baf_write_arr_seq(struct s5k5baf
*state
, u16 addr
,
478 u16 count
, const u16
*seq
)
480 struct i2c_client
*c
= v4l2_get_subdevdata(&state
->sd
);
481 __be16 buf
[count
+ 1];
484 s5k5baf_i2c_write(state
, REG_CMDWR_ADDR
, addr
);
488 buf
[0] = __constant_cpu_to_be16(REG_CMD_BUF
);
489 for (n
= 1; n
<= count
; ++n
)
490 buf
[n
] = cpu_to_be16(*seq
++);
493 ret
= i2c_master_send(c
, (char *)buf
, n
);
494 v4l2_dbg(3, debug
, c
, "i2c_write_seq(count=%d): %*ph\n", count
,
495 min(2 * count
, 64), seq
- count
);
498 v4l2_err(c
, "i2c_write_seq: error during transfer (%d)\n", ret
);
503 #define s5k5baf_write_seq(state, addr, seq...) \
504 s5k5baf_write_arr_seq(state, addr, sizeof((char[]){ seq }), \
505 (const u16 []){ seq });
507 /* add items count at the beginning of the list */
508 #define NSEQ(seq...) sizeof((char[]){ seq }), seq
511 * s5k5baf_write_nseq() - Writes sequences of values to sensor memory via i2c
512 * @nseq: sequence of u16 words in format:
513 * (N, address, value[1]...value[N-1])*,0
515 * u16 seq[] = { NSEQ(0x4000, 1, 1), NSEQ(0x4010, 640, 480), 0 };
516 * ret = s5k5baf_write_nseq(c, seq);
518 static void s5k5baf_write_nseq(struct s5k5baf
*state
, const u16
*nseq
)
522 while ((count
= *nseq
++)) {
526 s5k5baf_write_arr_seq(state
, addr
, count
, nseq
);
531 static void s5k5baf_synchronize(struct s5k5baf
*state
, int timeout
, u16 addr
)
533 unsigned long end
= jiffies
+ msecs_to_jiffies(timeout
);
536 s5k5baf_write(state
, addr
, 1);
538 reg
= s5k5baf_read(state
, addr
);
539 if (state
->error
|| !reg
)
541 usleep_range(5000, 10000);
542 } while (time_is_after_jiffies(end
));
544 v4l2_err(&state
->sd
, "timeout on register synchronize (%#x)\n", addr
);
545 state
->error
= -ETIMEDOUT
;
548 static u16
*s5k5baf_fw_get_seq(struct s5k5baf
*state
, u16 seq_id
)
550 struct s5k5baf_fw
*fw
= state
->fw
;
557 data
= fw
->data
+ 2 * fw
->count
;
559 for (i
= 0; i
< fw
->count
; ++i
) {
560 if (fw
->seq
[i
].id
== seq_id
)
561 return data
+ fw
->seq
[i
].offset
;
567 static void s5k5baf_hw_patch(struct s5k5baf
*state
)
569 u16
*seq
= s5k5baf_fw_get_seq(state
, S5K5BAF_FW_ID_PATCH
);
572 s5k5baf_write_nseq(state
, seq
);
575 static void s5k5baf_hw_set_clocks(struct s5k5baf
*state
)
577 unsigned long mclk
= state
->mclk_frequency
/ 1000;
579 static const u16 nseq_clk_cfg
[] = {
580 NSEQ(REG_I_USE_NPVI_CLOCKS
,
581 NPVI_CLOCKS
, NMIPI_CLOCKS
, 0,
582 SCLK_PVI_FREQ
/ 4, PCLK_MIN_FREQ
/ 4, PCLK_MAX_FREQ
/ 4,
583 SCLK_MIPI_FREQ
/ 4, PCLK_MIN_FREQ
/ 4, PCLK_MAX_FREQ
/ 4),
584 NSEQ(REG_I_USE_REGS_API
, 1),
588 s5k5baf_write_seq(state
, REG_I_INCLK_FREQ_L
, mclk
& 0xffff, mclk
>> 16);
589 s5k5baf_write_nseq(state
, nseq_clk_cfg
);
591 s5k5baf_synchronize(state
, 250, REG_I_INIT_PARAMS_UPDATED
);
592 status
= s5k5baf_read(state
, REG_I_ERROR_INFO
);
593 if (!state
->error
&& status
) {
594 v4l2_err(&state
->sd
, "error configuring PLL (%d)\n", status
);
595 state
->error
= -EINVAL
;
599 /* set custom color correction matrices for various illuminations */
600 static void s5k5baf_hw_set_ccm(struct s5k5baf
*state
)
602 u16
*seq
= s5k5baf_fw_get_seq(state
, S5K5BAF_FW_ID_CCM
);
605 s5k5baf_write_nseq(state
, seq
);
608 /* CIS sensor tuning, based on undocumented android driver code */
609 static void s5k5baf_hw_set_cis(struct s5k5baf
*state
)
611 u16
*seq
= s5k5baf_fw_get_seq(state
, S5K5BAF_FW_ID_CIS
);
616 s5k5baf_i2c_write(state
, REG_CMDWR_PAGE
, PAGE_IF_HW
);
617 s5k5baf_write_nseq(state
, seq
);
618 s5k5baf_i2c_write(state
, REG_CMDWR_PAGE
, PAGE_IF_SW
);
621 static void s5k5baf_hw_sync_cfg(struct s5k5baf
*state
)
623 s5k5baf_write(state
, REG_G_PREV_CFG_CHG
, 1);
624 if (state
->apply_crop
) {
625 s5k5baf_write(state
, REG_G_INPUTS_CHANGE_REQ
, 1);
626 s5k5baf_write(state
, REG_G_PREV_CFG_BYPASS_CHANGED
, 1);
628 s5k5baf_synchronize(state
, 500, REG_G_NEW_CFG_SYNC
);
630 /* Set horizontal and vertical image flipping */
631 static void s5k5baf_hw_set_mirror(struct s5k5baf
*state
)
633 u16 flip
= state
->ctrls
.vflip
->val
| (state
->ctrls
.vflip
->val
<< 1);
635 s5k5baf_write(state
, REG_P_PREV_MIRROR(0), flip
);
636 if (state
->streaming
)
637 s5k5baf_hw_sync_cfg(state
);
640 static void s5k5baf_hw_set_alg(struct s5k5baf
*state
, u16 alg
, bool enable
)
642 u16 cur_alg
, new_alg
;
644 if (!state
->valid_auto_alg
)
645 cur_alg
= s5k5baf_read(state
, REG_DBG_AUTOALG_EN
);
647 cur_alg
= state
->auto_alg
;
649 new_alg
= enable
? (cur_alg
| alg
) : (cur_alg
& ~alg
);
651 if (new_alg
!= cur_alg
)
652 s5k5baf_write(state
, REG_DBG_AUTOALG_EN
, new_alg
);
657 state
->valid_auto_alg
= 1;
658 state
->auto_alg
= new_alg
;
661 /* Configure auto/manual white balance and R/G/B gains */
662 static void s5k5baf_hw_set_awb(struct s5k5baf
*state
, int awb
)
664 struct s5k5baf_ctrls
*ctrls
= &state
->ctrls
;
667 s5k5baf_write_seq(state
, REG_SF_RGAIN
,
668 ctrls
->gain_red
->val
, 1,
669 S5K5BAF_GAIN_GREEN_DEF
, 1,
670 ctrls
->gain_blue
->val
, 1,
673 s5k5baf_hw_set_alg(state
, AALG_WB_EN
, awb
);
676 /* Program FW with exposure time, 'exposure' in us units */
677 static void s5k5baf_hw_set_user_exposure(struct s5k5baf
*state
, int exposure
)
679 unsigned int time
= exposure
/ 10;
681 s5k5baf_write_seq(state
, REG_SF_USR_EXPOSURE_L
,
682 time
& 0xffff, time
>> 16, 1);
685 static void s5k5baf_hw_set_user_gain(struct s5k5baf
*state
, int gain
)
687 s5k5baf_write_seq(state
, REG_SF_USR_TOT_GAIN
, gain
, 1);
690 /* Set auto/manual exposure and total gain */
691 static void s5k5baf_hw_set_auto_exposure(struct s5k5baf
*state
, int value
)
693 if (value
== V4L2_EXPOSURE_AUTO
) {
694 s5k5baf_hw_set_alg(state
, AALG_AE_EN
| AALG_DIVLEI_EN
, true);
696 unsigned int exp_time
= state
->ctrls
.exposure
->val
;
698 s5k5baf_hw_set_user_exposure(state
, exp_time
);
699 s5k5baf_hw_set_user_gain(state
, state
->ctrls
.gain
->val
);
700 s5k5baf_hw_set_alg(state
, AALG_AE_EN
| AALG_DIVLEI_EN
, false);
704 static void s5k5baf_hw_set_anti_flicker(struct s5k5baf
*state
, int v
)
706 if (v
== V4L2_CID_POWER_LINE_FREQUENCY_AUTO
) {
707 s5k5baf_hw_set_alg(state
, AALG_FLICKER_EN
, true);
709 /* The V4L2_CID_LINE_FREQUENCY control values match
710 * the register values */
711 s5k5baf_write_seq(state
, REG_SF_FLICKER_QUANT
, v
, 1);
712 s5k5baf_hw_set_alg(state
, AALG_FLICKER_EN
, false);
716 static void s5k5baf_hw_set_colorfx(struct s5k5baf
*state
, int val
)
718 static const u16 colorfx
[] = {
719 [V4L2_COLORFX_NONE
] = 0,
720 [V4L2_COLORFX_BW
] = 1,
721 [V4L2_COLORFX_NEGATIVE
] = 2,
722 [V4L2_COLORFX_SEPIA
] = 3,
723 [V4L2_COLORFX_SKY_BLUE
] = 4,
724 [V4L2_COLORFX_SKETCH
] = 5,
727 s5k5baf_write(state
, REG_G_SPEC_EFFECTS
, colorfx
[val
]);
730 static int s5k5baf_find_pixfmt(struct v4l2_mbus_framefmt
*mf
)
734 for (i
= 0; i
< ARRAY_SIZE(s5k5baf_formats
); i
++) {
735 if (mf
->colorspace
!= s5k5baf_formats
[i
].colorspace
)
737 if (mf
->code
== s5k5baf_formats
[i
].code
)
742 return (c
< 0) ? 0 : c
;
745 static int s5k5baf_clear_error(struct s5k5baf
*state
)
747 int ret
= state
->error
;
753 static int s5k5baf_hw_set_video_bus(struct s5k5baf
*state
)
757 if (state
->bus_type
== V4L2_MBUS_CSI2
)
758 en_pkts
= EN_PACKETS_CSI2
;
762 s5k5baf_write_seq(state
, REG_OIF_EN_MIPI_LANES
,
763 state
->nlanes
, en_pkts
, 1);
765 return s5k5baf_clear_error(state
);
768 static u16
s5k5baf_get_cfg_error(struct s5k5baf
*state
)
770 u16 err
= s5k5baf_read(state
, REG_G_PREV_CFG_ERROR
);
772 s5k5baf_write(state
, REG_G_PREV_CFG_ERROR
, 0);
776 static void s5k5baf_hw_set_fiv(struct s5k5baf
*state
, u16 fiv
)
778 s5k5baf_write(state
, REG_P_MAX_FR_TIME(0), fiv
);
779 s5k5baf_hw_sync_cfg(state
);
782 static void s5k5baf_hw_find_min_fiv(struct s5k5baf
*state
)
787 fiv
= s5k5baf_read(state
, REG_G_ACTUAL_P_FR_TIME
);
791 for (n
= 5; n
> 0; --n
) {
792 s5k5baf_hw_set_fiv(state
, fiv
);
793 err
= s5k5baf_get_cfg_error(state
);
797 case CFG_ERROR_RANGE
:
802 v4l2_info(&state
->sd
,
803 "found valid frame interval: %d00us\n", fiv
);
807 "error setting frame interval: %d\n", err
);
808 state
->error
= -EINVAL
;
811 v4l2_err(&state
->sd
, "cannot find correct frame interval\n");
812 state
->error
= -ERANGE
;
815 static void s5k5baf_hw_validate_cfg(struct s5k5baf
*state
)
819 err
= s5k5baf_get_cfg_error(state
);
825 state
->apply_cfg
= 1;
827 case CFG_ERROR_RANGE
:
828 s5k5baf_hw_find_min_fiv(state
);
830 state
->apply_cfg
= 1;
834 "error setting format: %d\n", err
);
835 state
->error
= -EINVAL
;
839 static void s5k5baf_rescale(struct v4l2_rect
*r
, const struct v4l2_rect
*v
,
840 const struct v4l2_rect
*n
,
841 const struct v4l2_rect
*d
)
843 r
->left
= v
->left
* n
->width
/ d
->width
;
844 r
->top
= v
->top
* n
->height
/ d
->height
;
845 r
->width
= v
->width
* n
->width
/ d
->width
;
846 r
->height
= v
->height
* n
->height
/ d
->height
;
849 static int s5k5baf_hw_set_crop_rects(struct s5k5baf
*state
)
851 struct v4l2_rect
*p
, r
;
855 p
= &state
->crop_sink
;
856 s5k5baf_write_seq(state
, REG_G_PREVREQ_IN_WIDTH
, p
->width
, p
->height
,
859 s5k5baf_rescale(&r
, &state
->crop_source
, &state
->crop_sink
,
861 s5k5baf_write_seq(state
, REG_G_PREVZOOM_IN_WIDTH
, r
.width
, r
.height
,
864 s5k5baf_synchronize(state
, 500, REG_G_INPUTS_CHANGE_REQ
);
865 s5k5baf_synchronize(state
, 500, REG_G_PREV_CFG_BYPASS_CHANGED
);
866 err
= s5k5baf_get_cfg_error(state
);
867 ret
= s5k5baf_clear_error(state
);
874 case CFG_ERROR_RANGE
:
875 /* retry crop with frame interval set to max */
876 s5k5baf_hw_set_fiv(state
, S5K5BAF_MAX_FR_TIME
);
877 err
= s5k5baf_get_cfg_error(state
);
878 ret
= s5k5baf_clear_error(state
);
883 "crop error on max frame interval: %d\n", err
);
884 state
->error
= -EINVAL
;
886 s5k5baf_hw_set_fiv(state
, state
->req_fiv
);
887 s5k5baf_hw_validate_cfg(state
);
890 v4l2_err(&state
->sd
, "crop error: %d\n", err
);
894 if (!state
->apply_cfg
)
897 p
= &state
->crop_source
;
898 s5k5baf_write_seq(state
, REG_P_OUT_WIDTH(0), p
->width
, p
->height
);
899 s5k5baf_hw_set_fiv(state
, state
->req_fiv
);
900 s5k5baf_hw_validate_cfg(state
);
902 return s5k5baf_clear_error(state
);
905 static void s5k5baf_hw_set_config(struct s5k5baf
*state
)
907 u16 reg_fmt
= s5k5baf_formats
[state
->pixfmt
].reg_p_fmt
;
908 struct v4l2_rect
*r
= &state
->crop_source
;
910 s5k5baf_write_seq(state
, REG_P_OUT_WIDTH(0),
911 r
->width
, r
->height
, reg_fmt
,
912 PCLK_MAX_FREQ
>> 2, PCLK_MIN_FREQ
>> 2,
913 PVI_MASK_MIPI
, CLK_MIPI_INDEX
,
914 FR_RATE_FIXED
, FR_RATE_Q_DYNAMIC
,
915 state
->req_fiv
, S5K5BAF_MIN_FR_TIME
);
916 s5k5baf_hw_sync_cfg(state
);
917 s5k5baf_hw_validate_cfg(state
);
921 static void s5k5baf_hw_set_test_pattern(struct s5k5baf
*state
, int id
)
923 s5k5baf_i2c_write(state
, REG_PATTERN_WIDTH
, 800);
924 s5k5baf_i2c_write(state
, REG_PATTERN_HEIGHT
, 511);
925 s5k5baf_i2c_write(state
, REG_PATTERN_PARAM
, 0);
926 s5k5baf_i2c_write(state
, REG_PATTERN_SET
, id
);
929 static void s5k5baf_gpio_assert(struct s5k5baf
*state
, int id
)
931 struct s5k5baf_gpio
*gpio
= &state
->gpios
[id
];
933 gpio_set_value(gpio
->gpio
, gpio
->level
);
936 static void s5k5baf_gpio_deassert(struct s5k5baf
*state
, int id
)
938 struct s5k5baf_gpio
*gpio
= &state
->gpios
[id
];
940 gpio_set_value(gpio
->gpio
, !gpio
->level
);
943 static int s5k5baf_power_on(struct s5k5baf
*state
)
947 ret
= regulator_bulk_enable(S5K5BAF_NUM_SUPPLIES
, state
->supplies
);
951 ret
= clk_set_rate(state
->clock
, state
->mclk_frequency
);
955 ret
= clk_prepare_enable(state
->clock
);
959 v4l2_dbg(1, debug
, &state
->sd
, "clock frequency: %ld\n",
960 clk_get_rate(state
->clock
));
962 s5k5baf_gpio_deassert(state
, STBY
);
963 usleep_range(50, 100);
964 s5k5baf_gpio_deassert(state
, RST
);
968 regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES
, state
->supplies
);
970 v4l2_err(&state
->sd
, "%s() failed (%d)\n", __func__
, ret
);
974 static int s5k5baf_power_off(struct s5k5baf
*state
)
978 state
->streaming
= 0;
979 state
->apply_cfg
= 0;
980 state
->apply_crop
= 0;
982 s5k5baf_gpio_assert(state
, RST
);
983 s5k5baf_gpio_assert(state
, STBY
);
985 if (!IS_ERR(state
->clock
))
986 clk_disable_unprepare(state
->clock
);
988 ret
= regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES
,
991 v4l2_err(&state
->sd
, "failed to disable regulators\n");
996 static void s5k5baf_hw_init(struct s5k5baf
*state
)
998 s5k5baf_i2c_write(state
, AHB_MSB_ADDR_PTR
, PAGE_IF_HW
);
999 s5k5baf_i2c_write(state
, REG_CLEAR_HOST_INT
, 0);
1000 s5k5baf_i2c_write(state
, REG_SW_LOAD_COMPLETE
, 1);
1001 s5k5baf_i2c_write(state
, REG_CMDRD_PAGE
, PAGE_IF_SW
);
1002 s5k5baf_i2c_write(state
, REG_CMDWR_PAGE
, PAGE_IF_SW
);
1006 * V4L2 subdev core and video operations
1009 static void s5k5baf_initialize_data(struct s5k5baf
*state
)
1012 state
->req_fiv
= 10000 / 15;
1013 state
->fiv
= state
->req_fiv
;
1014 state
->valid_auto_alg
= 0;
1017 static int s5k5baf_load_setfile(struct s5k5baf
*state
)
1019 struct i2c_client
*c
= v4l2_get_subdevdata(&state
->sd
);
1020 const struct firmware
*fw
;
1023 ret
= request_firmware(&fw
, S5K5BAF_FW_FILENAME
, &c
->dev
);
1025 dev_warn(&c
->dev
, "firmware file (%s) not loaded\n",
1026 S5K5BAF_FW_FILENAME
);
1030 ret
= s5k5baf_fw_parse(&c
->dev
, &state
->fw
, fw
->size
/ 2,
1033 release_firmware(fw
);
1038 static int s5k5baf_set_power(struct v4l2_subdev
*sd
, int on
)
1040 struct s5k5baf
*state
= to_s5k5baf(sd
);
1043 mutex_lock(&state
->lock
);
1045 if (!on
!= state
->power
)
1049 if (state
->fw
== NULL
)
1050 s5k5baf_load_setfile(state
);
1052 s5k5baf_initialize_data(state
);
1053 ret
= s5k5baf_power_on(state
);
1057 s5k5baf_hw_init(state
);
1058 s5k5baf_hw_patch(state
);
1059 s5k5baf_i2c_write(state
, REG_SET_HOST_INT
, 1);
1060 s5k5baf_hw_set_clocks(state
);
1062 ret
= s5k5baf_hw_set_video_bus(state
);
1066 s5k5baf_hw_set_cis(state
);
1067 s5k5baf_hw_set_ccm(state
);
1069 ret
= s5k5baf_clear_error(state
);
1073 s5k5baf_power_off(state
);
1078 mutex_unlock(&state
->lock
);
1081 ret
= v4l2_ctrl_handler_setup(&state
->ctrls
.handler
);
1086 static void s5k5baf_hw_set_stream(struct s5k5baf
*state
, int enable
)
1088 s5k5baf_write_seq(state
, REG_G_ENABLE_PREV
, enable
, 1);
1091 static int s5k5baf_s_stream(struct v4l2_subdev
*sd
, int on
)
1093 struct s5k5baf
*state
= to_s5k5baf(sd
);
1096 mutex_lock(&state
->lock
);
1098 if (state
->streaming
== !!on
) {
1104 s5k5baf_hw_set_config(state
);
1105 ret
= s5k5baf_hw_set_crop_rects(state
);
1108 s5k5baf_hw_set_stream(state
, 1);
1109 s5k5baf_i2c_write(state
, 0xb0cc, 0x000b);
1111 s5k5baf_hw_set_stream(state
, 0);
1113 ret
= s5k5baf_clear_error(state
);
1115 state
->streaming
= !state
->streaming
;
1118 mutex_unlock(&state
->lock
);
1123 static int s5k5baf_g_frame_interval(struct v4l2_subdev
*sd
,
1124 struct v4l2_subdev_frame_interval
*fi
)
1126 struct s5k5baf
*state
= to_s5k5baf(sd
);
1128 mutex_lock(&state
->lock
);
1129 fi
->interval
.numerator
= state
->fiv
;
1130 fi
->interval
.denominator
= 10000;
1131 mutex_unlock(&state
->lock
);
1136 static void s5k5baf_set_frame_interval(struct s5k5baf
*state
,
1137 struct v4l2_subdev_frame_interval
*fi
)
1139 struct v4l2_fract
*i
= &fi
->interval
;
1141 if (fi
->interval
.denominator
== 0)
1142 state
->req_fiv
= S5K5BAF_MAX_FR_TIME
;
1144 state
->req_fiv
= clamp_t(u32
,
1145 i
->numerator
* 10000 / i
->denominator
,
1146 S5K5BAF_MIN_FR_TIME
,
1147 S5K5BAF_MAX_FR_TIME
);
1149 state
->fiv
= state
->req_fiv
;
1150 if (state
->apply_cfg
) {
1151 s5k5baf_hw_set_fiv(state
, state
->req_fiv
);
1152 s5k5baf_hw_validate_cfg(state
);
1154 *i
= (struct v4l2_fract
){ state
->fiv
, 10000 };
1155 if (state
->fiv
== state
->req_fiv
)
1156 v4l2_info(&state
->sd
, "frame interval changed to %d00us\n",
1160 static int s5k5baf_s_frame_interval(struct v4l2_subdev
*sd
,
1161 struct v4l2_subdev_frame_interval
*fi
)
1163 struct s5k5baf
*state
= to_s5k5baf(sd
);
1165 mutex_lock(&state
->lock
);
1166 s5k5baf_set_frame_interval(state
, fi
);
1167 mutex_unlock(&state
->lock
);
1172 * V4L2 subdev pad level and video operations
1174 static int s5k5baf_enum_frame_interval(struct v4l2_subdev
*sd
,
1175 struct v4l2_subdev_fh
*fh
,
1176 struct v4l2_subdev_frame_interval_enum
*fie
)
1178 if (fie
->index
> S5K5BAF_MAX_FR_TIME
- S5K5BAF_MIN_FR_TIME
||
1179 fie
->pad
!= PAD_CIS
)
1182 v4l_bound_align_image(&fie
->width
, S5K5BAF_WIN_WIDTH_MIN
,
1183 S5K5BAF_CIS_WIDTH
, 1,
1184 &fie
->height
, S5K5BAF_WIN_HEIGHT_MIN
,
1185 S5K5BAF_CIS_HEIGHT
, 1, 0);
1187 fie
->interval
.numerator
= S5K5BAF_MIN_FR_TIME
+ fie
->index
;
1188 fie
->interval
.denominator
= 10000;
1193 static int s5k5baf_enum_mbus_code(struct v4l2_subdev
*sd
,
1194 struct v4l2_subdev_fh
*fh
,
1195 struct v4l2_subdev_mbus_code_enum
*code
)
1197 if (code
->pad
== PAD_CIS
) {
1198 if (code
->index
> 0)
1200 code
->code
= V4L2_MBUS_FMT_FIXED
;
1204 if (code
->index
>= ARRAY_SIZE(s5k5baf_formats
))
1207 code
->code
= s5k5baf_formats
[code
->index
].code
;
1211 static int s5k5baf_enum_frame_size(struct v4l2_subdev
*sd
,
1212 struct v4l2_subdev_fh
*fh
,
1213 struct v4l2_subdev_frame_size_enum
*fse
)
1220 if (fse
->pad
== PAD_CIS
) {
1221 fse
->code
= V4L2_MBUS_FMT_FIXED
;
1222 fse
->min_width
= S5K5BAF_CIS_WIDTH
;
1223 fse
->max_width
= S5K5BAF_CIS_WIDTH
;
1224 fse
->min_height
= S5K5BAF_CIS_HEIGHT
;
1225 fse
->max_height
= S5K5BAF_CIS_HEIGHT
;
1229 i
= ARRAY_SIZE(s5k5baf_formats
);
1231 if (fse
->code
== s5k5baf_formats
[i
].code
)
1233 fse
->code
= s5k5baf_formats
[i
].code
;
1234 fse
->min_width
= S5K5BAF_WIN_WIDTH_MIN
;
1235 fse
->max_width
= S5K5BAF_CIS_WIDTH
;
1236 fse
->max_height
= S5K5BAF_WIN_HEIGHT_MIN
;
1237 fse
->min_height
= S5K5BAF_CIS_HEIGHT
;
1242 static void s5k5baf_try_cis_format(struct v4l2_mbus_framefmt
*mf
)
1244 mf
->width
= S5K5BAF_CIS_WIDTH
;
1245 mf
->height
= S5K5BAF_CIS_HEIGHT
;
1246 mf
->code
= V4L2_MBUS_FMT_FIXED
;
1247 mf
->colorspace
= V4L2_COLORSPACE_JPEG
;
1248 mf
->field
= V4L2_FIELD_NONE
;
1251 static int s5k5baf_try_isp_format(struct v4l2_mbus_framefmt
*mf
)
1255 v4l_bound_align_image(&mf
->width
, S5K5BAF_WIN_WIDTH_MIN
,
1256 S5K5BAF_CIS_WIDTH
, 1,
1257 &mf
->height
, S5K5BAF_WIN_HEIGHT_MIN
,
1258 S5K5BAF_CIS_HEIGHT
, 1, 0);
1260 pixfmt
= s5k5baf_find_pixfmt(mf
);
1262 mf
->colorspace
= s5k5baf_formats
[pixfmt
].colorspace
;
1263 mf
->code
= s5k5baf_formats
[pixfmt
].code
;
1264 mf
->field
= V4L2_FIELD_NONE
;
1269 static int s5k5baf_get_fmt(struct v4l2_subdev
*sd
, struct v4l2_subdev_fh
*fh
,
1270 struct v4l2_subdev_format
*fmt
)
1272 struct s5k5baf
*state
= to_s5k5baf(sd
);
1273 const struct s5k5baf_pixfmt
*pixfmt
;
1274 struct v4l2_mbus_framefmt
*mf
;
1276 if (fmt
->which
== V4L2_SUBDEV_FORMAT_TRY
) {
1277 mf
= v4l2_subdev_get_try_format(fh
, fmt
->pad
);
1283 if (fmt
->pad
== PAD_CIS
) {
1284 s5k5baf_try_cis_format(mf
);
1287 mf
->field
= V4L2_FIELD_NONE
;
1288 mutex_lock(&state
->lock
);
1289 pixfmt
= &s5k5baf_formats
[state
->pixfmt
];
1290 mf
->width
= state
->crop_source
.width
;
1291 mf
->height
= state
->crop_source
.height
;
1292 mf
->code
= pixfmt
->code
;
1293 mf
->colorspace
= pixfmt
->colorspace
;
1294 mutex_unlock(&state
->lock
);
1299 static int s5k5baf_set_fmt(struct v4l2_subdev
*sd
, struct v4l2_subdev_fh
*fh
,
1300 struct v4l2_subdev_format
*fmt
)
1302 struct v4l2_mbus_framefmt
*mf
= &fmt
->format
;
1303 struct s5k5baf
*state
= to_s5k5baf(sd
);
1304 const struct s5k5baf_pixfmt
*pixfmt
;
1307 if (fmt
->which
== V4L2_SUBDEV_FORMAT_TRY
) {
1308 *v4l2_subdev_get_try_format(fh
, fmt
->pad
) = *mf
;
1312 if (fmt
->pad
== PAD_CIS
) {
1313 s5k5baf_try_cis_format(mf
);
1317 mutex_lock(&state
->lock
);
1319 if (state
->streaming
) {
1320 mutex_unlock(&state
->lock
);
1324 state
->pixfmt
= s5k5baf_try_isp_format(mf
);
1325 pixfmt
= &s5k5baf_formats
[state
->pixfmt
];
1326 mf
->code
= pixfmt
->code
;
1327 mf
->colorspace
= pixfmt
->colorspace
;
1328 mf
->width
= state
->crop_source
.width
;
1329 mf
->height
= state
->crop_source
.height
;
1331 mutex_unlock(&state
->lock
);
1335 enum selection_rect
{ R_CIS
, R_CROP_SINK
, R_COMPOSE
, R_CROP_SOURCE
, R_INVALID
};
1337 static enum selection_rect
s5k5baf_get_sel_rect(u32 pad
, u32 target
)
1340 case V4L2_SEL_TGT_CROP_BOUNDS
:
1341 return pad
? R_COMPOSE
: R_CIS
;
1342 case V4L2_SEL_TGT_CROP
:
1343 return pad
? R_CROP_SOURCE
: R_CROP_SINK
;
1344 case V4L2_SEL_TGT_COMPOSE_BOUNDS
:
1345 return pad
? R_INVALID
: R_CROP_SINK
;
1346 case V4L2_SEL_TGT_COMPOSE
:
1347 return pad
? R_INVALID
: R_COMPOSE
;
1353 static int s5k5baf_is_bound_target(u32 target
)
1355 return target
== V4L2_SEL_TGT_CROP_BOUNDS
||
1356 target
== V4L2_SEL_TGT_COMPOSE_BOUNDS
;
1359 static int s5k5baf_get_selection(struct v4l2_subdev
*sd
,
1360 struct v4l2_subdev_fh
*fh
,
1361 struct v4l2_subdev_selection
*sel
)
1363 static enum selection_rect rtype
;
1364 struct s5k5baf
*state
= to_s5k5baf(sd
);
1366 rtype
= s5k5baf_get_sel_rect(sel
->pad
, sel
->target
);
1372 sel
->r
= s5k5baf_cis_rect
;
1378 if (sel
->which
== V4L2_SUBDEV_FORMAT_TRY
) {
1379 if (rtype
== R_COMPOSE
)
1380 sel
->r
= *v4l2_subdev_get_try_compose(fh
, sel
->pad
);
1382 sel
->r
= *v4l2_subdev_get_try_crop(fh
, sel
->pad
);
1386 mutex_lock(&state
->lock
);
1389 sel
->r
= state
->crop_sink
;
1392 sel
->r
= state
->compose
;
1395 sel
->r
= state
->crop_source
;
1400 if (s5k5baf_is_bound_target(sel
->target
)) {
1404 mutex_unlock(&state
->lock
);
1409 /* bounds range [start, start+len) to [0, max) and aligns to 2 */
1410 static void s5k5baf_bound_range(u32
*start
, u32
*len
, u32 max
)
1414 if (*start
+ *len
> max
)
1415 *start
= max
- *len
;
1418 if (*len
< S5K5BAF_WIN_WIDTH_MIN
)
1419 *len
= S5K5BAF_WIN_WIDTH_MIN
;
1422 static void s5k5baf_bound_rect(struct v4l2_rect
*r
, u32 width
, u32 height
)
1424 s5k5baf_bound_range(&r
->left
, &r
->width
, width
);
1425 s5k5baf_bound_range(&r
->top
, &r
->height
, height
);
1428 static void s5k5baf_set_rect_and_adjust(struct v4l2_rect
**rects
,
1429 enum selection_rect first
,
1430 struct v4l2_rect
*v
)
1432 struct v4l2_rect
*r
, *br
;
1433 enum selection_rect i
= first
;
1439 s5k5baf_bound_rect(r
, br
->width
, br
->height
);
1440 } while (++i
!= R_INVALID
);
1444 static bool s5k5baf_cmp_rect(const struct v4l2_rect
*r1
,
1445 const struct v4l2_rect
*r2
)
1447 return !memcmp(r1
, r2
, sizeof(*r1
));
1450 static int s5k5baf_set_selection(struct v4l2_subdev
*sd
,
1451 struct v4l2_subdev_fh
*fh
,
1452 struct v4l2_subdev_selection
*sel
)
1454 static enum selection_rect rtype
;
1455 struct s5k5baf
*state
= to_s5k5baf(sd
);
1456 struct v4l2_rect
**rects
;
1459 rtype
= s5k5baf_get_sel_rect(sel
->pad
, sel
->target
);
1460 if (rtype
== R_INVALID
|| s5k5baf_is_bound_target(sel
->target
))
1463 /* allow only scaling on compose */
1464 if (rtype
== R_COMPOSE
) {
1469 if (sel
->which
== V4L2_SUBDEV_FORMAT_TRY
) {
1470 rects
= (struct v4l2_rect
* []) {
1472 v4l2_subdev_get_try_crop(fh
, PAD_CIS
),
1473 v4l2_subdev_get_try_compose(fh
, PAD_CIS
),
1474 v4l2_subdev_get_try_crop(fh
, PAD_OUT
)
1476 s5k5baf_set_rect_and_adjust(rects
, rtype
, &sel
->r
);
1480 rects
= (struct v4l2_rect
* []) {
1486 mutex_lock(&state
->lock
);
1487 if (state
->streaming
) {
1488 /* adjust sel->r to avoid output resolution change */
1489 if (rtype
< R_CROP_SOURCE
) {
1490 if (sel
->r
.width
< state
->crop_source
.width
)
1491 sel
->r
.width
= state
->crop_source
.width
;
1492 if (sel
->r
.height
< state
->crop_source
.height
)
1493 sel
->r
.height
= state
->crop_source
.height
;
1495 sel
->r
.width
= state
->crop_source
.width
;
1496 sel
->r
.height
= state
->crop_source
.height
;
1499 s5k5baf_set_rect_and_adjust(rects
, rtype
, &sel
->r
);
1500 if (!s5k5baf_cmp_rect(&state
->crop_sink
, &s5k5baf_cis_rect
) ||
1501 !s5k5baf_cmp_rect(&state
->compose
, &s5k5baf_cis_rect
))
1502 state
->apply_crop
= 1;
1503 if (state
->streaming
)
1504 ret
= s5k5baf_hw_set_crop_rects(state
);
1505 mutex_unlock(&state
->lock
);
1510 static const struct v4l2_subdev_pad_ops s5k5baf_cis_pad_ops
= {
1511 .enum_mbus_code
= s5k5baf_enum_mbus_code
,
1512 .enum_frame_size
= s5k5baf_enum_frame_size
,
1513 .get_fmt
= s5k5baf_get_fmt
,
1514 .set_fmt
= s5k5baf_set_fmt
,
1517 static const struct v4l2_subdev_pad_ops s5k5baf_pad_ops
= {
1518 .enum_mbus_code
= s5k5baf_enum_mbus_code
,
1519 .enum_frame_size
= s5k5baf_enum_frame_size
,
1520 .enum_frame_interval
= s5k5baf_enum_frame_interval
,
1521 .get_fmt
= s5k5baf_get_fmt
,
1522 .set_fmt
= s5k5baf_set_fmt
,
1523 .get_selection
= s5k5baf_get_selection
,
1524 .set_selection
= s5k5baf_set_selection
,
1527 static const struct v4l2_subdev_video_ops s5k5baf_video_ops
= {
1528 .g_frame_interval
= s5k5baf_g_frame_interval
,
1529 .s_frame_interval
= s5k5baf_s_frame_interval
,
1530 .s_stream
= s5k5baf_s_stream
,
1534 * V4L2 subdev controls
1537 static int s5k5baf_s_ctrl(struct v4l2_ctrl
*ctrl
)
1539 struct v4l2_subdev
*sd
= ctrl_to_sd(ctrl
);
1540 struct s5k5baf
*state
= to_s5k5baf(sd
);
1543 v4l2_dbg(1, debug
, sd
, "ctrl: %s, value: %d\n", ctrl
->name
, ctrl
->val
);
1545 mutex_lock(&state
->lock
);
1547 if (state
->power
== 0)
1551 case V4L2_CID_AUTO_WHITE_BALANCE
:
1552 s5k5baf_hw_set_awb(state
, ctrl
->val
);
1555 case V4L2_CID_BRIGHTNESS
:
1556 s5k5baf_write(state
, REG_USER_BRIGHTNESS
, ctrl
->val
);
1559 case V4L2_CID_COLORFX
:
1560 s5k5baf_hw_set_colorfx(state
, ctrl
->val
);
1563 case V4L2_CID_CONTRAST
:
1564 s5k5baf_write(state
, REG_USER_CONTRAST
, ctrl
->val
);
1567 case V4L2_CID_EXPOSURE_AUTO
:
1568 s5k5baf_hw_set_auto_exposure(state
, ctrl
->val
);
1571 case V4L2_CID_HFLIP
:
1572 s5k5baf_hw_set_mirror(state
);
1575 case V4L2_CID_POWER_LINE_FREQUENCY
:
1576 s5k5baf_hw_set_anti_flicker(state
, ctrl
->val
);
1579 case V4L2_CID_SATURATION
:
1580 s5k5baf_write(state
, REG_USER_SATURATION
, ctrl
->val
);
1583 case V4L2_CID_SHARPNESS
:
1584 s5k5baf_write(state
, REG_USER_SHARPBLUR
, ctrl
->val
);
1587 case V4L2_CID_WHITE_BALANCE_TEMPERATURE
:
1588 s5k5baf_write(state
, REG_P_COLORTEMP(0), ctrl
->val
);
1589 if (state
->apply_cfg
)
1590 s5k5baf_hw_sync_cfg(state
);
1593 case V4L2_CID_TEST_PATTERN
:
1594 s5k5baf_hw_set_test_pattern(state
, ctrl
->val
);
1598 ret
= s5k5baf_clear_error(state
);
1599 mutex_unlock(&state
->lock
);
1603 static const struct v4l2_ctrl_ops s5k5baf_ctrl_ops
= {
1604 .s_ctrl
= s5k5baf_s_ctrl
,
1607 static const char * const s5k5baf_test_pattern_menu
[] = {
1617 static int s5k5baf_initialize_ctrls(struct s5k5baf
*state
)
1619 const struct v4l2_ctrl_ops
*ops
= &s5k5baf_ctrl_ops
;
1620 struct s5k5baf_ctrls
*ctrls
= &state
->ctrls
;
1621 struct v4l2_ctrl_handler
*hdl
= &ctrls
->handler
;
1624 ret
= v4l2_ctrl_handler_init(hdl
, 16);
1626 v4l2_err(&state
->sd
, "cannot init ctrl handler (%d)\n", ret
);
1630 /* Auto white balance cluster */
1631 ctrls
->awb
= v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_AUTO_WHITE_BALANCE
,
1633 ctrls
->gain_red
= v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_RED_BALANCE
,
1634 0, 255, 1, S5K5BAF_GAIN_RED_DEF
);
1635 ctrls
->gain_blue
= v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_BLUE_BALANCE
,
1636 0, 255, 1, S5K5BAF_GAIN_BLUE_DEF
);
1637 v4l2_ctrl_auto_cluster(3, &ctrls
->awb
, 0, false);
1639 ctrls
->hflip
= v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_HFLIP
, 0, 1, 1, 0);
1640 ctrls
->vflip
= v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_VFLIP
, 0, 1, 1, 0);
1641 v4l2_ctrl_cluster(2, &ctrls
->hflip
);
1643 ctrls
->auto_exp
= v4l2_ctrl_new_std_menu(hdl
, ops
,
1644 V4L2_CID_EXPOSURE_AUTO
,
1645 V4L2_EXPOSURE_MANUAL
, 0, V4L2_EXPOSURE_AUTO
);
1646 /* Exposure time: x 1 us */
1647 ctrls
->exposure
= v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_EXPOSURE
,
1648 0, 6000000U, 1, 100000U);
1649 /* Total gain: 256 <=> 1x */
1650 ctrls
->gain
= v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_GAIN
,
1652 v4l2_ctrl_auto_cluster(3, &ctrls
->auto_exp
, 0, false);
1654 v4l2_ctrl_new_std_menu(hdl
, ops
, V4L2_CID_POWER_LINE_FREQUENCY
,
1655 V4L2_CID_POWER_LINE_FREQUENCY_AUTO
, 0,
1656 V4L2_CID_POWER_LINE_FREQUENCY_AUTO
);
1658 v4l2_ctrl_new_std_menu(hdl
, ops
, V4L2_CID_COLORFX
,
1659 V4L2_COLORFX_SKY_BLUE
, ~0x6f, V4L2_COLORFX_NONE
);
1661 v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_WHITE_BALANCE_TEMPERATURE
,
1664 v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_SATURATION
, -127, 127, 1, 0);
1665 v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_BRIGHTNESS
, -127, 127, 1, 0);
1666 v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_CONTRAST
, -127, 127, 1, 0);
1667 v4l2_ctrl_new_std(hdl
, ops
, V4L2_CID_SHARPNESS
, -127, 127, 1, 0);
1669 v4l2_ctrl_new_std_menu_items(hdl
, ops
, V4L2_CID_TEST_PATTERN
,
1670 ARRAY_SIZE(s5k5baf_test_pattern_menu
) - 1,
1671 0, 0, s5k5baf_test_pattern_menu
);
1674 v4l2_err(&state
->sd
, "error creating controls (%d)\n",
1677 v4l2_ctrl_handler_free(hdl
);
1681 state
->sd
.ctrl_handler
= hdl
;
1686 * V4L2 subdev internal operations
1688 static int s5k5baf_open(struct v4l2_subdev
*sd
, struct v4l2_subdev_fh
*fh
)
1690 struct v4l2_mbus_framefmt
*mf
;
1692 mf
= v4l2_subdev_get_try_format(fh
, PAD_CIS
);
1693 s5k5baf_try_cis_format(mf
);
1695 if (s5k5baf_is_cis_subdev(sd
))
1698 mf
= v4l2_subdev_get_try_format(fh
, PAD_OUT
);
1699 mf
->colorspace
= s5k5baf_formats
[0].colorspace
;
1700 mf
->code
= s5k5baf_formats
[0].code
;
1701 mf
->width
= s5k5baf_cis_rect
.width
;
1702 mf
->height
= s5k5baf_cis_rect
.height
;
1703 mf
->field
= V4L2_FIELD_NONE
;
1705 *v4l2_subdev_get_try_crop(fh
, PAD_CIS
) = s5k5baf_cis_rect
;
1706 *v4l2_subdev_get_try_compose(fh
, PAD_CIS
) = s5k5baf_cis_rect
;
1707 *v4l2_subdev_get_try_crop(fh
, PAD_OUT
) = s5k5baf_cis_rect
;
1712 static int s5k5baf_check_fw_revision(struct s5k5baf
*state
)
1714 u16 api_ver
= 0, fw_rev
= 0, s_id
= 0;
1717 api_ver
= s5k5baf_read(state
, REG_FW_APIVER
);
1718 fw_rev
= s5k5baf_read(state
, REG_FW_REVISION
) & 0xff;
1719 s_id
= s5k5baf_read(state
, REG_FW_SENSOR_ID
);
1720 ret
= s5k5baf_clear_error(state
);
1724 v4l2_info(&state
->sd
, "FW API=%#x, revision=%#x sensor_id=%#x\n",
1725 api_ver
, fw_rev
, s_id
);
1727 if (api_ver
!= S5K5BAF_FW_APIVER
) {
1728 v4l2_err(&state
->sd
, "FW API version not supported\n");
1735 static int s5k5baf_registered(struct v4l2_subdev
*sd
)
1737 struct s5k5baf
*state
= to_s5k5baf(sd
);
1740 ret
= v4l2_device_register_subdev(sd
->v4l2_dev
, &state
->cis_sd
);
1742 v4l2_err(sd
, "failed to register subdev %s\n",
1743 state
->cis_sd
.name
);
1745 ret
= media_entity_create_link(&state
->cis_sd
.entity
, PAD_CIS
,
1746 &state
->sd
.entity
, PAD_CIS
,
1747 MEDIA_LNK_FL_IMMUTABLE
|
1748 MEDIA_LNK_FL_ENABLED
);
1752 static void s5k5baf_unregistered(struct v4l2_subdev
*sd
)
1754 struct s5k5baf
*state
= to_s5k5baf(sd
);
1755 v4l2_device_unregister_subdev(&state
->cis_sd
);
1758 static const struct v4l2_subdev_ops s5k5baf_cis_subdev_ops
= {
1759 .pad
= &s5k5baf_cis_pad_ops
,
1762 static const struct v4l2_subdev_internal_ops s5k5baf_cis_subdev_internal_ops
= {
1763 .open
= s5k5baf_open
,
1766 static const struct v4l2_subdev_internal_ops s5k5baf_subdev_internal_ops
= {
1767 .registered
= s5k5baf_registered
,
1768 .unregistered
= s5k5baf_unregistered
,
1769 .open
= s5k5baf_open
,
1772 static const struct v4l2_subdev_core_ops s5k5baf_core_ops
= {
1773 .s_power
= s5k5baf_set_power
,
1774 .log_status
= v4l2_ctrl_subdev_log_status
,
1777 static const struct v4l2_subdev_ops s5k5baf_subdev_ops
= {
1778 .core
= &s5k5baf_core_ops
,
1779 .pad
= &s5k5baf_pad_ops
,
1780 .video
= &s5k5baf_video_ops
,
1783 static int s5k5baf_configure_gpios(struct s5k5baf
*state
)
1785 static const char const *name
[] = { "S5K5BAF_STBY", "S5K5BAF_RST" };
1786 struct i2c_client
*c
= v4l2_get_subdevdata(&state
->sd
);
1787 struct s5k5baf_gpio
*g
= state
->gpios
;
1790 for (i
= 0; i
< NUM_GPIOS
; ++i
) {
1791 int flags
= GPIOF_DIR_OUT
;
1793 flags
|= GPIOF_INIT_HIGH
;
1794 ret
= devm_gpio_request_one(&c
->dev
, g
[i
].gpio
, flags
, name
[i
]);
1796 v4l2_err(c
, "failed to request gpio %s\n", name
[i
]);
1803 static int s5k5baf_parse_gpios(struct s5k5baf_gpio
*gpios
, struct device
*dev
)
1805 static const char * const names
[] = {
1809 struct device_node
*node
= dev
->of_node
;
1810 enum of_gpio_flags flags
;
1813 for (i
= 0; i
< NUM_GPIOS
; ++i
) {
1814 ret
= of_get_named_gpio_flags(node
, names
[i
], 0, &flags
);
1816 dev_err(dev
, "no %s GPIO pin provided\n", names
[i
]);
1819 gpios
[i
].gpio
= ret
;
1820 gpios
[i
].level
= !(flags
& OF_GPIO_ACTIVE_LOW
);
1826 static int s5k5baf_parse_device_node(struct s5k5baf
*state
, struct device
*dev
)
1828 struct device_node
*node
= dev
->of_node
;
1829 struct device_node
*node_ep
;
1830 struct v4l2_of_endpoint ep
;
1834 dev_err(dev
, "no device-tree node provided\n");
1838 ret
= of_property_read_u32(node
, "clock-frequency",
1839 &state
->mclk_frequency
);
1841 state
->mclk_frequency
= S5K5BAF_DEFAULT_MCLK_FREQ
;
1842 dev_info(dev
, "using default %u Hz clock frequency\n",
1843 state
->mclk_frequency
);
1846 ret
= s5k5baf_parse_gpios(state
->gpios
, dev
);
1850 node_ep
= v4l2_of_get_next_endpoint(node
, NULL
);
1852 dev_err(dev
, "no endpoint defined at node %s\n",
1857 v4l2_of_parse_endpoint(node_ep
, &ep
);
1858 of_node_put(node_ep
);
1859 state
->bus_type
= ep
.bus_type
;
1861 switch (state
->bus_type
) {
1862 case V4L2_MBUS_CSI2
:
1863 state
->nlanes
= ep
.bus
.mipi_csi2
.num_data_lanes
;
1865 case V4L2_MBUS_PARALLEL
:
1868 dev_err(dev
, "unsupported bus in endpoint defined at node %s\n",
1876 static int s5k5baf_configure_subdevs(struct s5k5baf
*state
,
1877 struct i2c_client
*c
)
1879 struct v4l2_subdev
*sd
;
1882 sd
= &state
->cis_sd
;
1883 v4l2_subdev_init(sd
, &s5k5baf_cis_subdev_ops
);
1884 sd
->owner
= THIS_MODULE
;
1885 v4l2_set_subdevdata(sd
, state
);
1886 snprintf(sd
->name
, sizeof(sd
->name
), "S5K5BAF-CIS %d-%04x",
1887 i2c_adapter_id(c
->adapter
), c
->addr
);
1889 sd
->internal_ops
= &s5k5baf_cis_subdev_internal_ops
;
1890 sd
->flags
|= V4L2_SUBDEV_FL_HAS_DEVNODE
;
1892 state
->cis_pad
.flags
= MEDIA_PAD_FL_SOURCE
;
1893 sd
->entity
.type
= MEDIA_ENT_T_V4L2_SUBDEV_SENSOR
;
1894 ret
= media_entity_init(&sd
->entity
, NUM_CIS_PADS
, &state
->cis_pad
, 0);
1899 v4l2_i2c_subdev_init(sd
, c
, &s5k5baf_subdev_ops
);
1900 snprintf(sd
->name
, sizeof(sd
->name
), "S5K5BAF-ISP %d-%04x",
1901 i2c_adapter_id(c
->adapter
), c
->addr
);
1903 sd
->internal_ops
= &s5k5baf_subdev_internal_ops
;
1904 sd
->flags
|= V4L2_SUBDEV_FL_HAS_DEVNODE
;
1906 state
->pads
[PAD_CIS
].flags
= MEDIA_PAD_FL_SINK
;
1907 state
->pads
[PAD_OUT
].flags
= MEDIA_PAD_FL_SOURCE
;
1908 sd
->entity
.type
= MEDIA_ENT_T_V4L2_SUBDEV
;
1909 ret
= media_entity_init(&sd
->entity
, NUM_ISP_PADS
, state
->pads
, 0);
1914 media_entity_cleanup(&state
->cis_sd
.entity
);
1916 dev_err(&c
->dev
, "cannot init media entity %s\n", sd
->name
);
1920 static int s5k5baf_configure_regulators(struct s5k5baf
*state
)
1922 struct i2c_client
*c
= v4l2_get_subdevdata(&state
->sd
);
1926 for (i
= 0; i
< S5K5BAF_NUM_SUPPLIES
; i
++)
1927 state
->supplies
[i
].supply
= s5k5baf_supply_names
[i
];
1929 ret
= devm_regulator_bulk_get(&c
->dev
, S5K5BAF_NUM_SUPPLIES
,
1932 v4l2_err(c
, "failed to get regulators\n");
1936 static int s5k5baf_probe(struct i2c_client
*c
,
1937 const struct i2c_device_id
*id
)
1939 struct s5k5baf
*state
;
1942 state
= devm_kzalloc(&c
->dev
, sizeof(*state
), GFP_KERNEL
);
1946 mutex_init(&state
->lock
);
1947 state
->crop_sink
= s5k5baf_cis_rect
;
1948 state
->compose
= s5k5baf_cis_rect
;
1949 state
->crop_source
= s5k5baf_cis_rect
;
1951 ret
= s5k5baf_parse_device_node(state
, &c
->dev
);
1955 ret
= s5k5baf_configure_subdevs(state
, c
);
1959 ret
= s5k5baf_configure_gpios(state
);
1963 ret
= s5k5baf_configure_regulators(state
);
1967 state
->clock
= devm_clk_get(state
->sd
.dev
, S5K5BAF_CLK_NAME
);
1968 if (IS_ERR(state
->clock
)) {
1969 ret
= -EPROBE_DEFER
;
1973 ret
= s5k5baf_power_on(state
);
1975 ret
= -EPROBE_DEFER
;
1978 s5k5baf_hw_init(state
);
1979 ret
= s5k5baf_check_fw_revision(state
);
1981 s5k5baf_power_off(state
);
1985 ret
= s5k5baf_initialize_ctrls(state
);
1989 ret
= v4l2_async_register_subdev(&state
->sd
);
1996 v4l2_ctrl_handler_free(state
->sd
.ctrl_handler
);
1998 media_entity_cleanup(&state
->sd
.entity
);
1999 media_entity_cleanup(&state
->cis_sd
.entity
);
2003 static int s5k5baf_remove(struct i2c_client
*c
)
2005 struct v4l2_subdev
*sd
= i2c_get_clientdata(c
);
2006 struct s5k5baf
*state
= to_s5k5baf(sd
);
2008 v4l2_async_unregister_subdev(sd
);
2009 v4l2_ctrl_handler_free(sd
->ctrl_handler
);
2010 media_entity_cleanup(&sd
->entity
);
2012 sd
= &state
->cis_sd
;
2013 v4l2_device_unregister_subdev(sd
);
2014 media_entity_cleanup(&sd
->entity
);
2019 static const struct i2c_device_id s5k5baf_id
[] = {
2020 { S5K5BAF_DRIVER_NAME
, 0 },
2023 MODULE_DEVICE_TABLE(i2c
, s5k5baf_id
);
2025 static const struct of_device_id s5k5baf_of_match
[] = {
2026 { .compatible
= "samsung,s5k5baf" },
2029 MODULE_DEVICE_TABLE(of
, s5k5baf_of_match
);
2031 static struct i2c_driver s5k5baf_i2c_driver
= {
2033 .of_match_table
= s5k5baf_of_match
,
2034 .name
= S5K5BAF_DRIVER_NAME
2036 .probe
= s5k5baf_probe
,
2037 .remove
= s5k5baf_remove
,
2038 .id_table
= s5k5baf_id
,
2041 module_i2c_driver(s5k5baf_i2c_driver
);
2043 MODULE_DESCRIPTION("Samsung S5K5BAF(X) UXGA camera driver");
2044 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
2045 MODULE_LICENSE("GPL v2");