2 * saa7191.c - Philips SAA7191 video decoder driver
4 * Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
5 * Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/delay.h>
13 #include <linux/errno.h>
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/major.h>
18 #include <linux/module.h>
20 #include <linux/slab.h>
22 #include <linux/videodev2.h>
23 #include <linux/i2c.h>
24 #include <media/v4l2-device.h>
28 #define SAA7191_MODULE_VERSION "0.0.5"
30 MODULE_DESCRIPTION("Philips SAA7191 video decoder driver");
31 MODULE_VERSION(SAA7191_MODULE_VERSION
);
32 MODULE_AUTHOR("Mikael Nousiainen <tmnousia@cc.hut.fi>");
33 MODULE_LICENSE("GPL");
36 // #define SAA7191_DEBUG
39 #define dprintk(x...) printk("SAA7191: " x);
44 #define SAA7191_SYNC_COUNT 30
45 #define SAA7191_SYNC_DELAY 100 /* milliseconds */
48 struct v4l2_subdev sd
;
50 /* the register values are stored here as the actual
51 * I2C-registers are write-only */
58 static inline struct saa7191
*to_saa7191(struct v4l2_subdev
*sd
)
60 return container_of(sd
, struct saa7191
, sd
);
63 static const u8 initseq
[] = {
66 0x50, /* (0x50) SAA7191_REG_IDEL */
68 /* 50 Hz signal timing */
69 0x30, /* (0x30) SAA7191_REG_HSYB */
70 0x00, /* (0x00) SAA7191_REG_HSYS */
71 0xe8, /* (0xe8) SAA7191_REG_HCLB */
72 0xb6, /* (0xb6) SAA7191_REG_HCLS */
73 0xf4, /* (0xf4) SAA7191_REG_HPHI */
76 SAA7191_LUMA_APER_1
, /* (0x01) SAA7191_REG_LUMA - CVBS mode */
77 0x00, /* (0x00) SAA7191_REG_HUEC */
78 0xf8, /* (0xf8) SAA7191_REG_CKTQ */
79 0xf8, /* (0xf8) SAA7191_REG_CKTS */
80 0x90, /* (0x90) SAA7191_REG_PLSE */
81 0x90, /* (0x90) SAA7191_REG_SESE */
82 0x00, /* (0x00) SAA7191_REG_GAIN */
83 SAA7191_STDC_NFEN
| SAA7191_STDC_HRMV
, /* (0x0c) SAA7191_REG_STDC
85 * slow time constant */
86 SAA7191_IOCK_OEDC
| SAA7191_IOCK_OEHS
| SAA7191_IOCK_OEVS
87 | SAA7191_IOCK_OEDY
, /* (0x78) SAA7191_REG_IOCK
88 * - chroma from CVBS, GPSW1 & 2 off */
89 SAA7191_CTL3_AUFD
| SAA7191_CTL3_SCEN
| SAA7191_CTL3_OFTS
90 | SAA7191_CTL3_YDEL0
, /* (0x99) SAA7191_REG_CTL3
91 * - automatic field detection */
92 0x00, /* (0x00) SAA7191_REG_CTL4 */
93 0x2c, /* (0x2c) SAA7191_REG_CHCV - PAL nominal value */
97 /* 60 Hz signal timing */
98 0x34, /* (0x34) SAA7191_REG_HS6B */
99 0x0a, /* (0x0a) SAA7191_REG_HS6S */
100 0xf4, /* (0xf4) SAA7191_REG_HC6B */
101 0xce, /* (0xce) SAA7191_REG_HC6S */
102 0xf4, /* (0xf4) SAA7191_REG_HP6I */
105 /* SAA7191 register handling */
107 static u8
saa7191_read_reg(struct v4l2_subdev
*sd
, u8 reg
)
109 return to_saa7191(sd
)->reg
[reg
];
112 static int saa7191_read_status(struct v4l2_subdev
*sd
, u8
*value
)
114 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
117 ret
= i2c_master_recv(client
, value
, 1);
119 printk(KERN_ERR
"SAA7191: saa7191_read_status(): read failed\n");
127 static int saa7191_write_reg(struct v4l2_subdev
*sd
, u8 reg
, u8 value
)
129 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
131 to_saa7191(sd
)->reg
[reg
] = value
;
132 return i2c_smbus_write_byte_data(client
, reg
, value
);
135 /* the first byte of data must be the first subaddress number (register) */
136 static int saa7191_write_block(struct v4l2_subdev
*sd
,
137 u8 length
, const u8
*data
)
139 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
140 struct saa7191
*decoder
= to_saa7191(sd
);
144 for (i
= 0; i
< (length
- 1); i
++) {
145 decoder
->reg
[data
[0] + i
] = data
[i
+ 1];
148 ret
= i2c_master_send(client
, data
, length
);
150 printk(KERN_ERR
"SAA7191: saa7191_write_block(): "
158 /* Helper functions */
160 static int saa7191_s_routing(struct v4l2_subdev
*sd
,
161 u32 input
, u32 output
, u32 config
)
163 struct saa7191
*decoder
= to_saa7191(sd
);
164 u8 luma
= saa7191_read_reg(sd
, SAA7191_REG_LUMA
);
165 u8 iock
= saa7191_read_reg(sd
, SAA7191_REG_IOCK
);
169 case SAA7191_INPUT_COMPOSITE
: /* Set Composite input */
170 iock
&= ~(SAA7191_IOCK_CHRS
| SAA7191_IOCK_GPSW1
171 | SAA7191_IOCK_GPSW2
);
172 /* Chrominance trap active */
173 luma
&= ~SAA7191_LUMA_BYPS
;
175 case SAA7191_INPUT_SVIDEO
: /* Set S-Video input */
176 iock
|= SAA7191_IOCK_CHRS
| SAA7191_IOCK_GPSW2
;
177 /* Chrominance trap bypassed */
178 luma
|= SAA7191_LUMA_BYPS
;
184 err
= saa7191_write_reg(sd
, SAA7191_REG_LUMA
, luma
);
187 err
= saa7191_write_reg(sd
, SAA7191_REG_IOCK
, iock
);
191 decoder
->input
= input
;
196 static int saa7191_s_std(struct v4l2_subdev
*sd
, v4l2_std_id norm
)
198 struct saa7191
*decoder
= to_saa7191(sd
);
199 u8 stdc
= saa7191_read_reg(sd
, SAA7191_REG_STDC
);
200 u8 ctl3
= saa7191_read_reg(sd
, SAA7191_REG_CTL3
);
201 u8 chcv
= saa7191_read_reg(sd
, SAA7191_REG_CHCV
);
204 if (norm
& V4L2_STD_PAL
) {
205 stdc
&= ~SAA7191_STDC_SECS
;
206 ctl3
&= ~(SAA7191_CTL3_AUFD
| SAA7191_CTL3_FSEL
);
207 chcv
= SAA7191_CHCV_PAL
;
208 } else if (norm
& V4L2_STD_NTSC
) {
209 stdc
&= ~SAA7191_STDC_SECS
;
210 ctl3
&= ~SAA7191_CTL3_AUFD
;
211 ctl3
|= SAA7191_CTL3_FSEL
;
212 chcv
= SAA7191_CHCV_NTSC
;
213 } else if (norm
& V4L2_STD_SECAM
) {
214 stdc
|= SAA7191_STDC_SECS
;
215 ctl3
&= ~(SAA7191_CTL3_AUFD
| SAA7191_CTL3_FSEL
);
216 chcv
= SAA7191_CHCV_PAL
;
221 err
= saa7191_write_reg(sd
, SAA7191_REG_CTL3
, ctl3
);
224 err
= saa7191_write_reg(sd
, SAA7191_REG_STDC
, stdc
);
227 err
= saa7191_write_reg(sd
, SAA7191_REG_CHCV
, chcv
);
231 decoder
->norm
= norm
;
233 dprintk("ctl3: %02x stdc: %02x chcv: %02x\n", ctl3
,
235 dprintk("norm: %llx\n", norm
);
240 static int saa7191_wait_for_signal(struct v4l2_subdev
*sd
, u8
*status
)
244 dprintk("Checking for signal...\n");
246 for (i
= 0; i
< SAA7191_SYNC_COUNT
; i
++) {
247 if (saa7191_read_status(sd
, status
))
250 if (((*status
) & SAA7191_STATUS_HLCK
) == 0) {
251 dprintk("Signal found\n");
255 msleep(SAA7191_SYNC_DELAY
);
258 dprintk("No signal\n");
263 static int saa7191_querystd(struct v4l2_subdev
*sd
, v4l2_std_id
*norm
)
265 struct saa7191
*decoder
= to_saa7191(sd
);
266 u8 stdc
= saa7191_read_reg(sd
, SAA7191_REG_STDC
);
267 u8 ctl3
= saa7191_read_reg(sd
, SAA7191_REG_CTL3
);
269 v4l2_std_id old_norm
= decoder
->norm
;
272 dprintk("SAA7191 extended signal auto-detection...\n");
274 *norm
= V4L2_STD_NTSC
| V4L2_STD_PAL
| V4L2_STD_SECAM
;
275 stdc
&= ~SAA7191_STDC_SECS
;
276 ctl3
&= ~(SAA7191_CTL3_FSEL
);
278 err
= saa7191_write_reg(sd
, SAA7191_REG_STDC
, stdc
);
283 err
= saa7191_write_reg(sd
, SAA7191_REG_CTL3
, ctl3
);
289 ctl3
|= SAA7191_CTL3_AUFD
;
290 err
= saa7191_write_reg(sd
, SAA7191_REG_CTL3
, ctl3
);
296 msleep(SAA7191_SYNC_DELAY
);
298 err
= saa7191_wait_for_signal(sd
, &status
);
302 if (status
& SAA7191_STATUS_FIDT
) {
303 /* 60Hz signal -> NTSC */
304 dprintk("60Hz signal: NTSC\n");
305 *norm
= V4L2_STD_NTSC
;
310 dprintk("50Hz signal: Trying PAL...\n");
313 err
= saa7191_s_std(sd
, V4L2_STD_PAL
);
317 msleep(SAA7191_SYNC_DELAY
);
319 err
= saa7191_wait_for_signal(sd
, &status
);
324 if (status
& SAA7191_STATUS_FIDT
) {
325 dprintk("No 50Hz signal\n");
326 saa7191_s_std(sd
, old_norm
);
330 if (status
& SAA7191_STATUS_CODE
) {
332 *norm
= V4L2_STD_PAL
;
333 return saa7191_s_std(sd
, old_norm
);
336 dprintk("No color detected with PAL - Trying SECAM...\n");
338 /* no color detected ? -> try SECAM */
339 err
= saa7191_s_std(sd
, V4L2_STD_SECAM
);
343 msleep(SAA7191_SYNC_DELAY
);
345 err
= saa7191_wait_for_signal(sd
, &status
);
350 if (status
& SAA7191_STATUS_FIDT
) {
351 dprintk("No 50Hz signal\n");
356 if (status
& SAA7191_STATUS_CODE
) {
357 /* Color detected -> SECAM */
359 *norm
= V4L2_STD_SECAM
;
360 return saa7191_s_std(sd
, old_norm
);
363 dprintk("No color detected with SECAM - Going back to PAL.\n");
366 return saa7191_s_std(sd
, old_norm
);
369 static int saa7191_autodetect_norm(struct v4l2_subdev
*sd
)
373 dprintk("SAA7191 signal auto-detection...\n");
375 dprintk("Reading status...\n");
377 if (saa7191_read_status(sd
, &status
))
380 dprintk("Checking for signal...\n");
383 if (status
& SAA7191_STATUS_HLCK
) {
384 dprintk("No signal\n");
388 dprintk("Signal found\n");
390 if (status
& SAA7191_STATUS_FIDT
) {
391 /* 60hz signal -> NTSC */
393 return saa7191_s_std(sd
, V4L2_STD_NTSC
);
395 /* 50hz signal -> PAL */
397 return saa7191_s_std(sd
, V4L2_STD_PAL
);
401 static int saa7191_g_ctrl(struct v4l2_subdev
*sd
, struct v4l2_control
*ctrl
)
407 case SAA7191_CONTROL_BANDPASS
:
408 case SAA7191_CONTROL_BANDPASS_WEIGHT
:
409 case SAA7191_CONTROL_CORING
:
410 reg
= saa7191_read_reg(sd
, SAA7191_REG_LUMA
);
412 case SAA7191_CONTROL_BANDPASS
:
413 ctrl
->value
= ((s32
)reg
& SAA7191_LUMA_BPSS_MASK
)
414 >> SAA7191_LUMA_BPSS_SHIFT
;
416 case SAA7191_CONTROL_BANDPASS_WEIGHT
:
417 ctrl
->value
= ((s32
)reg
& SAA7191_LUMA_APER_MASK
)
418 >> SAA7191_LUMA_APER_SHIFT
;
420 case SAA7191_CONTROL_CORING
:
421 ctrl
->value
= ((s32
)reg
& SAA7191_LUMA_CORI_MASK
)
422 >> SAA7191_LUMA_CORI_SHIFT
;
426 case SAA7191_CONTROL_FORCE_COLOUR
:
427 case SAA7191_CONTROL_CHROMA_GAIN
:
428 reg
= saa7191_read_reg(sd
, SAA7191_REG_GAIN
);
429 if (ctrl
->id
== SAA7191_CONTROL_FORCE_COLOUR
)
430 ctrl
->value
= ((s32
)reg
& SAA7191_GAIN_COLO
) ? 1 : 0;
432 ctrl
->value
= ((s32
)reg
& SAA7191_GAIN_LFIS_MASK
)
433 >> SAA7191_GAIN_LFIS_SHIFT
;
436 reg
= saa7191_read_reg(sd
, SAA7191_REG_HUEC
);
441 ctrl
->value
= (s32
)reg
;
443 case SAA7191_CONTROL_VTRC
:
444 reg
= saa7191_read_reg(sd
, SAA7191_REG_STDC
);
445 ctrl
->value
= ((s32
)reg
& SAA7191_STDC_VTRC
) ? 1 : 0;
447 case SAA7191_CONTROL_LUMA_DELAY
:
448 reg
= saa7191_read_reg(sd
, SAA7191_REG_CTL3
);
449 ctrl
->value
= ((s32
)reg
& SAA7191_CTL3_YDEL_MASK
)
450 >> SAA7191_CTL3_YDEL_SHIFT
;
451 if (ctrl
->value
>= 4)
454 case SAA7191_CONTROL_VNR
:
455 reg
= saa7191_read_reg(sd
, SAA7191_REG_CTL4
);
456 ctrl
->value
= ((s32
)reg
& SAA7191_CTL4_VNOI_MASK
)
457 >> SAA7191_CTL4_VNOI_SHIFT
;
466 static int saa7191_s_ctrl(struct v4l2_subdev
*sd
, struct v4l2_control
*ctrl
)
472 case SAA7191_CONTROL_BANDPASS
:
473 case SAA7191_CONTROL_BANDPASS_WEIGHT
:
474 case SAA7191_CONTROL_CORING
:
475 reg
= saa7191_read_reg(sd
, SAA7191_REG_LUMA
);
477 case SAA7191_CONTROL_BANDPASS
:
478 reg
&= ~SAA7191_LUMA_BPSS_MASK
;
479 reg
|= (ctrl
->value
<< SAA7191_LUMA_BPSS_SHIFT
)
480 & SAA7191_LUMA_BPSS_MASK
;
482 case SAA7191_CONTROL_BANDPASS_WEIGHT
:
483 reg
&= ~SAA7191_LUMA_APER_MASK
;
484 reg
|= (ctrl
->value
<< SAA7191_LUMA_APER_SHIFT
)
485 & SAA7191_LUMA_APER_MASK
;
487 case SAA7191_CONTROL_CORING
:
488 reg
&= ~SAA7191_LUMA_CORI_MASK
;
489 reg
|= (ctrl
->value
<< SAA7191_LUMA_CORI_SHIFT
)
490 & SAA7191_LUMA_CORI_MASK
;
493 ret
= saa7191_write_reg(sd
, SAA7191_REG_LUMA
, reg
);
495 case SAA7191_CONTROL_FORCE_COLOUR
:
496 case SAA7191_CONTROL_CHROMA_GAIN
:
497 reg
= saa7191_read_reg(sd
, SAA7191_REG_GAIN
);
498 if (ctrl
->id
== SAA7191_CONTROL_FORCE_COLOUR
) {
500 reg
|= SAA7191_GAIN_COLO
;
502 reg
&= ~SAA7191_GAIN_COLO
;
504 reg
&= ~SAA7191_GAIN_LFIS_MASK
;
505 reg
|= (ctrl
->value
<< SAA7191_GAIN_LFIS_SHIFT
)
506 & SAA7191_GAIN_LFIS_MASK
;
508 ret
= saa7191_write_reg(sd
, SAA7191_REG_GAIN
, reg
);
511 reg
= ctrl
->value
& 0xff;
516 ret
= saa7191_write_reg(sd
, SAA7191_REG_HUEC
, reg
);
518 case SAA7191_CONTROL_VTRC
:
519 reg
= saa7191_read_reg(sd
, SAA7191_REG_STDC
);
521 reg
|= SAA7191_STDC_VTRC
;
523 reg
&= ~SAA7191_STDC_VTRC
;
524 ret
= saa7191_write_reg(sd
, SAA7191_REG_STDC
, reg
);
526 case SAA7191_CONTROL_LUMA_DELAY
: {
527 s32 value
= ctrl
->value
;
530 reg
= saa7191_read_reg(sd
, SAA7191_REG_CTL3
);
531 reg
&= ~SAA7191_CTL3_YDEL_MASK
;
532 reg
|= (value
<< SAA7191_CTL3_YDEL_SHIFT
)
533 & SAA7191_CTL3_YDEL_MASK
;
534 ret
= saa7191_write_reg(sd
, SAA7191_REG_CTL3
, reg
);
537 case SAA7191_CONTROL_VNR
:
538 reg
= saa7191_read_reg(sd
, SAA7191_REG_CTL4
);
539 reg
&= ~SAA7191_CTL4_VNOI_MASK
;
540 reg
|= (ctrl
->value
<< SAA7191_CTL4_VNOI_SHIFT
)
541 & SAA7191_CTL4_VNOI_MASK
;
542 ret
= saa7191_write_reg(sd
, SAA7191_REG_CTL4
, reg
);
553 static int saa7191_g_input_status(struct v4l2_subdev
*sd
, u32
*status
)
556 int res
= V4L2_IN_ST_NO_SIGNAL
;
558 if (saa7191_read_status(sd
, &status_reg
))
560 if ((status_reg
& SAA7191_STATUS_HLCK
) == 0)
562 if (!(status_reg
& SAA7191_STATUS_CODE
))
563 res
|= V4L2_IN_ST_NO_COLOR
;
569 /* ----------------------------------------------------------------------- */
571 static const struct v4l2_subdev_core_ops saa7191_core_ops
= {
572 .g_ctrl
= saa7191_g_ctrl
,
573 .s_ctrl
= saa7191_s_ctrl
,
574 .s_std
= saa7191_s_std
,
577 static const struct v4l2_subdev_video_ops saa7191_video_ops
= {
578 .s_routing
= saa7191_s_routing
,
579 .querystd
= saa7191_querystd
,
580 .g_input_status
= saa7191_g_input_status
,
583 static const struct v4l2_subdev_ops saa7191_ops
= {
584 .core
= &saa7191_core_ops
,
585 .video
= &saa7191_video_ops
,
588 static int saa7191_probe(struct i2c_client
*client
,
589 const struct i2c_device_id
*id
)
592 struct saa7191
*decoder
;
593 struct v4l2_subdev
*sd
;
595 v4l_info(client
, "chip found @ 0x%x (%s)\n",
596 client
->addr
<< 1, client
->adapter
->name
);
598 decoder
= devm_kzalloc(&client
->dev
, sizeof(*decoder
), GFP_KERNEL
);
603 v4l2_i2c_subdev_init(sd
, client
, &saa7191_ops
);
605 err
= saa7191_write_block(sd
, sizeof(initseq
), initseq
);
607 printk(KERN_ERR
"SAA7191 initialization failed\n");
611 printk(KERN_INFO
"SAA7191 initialized\n");
613 decoder
->input
= SAA7191_INPUT_COMPOSITE
;
614 decoder
->norm
= V4L2_STD_PAL
;
616 err
= saa7191_autodetect_norm(sd
);
617 if (err
&& (err
!= -EBUSY
))
618 printk(KERN_ERR
"SAA7191: Signal auto-detection failed\n");
623 static int saa7191_remove(struct i2c_client
*client
)
625 struct v4l2_subdev
*sd
= i2c_get_clientdata(client
);
627 v4l2_device_unregister_subdev(sd
);
631 static const struct i2c_device_id saa7191_id
[] = {
635 MODULE_DEVICE_TABLE(i2c
, saa7191_id
);
637 static struct i2c_driver saa7191_driver
= {
639 .owner
= THIS_MODULE
,
642 .probe
= saa7191_probe
,
643 .remove
= saa7191_remove
,
644 .id_table
= saa7191_id
,
647 module_i2c_driver(saa7191_driver
);