drivers/media/i2c/ths8200.c

   1 /*
   2  * ths8200 - Texas Instruments THS8200 video encoder driver
   3  *
   4  * Copyright 2013 Cisco Systems, Inc. and/or its affiliates.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation version 2.
  13  *
  14  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  15  * kind, whether express or implied; without even the implied warranty
  16  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <linux/i2c.h>
  21 #include <linux/module.h>
  22 #include <linux/v4l2-dv-timings.h>
  23
  24 #include <media/v4l2-dv-timings.h>
  25 #include <media/v4l2-async.h>
  26 #include <media/v4l2-device.h>
  27
  28 #include "ths8200_regs.h"
  29
  30 static int debug;
  31 module_param(debug, int, 0644);
  32 MODULE_PARM_DESC(debug, "debug level (0-2)");
  33
  34 MODULE_DESCRIPTION("Texas Instruments THS8200 video encoder driver");
  35 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  36 MODULE_AUTHOR("Martin Bugge <martin.bugge@cisco.com>");
  37 MODULE_LICENSE("GPL v2");
  38
  39 struct ths8200_state {
  40         struct v4l2_subdev sd;
  41         uint8_t chip_version;
  42         /* Is the ths8200 powered on? */
  43         bool power_on;
  44         struct v4l2_dv_timings dv_timings;
  45 };
  46
  47 static const struct v4l2_dv_timings_cap ths8200_timings_cap = {
  48         .type = V4L2_DV_BT_656_1120,
  49         .bt = {
  50                 .max_width = 1920,
  51                 .max_height = 1080,
  52                 .min_pixelclock = 27000000,
  53                 .max_pixelclock = 148500000,
  54                 .standards = V4L2_DV_BT_STD_CEA861,
  55                 .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE,
  56         },
  57 };
  58
  59 static inline struct ths8200_state *to_state(struct v4l2_subdev *sd)
  60 {
  61         return container_of(sd, struct ths8200_state, sd);
  62 }
  63
  64 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
  65 {
  66         return V4L2_DV_BT_BLANKING_WIDTH(t);
  67 }
  68
  69 static inline unsigned htotal(const struct v4l2_bt_timings *t)
  70 {
  71         return V4L2_DV_BT_FRAME_WIDTH(t);
  72 }
  73
  74 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
  75 {
  76         return V4L2_DV_BT_BLANKING_HEIGHT(t);
  77 }
  78
  79 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
  80 {
  81         return V4L2_DV_BT_FRAME_HEIGHT(t);
  82 }
  83
  84 static int ths8200_read(struct v4l2_subdev *sd, u8 reg)
  85 {
  86         struct i2c_client *client = v4l2_get_subdevdata(sd);
  87
  88         return i2c_smbus_read_byte_data(client, reg);
  89 }
  90
  91 static int ths8200_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  92 {
  93         struct i2c_client *client = v4l2_get_subdevdata(sd);
  94         int ret;
  95         int i;
  96
  97         for (i = 0; i < 3; i++) {
  98                 ret = i2c_smbus_write_byte_data(client, reg, val);
  99                 if (ret == 0)
 100                         return 0;
 101         }
 102         v4l2_err(sd, "I2C Write Problem\n");
 103         return ret;
 104 }
 105
 106 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
 107  * and then the value-mask (to be OR-ed).
 108  */
 109 static inline void
 110 ths8200_write_and_or(struct v4l2_subdev *sd, u8 reg,
 111                      uint8_t clr_mask, uint8_t val_mask)
 112 {
 113         ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask);
 114 }
 115
 116 #ifdef CONFIG_VIDEO_ADV_DEBUG
 117
 118 static int ths8200_g_register(struct v4l2_subdev *sd,
 119                               struct v4l2_dbg_register *reg)
 120 {
 121         reg->val = ths8200_read(sd, reg->reg & 0xff);
 122         reg->size = 1;
 123
 124         return 0;
 125 }
 126
 127 static int ths8200_s_register(struct v4l2_subdev *sd,
 128                               const struct v4l2_dbg_register *reg)
 129 {
 130         ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff);
 131
 132         return 0;
 133 }
 134 #endif
 135
 136 static int ths8200_log_status(struct v4l2_subdev *sd)
 137 {
 138         struct ths8200_state *state = to_state(sd);
 139         uint8_t reg_03 = ths8200_read(sd, THS8200_CHIP_CTL);
 140
 141         v4l2_info(sd, "----- Chip status -----\n");
 142         v4l2_info(sd, "version: %u\n", state->chip_version);
 143         v4l2_info(sd, "power: %s\n", (reg_03 & 0x0c) ? "off" : "on");
 144         v4l2_info(sd, "reset: %s\n", (reg_03 & 0x01) ? "off" : "on");
 145         v4l2_info(sd, "test pattern: %s\n",
 146                   (reg_03 & 0x20) ? "enabled" : "disabled");
 147         v4l2_info(sd, "format: %ux%u\n",
 148                   ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_MSB) * 256 +
 149                   ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_LSB),
 150                   (ths8200_read(sd, THS8200_DTG2_LINE_CNT_MSB) & 0x07) * 256 +
 151                   ths8200_read(sd, THS8200_DTG2_LINE_CNT_LSB));
 152         v4l2_print_dv_timings(sd->name, "Configured format:",
 153                               &state->dv_timings, true);
 154         return 0;
 155 }
 156
 157 /* Power up/down ths8200 */
 158 static int ths8200_s_power(struct v4l2_subdev *sd, int on)
 159 {
 160         struct ths8200_state *state = to_state(sd);
 161
 162         v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
 163
 164         state->power_on = on;
 165
 166         /* Power up/down - leave in reset state until input video is present */
 167         ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xf2, (on ? 0x00 : 0x0c));
 168
 169         return 0;
 170 }
 171
 172 static const struct v4l2_subdev_core_ops ths8200_core_ops = {
 173         .log_status = ths8200_log_status,
 174         .s_power = ths8200_s_power,
 175 #ifdef CONFIG_VIDEO_ADV_DEBUG
 176         .g_register = ths8200_g_register,
 177         .s_register = ths8200_s_register,
 178 #endif
 179 };
 180
 181 /* -----------------------------------------------------------------------------
 182  * V4L2 subdev video operations
 183  */
 184
 185 static int ths8200_s_stream(struct v4l2_subdev *sd, int enable)
 186 {
 187         struct ths8200_state *state = to_state(sd);
 188
 189         if (enable && !state->power_on)
 190                 ths8200_s_power(sd, true);
 191
 192         ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xfe,
 193                              (enable ? 0x01 : 0x00));
 194
 195         v4l2_dbg(1, debug, sd, "%s: %sable\n",
 196                  __func__, (enable ? "en" : "dis"));
 197
 198         return 0;
 199 }
 200
 201 static void ths8200_core_init(struct v4l2_subdev *sd)
 202 {
 203         /* setup clocks */
 204         ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0x3f, 0xc0);
 205
 206         /**** Data path control (DATA) ****/
 207         /* Set FSADJ 700 mV,
 208          * bypass 422-444 interpolation,
 209          * input format 30 bit RGB444
 210          */
 211         ths8200_write(sd, THS8200_DATA_CNTL, 0x70);
 212
 213         /* DTG Mode (Video blocked during blanking
 214          * VESA slave
 215          */
 216         ths8200_write(sd, THS8200_DTG1_MODE, 0x87);
 217
 218         /**** Display Timing Generator Control, Part 1 (DTG1). ****/
 219
 220         /* Disable embedded syncs on the output by setting
 221          * the amplitude to zero for all channels.
 222          */
 223         ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x2a);
 224         ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x2a);
 225 }
 226
 227 static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt)
 228 {
 229         uint8_t polarity = 0;
 230         uint16_t line_start_active_video = (bt->vsync + bt->vbackporch);
 231         uint16_t line_start_front_porch  = (vtotal(bt) - bt->vfrontporch);
 232
 233         /*** System ****/
 234         /* Set chip in reset while it is configured */
 235         ths8200_s_stream(sd, false);
 236
 237         /* configure video output timings */
 238         ths8200_write(sd, THS8200_DTG1_SPEC_A, bt->hsync);
 239         ths8200_write(sd, THS8200_DTG1_SPEC_B, bt->hfrontporch);
 240
 241         /* Zero for progressive scan formats.*/
 242         if (!bt->interlaced)
 243                 ths8200_write(sd, THS8200_DTG1_SPEC_C, 0x00);
 244
 245         /* Distance from leading edge of h sync to start of active video.
 246          * MSB in 0x2b
 247          */
 248         ths8200_write(sd, THS8200_DTG1_SPEC_D_LSB,
 249                       (bt->hbackporch + bt->hsync) & 0xff);
 250         /* Zero for SDTV-mode. MSB in 0x2b */
 251         ths8200_write(sd, THS8200_DTG1_SPEC_E_LSB, 0x00);
 252         /*
 253          * MSB for dtg1_spec(d/e/h). See comment for
 254          * corresponding LSB registers.
 255          */
 256         ths8200_write(sd, THS8200_DTG1_SPEC_DEH_MSB,
 257                       ((bt->hbackporch + bt->hsync) & 0x100) >> 1);
 258
 259         /* h front porch */
 260         ths8200_write(sd, THS8200_DTG1_SPEC_K_LSB, (bt->hfrontporch) & 0xff);
 261         ths8200_write(sd, THS8200_DTG1_SPEC_K_MSB,
 262                       ((bt->hfrontporch) & 0x700) >> 8);
 263
 264         /* Half the line length. Used to calculate SDTV line types. */
 265         ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff);
 266         ths8200_write(sd, THS8200_DTG1_SPEC_G_MSB,
 267                       ((htotal(bt)/2) >> 8) & 0x0f);
 268
 269         /* Total pixels per line (ex. 720p: 1650) */
 270         ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8);
 271         ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff);
 272
 273         /* Frame height and field height */
 274         /* Field height should be programmed higher than frame_size for
 275          * progressive scan formats
 276          */
 277         ths8200_write(sd, THS8200_DTG1_FRAME_FIELD_SZ_MSB,
 278                       ((vtotal(bt) >> 4) & 0xf0) + 0x7);
 279         ths8200_write(sd, THS8200_DTG1_FRAME_SZ_LSB, vtotal(bt) & 0xff);
 280
 281         /* Should be programmed higher than frame_size
 282          * for progressive formats
 283          */
 284         if (!bt->interlaced)
 285                 ths8200_write(sd, THS8200_DTG1_FIELD_SZ_LSB, 0xff);
 286
 287         /**** Display Timing Generator Control, Part 2 (DTG2). ****/
 288         /* Set breakpoint line numbers and types
 289          * THS8200 generates line types with different properties. A line type
 290          * that sets all the RGB-outputs to zero is used in the blanking areas,
 291          * while a line type that enable the RGB-outputs is used in active video
 292          * area. The line numbers for start of active video, start of front
 293          * porch and after the last line in the frame must be set with the
 294          * corresponding line types.
 295          *
 296          * Line types:
 297          * 0x9 - Full normal sync pulse: Blocks data when dtg1_pass is off.
 298          *       Used in blanking area.
 299          * 0x0 - Active video: Video data is always passed. Used in active
 300          *       video area.
 301          */
 302         ths8200_write_and_or(sd, THS8200_DTG2_BP1_2_MSB, 0x88,
 303                              ((line_start_active_video >> 4) & 0x70) +
 304                              ((line_start_front_porch >> 8) & 0x07));
 305         ths8200_write(sd, THS8200_DTG2_BP3_4_MSB, ((vtotal(bt)) >> 4) & 0x70);
 306         ths8200_write(sd, THS8200_DTG2_BP1_LSB, line_start_active_video & 0xff);
 307         ths8200_write(sd, THS8200_DTG2_BP2_LSB, line_start_front_porch & 0xff);
 308         ths8200_write(sd, THS8200_DTG2_BP3_LSB, (vtotal(bt)) & 0xff);
 309
 310         /* line types */
 311         ths8200_write(sd, THS8200_DTG2_LINETYPE1, 0x90);
 312         ths8200_write(sd, THS8200_DTG2_LINETYPE2, 0x90);
 313
 314         /* h sync width transmitted */
 315         ths8200_write(sd, THS8200_DTG2_HLENGTH_LSB, bt->hsync & 0xff);
 316         ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0x3f,
 317                              (bt->hsync >> 2) & 0xc0);
 318
 319         /* The pixel value h sync is asserted on */
 320         ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0xe0,
 321                              (htotal(bt) >> 8) & 0x1f);
 322         ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt));
 323
 324         /* v sync width transmitted */
 325         ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync) & 0xff);
 326         ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f,
 327                              ((bt->vsync) >> 2) & 0xc0);
 328
 329         /* The pixel value v sync is asserted on */
 330         ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8,
 331                              (vtotal(bt)>>8) & 0x7);
 332         ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt));
 333
 334         /* For progressive video vlength2 must be set to all 0 and vdly2 must
 335          * be set to all 1.
 336          */
 337         ths8200_write(sd, THS8200_DTG2_VLENGTH2_LSB, 0x00);
 338         ths8200_write(sd, THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB, 0x07);
 339         ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff);
 340
 341         /* Internal delay factors to synchronize the sync pulses and the data */
 342         /* Experimental values delays (hor 4, ver 1) */
 343         ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, (htotal(bt)>>8) & 0x1f);
 344         ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, (htotal(bt) - 4) & 0xff);
 345         ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0);
 346         ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 1);
 347
 348         /* Polarity of received and transmitted sync signals */
 349         if (bt->polarities & V4L2_DV_HSYNC_POS_POL) {
 350                 polarity |= 0x01; /* HS_IN */
 351                 polarity |= 0x08; /* HS_OUT */
 352         }
 353         if (bt->polarities & V4L2_DV_VSYNC_POS_POL) {
 354                 polarity |= 0x02; /* VS_IN */
 355                 polarity |= 0x10; /* VS_OUT */
 356         }
 357
 358         /* RGB mode, no embedded timings */
 359         /* Timing of video input bus is derived from HS, VS, and FID dedicated
 360          * inputs
 361          */
 362         ths8200_write(sd, THS8200_DTG2_CNTL, 0x47 | polarity);
 363
 364         /* leave reset */
 365         ths8200_s_stream(sd, true);
 366
 367         v4l2_dbg(1, debug, sd, "%s: frame %dx%d, polarity %d\n"
 368                  "horizontal: front porch %d, back porch %d, sync %d\n"
 369                  "vertical: sync %d\n", __func__, htotal(bt), vtotal(bt),
 370                  polarity, bt->hfrontporch, bt->hbackporch,
 371                  bt->hsync, bt->vsync);
 372 }
 373
 374 static int ths8200_s_dv_timings(struct v4l2_subdev *sd,
 375                                 struct v4l2_dv_timings *timings)
 376 {
 377         struct ths8200_state *state = to_state(sd);
 378
 379         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 380
 381         if (!v4l2_dv_valid_timings(timings, &ths8200_timings_cap))
 382                 return -EINVAL;
 383
 384         if (!v4l2_find_dv_timings_cap(timings, &ths8200_timings_cap, 10)) {
 385                 v4l2_dbg(1, debug, sd, "Unsupported format\n");
 386                 return -EINVAL;
 387         }
 388
 389         timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
 390
 391         /* save timings */
 392         state->dv_timings = *timings;
 393
 394         ths8200_setup(sd, &timings->bt);
 395
 396         return 0;
 397 }
 398
 399 static int ths8200_g_dv_timings(struct v4l2_subdev *sd,
 400                                 struct v4l2_dv_timings *timings)
 401 {
 402         struct ths8200_state *state = to_state(sd);
 403
 404         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 405
 406         *timings = state->dv_timings;
 407
 408         return 0;
 409 }
 410
 411 static int ths8200_enum_dv_timings(struct v4l2_subdev *sd,
 412                                    struct v4l2_enum_dv_timings *timings)
 413 {
 414         return v4l2_enum_dv_timings_cap(timings, &ths8200_timings_cap);
 415 }
 416
 417 static int ths8200_dv_timings_cap(struct v4l2_subdev *sd,
 418                                   struct v4l2_dv_timings_cap *cap)
 419 {
 420         *cap = ths8200_timings_cap;
 421         return 0;
 422 }
 423
 424 /* Specific video subsystem operation handlers */
 425 static const struct v4l2_subdev_video_ops ths8200_video_ops = {
 426         .s_stream = ths8200_s_stream,
 427         .s_dv_timings = ths8200_s_dv_timings,
 428         .g_dv_timings = ths8200_g_dv_timings,
 429         .enum_dv_timings = ths8200_enum_dv_timings,
 430         .dv_timings_cap = ths8200_dv_timings_cap,
 431 };
 432
 433 /* V4L2 top level operation handlers */
 434 static const struct v4l2_subdev_ops ths8200_ops = {
 435         .core  = &ths8200_core_ops,
 436         .video = &ths8200_video_ops,
 437 };
 438
 439 static int ths8200_probe(struct i2c_client *client,
 440                          const struct i2c_device_id *id)
 441 {
 442         struct ths8200_state *state;
 443         struct v4l2_subdev *sd;
 444         int error;
 445
 446         /* Check if the adapter supports the needed features */
 447         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
 448                 return -EIO;
 449
 450         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
 451         if (!state)
 452                 return -ENOMEM;
 453
 454         sd = &state->sd;
 455         v4l2_i2c_subdev_init(sd, client, &ths8200_ops);
 456
 457         state->chip_version = ths8200_read(sd, THS8200_VERSION);
 458         v4l2_dbg(1, debug, sd, "chip version 0x%x\n", state->chip_version);
 459
 460         ths8200_core_init(sd);
 461
 462         error = v4l2_async_register_subdev(&state->sd);
 463         if (error)
 464                 return error;
 465
 466         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
 467                   client->addr << 1, client->adapter->name);
 468
 469         return 0;
 470 }
 471
 472 static int ths8200_remove(struct i2c_client *client)
 473 {
 474         struct v4l2_subdev *sd = i2c_get_clientdata(client);
 475         struct ths8200_state *decoder = to_state(sd);
 476
 477         v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
 478                  client->addr << 1, client->adapter->name);
 479
 480         ths8200_s_power(sd, false);
 481         v4l2_async_unregister_subdev(&decoder->sd);
 482         v4l2_device_unregister_subdev(sd);
 483
 484         return 0;
 485 }
 486
 487 static struct i2c_device_id ths8200_id[] = {
 488         { "ths8200", 0 },
 489         {},
 490 };
 491 MODULE_DEVICE_TABLE(i2c, ths8200_id);
 492
 493 #if IS_ENABLED(CONFIG_OF)
 494 static const struct of_device_id ths8200_of_match[] = {
 495         { .compatible = "ti,ths8200", },
 496         { /* sentinel */ },
 497 };
 498 MODULE_DEVICE_TABLE(of, ths8200_of_match);
 499 #endif
 500
 501 static struct i2c_driver ths8200_driver = {
 502         .driver = {
 503                 .owner = THIS_MODULE,
 504                 .name = "ths8200",
 505                 .of_match_table = of_match_ptr(ths8200_of_match),
 506         },
 507         .probe = ths8200_probe,
 508         .remove = ths8200_remove,
 509         .id_table = ths8200_id,
 510 };
 511
 512 module_i2c_driver(ths8200_driver);