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[media] cx23885: add DVBSky S950 support
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885-cards.c
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/delay.h>
22 #include <media/cx25840.h>
23 #include <linux/firmware.h>
24 #include <misc/altera.h>
25
26 #include "cx23885.h"
27 #include "tuner-xc2028.h"
28 #include "netup-eeprom.h"
29 #include "netup-init.h"
30 #include "altera-ci.h"
31 #include "xc4000.h"
32 #include "xc5000.h"
33 #include "cx23888-ir.h"
34
35 static unsigned int netup_card_rev = 4;
36 module_param(netup_card_rev, int, 0644);
37 MODULE_PARM_DESC(netup_card_rev,
38 "NetUP Dual DVB-T/C CI card revision");
39 static unsigned int enable_885_ir;
40 module_param(enable_885_ir, int, 0644);
41 MODULE_PARM_DESC(enable_885_ir,
42 "Enable integrated IR controller for supported\n"
43 "\t\t CX2388[57] boards that are wired for it:\n"
44 "\t\t\tHVR-1250 (reported safe)\n"
45 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n"
46 "\t\t\tTeVii S470 (reported unsafe)\n"
47 "\t\t This can cause an interrupt storm with some cards.\n"
48 "\t\t Default: 0 [Disabled]");
49
50 /* ------------------------------------------------------------------ */
51 /* board config info */
52
53 struct cx23885_board cx23885_boards[] = {
54 [CX23885_BOARD_UNKNOWN] = {
55 .name = "UNKNOWN/GENERIC",
56 /* Ensure safe default for unknown boards */
57 .clk_freq = 0,
58 .input = {{
59 .type = CX23885_VMUX_COMPOSITE1,
60 .vmux = 0,
61 }, {
62 .type = CX23885_VMUX_COMPOSITE2,
63 .vmux = 1,
64 }, {
65 .type = CX23885_VMUX_COMPOSITE3,
66 .vmux = 2,
67 }, {
68 .type = CX23885_VMUX_COMPOSITE4,
69 .vmux = 3,
70 } },
71 },
72 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
73 .name = "Hauppauge WinTV-HVR1800lp",
74 .portc = CX23885_MPEG_DVB,
75 .input = {{
76 .type = CX23885_VMUX_TELEVISION,
77 .vmux = 0,
78 .gpio0 = 0xff00,
79 }, {
80 .type = CX23885_VMUX_DEBUG,
81 .vmux = 0,
82 .gpio0 = 0xff01,
83 }, {
84 .type = CX23885_VMUX_COMPOSITE1,
85 .vmux = 1,
86 .gpio0 = 0xff02,
87 }, {
88 .type = CX23885_VMUX_SVIDEO,
89 .vmux = 2,
90 .gpio0 = 0xff02,
91 } },
92 },
93 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
94 .name = "Hauppauge WinTV-HVR1800",
95 .porta = CX23885_ANALOG_VIDEO,
96 .portb = CX23885_MPEG_ENCODER,
97 .portc = CX23885_MPEG_DVB,
98 .tuner_type = TUNER_PHILIPS_TDA8290,
99 .tuner_addr = 0x42, /* 0x84 >> 1 */
100 .tuner_bus = 1,
101 .input = {{
102 .type = CX23885_VMUX_TELEVISION,
103 .vmux = CX25840_VIN7_CH3 |
104 CX25840_VIN5_CH2 |
105 CX25840_VIN2_CH1,
106 .amux = CX25840_AUDIO8,
107 .gpio0 = 0,
108 }, {
109 .type = CX23885_VMUX_COMPOSITE1,
110 .vmux = CX25840_VIN7_CH3 |
111 CX25840_VIN4_CH2 |
112 CX25840_VIN6_CH1,
113 .amux = CX25840_AUDIO7,
114 .gpio0 = 0,
115 }, {
116 .type = CX23885_VMUX_SVIDEO,
117 .vmux = CX25840_VIN7_CH3 |
118 CX25840_VIN4_CH2 |
119 CX25840_VIN8_CH1 |
120 CX25840_SVIDEO_ON,
121 .amux = CX25840_AUDIO7,
122 .gpio0 = 0,
123 } },
124 },
125 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
126 .name = "Hauppauge WinTV-HVR1250",
127 .porta = CX23885_ANALOG_VIDEO,
128 .portc = CX23885_MPEG_DVB,
129 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
130 .tuner_type = TUNER_PHILIPS_TDA8290,
131 .tuner_addr = 0x42, /* 0x84 >> 1 */
132 .tuner_bus = 1,
133 #endif
134 .force_bff = 1,
135 .input = {{
136 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
137 .type = CX23885_VMUX_TELEVISION,
138 .vmux = CX25840_VIN7_CH3 |
139 CX25840_VIN5_CH2 |
140 CX25840_VIN2_CH1,
141 .amux = CX25840_AUDIO8,
142 .gpio0 = 0xff00,
143 }, {
144 #endif
145 .type = CX23885_VMUX_COMPOSITE1,
146 .vmux = CX25840_VIN7_CH3 |
147 CX25840_VIN4_CH2 |
148 CX25840_VIN6_CH1,
149 .amux = CX25840_AUDIO7,
150 .gpio0 = 0xff02,
151 }, {
152 .type = CX23885_VMUX_SVIDEO,
153 .vmux = CX25840_VIN7_CH3 |
154 CX25840_VIN4_CH2 |
155 CX25840_VIN8_CH1 |
156 CX25840_SVIDEO_ON,
157 .amux = CX25840_AUDIO7,
158 .gpio0 = 0xff02,
159 } },
160 },
161 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
162 .name = "DViCO FusionHDTV5 Express",
163 .portb = CX23885_MPEG_DVB,
164 },
165 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
166 .name = "Hauppauge WinTV-HVR1500Q",
167 .portc = CX23885_MPEG_DVB,
168 },
169 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
170 .name = "Hauppauge WinTV-HVR1500",
171 .porta = CX23885_ANALOG_VIDEO,
172 .portc = CX23885_MPEG_DVB,
173 .tuner_type = TUNER_XC2028,
174 .tuner_addr = 0x61, /* 0xc2 >> 1 */
175 .input = {{
176 .type = CX23885_VMUX_TELEVISION,
177 .vmux = CX25840_VIN7_CH3 |
178 CX25840_VIN5_CH2 |
179 CX25840_VIN2_CH1,
180 .gpio0 = 0,
181 }, {
182 .type = CX23885_VMUX_COMPOSITE1,
183 .vmux = CX25840_VIN7_CH3 |
184 CX25840_VIN4_CH2 |
185 CX25840_VIN6_CH1,
186 .gpio0 = 0,
187 }, {
188 .type = CX23885_VMUX_SVIDEO,
189 .vmux = CX25840_VIN7_CH3 |
190 CX25840_VIN4_CH2 |
191 CX25840_VIN8_CH1 |
192 CX25840_SVIDEO_ON,
193 .gpio0 = 0,
194 } },
195 },
196 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
197 .name = "Hauppauge WinTV-HVR1200",
198 .portc = CX23885_MPEG_DVB,
199 },
200 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
201 .name = "Hauppauge WinTV-HVR1700",
202 .portc = CX23885_MPEG_DVB,
203 },
204 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
205 .name = "Hauppauge WinTV-HVR1400",
206 .portc = CX23885_MPEG_DVB,
207 },
208 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
209 .name = "DViCO FusionHDTV7 Dual Express",
210 .portb = CX23885_MPEG_DVB,
211 .portc = CX23885_MPEG_DVB,
212 },
213 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
214 .name = "DViCO FusionHDTV DVB-T Dual Express",
215 .portb = CX23885_MPEG_DVB,
216 .portc = CX23885_MPEG_DVB,
217 },
218 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
219 .name = "Leadtek Winfast PxDVR3200 H",
220 .portc = CX23885_MPEG_DVB,
221 },
222 [CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200] = {
223 .name = "Leadtek Winfast PxPVR2200",
224 .porta = CX23885_ANALOG_VIDEO,
225 .tuner_type = TUNER_XC2028,
226 .tuner_addr = 0x61,
227 .tuner_bus = 1,
228 .input = {{
229 .type = CX23885_VMUX_TELEVISION,
230 .vmux = CX25840_VIN2_CH1 |
231 CX25840_VIN5_CH2,
232 .amux = CX25840_AUDIO8,
233 .gpio0 = 0x704040,
234 }, {
235 .type = CX23885_VMUX_COMPOSITE1,
236 .vmux = CX25840_COMPOSITE1,
237 .amux = CX25840_AUDIO7,
238 .gpio0 = 0x704040,
239 }, {
240 .type = CX23885_VMUX_SVIDEO,
241 .vmux = CX25840_SVIDEO_LUMA3 |
242 CX25840_SVIDEO_CHROMA4,
243 .amux = CX25840_AUDIO7,
244 .gpio0 = 0x704040,
245 }, {
246 .type = CX23885_VMUX_COMPONENT,
247 .vmux = CX25840_VIN7_CH1 |
248 CX25840_VIN6_CH2 |
249 CX25840_VIN8_CH3 |
250 CX25840_COMPONENT_ON,
251 .amux = CX25840_AUDIO7,
252 .gpio0 = 0x704040,
253 } },
254 },
255 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
256 .name = "Leadtek Winfast PxDVR3200 H XC4000",
257 .porta = CX23885_ANALOG_VIDEO,
258 .portc = CX23885_MPEG_DVB,
259 .tuner_type = TUNER_XC4000,
260 .tuner_addr = 0x61,
261 .radio_type = UNSET,
262 .radio_addr = ADDR_UNSET,
263 .input = {{
264 .type = CX23885_VMUX_TELEVISION,
265 .vmux = CX25840_VIN2_CH1 |
266 CX25840_VIN5_CH2 |
267 CX25840_NONE0_CH3,
268 }, {
269 .type = CX23885_VMUX_COMPOSITE1,
270 .vmux = CX25840_COMPOSITE1,
271 }, {
272 .type = CX23885_VMUX_SVIDEO,
273 .vmux = CX25840_SVIDEO_LUMA3 |
274 CX25840_SVIDEO_CHROMA4,
275 }, {
276 .type = CX23885_VMUX_COMPONENT,
277 .vmux = CX25840_VIN7_CH1 |
278 CX25840_VIN6_CH2 |
279 CX25840_VIN8_CH3 |
280 CX25840_COMPONENT_ON,
281 } },
282 },
283 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
284 .name = "Compro VideoMate E650F",
285 .portc = CX23885_MPEG_DVB,
286 },
287 [CX23885_BOARD_TBS_6920] = {
288 .name = "TurboSight TBS 6920",
289 .portb = CX23885_MPEG_DVB,
290 },
291 [CX23885_BOARD_TBS_6980] = {
292 .name = "TurboSight TBS 6980",
293 .portb = CX23885_MPEG_DVB,
294 .portc = CX23885_MPEG_DVB,
295 },
296 [CX23885_BOARD_TBS_6981] = {
297 .name = "TurboSight TBS 6981",
298 .portb = CX23885_MPEG_DVB,
299 .portc = CX23885_MPEG_DVB,
300 },
301 [CX23885_BOARD_TEVII_S470] = {
302 .name = "TeVii S470",
303 .portb = CX23885_MPEG_DVB,
304 },
305 [CX23885_BOARD_DVBWORLD_2005] = {
306 .name = "DVBWorld DVB-S2 2005",
307 .portb = CX23885_MPEG_DVB,
308 },
309 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
310 .ci_type = 1,
311 .name = "NetUP Dual DVB-S2 CI",
312 .portb = CX23885_MPEG_DVB,
313 .portc = CX23885_MPEG_DVB,
314 },
315 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
316 .name = "Hauppauge WinTV-HVR1270",
317 .portc = CX23885_MPEG_DVB,
318 },
319 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
320 .name = "Hauppauge WinTV-HVR1275",
321 .portc = CX23885_MPEG_DVB,
322 },
323 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
324 .name = "Hauppauge WinTV-HVR1255",
325 .porta = CX23885_ANALOG_VIDEO,
326 .portc = CX23885_MPEG_DVB,
327 .tuner_type = TUNER_ABSENT,
328 .tuner_addr = 0x42, /* 0x84 >> 1 */
329 .force_bff = 1,
330 .input = {{
331 .type = CX23885_VMUX_TELEVISION,
332 .vmux = CX25840_VIN7_CH3 |
333 CX25840_VIN5_CH2 |
334 CX25840_VIN2_CH1 |
335 CX25840_DIF_ON,
336 .amux = CX25840_AUDIO8,
337 }, {
338 .type = CX23885_VMUX_COMPOSITE1,
339 .vmux = CX25840_VIN7_CH3 |
340 CX25840_VIN4_CH2 |
341 CX25840_VIN6_CH1,
342 .amux = CX25840_AUDIO7,
343 }, {
344 .type = CX23885_VMUX_SVIDEO,
345 .vmux = CX25840_VIN7_CH3 |
346 CX25840_VIN4_CH2 |
347 CX25840_VIN8_CH1 |
348 CX25840_SVIDEO_ON,
349 .amux = CX25840_AUDIO7,
350 } },
351 },
352 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
353 .name = "Hauppauge WinTV-HVR1255",
354 .porta = CX23885_ANALOG_VIDEO,
355 .portc = CX23885_MPEG_DVB,
356 .tuner_type = TUNER_ABSENT,
357 .tuner_addr = 0x42, /* 0x84 >> 1 */
358 .force_bff = 1,
359 .input = {{
360 .type = CX23885_VMUX_TELEVISION,
361 .vmux = CX25840_VIN7_CH3 |
362 CX25840_VIN5_CH2 |
363 CX25840_VIN2_CH1 |
364 CX25840_DIF_ON,
365 .amux = CX25840_AUDIO8,
366 }, {
367 .type = CX23885_VMUX_SVIDEO,
368 .vmux = CX25840_VIN7_CH3 |
369 CX25840_VIN4_CH2 |
370 CX25840_VIN8_CH1 |
371 CX25840_SVIDEO_ON,
372 .amux = CX25840_AUDIO7,
373 } },
374 },
375 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
376 .name = "Hauppauge WinTV-HVR1210",
377 .portc = CX23885_MPEG_DVB,
378 },
379 [CX23885_BOARD_MYGICA_X8506] = {
380 .name = "Mygica X8506 DMB-TH",
381 .tuner_type = TUNER_XC5000,
382 .tuner_addr = 0x61,
383 .tuner_bus = 1,
384 .porta = CX23885_ANALOG_VIDEO,
385 .portb = CX23885_MPEG_DVB,
386 .input = {
387 {
388 .type = CX23885_VMUX_TELEVISION,
389 .vmux = CX25840_COMPOSITE2,
390 },
391 {
392 .type = CX23885_VMUX_COMPOSITE1,
393 .vmux = CX25840_COMPOSITE8,
394 },
395 {
396 .type = CX23885_VMUX_SVIDEO,
397 .vmux = CX25840_SVIDEO_LUMA3 |
398 CX25840_SVIDEO_CHROMA4,
399 },
400 {
401 .type = CX23885_VMUX_COMPONENT,
402 .vmux = CX25840_COMPONENT_ON |
403 CX25840_VIN1_CH1 |
404 CX25840_VIN6_CH2 |
405 CX25840_VIN7_CH3,
406 },
407 },
408 },
409 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
410 .name = "Magic-Pro ProHDTV Extreme 2",
411 .tuner_type = TUNER_XC5000,
412 .tuner_addr = 0x61,
413 .tuner_bus = 1,
414 .porta = CX23885_ANALOG_VIDEO,
415 .portb = CX23885_MPEG_DVB,
416 .input = {
417 {
418 .type = CX23885_VMUX_TELEVISION,
419 .vmux = CX25840_COMPOSITE2,
420 },
421 {
422 .type = CX23885_VMUX_COMPOSITE1,
423 .vmux = CX25840_COMPOSITE8,
424 },
425 {
426 .type = CX23885_VMUX_SVIDEO,
427 .vmux = CX25840_SVIDEO_LUMA3 |
428 CX25840_SVIDEO_CHROMA4,
429 },
430 {
431 .type = CX23885_VMUX_COMPONENT,
432 .vmux = CX25840_COMPONENT_ON |
433 CX25840_VIN1_CH1 |
434 CX25840_VIN6_CH2 |
435 CX25840_VIN7_CH3,
436 },
437 },
438 },
439 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
440 .name = "Hauppauge WinTV-HVR1850",
441 .porta = CX23885_ANALOG_VIDEO,
442 .portb = CX23885_MPEG_ENCODER,
443 .portc = CX23885_MPEG_DVB,
444 .tuner_type = TUNER_ABSENT,
445 .tuner_addr = 0x42, /* 0x84 >> 1 */
446 .force_bff = 1,
447 .input = {{
448 .type = CX23885_VMUX_TELEVISION,
449 .vmux = CX25840_VIN7_CH3 |
450 CX25840_VIN5_CH2 |
451 CX25840_VIN2_CH1 |
452 CX25840_DIF_ON,
453 .amux = CX25840_AUDIO8,
454 }, {
455 .type = CX23885_VMUX_COMPOSITE1,
456 .vmux = CX25840_VIN7_CH3 |
457 CX25840_VIN4_CH2 |
458 CX25840_VIN6_CH1,
459 .amux = CX25840_AUDIO7,
460 }, {
461 .type = CX23885_VMUX_SVIDEO,
462 .vmux = CX25840_VIN7_CH3 |
463 CX25840_VIN4_CH2 |
464 CX25840_VIN8_CH1 |
465 CX25840_SVIDEO_ON,
466 .amux = CX25840_AUDIO7,
467 } },
468 },
469 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
470 .name = "Compro VideoMate E800",
471 .portc = CX23885_MPEG_DVB,
472 },
473 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
474 .name = "Hauppauge WinTV-HVR1290",
475 .portc = CX23885_MPEG_DVB,
476 },
477 [CX23885_BOARD_MYGICA_X8558PRO] = {
478 .name = "Mygica X8558 PRO DMB-TH",
479 .portb = CX23885_MPEG_DVB,
480 .portc = CX23885_MPEG_DVB,
481 },
482 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
483 .name = "LEADTEK WinFast PxTV1200",
484 .porta = CX23885_ANALOG_VIDEO,
485 .tuner_type = TUNER_XC2028,
486 .tuner_addr = 0x61,
487 .tuner_bus = 1,
488 .input = {{
489 .type = CX23885_VMUX_TELEVISION,
490 .vmux = CX25840_VIN2_CH1 |
491 CX25840_VIN5_CH2 |
492 CX25840_NONE0_CH3,
493 }, {
494 .type = CX23885_VMUX_COMPOSITE1,
495 .vmux = CX25840_COMPOSITE1,
496 }, {
497 .type = CX23885_VMUX_SVIDEO,
498 .vmux = CX25840_SVIDEO_LUMA3 |
499 CX25840_SVIDEO_CHROMA4,
500 }, {
501 .type = CX23885_VMUX_COMPONENT,
502 .vmux = CX25840_VIN7_CH1 |
503 CX25840_VIN6_CH2 |
504 CX25840_VIN8_CH3 |
505 CX25840_COMPONENT_ON,
506 } },
507 },
508 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
509 .name = "GoTView X5 3D Hybrid",
510 .tuner_type = TUNER_XC5000,
511 .tuner_addr = 0x64,
512 .tuner_bus = 1,
513 .porta = CX23885_ANALOG_VIDEO,
514 .portb = CX23885_MPEG_DVB,
515 .input = {{
516 .type = CX23885_VMUX_TELEVISION,
517 .vmux = CX25840_VIN2_CH1 |
518 CX25840_VIN5_CH2,
519 .gpio0 = 0x02,
520 }, {
521 .type = CX23885_VMUX_COMPOSITE1,
522 .vmux = CX23885_VMUX_COMPOSITE1,
523 }, {
524 .type = CX23885_VMUX_SVIDEO,
525 .vmux = CX25840_SVIDEO_LUMA3 |
526 CX25840_SVIDEO_CHROMA4,
527 } },
528 },
529 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
530 .ci_type = 2,
531 .name = "NetUP Dual DVB-T/C-CI RF",
532 .porta = CX23885_ANALOG_VIDEO,
533 .portb = CX23885_MPEG_DVB,
534 .portc = CX23885_MPEG_DVB,
535 .num_fds_portb = 2,
536 .num_fds_portc = 2,
537 .tuner_type = TUNER_XC5000,
538 .tuner_addr = 0x64,
539 .input = { {
540 .type = CX23885_VMUX_TELEVISION,
541 .vmux = CX25840_COMPOSITE1,
542 } },
543 },
544 [CX23885_BOARD_MPX885] = {
545 .name = "MPX-885",
546 .porta = CX23885_ANALOG_VIDEO,
547 .input = {{
548 .type = CX23885_VMUX_COMPOSITE1,
549 .vmux = CX25840_COMPOSITE1,
550 .amux = CX25840_AUDIO6,
551 .gpio0 = 0,
552 }, {
553 .type = CX23885_VMUX_COMPOSITE2,
554 .vmux = CX25840_COMPOSITE2,
555 .amux = CX25840_AUDIO6,
556 .gpio0 = 0,
557 }, {
558 .type = CX23885_VMUX_COMPOSITE3,
559 .vmux = CX25840_COMPOSITE3,
560 .amux = CX25840_AUDIO7,
561 .gpio0 = 0,
562 }, {
563 .type = CX23885_VMUX_COMPOSITE4,
564 .vmux = CX25840_COMPOSITE4,
565 .amux = CX25840_AUDIO7,
566 .gpio0 = 0,
567 } },
568 },
569 [CX23885_BOARD_MYGICA_X8507] = {
570 .name = "Mygica X8502/X8507 ISDB-T",
571 .tuner_type = TUNER_XC5000,
572 .tuner_addr = 0x61,
573 .tuner_bus = 1,
574 .porta = CX23885_ANALOG_VIDEO,
575 .portb = CX23885_MPEG_DVB,
576 .input = {
577 {
578 .type = CX23885_VMUX_TELEVISION,
579 .vmux = CX25840_COMPOSITE2,
580 .amux = CX25840_AUDIO8,
581 },
582 {
583 .type = CX23885_VMUX_COMPOSITE1,
584 .vmux = CX25840_COMPOSITE8,
585 .amux = CX25840_AUDIO7,
586 },
587 {
588 .type = CX23885_VMUX_SVIDEO,
589 .vmux = CX25840_SVIDEO_LUMA3 |
590 CX25840_SVIDEO_CHROMA4,
591 .amux = CX25840_AUDIO7,
592 },
593 {
594 .type = CX23885_VMUX_COMPONENT,
595 .vmux = CX25840_COMPONENT_ON |
596 CX25840_VIN1_CH1 |
597 CX25840_VIN6_CH2 |
598 CX25840_VIN7_CH3,
599 .amux = CX25840_AUDIO7,
600 },
601 },
602 },
603 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
604 .name = "TerraTec Cinergy T PCIe Dual",
605 .portb = CX23885_MPEG_DVB,
606 .portc = CX23885_MPEG_DVB,
607 },
608 [CX23885_BOARD_TEVII_S471] = {
609 .name = "TeVii S471",
610 .portb = CX23885_MPEG_DVB,
611 },
612 [CX23885_BOARD_PROF_8000] = {
613 .name = "Prof Revolution DVB-S2 8000",
614 .portb = CX23885_MPEG_DVB,
615 },
616 [CX23885_BOARD_HAUPPAUGE_HVR4400] = {
617 .name = "Hauppauge WinTV-HVR4400",
618 .porta = CX23885_ANALOG_VIDEO,
619 .portb = CX23885_MPEG_DVB,
620 .portc = CX23885_MPEG_DVB,
621 .tuner_type = TUNER_NXP_TDA18271,
622 .tuner_addr = 0x60, /* 0xc0 >> 1 */
623 .tuner_bus = 1,
624 },
625 [CX23885_BOARD_AVERMEDIA_HC81R] = {
626 .name = "AVerTV Hybrid Express Slim HC81R",
627 .tuner_type = TUNER_XC2028,
628 .tuner_addr = 0x61, /* 0xc2 >> 1 */
629 .tuner_bus = 1,
630 .porta = CX23885_ANALOG_VIDEO,
631 .input = {{
632 .type = CX23885_VMUX_TELEVISION,
633 .vmux = CX25840_VIN2_CH1 |
634 CX25840_VIN5_CH2 |
635 CX25840_NONE0_CH3 |
636 CX25840_NONE1_CH3,
637 .amux = CX25840_AUDIO8,
638 }, {
639 .type = CX23885_VMUX_SVIDEO,
640 .vmux = CX25840_VIN8_CH1 |
641 CX25840_NONE_CH2 |
642 CX25840_VIN7_CH3 |
643 CX25840_SVIDEO_ON,
644 .amux = CX25840_AUDIO6,
645 }, {
646 .type = CX23885_VMUX_COMPONENT,
647 .vmux = CX25840_VIN1_CH1 |
648 CX25840_NONE_CH2 |
649 CX25840_NONE0_CH3 |
650 CX25840_NONE1_CH3,
651 .amux = CX25840_AUDIO6,
652 } },
653 },
654 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2] = {
655 .name = "DViCO FusionHDTV DVB-T Dual Express2",
656 .portb = CX23885_MPEG_DVB,
657 .portc = CX23885_MPEG_DVB,
658 },
659 [CX23885_BOARD_HAUPPAUGE_IMPACTVCBE] = {
660 .name = "Hauppauge ImpactVCB-e",
661 .tuner_type = TUNER_ABSENT,
662 .porta = CX23885_ANALOG_VIDEO,
663 .input = {{
664 .type = CX23885_VMUX_COMPOSITE1,
665 .vmux = CX25840_VIN7_CH3 |
666 CX25840_VIN4_CH2 |
667 CX25840_VIN6_CH1,
668 .amux = CX25840_AUDIO7,
669 }, {
670 .type = CX23885_VMUX_SVIDEO,
671 .vmux = CX25840_VIN7_CH3 |
672 CX25840_VIN4_CH2 |
673 CX25840_VIN8_CH1 |
674 CX25840_SVIDEO_ON,
675 .amux = CX25840_AUDIO7,
676 } },
677 },
678 [CX23885_BOARD_DVBSKY_T9580] = {
679 .name = "DVBSky T9580",
680 .portb = CX23885_MPEG_DVB,
681 .portc = CX23885_MPEG_DVB,
682 },
683 [CX23885_BOARD_DVBSKY_T980C] = {
684 .name = "DVBSky T980C",
685 .portb = CX23885_MPEG_DVB,
686 },
687 [CX23885_BOARD_DVBSKY_S950C] = {
688 .name = "DVBSky S950C",
689 .portb = CX23885_MPEG_DVB,
690 },
691 [CX23885_BOARD_TT_CT2_4500_CI] = {
692 .name = "Technotrend TT-budget CT2-4500 CI",
693 .portb = CX23885_MPEG_DVB,
694 },
695 [CX23885_BOARD_DVBSKY_S950] = {
696 .name = "DVBSky S950",
697 .portb = CX23885_MPEG_DVB,
698 },
699 };
700 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
701
702 /* ------------------------------------------------------------------ */
703 /* PCI subsystem IDs */
704
705 struct cx23885_subid cx23885_subids[] = {
706 {
707 .subvendor = 0x0070,
708 .subdevice = 0x3400,
709 .card = CX23885_BOARD_UNKNOWN,
710 }, {
711 .subvendor = 0x0070,
712 .subdevice = 0x7600,
713 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
714 }, {
715 .subvendor = 0x0070,
716 .subdevice = 0x7800,
717 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
718 }, {
719 .subvendor = 0x0070,
720 .subdevice = 0x7801,
721 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
722 }, {
723 .subvendor = 0x0070,
724 .subdevice = 0x7809,
725 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
726 }, {
727 .subvendor = 0x0070,
728 .subdevice = 0x7911,
729 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
730 }, {
731 .subvendor = 0x18ac,
732 .subdevice = 0xd500,
733 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
734 }, {
735 .subvendor = 0x0070,
736 .subdevice = 0x7790,
737 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
738 }, {
739 .subvendor = 0x0070,
740 .subdevice = 0x7797,
741 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
742 }, {
743 .subvendor = 0x0070,
744 .subdevice = 0x7710,
745 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
746 }, {
747 .subvendor = 0x0070,
748 .subdevice = 0x7717,
749 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
750 }, {
751 .subvendor = 0x0070,
752 .subdevice = 0x71d1,
753 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
754 }, {
755 .subvendor = 0x0070,
756 .subdevice = 0x71d3,
757 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
758 }, {
759 .subvendor = 0x0070,
760 .subdevice = 0x8101,
761 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
762 }, {
763 .subvendor = 0x0070,
764 .subdevice = 0x8010,
765 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
766 }, {
767 .subvendor = 0x18ac,
768 .subdevice = 0xd618,
769 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
770 }, {
771 .subvendor = 0x18ac,
772 .subdevice = 0xdb78,
773 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
774 }, {
775 .subvendor = 0x107d,
776 .subdevice = 0x6681,
777 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
778 }, {
779 .subvendor = 0x107d,
780 .subdevice = 0x6f21,
781 .card = CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200,
782 }, {
783 .subvendor = 0x107d,
784 .subdevice = 0x6f39,
785 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
786 }, {
787 .subvendor = 0x185b,
788 .subdevice = 0xe800,
789 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
790 }, {
791 .subvendor = 0x6920,
792 .subdevice = 0x8888,
793 .card = CX23885_BOARD_TBS_6920,
794 }, {
795 .subvendor = 0x6980,
796 .subdevice = 0x8888,
797 .card = CX23885_BOARD_TBS_6980,
798 }, {
799 .subvendor = 0x6981,
800 .subdevice = 0x8888,
801 .card = CX23885_BOARD_TBS_6981,
802 }, {
803 .subvendor = 0xd470,
804 .subdevice = 0x9022,
805 .card = CX23885_BOARD_TEVII_S470,
806 }, {
807 .subvendor = 0x0001,
808 .subdevice = 0x2005,
809 .card = CX23885_BOARD_DVBWORLD_2005,
810 }, {
811 .subvendor = 0x1b55,
812 .subdevice = 0x2a2c,
813 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
814 }, {
815 .subvendor = 0x0070,
816 .subdevice = 0x2211,
817 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
818 }, {
819 .subvendor = 0x0070,
820 .subdevice = 0x2215,
821 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
822 }, {
823 .subvendor = 0x0070,
824 .subdevice = 0x221d,
825 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
826 }, {
827 .subvendor = 0x0070,
828 .subdevice = 0x2251,
829 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
830 }, {
831 .subvendor = 0x0070,
832 .subdevice = 0x2259,
833 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
834 }, {
835 .subvendor = 0x0070,
836 .subdevice = 0x2291,
837 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
838 }, {
839 .subvendor = 0x0070,
840 .subdevice = 0x2295,
841 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
842 }, {
843 .subvendor = 0x0070,
844 .subdevice = 0x2299,
845 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
846 }, {
847 .subvendor = 0x0070,
848 .subdevice = 0x229d,
849 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
850 }, {
851 .subvendor = 0x0070,
852 .subdevice = 0x22f0,
853 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
854 }, {
855 .subvendor = 0x0070,
856 .subdevice = 0x22f1,
857 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
858 }, {
859 .subvendor = 0x0070,
860 .subdevice = 0x22f2,
861 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
862 }, {
863 .subvendor = 0x0070,
864 .subdevice = 0x22f3,
865 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
866 }, {
867 .subvendor = 0x0070,
868 .subdevice = 0x22f4,
869 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
870 }, {
871 .subvendor = 0x0070,
872 .subdevice = 0x22f5,
873 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
874 }, {
875 .subvendor = 0x14f1,
876 .subdevice = 0x8651,
877 .card = CX23885_BOARD_MYGICA_X8506,
878 }, {
879 .subvendor = 0x14f1,
880 .subdevice = 0x8657,
881 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
882 }, {
883 .subvendor = 0x0070,
884 .subdevice = 0x8541,
885 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
886 }, {
887 .subvendor = 0x1858,
888 .subdevice = 0xe800,
889 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
890 }, {
891 .subvendor = 0x0070,
892 .subdevice = 0x8551,
893 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
894 }, {
895 .subvendor = 0x14f1,
896 .subdevice = 0x8578,
897 .card = CX23885_BOARD_MYGICA_X8558PRO,
898 }, {
899 .subvendor = 0x107d,
900 .subdevice = 0x6f22,
901 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
902 }, {
903 .subvendor = 0x5654,
904 .subdevice = 0x2390,
905 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
906 }, {
907 .subvendor = 0x1b55,
908 .subdevice = 0xe2e4,
909 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
910 }, {
911 .subvendor = 0x14f1,
912 .subdevice = 0x8502,
913 .card = CX23885_BOARD_MYGICA_X8507,
914 }, {
915 .subvendor = 0x153b,
916 .subdevice = 0x117e,
917 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
918 }, {
919 .subvendor = 0xd471,
920 .subdevice = 0x9022,
921 .card = CX23885_BOARD_TEVII_S471,
922 }, {
923 .subvendor = 0x8000,
924 .subdevice = 0x3034,
925 .card = CX23885_BOARD_PROF_8000,
926 }, {
927 .subvendor = 0x0070,
928 .subdevice = 0xc108,
929 .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
930 }, {
931 .subvendor = 0x0070,
932 .subdevice = 0xc138,
933 .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
934 }, {
935 .subvendor = 0x0070,
936 .subdevice = 0xc12a,
937 .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
938 }, {
939 .subvendor = 0x0070,
940 .subdevice = 0xc1f8,
941 .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
942 }, {
943 .subvendor = 0x1461,
944 .subdevice = 0xd939,
945 .card = CX23885_BOARD_AVERMEDIA_HC81R,
946 }, {
947 .subvendor = 0x0070,
948 .subdevice = 0x7133,
949 .card = CX23885_BOARD_HAUPPAUGE_IMPACTVCBE,
950 }, {
951 .subvendor = 0x18ac,
952 .subdevice = 0xdb98,
953 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2,
954 }, {
955 .subvendor = 0x4254,
956 .subdevice = 0x9580,
957 .card = CX23885_BOARD_DVBSKY_T9580,
958 }, {
959 .subvendor = 0x4254,
960 .subdevice = 0x980c,
961 .card = CX23885_BOARD_DVBSKY_T980C,
962 }, {
963 .subvendor = 0x4254,
964 .subdevice = 0x950c,
965 .card = CX23885_BOARD_DVBSKY_S950C,
966 }, {
967 .subvendor = 0x13c2,
968 .subdevice = 0x3013,
969 .card = CX23885_BOARD_TT_CT2_4500_CI,
970 }, {
971 .subvendor = 0x4254,
972 .subdevice = 0x0950,
973 .card = CX23885_BOARD_DVBSKY_S950,
974 },
975 };
976 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
977
978 void cx23885_card_list(struct cx23885_dev *dev)
979 {
980 int i;
981
982 if (0 == dev->pci->subsystem_vendor &&
983 0 == dev->pci->subsystem_device) {
984 printk(KERN_INFO
985 "%s: Board has no valid PCIe Subsystem ID and can't\n"
986 "%s: be autodetected. Pass card=<n> insmod option\n"
987 "%s: to workaround that. Redirect complaints to the\n"
988 "%s: vendor of the TV card. Best regards,\n"
989 "%s: -- tux\n",
990 dev->name, dev->name, dev->name, dev->name, dev->name);
991 } else {
992 printk(KERN_INFO
993 "%s: Your board isn't known (yet) to the driver.\n"
994 "%s: Try to pick one of the existing card configs via\n"
995 "%s: card=<n> insmod option. Updating to the latest\n"
996 "%s: version might help as well.\n",
997 dev->name, dev->name, dev->name, dev->name);
998 }
999 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
1000 dev->name);
1001 for (i = 0; i < cx23885_bcount; i++)
1002 printk(KERN_INFO "%s: card=%d -> %s\n",
1003 dev->name, i, cx23885_boards[i].name);
1004 }
1005
1006 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
1007 {
1008 struct tveeprom tv;
1009
1010 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
1011 eeprom_data);
1012
1013 /* Make sure we support the board model */
1014 switch (tv.model) {
1015 case 22001:
1016 /* WinTV-HVR1270 (PCIe, Retail, half height)
1017 * ATSC/QAM and basic analog, IR Blast */
1018 case 22009:
1019 /* WinTV-HVR1210 (PCIe, Retail, half height)
1020 * DVB-T and basic analog, IR Blast */
1021 case 22011:
1022 /* WinTV-HVR1270 (PCIe, Retail, half height)
1023 * ATSC/QAM and basic analog, IR Recv */
1024 case 22019:
1025 /* WinTV-HVR1210 (PCIe, Retail, half height)
1026 * DVB-T and basic analog, IR Recv */
1027 case 22021:
1028 /* WinTV-HVR1275 (PCIe, Retail, half height)
1029 * ATSC/QAM and basic analog, IR Recv */
1030 case 22029:
1031 /* WinTV-HVR1210 (PCIe, Retail, half height)
1032 * DVB-T and basic analog, IR Recv */
1033 case 22101:
1034 /* WinTV-HVR1270 (PCIe, Retail, full height)
1035 * ATSC/QAM and basic analog, IR Blast */
1036 case 22109:
1037 /* WinTV-HVR1210 (PCIe, Retail, full height)
1038 * DVB-T and basic analog, IR Blast */
1039 case 22111:
1040 /* WinTV-HVR1270 (PCIe, Retail, full height)
1041 * ATSC/QAM and basic analog, IR Recv */
1042 case 22119:
1043 /* WinTV-HVR1210 (PCIe, Retail, full height)
1044 * DVB-T and basic analog, IR Recv */
1045 case 22121:
1046 /* WinTV-HVR1275 (PCIe, Retail, full height)
1047 * ATSC/QAM and basic analog, IR Recv */
1048 case 22129:
1049 /* WinTV-HVR1210 (PCIe, Retail, full height)
1050 * DVB-T and basic analog, IR Recv */
1051 case 71009:
1052 /* WinTV-HVR1200 (PCIe, Retail, full height)
1053 * DVB-T and basic analog */
1054 case 71100:
1055 /* WinTV-ImpactVCB-e (PCIe, Retail, half height)
1056 * Basic analog */
1057 case 71359:
1058 /* WinTV-HVR1200 (PCIe, OEM, half height)
1059 * DVB-T and basic analog */
1060 case 71439:
1061 /* WinTV-HVR1200 (PCIe, OEM, half height)
1062 * DVB-T and basic analog */
1063 case 71449:
1064 /* WinTV-HVR1200 (PCIe, OEM, full height)
1065 * DVB-T and basic analog */
1066 case 71939:
1067 /* WinTV-HVR1200 (PCIe, OEM, half height)
1068 * DVB-T and basic analog */
1069 case 71949:
1070 /* WinTV-HVR1200 (PCIe, OEM, full height)
1071 * DVB-T and basic analog */
1072 case 71959:
1073 /* WinTV-HVR1200 (PCIe, OEM, full height)
1074 * DVB-T and basic analog */
1075 case 71979:
1076 /* WinTV-HVR1200 (PCIe, OEM, half height)
1077 * DVB-T and basic analog */
1078 case 71999:
1079 /* WinTV-HVR1200 (PCIe, OEM, full height)
1080 * DVB-T and basic analog */
1081 case 76601:
1082 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
1083 channel ATSC and MPEG2 HW Encoder */
1084 case 77001:
1085 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
1086 and Basic analog */
1087 case 77011:
1088 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
1089 and Basic analog */
1090 case 77041:
1091 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
1092 and Basic analog */
1093 case 77051:
1094 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
1095 and Basic analog */
1096 case 78011:
1097 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
1098 Dual channel ATSC and MPEG2 HW Encoder */
1099 case 78501:
1100 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
1101 Dual channel ATSC and MPEG2 HW Encoder */
1102 case 78521:
1103 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
1104 Dual channel ATSC and MPEG2 HW Encoder */
1105 case 78531:
1106 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
1107 Dual channel ATSC and MPEG2 HW Encoder */
1108 case 78631:
1109 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
1110 Dual channel ATSC and MPEG2 HW Encoder */
1111 case 79001:
1112 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
1113 ATSC and Basic analog */
1114 case 79101:
1115 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
1116 ATSC and Basic analog */
1117 case 79501:
1118 /* WinTV-HVR1250 (PCIe, No IR, half height,
1119 ATSC [at least] and Basic analog) */
1120 case 79561:
1121 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
1122 ATSC and Basic analog */
1123 case 79571:
1124 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
1125 ATSC and Basic analog */
1126 case 79671:
1127 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
1128 ATSC and Basic analog */
1129 case 80019:
1130 /* WinTV-HVR1400 (Express Card, Retail, IR,
1131 * DVB-T and Basic analog */
1132 case 81509:
1133 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
1134 * DVB-T and MPEG2 HW Encoder */
1135 case 81519:
1136 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
1137 * DVB-T and MPEG2 HW Encoder */
1138 break;
1139 case 85021:
1140 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
1141 Dual channel ATSC and MPEG2 HW Encoder */
1142 break;
1143 case 85721:
1144 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
1145 Dual channel ATSC and Basic analog */
1146 break;
1147 default:
1148 printk(KERN_WARNING "%s: warning: "
1149 "unknown hauppauge model #%d\n",
1150 dev->name, tv.model);
1151 break;
1152 }
1153
1154 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
1155 dev->name, tv.model);
1156 }
1157
1158 /* Some TBS cards require initing a chip using a bitbanged SPI attached
1159 to the cx23885 gpio's. If this chip doesn't get init'ed the demod
1160 doesn't respond to any command. */
1161 static void tbs_card_init(struct cx23885_dev *dev)
1162 {
1163 int i;
1164 const u8 buf[] = {
1165 0xe0, 0x06, 0x66, 0x33, 0x65,
1166 0x01, 0x17, 0x06, 0xde};
1167
1168 switch (dev->board) {
1169 case CX23885_BOARD_TBS_6980:
1170 case CX23885_BOARD_TBS_6981:
1171 cx_set(GP0_IO, 0x00070007);
1172 usleep_range(1000, 10000);
1173 cx_clear(GP0_IO, 2);
1174 usleep_range(1000, 10000);
1175 for (i = 0; i < 9 * 8; i++) {
1176 cx_clear(GP0_IO, 7);
1177 usleep_range(1000, 10000);
1178 cx_set(GP0_IO,
1179 ((buf[i >> 3] >> (7 - (i & 7))) & 1) | 4);
1180 usleep_range(1000, 10000);
1181 }
1182 cx_set(GP0_IO, 7);
1183 break;
1184 }
1185 }
1186
1187 int cx23885_tuner_callback(void *priv, int component, int command, int arg)
1188 {
1189 struct cx23885_tsport *port = priv;
1190 struct cx23885_dev *dev = port->dev;
1191 u32 bitmask = 0;
1192
1193 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
1194 return 0;
1195
1196 if (command != 0) {
1197 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
1198 __func__, command);
1199 return -EINVAL;
1200 }
1201
1202 switch (dev->board) {
1203 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1204 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1205 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1206 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1207 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1208 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1209 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1210 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1211 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1212 /* Tuner Reset Command */
1213 bitmask = 0x04;
1214 break;
1215 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1216 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1217 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1218 /* Two identical tuners on two different i2c buses,
1219 * we need to reset the correct gpio. */
1220 if (port->nr == 1)
1221 bitmask = 0x01;
1222 else if (port->nr == 2)
1223 bitmask = 0x04;
1224 break;
1225 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1226 /* Tuner Reset Command */
1227 bitmask = 0x02;
1228 break;
1229 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1230 altera_ci_tuner_reset(dev, port->nr);
1231 break;
1232 case CX23885_BOARD_AVERMEDIA_HC81R:
1233 /* XC3028L Reset Command */
1234 bitmask = 1 << 2;
1235 break;
1236 }
1237
1238 if (bitmask) {
1239 /* Drive the tuner into reset and back out */
1240 cx_clear(GP0_IO, bitmask);
1241 mdelay(200);
1242 cx_set(GP0_IO, bitmask);
1243 }
1244
1245 return 0;
1246 }
1247
1248 void cx23885_gpio_setup(struct cx23885_dev *dev)
1249 {
1250 switch (dev->board) {
1251 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1252 /* GPIO-0 cx24227 demodulator reset */
1253 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1254 break;
1255 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1256 /* GPIO-0 cx24227 demodulator */
1257 /* GPIO-2 xc3028 tuner */
1258
1259 /* Put the parts into reset */
1260 cx_set(GP0_IO, 0x00050000);
1261 cx_clear(GP0_IO, 0x00000005);
1262 msleep(5);
1263
1264 /* Bring the parts out of reset */
1265 cx_set(GP0_IO, 0x00050005);
1266 break;
1267 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1268 /* GPIO-0 cx24227 demodulator reset */
1269 /* GPIO-2 xc5000 tuner reset */
1270 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
1271 break;
1272 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1273 /* GPIO-0 656_CLK */
1274 /* GPIO-1 656_D0 */
1275 /* GPIO-2 8295A Reset */
1276 /* GPIO-3-10 cx23417 data0-7 */
1277 /* GPIO-11-14 cx23417 addr0-3 */
1278 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1279 /* GPIO-19 IR_RX */
1280
1281 /* CX23417 GPIO's */
1282 /* EIO15 Zilog Reset */
1283 /* EIO14 S5H1409/CX24227 Reset */
1284 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
1285
1286 /* Put the demod into reset and protect the eeprom */
1287 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
1288 mdelay(100);
1289
1290 /* Bring the demod and blaster out of reset */
1291 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
1292 mdelay(100);
1293
1294 /* Force the TDA8295A into reset and back */
1295 cx23885_gpio_enable(dev, GPIO_2, 1);
1296 cx23885_gpio_set(dev, GPIO_2);
1297 mdelay(20);
1298 cx23885_gpio_clear(dev, GPIO_2);
1299 mdelay(20);
1300 cx23885_gpio_set(dev, GPIO_2);
1301 mdelay(20);
1302 break;
1303 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1304 /* GPIO-0 tda10048 demodulator reset */
1305 /* GPIO-2 tda18271 tuner reset */
1306
1307 /* Put the parts into reset and back */
1308 cx_set(GP0_IO, 0x00050000);
1309 mdelay(20);
1310 cx_clear(GP0_IO, 0x00000005);
1311 mdelay(20);
1312 cx_set(GP0_IO, 0x00050005);
1313 break;
1314 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1315 /* GPIO-0 TDA10048 demodulator reset */
1316 /* GPIO-2 TDA8295A Reset */
1317 /* GPIO-3-10 cx23417 data0-7 */
1318 /* GPIO-11-14 cx23417 addr0-3 */
1319 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1320
1321 /* The following GPIO's are on the interna AVCore (cx25840) */
1322 /* GPIO-19 IR_RX */
1323 /* GPIO-20 IR_TX 416/DVBT Select */
1324 /* GPIO-21 IIS DAT */
1325 /* GPIO-22 IIS WCLK */
1326 /* GPIO-23 IIS BCLK */
1327
1328 /* Put the parts into reset and back */
1329 cx_set(GP0_IO, 0x00050000);
1330 mdelay(20);
1331 cx_clear(GP0_IO, 0x00000005);
1332 mdelay(20);
1333 cx_set(GP0_IO, 0x00050005);
1334 break;
1335 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1336 /* GPIO-0 Dibcom7000p demodulator reset */
1337 /* GPIO-2 xc3028L tuner reset */
1338 /* GPIO-13 LED */
1339
1340 /* Put the parts into reset and back */
1341 cx_set(GP0_IO, 0x00050000);
1342 mdelay(20);
1343 cx_clear(GP0_IO, 0x00000005);
1344 mdelay(20);
1345 cx_set(GP0_IO, 0x00050005);
1346 break;
1347 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1348 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
1349 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
1350 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
1351 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
1352
1353 /* Put the parts into reset and back */
1354 cx_set(GP0_IO, 0x000f0000);
1355 mdelay(20);
1356 cx_clear(GP0_IO, 0x0000000f);
1357 mdelay(20);
1358 cx_set(GP0_IO, 0x000f000f);
1359 break;
1360 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1361 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1362 /* GPIO-0 portb xc3028 reset */
1363 /* GPIO-1 portb zl10353 reset */
1364 /* GPIO-2 portc xc3028 reset */
1365 /* GPIO-3 portc zl10353 reset */
1366
1367 /* Put the parts into reset and back */
1368 cx_set(GP0_IO, 0x000f0000);
1369 mdelay(20);
1370 cx_clear(GP0_IO, 0x0000000f);
1371 mdelay(20);
1372 cx_set(GP0_IO, 0x000f000f);
1373 break;
1374 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1375 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1376 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1377 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1378 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1379 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1380 /* GPIO-2 xc3028 tuner reset */
1381
1382 /* The following GPIO's are on the internal AVCore (cx25840) */
1383 /* GPIO-? zl10353 demod reset */
1384
1385 /* Put the parts into reset and back */
1386 cx_set(GP0_IO, 0x00040000);
1387 mdelay(20);
1388 cx_clear(GP0_IO, 0x00000004);
1389 mdelay(20);
1390 cx_set(GP0_IO, 0x00040004);
1391 break;
1392 case CX23885_BOARD_TBS_6920:
1393 case CX23885_BOARD_TBS_6980:
1394 case CX23885_BOARD_TBS_6981:
1395 case CX23885_BOARD_PROF_8000:
1396 cx_write(MC417_CTL, 0x00000036);
1397 cx_write(MC417_OEN, 0x00001000);
1398 cx_set(MC417_RWD, 0x00000002);
1399 mdelay(200);
1400 cx_clear(MC417_RWD, 0x00000800);
1401 mdelay(200);
1402 cx_set(MC417_RWD, 0x00000800);
1403 mdelay(200);
1404 break;
1405 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1406 /* GPIO-0 INTA from CiMax1
1407 GPIO-1 INTB from CiMax2
1408 GPIO-2 reset chips
1409 GPIO-3 to GPIO-10 data/addr for CA
1410 GPIO-11 ~CS0 to CiMax1
1411 GPIO-12 ~CS1 to CiMax2
1412 GPIO-13 ADL0 load LSB addr
1413 GPIO-14 ADL1 load MSB addr
1414 GPIO-15 ~RDY from CiMax
1415 GPIO-17 ~RD to CiMax
1416 GPIO-18 ~WR to CiMax
1417 */
1418 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
1419 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
1420 cx_clear(GP0_IO, 0x00030004);
1421 mdelay(100);/* reset delay */
1422 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
1423 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
1424 /* GPIO-15 IN as ~ACK, rest as OUT */
1425 cx_write(MC417_OEN, 0x00001000);
1426 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1427 cx_write(MC417_RWD, 0x0000c300);
1428 /* enable irq */
1429 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1430 break;
1431 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1432 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1433 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1434 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1435 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1436 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
1437 /* GPIO-6 I2C Gate which can isolate the demod from the bus */
1438 /* GPIO-9 Demod reset */
1439
1440 /* Put the parts into reset and back */
1441 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
1442 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
1443 cx23885_gpio_clear(dev, GPIO_9);
1444 mdelay(20);
1445 cx23885_gpio_set(dev, GPIO_9);
1446 break;
1447 case CX23885_BOARD_MYGICA_X8506:
1448 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1449 case CX23885_BOARD_MYGICA_X8507:
1450 /* GPIO-0 (0)Analog / (1)Digital TV */
1451 /* GPIO-1 reset XC5000 */
1452 /* GPIO-2 demod reset */
1453 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
1454 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
1455 mdelay(100);
1456 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
1457 mdelay(100);
1458 break;
1459 case CX23885_BOARD_MYGICA_X8558PRO:
1460 /* GPIO-0 reset first ATBM8830 */
1461 /* GPIO-1 reset second ATBM8830 */
1462 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
1463 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
1464 mdelay(100);
1465 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
1466 mdelay(100);
1467 break;
1468 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1469 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1470 /* GPIO-0 656_CLK */
1471 /* GPIO-1 656_D0 */
1472 /* GPIO-2 Wake# */
1473 /* GPIO-3-10 cx23417 data0-7 */
1474 /* GPIO-11-14 cx23417 addr0-3 */
1475 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1476 /* GPIO-19 IR_RX */
1477 /* GPIO-20 C_IR_TX */
1478 /* GPIO-21 I2S DAT */
1479 /* GPIO-22 I2S WCLK */
1480 /* GPIO-23 I2S BCLK */
1481 /* ALT GPIO: EXP GPIO LATCH */
1482
1483 /* CX23417 GPIO's */
1484 /* GPIO-14 S5H1411/CX24228 Reset */
1485 /* GPIO-13 EEPROM write protect */
1486 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
1487
1488 /* Put the demod into reset and protect the eeprom */
1489 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
1490 mdelay(100);
1491
1492 /* Bring the demod out of reset */
1493 mc417_gpio_set(dev, GPIO_14);
1494 mdelay(100);
1495
1496 /* CX24228 GPIO */
1497 /* Connected to IF / Mux */
1498 break;
1499 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1500 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1501 break;
1502 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1503 /* GPIO-0 ~INT in
1504 GPIO-1 TMS out
1505 GPIO-2 ~reset chips out
1506 GPIO-3 to GPIO-10 data/addr for CA in/out
1507 GPIO-11 ~CS out
1508 GPIO-12 ADDR out
1509 GPIO-13 ~WR out
1510 GPIO-14 ~RD out
1511 GPIO-15 ~RDY in
1512 GPIO-16 TCK out
1513 GPIO-17 TDO in
1514 GPIO-18 TDI out
1515 */
1516 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
1517 /* GPIO-0 as INT, reset & TMS low */
1518 cx_clear(GP0_IO, 0x00010006);
1519 mdelay(100);/* reset delay */
1520 cx_set(GP0_IO, 0x00000004); /* reset high */
1521 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
1522 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
1523 cx_write(MC417_OEN, 0x00005000);
1524 /* ~RD, ~WR high; ADDR low; ~CS high */
1525 cx_write(MC417_RWD, 0x00000d00);
1526 /* enable irq */
1527 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1528 break;
1529 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1530 /* GPIO-8 tda10071 demod reset */
1531 /* GPIO-9 si2165 demod reset */
1532
1533 /* Put the parts into reset and back */
1534 cx23885_gpio_enable(dev, GPIO_8 | GPIO_9, 1);
1535
1536 cx23885_gpio_clear(dev, GPIO_8 | GPIO_9);
1537 mdelay(100);
1538 cx23885_gpio_set(dev, GPIO_8 | GPIO_9);
1539 mdelay(100);
1540
1541 break;
1542 case CX23885_BOARD_AVERMEDIA_HC81R:
1543 cx_clear(MC417_CTL, 1);
1544 /* GPIO-0,1,2 setup direction as output */
1545 cx_set(GP0_IO, 0x00070000);
1546 mdelay(10);
1547 /* AF9013 demod reset */
1548 cx_set(GP0_IO, 0x00010001);
1549 mdelay(10);
1550 cx_clear(GP0_IO, 0x00010001);
1551 mdelay(10);
1552 cx_set(GP0_IO, 0x00010001);
1553 mdelay(10);
1554 /* demod tune? */
1555 cx_clear(GP0_IO, 0x00030003);
1556 mdelay(10);
1557 cx_set(GP0_IO, 0x00020002);
1558 mdelay(10);
1559 cx_set(GP0_IO, 0x00010001);
1560 mdelay(10);
1561 cx_clear(GP0_IO, 0x00020002);
1562 /* XC3028L tuner reset */
1563 cx_set(GP0_IO, 0x00040004);
1564 cx_clear(GP0_IO, 0x00040004);
1565 cx_set(GP0_IO, 0x00040004);
1566 mdelay(60);
1567 break;
1568 case CX23885_BOARD_DVBSKY_T9580:
1569 /* enable GPIO3-18 pins */
1570 cx_write(MC417_CTL, 0x00000037);
1571 cx23885_gpio_enable(dev, GPIO_2 | GPIO_11, 1);
1572 cx23885_gpio_clear(dev, GPIO_2 | GPIO_11);
1573 mdelay(100);
1574 cx23885_gpio_set(dev, GPIO_2 | GPIO_11);
1575 break;
1576 case CX23885_BOARD_DVBSKY_T980C:
1577 case CX23885_BOARD_DVBSKY_S950C:
1578 case CX23885_BOARD_TT_CT2_4500_CI:
1579 /*
1580 * GPIO-0 INTA from CiMax, input
1581 * GPIO-1 reset CiMax, output, high active
1582 * GPIO-2 reset demod, output, low active
1583 * GPIO-3 to GPIO-10 data/addr for CAM
1584 * GPIO-11 ~CS0 to CiMax1
1585 * GPIO-12 ~CS1 to CiMax2
1586 * GPIO-13 ADL0 load LSB addr
1587 * GPIO-14 ADL1 load MSB addr
1588 * GPIO-15 ~RDY from CiMax
1589 * GPIO-17 ~RD to CiMax
1590 * GPIO-18 ~WR to CiMax
1591 */
1592
1593 cx_set(GP0_IO, 0x00060002); /* GPIO 1/2 as output */
1594 cx_clear(GP0_IO, 0x00010004); /* GPIO 0 as input */
1595 mdelay(100); /* reset delay */
1596 cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */
1597 cx_clear(GP0_IO, 0x00010002);
1598 cx_write(MC417_CTL, 0x00000037); /* enable GPIO3-18 pins */
1599
1600 /* GPIO-15 IN as ~ACK, rest as OUT */
1601 cx_write(MC417_OEN, 0x00001000);
1602
1603 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1604 cx_write(MC417_RWD, 0x0000c300);
1605
1606 /* enable irq */
1607 cx_write(GPIO_ISM, 0x00000000); /* INTERRUPTS active low */
1608 break;
1609 case CX23885_BOARD_DVBSKY_S950:
1610 cx23885_gpio_enable(dev, GPIO_2, 1);
1611 cx23885_gpio_clear(dev, GPIO_2);
1612 msleep(100);
1613 cx23885_gpio_set(dev, GPIO_2);
1614 break;
1615 }
1616 }
1617
1618 int cx23885_ir_init(struct cx23885_dev *dev)
1619 {
1620 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
1621 {
1622 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1623 .pin = CX23885_PIN_IR_RX_GPIO19,
1624 .function = CX23885_PAD_IR_RX,
1625 .value = 0,
1626 .strength = CX25840_PIN_DRIVE_MEDIUM,
1627 }, {
1628 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
1629 .pin = CX23885_PIN_IR_TX_GPIO20,
1630 .function = CX23885_PAD_IR_TX,
1631 .value = 0,
1632 .strength = CX25840_PIN_DRIVE_MEDIUM,
1633 }
1634 };
1635 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1636
1637 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1638 {
1639 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1640 .pin = CX23885_PIN_IR_RX_GPIO19,
1641 .function = CX23885_PAD_IR_RX,
1642 .value = 0,
1643 .strength = CX25840_PIN_DRIVE_MEDIUM,
1644 }
1645 };
1646 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
1647
1648 struct v4l2_subdev_ir_parameters params;
1649 int ret = 0;
1650 switch (dev->board) {
1651 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1652 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1653 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1654 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1655 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1656 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1657 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1658 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1659 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1660 /* FIXME: Implement me */
1661 break;
1662 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1663 ret = cx23888_ir_probe(dev);
1664 if (ret)
1665 break;
1666 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1667 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1668 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1669 break;
1670 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1671 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1672 ret = cx23888_ir_probe(dev);
1673 if (ret)
1674 break;
1675 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1676 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1677 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1678 /*
1679 * For these boards we need to invert the Tx output via the
1680 * IR controller to have the LED off while idle
1681 */
1682 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
1683 params.enable = false;
1684 params.shutdown = false;
1685 params.invert_level = true;
1686 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1687 params.shutdown = true;
1688 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1689 break;
1690 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1691 case CX23885_BOARD_TEVII_S470:
1692 case CX23885_BOARD_MYGICA_X8507:
1693 case CX23885_BOARD_TBS_6980:
1694 case CX23885_BOARD_TBS_6981:
1695 case CX23885_BOARD_DVBSKY_T9580:
1696 case CX23885_BOARD_DVBSKY_T980C:
1697 case CX23885_BOARD_DVBSKY_S950C:
1698 case CX23885_BOARD_TT_CT2_4500_CI:
1699 case CX23885_BOARD_DVBSKY_S950:
1700 if (!enable_885_ir)
1701 break;
1702 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1703 if (dev->sd_ir == NULL) {
1704 ret = -ENODEV;
1705 break;
1706 }
1707 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1708 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1709 break;
1710 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1711 if (!enable_885_ir)
1712 break;
1713 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1714 if (dev->sd_ir == NULL) {
1715 ret = -ENODEV;
1716 break;
1717 }
1718 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1719 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1720 break;
1721 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1722 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1723 request_module("ir-kbd-i2c");
1724 break;
1725 }
1726
1727 return ret;
1728 }
1729
1730 void cx23885_ir_fini(struct cx23885_dev *dev)
1731 {
1732 switch (dev->board) {
1733 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1734 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1735 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1736 cx23885_irq_remove(dev, PCI_MSK_IR);
1737 cx23888_ir_remove(dev);
1738 dev->sd_ir = NULL;
1739 break;
1740 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1741 case CX23885_BOARD_TEVII_S470:
1742 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1743 case CX23885_BOARD_MYGICA_X8507:
1744 case CX23885_BOARD_TBS_6980:
1745 case CX23885_BOARD_TBS_6981:
1746 case CX23885_BOARD_DVBSKY_T9580:
1747 case CX23885_BOARD_DVBSKY_T980C:
1748 case CX23885_BOARD_DVBSKY_S950C:
1749 case CX23885_BOARD_TT_CT2_4500_CI:
1750 case CX23885_BOARD_DVBSKY_S950:
1751 cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
1752 /* sd_ir is a duplicate pointer to the AV Core, just clear it */
1753 dev->sd_ir = NULL;
1754 break;
1755 }
1756 }
1757
1758 static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
1759 {
1760 int data;
1761 int tdo = 0;
1762 struct cx23885_dev *dev = (struct cx23885_dev *)device;
1763 /*TMS*/
1764 data = ((cx_read(GP0_IO)) & (~0x00000002));
1765 data |= (tms ? 0x00020002 : 0x00020000);
1766 cx_write(GP0_IO, data);
1767
1768 /*TDI*/
1769 data = ((cx_read(MC417_RWD)) & (~0x0000a000));
1770 data |= (tdi ? 0x00008000 : 0);
1771 cx_write(MC417_RWD, data);
1772 if (read_tdo)
1773 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
1774
1775 cx_write(MC417_RWD, data | 0x00002000);
1776 udelay(1);
1777 /*TCK*/
1778 cx_write(MC417_RWD, data);
1779
1780 return tdo;
1781 }
1782
1783 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1784 {
1785 switch (dev->board) {
1786 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1787 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1788 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1789 if (dev->sd_ir)
1790 cx23885_irq_add_enable(dev, PCI_MSK_IR);
1791 break;
1792 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1793 case CX23885_BOARD_TEVII_S470:
1794 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1795 case CX23885_BOARD_MYGICA_X8507:
1796 case CX23885_BOARD_TBS_6980:
1797 case CX23885_BOARD_TBS_6981:
1798 case CX23885_BOARD_DVBSKY_T9580:
1799 case CX23885_BOARD_DVBSKY_T980C:
1800 case CX23885_BOARD_DVBSKY_S950C:
1801 case CX23885_BOARD_TT_CT2_4500_CI:
1802 case CX23885_BOARD_DVBSKY_S950:
1803 if (dev->sd_ir)
1804 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
1805 break;
1806 }
1807 }
1808
1809 void cx23885_card_setup(struct cx23885_dev *dev)
1810 {
1811 struct cx23885_tsport *ts1 = &dev->ts1;
1812 struct cx23885_tsport *ts2 = &dev->ts2;
1813
1814 static u8 eeprom[256];
1815
1816 if (dev->i2c_bus[0].i2c_rc == 0) {
1817 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1818 tveeprom_read(&dev->i2c_bus[0].i2c_client,
1819 eeprom, sizeof(eeprom));
1820 }
1821
1822 switch (dev->board) {
1823 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1824 if (dev->i2c_bus[0].i2c_rc == 0) {
1825 if (eeprom[0x80] != 0x84)
1826 hauppauge_eeprom(dev, eeprom+0xc0);
1827 else
1828 hauppauge_eeprom(dev, eeprom+0x80);
1829 }
1830 break;
1831 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1832 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1833 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1834 if (dev->i2c_bus[0].i2c_rc == 0)
1835 hauppauge_eeprom(dev, eeprom+0x80);
1836 break;
1837 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1838 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1839 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1840 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1841 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1842 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1843 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1844 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1845 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1846 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1847 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1848 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1849 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
1850 if (dev->i2c_bus[0].i2c_rc == 0)
1851 hauppauge_eeprom(dev, eeprom+0xc0);
1852 break;
1853 }
1854
1855 switch (dev->board) {
1856 case CX23885_BOARD_AVERMEDIA_HC81R:
1857 /* Defaults for VID B */
1858 ts1->gen_ctrl_val = 0x4; /* Parallel */
1859 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1860 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1861 /* Defaults for VID C */
1862 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1863 ts2->gen_ctrl_val = 0x10e;
1864 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1865 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1866 break;
1867 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1868 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1869 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2:
1870 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1871 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1872 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1873 /* break omitted intentionally */
1874 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
1875 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1876 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1877 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1878 break;
1879 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1880 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1881 /* Defaults for VID B - Analog encoder */
1882 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1883 ts1->gen_ctrl_val = 0x10e;
1884 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1885 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1886
1887 /* APB_TSVALERR_POL (active low)*/
1888 ts1->vld_misc_val = 0x2000;
1889 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
1890 cx_write(0x130184, 0xc);
1891
1892 /* Defaults for VID C */
1893 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1894 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1895 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1896 break;
1897 case CX23885_BOARD_TBS_6920:
1898 ts1->gen_ctrl_val = 0x4; /* Parallel */
1899 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1900 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1901 break;
1902 case CX23885_BOARD_TEVII_S470:
1903 case CX23885_BOARD_TEVII_S471:
1904 case CX23885_BOARD_DVBWORLD_2005:
1905 case CX23885_BOARD_PROF_8000:
1906 case CX23885_BOARD_DVBSKY_T980C:
1907 case CX23885_BOARD_DVBSKY_S950C:
1908 case CX23885_BOARD_TT_CT2_4500_CI:
1909 case CX23885_BOARD_DVBSKY_S950:
1910 ts1->gen_ctrl_val = 0x5; /* Parallel */
1911 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1912 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1913 break;
1914 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1915 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1916 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1917 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1918 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1919 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1920 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1921 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1922 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1923 break;
1924 case CX23885_BOARD_TBS_6980:
1925 case CX23885_BOARD_TBS_6981:
1926 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1927 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1928 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1929 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1930 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1931 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1932 tbs_card_init(dev);
1933 break;
1934 case CX23885_BOARD_MYGICA_X8506:
1935 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1936 case CX23885_BOARD_MYGICA_X8507:
1937 ts1->gen_ctrl_val = 0x5; /* Parallel */
1938 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1939 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1940 break;
1941 case CX23885_BOARD_MYGICA_X8558PRO:
1942 ts1->gen_ctrl_val = 0x5; /* Parallel */
1943 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1944 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1945 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1946 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1947 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1948 break;
1949 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1950 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1951 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1952 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1953 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1954 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1955 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1956 break;
1957 case CX23885_BOARD_DVBSKY_T9580:
1958 ts1->gen_ctrl_val = 0x5; /* Parallel */
1959 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1960 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1961 ts2->gen_ctrl_val = 0x8; /* Serial bus */
1962 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1963 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1964 break;
1965 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1966 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1967 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1968 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1969 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1970 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1971 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1972 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
1973 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1974 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
1975 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1976 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1977 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1978 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1979 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1980 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1981 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1982 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1983 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1984 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1985 default:
1986 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1987 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1988 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1989 }
1990
1991 /* Certain boards support analog, or require the avcore to be
1992 * loaded, ensure this happens.
1993 */
1994 switch (dev->board) {
1995 case CX23885_BOARD_TEVII_S470:
1996 /* Currently only enabled for the integrated IR controller */
1997 if (!enable_885_ir)
1998 break;
1999 case CX23885_BOARD_HAUPPAUGE_HVR1250:
2000 case CX23885_BOARD_HAUPPAUGE_HVR1800:
2001 case CX23885_BOARD_HAUPPAUGE_IMPACTVCBE:
2002 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
2003 case CX23885_BOARD_HAUPPAUGE_HVR1700:
2004 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
2005 case CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200:
2006 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
2007 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
2008 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2009 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
2010 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
2011 case CX23885_BOARD_HAUPPAUGE_HVR1255:
2012 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
2013 case CX23885_BOARD_HAUPPAUGE_HVR1270:
2014 case CX23885_BOARD_HAUPPAUGE_HVR1850:
2015 case CX23885_BOARD_MYGICA_X8506:
2016 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
2017 case CX23885_BOARD_HAUPPAUGE_HVR1290:
2018 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
2019 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
2020 case CX23885_BOARD_HAUPPAUGE_HVR1500:
2021 case CX23885_BOARD_MPX885:
2022 case CX23885_BOARD_MYGICA_X8507:
2023 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
2024 case CX23885_BOARD_AVERMEDIA_HC81R:
2025 case CX23885_BOARD_TBS_6980:
2026 case CX23885_BOARD_TBS_6981:
2027 case CX23885_BOARD_DVBSKY_T9580:
2028 case CX23885_BOARD_DVBSKY_T980C:
2029 case CX23885_BOARD_DVBSKY_S950C:
2030 case CX23885_BOARD_TT_CT2_4500_CI:
2031 case CX23885_BOARD_DVBSKY_S950:
2032 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
2033 &dev->i2c_bus[2].i2c_adap,
2034 "cx25840", 0x88 >> 1, NULL);
2035 if (dev->sd_cx25840) {
2036 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
2037 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
2038 }
2039 break;
2040 }
2041
2042 /* AUX-PLL 27MHz CLK */
2043 switch (dev->board) {
2044 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2045 netup_initialize(dev);
2046 break;
2047 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
2048 int ret;
2049 const struct firmware *fw;
2050 const char *filename = "dvb-netup-altera-01.fw";
2051 char *action = "configure";
2052 static struct netup_card_info cinfo;
2053 struct altera_config netup_config = {
2054 .dev = dev,
2055 .action = action,
2056 .jtag_io = netup_jtag_io,
2057 };
2058
2059 netup_initialize(dev);
2060
2061 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
2062 if (netup_card_rev)
2063 cinfo.rev = netup_card_rev;
2064
2065 switch (cinfo.rev) {
2066 case 0x4:
2067 filename = "dvb-netup-altera-04.fw";
2068 break;
2069 default:
2070 filename = "dvb-netup-altera-01.fw";
2071 break;
2072 }
2073 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
2074 cinfo.rev, filename);
2075
2076 ret = request_firmware(&fw, filename, &dev->pci->dev);
2077 if (ret != 0)
2078 printk(KERN_ERR "did not find the firmware file. (%s) "
2079 "Please see linux/Documentation/dvb/ for more details "
2080 "on firmware-problems.", filename);
2081 else
2082 altera_init(&netup_config, fw);
2083
2084 release_firmware(fw);
2085 break;
2086 }
2087 }
2088 }
Linux kernel - Deliverables
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