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[media] cx23885: add basic DVB-S2 support for Hauppauge HVR-4400
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885-cards.c
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <media/cx25840.h>
27 #include <linux/firmware.h>
28 #include <misc/altera.h>
29
30 #include "cx23885.h"
31 #include "tuner-xc2028.h"
32 #include "netup-eeprom.h"
33 #include "netup-init.h"
34 #include "altera-ci.h"
35 #include "xc4000.h"
36 #include "xc5000.h"
37 #include "cx23888-ir.h"
38
39 static unsigned int netup_card_rev = 4;
40 module_param(netup_card_rev, int, 0644);
41 MODULE_PARM_DESC(netup_card_rev,
42 "NetUP Dual DVB-T/C CI card revision");
43 static unsigned int enable_885_ir;
44 module_param(enable_885_ir, int, 0644);
45 MODULE_PARM_DESC(enable_885_ir,
46 "Enable integrated IR controller for supported\n"
47 "\t\t CX2388[57] boards that are wired for it:\n"
48 "\t\t\tHVR-1250 (reported safe)\n"
49 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n"
50 "\t\t\tTeVii S470 (reported unsafe)\n"
51 "\t\t This can cause an interrupt storm with some cards.\n"
52 "\t\t Default: 0 [Disabled]");
53
54 /* ------------------------------------------------------------------ */
55 /* board config info */
56
57 struct cx23885_board cx23885_boards[] = {
58 [CX23885_BOARD_UNKNOWN] = {
59 .name = "UNKNOWN/GENERIC",
60 /* Ensure safe default for unknown boards */
61 .clk_freq = 0,
62 .input = {{
63 .type = CX23885_VMUX_COMPOSITE1,
64 .vmux = 0,
65 }, {
66 .type = CX23885_VMUX_COMPOSITE2,
67 .vmux = 1,
68 }, {
69 .type = CX23885_VMUX_COMPOSITE3,
70 .vmux = 2,
71 }, {
72 .type = CX23885_VMUX_COMPOSITE4,
73 .vmux = 3,
74 } },
75 },
76 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
77 .name = "Hauppauge WinTV-HVR1800lp",
78 .portc = CX23885_MPEG_DVB,
79 .input = {{
80 .type = CX23885_VMUX_TELEVISION,
81 .vmux = 0,
82 .gpio0 = 0xff00,
83 }, {
84 .type = CX23885_VMUX_DEBUG,
85 .vmux = 0,
86 .gpio0 = 0xff01,
87 }, {
88 .type = CX23885_VMUX_COMPOSITE1,
89 .vmux = 1,
90 .gpio0 = 0xff02,
91 }, {
92 .type = CX23885_VMUX_SVIDEO,
93 .vmux = 2,
94 .gpio0 = 0xff02,
95 } },
96 },
97 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
98 .name = "Hauppauge WinTV-HVR1800",
99 .porta = CX23885_ANALOG_VIDEO,
100 .portb = CX23885_MPEG_ENCODER,
101 .portc = CX23885_MPEG_DVB,
102 .tuner_type = TUNER_PHILIPS_TDA8290,
103 .tuner_addr = 0x42, /* 0x84 >> 1 */
104 .tuner_bus = 1,
105 .input = {{
106 .type = CX23885_VMUX_TELEVISION,
107 .vmux = CX25840_VIN7_CH3 |
108 CX25840_VIN5_CH2 |
109 CX25840_VIN2_CH1,
110 .amux = CX25840_AUDIO8,
111 .gpio0 = 0,
112 }, {
113 .type = CX23885_VMUX_COMPOSITE1,
114 .vmux = CX25840_VIN7_CH3 |
115 CX25840_VIN4_CH2 |
116 CX25840_VIN6_CH1,
117 .amux = CX25840_AUDIO7,
118 .gpio0 = 0,
119 }, {
120 .type = CX23885_VMUX_SVIDEO,
121 .vmux = CX25840_VIN7_CH3 |
122 CX25840_VIN4_CH2 |
123 CX25840_VIN8_CH1 |
124 CX25840_SVIDEO_ON,
125 .amux = CX25840_AUDIO7,
126 .gpio0 = 0,
127 } },
128 },
129 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
130 .name = "Hauppauge WinTV-HVR1250",
131 .porta = CX23885_ANALOG_VIDEO,
132 .portc = CX23885_MPEG_DVB,
133 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
134 .tuner_type = TUNER_PHILIPS_TDA8290,
135 .tuner_addr = 0x42, /* 0x84 >> 1 */
136 .tuner_bus = 1,
137 #endif
138 .force_bff = 1,
139 .input = {{
140 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
141 .type = CX23885_VMUX_TELEVISION,
142 .vmux = CX25840_VIN7_CH3 |
143 CX25840_VIN5_CH2 |
144 CX25840_VIN2_CH1,
145 .amux = CX25840_AUDIO8,
146 .gpio0 = 0xff00,
147 }, {
148 #endif
149 .type = CX23885_VMUX_COMPOSITE1,
150 .vmux = CX25840_VIN7_CH3 |
151 CX25840_VIN4_CH2 |
152 CX25840_VIN6_CH1,
153 .amux = CX25840_AUDIO7,
154 .gpio0 = 0xff02,
155 }, {
156 .type = CX23885_VMUX_SVIDEO,
157 .vmux = CX25840_VIN7_CH3 |
158 CX25840_VIN4_CH2 |
159 CX25840_VIN8_CH1 |
160 CX25840_SVIDEO_ON,
161 .amux = CX25840_AUDIO7,
162 .gpio0 = 0xff02,
163 } },
164 },
165 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
166 .name = "DViCO FusionHDTV5 Express",
167 .portb = CX23885_MPEG_DVB,
168 },
169 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
170 .name = "Hauppauge WinTV-HVR1500Q",
171 .portc = CX23885_MPEG_DVB,
172 },
173 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
174 .name = "Hauppauge WinTV-HVR1500",
175 .porta = CX23885_ANALOG_VIDEO,
176 .portc = CX23885_MPEG_DVB,
177 .tuner_type = TUNER_XC2028,
178 .tuner_addr = 0x61, /* 0xc2 >> 1 */
179 .input = {{
180 .type = CX23885_VMUX_TELEVISION,
181 .vmux = CX25840_VIN7_CH3 |
182 CX25840_VIN5_CH2 |
183 CX25840_VIN2_CH1,
184 .gpio0 = 0,
185 }, {
186 .type = CX23885_VMUX_COMPOSITE1,
187 .vmux = CX25840_VIN7_CH3 |
188 CX25840_VIN4_CH2 |
189 CX25840_VIN6_CH1,
190 .gpio0 = 0,
191 }, {
192 .type = CX23885_VMUX_SVIDEO,
193 .vmux = CX25840_VIN7_CH3 |
194 CX25840_VIN4_CH2 |
195 CX25840_VIN8_CH1 |
196 CX25840_SVIDEO_ON,
197 .gpio0 = 0,
198 } },
199 },
200 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
201 .name = "Hauppauge WinTV-HVR1200",
202 .portc = CX23885_MPEG_DVB,
203 },
204 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
205 .name = "Hauppauge WinTV-HVR1700",
206 .portc = CX23885_MPEG_DVB,
207 },
208 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
209 .name = "Hauppauge WinTV-HVR1400",
210 .portc = CX23885_MPEG_DVB,
211 },
212 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
213 .name = "DViCO FusionHDTV7 Dual Express",
214 .portb = CX23885_MPEG_DVB,
215 .portc = CX23885_MPEG_DVB,
216 },
217 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
218 .name = "DViCO FusionHDTV DVB-T Dual Express",
219 .portb = CX23885_MPEG_DVB,
220 .portc = CX23885_MPEG_DVB,
221 },
222 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
223 .name = "Leadtek Winfast PxDVR3200 H",
224 .portc = CX23885_MPEG_DVB,
225 },
226 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
227 .name = "Leadtek Winfast PxDVR3200 H XC4000",
228 .porta = CX23885_ANALOG_VIDEO,
229 .portc = CX23885_MPEG_DVB,
230 .tuner_type = TUNER_XC4000,
231 .tuner_addr = 0x61,
232 .radio_type = UNSET,
233 .radio_addr = ADDR_UNSET,
234 .input = {{
235 .type = CX23885_VMUX_TELEVISION,
236 .vmux = CX25840_VIN2_CH1 |
237 CX25840_VIN5_CH2 |
238 CX25840_NONE0_CH3,
239 }, {
240 .type = CX23885_VMUX_COMPOSITE1,
241 .vmux = CX25840_COMPOSITE1,
242 }, {
243 .type = CX23885_VMUX_SVIDEO,
244 .vmux = CX25840_SVIDEO_LUMA3 |
245 CX25840_SVIDEO_CHROMA4,
246 }, {
247 .type = CX23885_VMUX_COMPONENT,
248 .vmux = CX25840_VIN7_CH1 |
249 CX25840_VIN6_CH2 |
250 CX25840_VIN8_CH3 |
251 CX25840_COMPONENT_ON,
252 } },
253 },
254 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
255 .name = "Compro VideoMate E650F",
256 .portc = CX23885_MPEG_DVB,
257 },
258 [CX23885_BOARD_TBS_6920] = {
259 .name = "TurboSight TBS 6920",
260 .portb = CX23885_MPEG_DVB,
261 },
262 [CX23885_BOARD_TEVII_S470] = {
263 .name = "TeVii S470",
264 .portb = CX23885_MPEG_DVB,
265 },
266 [CX23885_BOARD_DVBWORLD_2005] = {
267 .name = "DVBWorld DVB-S2 2005",
268 .portb = CX23885_MPEG_DVB,
269 },
270 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
271 .ci_type = 1,
272 .name = "NetUP Dual DVB-S2 CI",
273 .portb = CX23885_MPEG_DVB,
274 .portc = CX23885_MPEG_DVB,
275 },
276 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
277 .name = "Hauppauge WinTV-HVR1270",
278 .portc = CX23885_MPEG_DVB,
279 },
280 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
281 .name = "Hauppauge WinTV-HVR1275",
282 .portc = CX23885_MPEG_DVB,
283 },
284 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
285 .name = "Hauppauge WinTV-HVR1255",
286 .porta = CX23885_ANALOG_VIDEO,
287 .portc = CX23885_MPEG_DVB,
288 .tuner_type = TUNER_ABSENT,
289 .tuner_addr = 0x42, /* 0x84 >> 1 */
290 .force_bff = 1,
291 .input = {{
292 .type = CX23885_VMUX_TELEVISION,
293 .vmux = CX25840_VIN7_CH3 |
294 CX25840_VIN5_CH2 |
295 CX25840_VIN2_CH1 |
296 CX25840_DIF_ON,
297 .amux = CX25840_AUDIO8,
298 }, {
299 .type = CX23885_VMUX_COMPOSITE1,
300 .vmux = CX25840_VIN7_CH3 |
301 CX25840_VIN4_CH2 |
302 CX25840_VIN6_CH1,
303 .amux = CX25840_AUDIO7,
304 }, {
305 .type = CX23885_VMUX_SVIDEO,
306 .vmux = CX25840_VIN7_CH3 |
307 CX25840_VIN4_CH2 |
308 CX25840_VIN8_CH1 |
309 CX25840_SVIDEO_ON,
310 .amux = CX25840_AUDIO7,
311 } },
312 },
313 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
314 .name = "Hauppauge WinTV-HVR1255",
315 .porta = CX23885_ANALOG_VIDEO,
316 .portc = CX23885_MPEG_DVB,
317 .tuner_type = TUNER_ABSENT,
318 .tuner_addr = 0x42, /* 0x84 >> 1 */
319 .force_bff = 1,
320 .input = {{
321 .type = CX23885_VMUX_TELEVISION,
322 .vmux = CX25840_VIN7_CH3 |
323 CX25840_VIN5_CH2 |
324 CX25840_VIN2_CH1 |
325 CX25840_DIF_ON,
326 .amux = CX25840_AUDIO8,
327 }, {
328 .type = CX23885_VMUX_SVIDEO,
329 .vmux = CX25840_VIN7_CH3 |
330 CX25840_VIN4_CH2 |
331 CX25840_VIN8_CH1 |
332 CX25840_SVIDEO_ON,
333 .amux = CX25840_AUDIO7,
334 } },
335 },
336 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
337 .name = "Hauppauge WinTV-HVR1210",
338 .portc = CX23885_MPEG_DVB,
339 },
340 [CX23885_BOARD_MYGICA_X8506] = {
341 .name = "Mygica X8506 DMB-TH",
342 .tuner_type = TUNER_XC5000,
343 .tuner_addr = 0x61,
344 .tuner_bus = 1,
345 .porta = CX23885_ANALOG_VIDEO,
346 .portb = CX23885_MPEG_DVB,
347 .input = {
348 {
349 .type = CX23885_VMUX_TELEVISION,
350 .vmux = CX25840_COMPOSITE2,
351 },
352 {
353 .type = CX23885_VMUX_COMPOSITE1,
354 .vmux = CX25840_COMPOSITE8,
355 },
356 {
357 .type = CX23885_VMUX_SVIDEO,
358 .vmux = CX25840_SVIDEO_LUMA3 |
359 CX25840_SVIDEO_CHROMA4,
360 },
361 {
362 .type = CX23885_VMUX_COMPONENT,
363 .vmux = CX25840_COMPONENT_ON |
364 CX25840_VIN1_CH1 |
365 CX25840_VIN6_CH2 |
366 CX25840_VIN7_CH3,
367 },
368 },
369 },
370 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
371 .name = "Magic-Pro ProHDTV Extreme 2",
372 .tuner_type = TUNER_XC5000,
373 .tuner_addr = 0x61,
374 .tuner_bus = 1,
375 .porta = CX23885_ANALOG_VIDEO,
376 .portb = CX23885_MPEG_DVB,
377 .input = {
378 {
379 .type = CX23885_VMUX_TELEVISION,
380 .vmux = CX25840_COMPOSITE2,
381 },
382 {
383 .type = CX23885_VMUX_COMPOSITE1,
384 .vmux = CX25840_COMPOSITE8,
385 },
386 {
387 .type = CX23885_VMUX_SVIDEO,
388 .vmux = CX25840_SVIDEO_LUMA3 |
389 CX25840_SVIDEO_CHROMA4,
390 },
391 {
392 .type = CX23885_VMUX_COMPONENT,
393 .vmux = CX25840_COMPONENT_ON |
394 CX25840_VIN1_CH1 |
395 CX25840_VIN6_CH2 |
396 CX25840_VIN7_CH3,
397 },
398 },
399 },
400 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
401 .name = "Hauppauge WinTV-HVR1850",
402 .porta = CX23885_ANALOG_VIDEO,
403 .portb = CX23885_MPEG_ENCODER,
404 .portc = CX23885_MPEG_DVB,
405 .tuner_type = TUNER_ABSENT,
406 .tuner_addr = 0x42, /* 0x84 >> 1 */
407 .force_bff = 1,
408 .input = {{
409 .type = CX23885_VMUX_TELEVISION,
410 .vmux = CX25840_VIN7_CH3 |
411 CX25840_VIN5_CH2 |
412 CX25840_VIN2_CH1 |
413 CX25840_DIF_ON,
414 .amux = CX25840_AUDIO8,
415 }, {
416 .type = CX23885_VMUX_COMPOSITE1,
417 .vmux = CX25840_VIN7_CH3 |
418 CX25840_VIN4_CH2 |
419 CX25840_VIN6_CH1,
420 .amux = CX25840_AUDIO7,
421 }, {
422 .type = CX23885_VMUX_SVIDEO,
423 .vmux = CX25840_VIN7_CH3 |
424 CX25840_VIN4_CH2 |
425 CX25840_VIN8_CH1 |
426 CX25840_SVIDEO_ON,
427 .amux = CX25840_AUDIO7,
428 } },
429 },
430 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
431 .name = "Compro VideoMate E800",
432 .portc = CX23885_MPEG_DVB,
433 },
434 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
435 .name = "Hauppauge WinTV-HVR1290",
436 .portc = CX23885_MPEG_DVB,
437 },
438 [CX23885_BOARD_MYGICA_X8558PRO] = {
439 .name = "Mygica X8558 PRO DMB-TH",
440 .portb = CX23885_MPEG_DVB,
441 .portc = CX23885_MPEG_DVB,
442 },
443 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
444 .name = "LEADTEK WinFast PxTV1200",
445 .porta = CX23885_ANALOG_VIDEO,
446 .tuner_type = TUNER_XC2028,
447 .tuner_addr = 0x61,
448 .tuner_bus = 1,
449 .input = {{
450 .type = CX23885_VMUX_TELEVISION,
451 .vmux = CX25840_VIN2_CH1 |
452 CX25840_VIN5_CH2 |
453 CX25840_NONE0_CH3,
454 }, {
455 .type = CX23885_VMUX_COMPOSITE1,
456 .vmux = CX25840_COMPOSITE1,
457 }, {
458 .type = CX23885_VMUX_SVIDEO,
459 .vmux = CX25840_SVIDEO_LUMA3 |
460 CX25840_SVIDEO_CHROMA4,
461 }, {
462 .type = CX23885_VMUX_COMPONENT,
463 .vmux = CX25840_VIN7_CH1 |
464 CX25840_VIN6_CH2 |
465 CX25840_VIN8_CH3 |
466 CX25840_COMPONENT_ON,
467 } },
468 },
469 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
470 .name = "GoTView X5 3D Hybrid",
471 .tuner_type = TUNER_XC5000,
472 .tuner_addr = 0x64,
473 .tuner_bus = 1,
474 .porta = CX23885_ANALOG_VIDEO,
475 .portb = CX23885_MPEG_DVB,
476 .input = {{
477 .type = CX23885_VMUX_TELEVISION,
478 .vmux = CX25840_VIN2_CH1 |
479 CX25840_VIN5_CH2,
480 .gpio0 = 0x02,
481 }, {
482 .type = CX23885_VMUX_COMPOSITE1,
483 .vmux = CX23885_VMUX_COMPOSITE1,
484 }, {
485 .type = CX23885_VMUX_SVIDEO,
486 .vmux = CX25840_SVIDEO_LUMA3 |
487 CX25840_SVIDEO_CHROMA4,
488 } },
489 },
490 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
491 .ci_type = 2,
492 .name = "NetUP Dual DVB-T/C-CI RF",
493 .porta = CX23885_ANALOG_VIDEO,
494 .portb = CX23885_MPEG_DVB,
495 .portc = CX23885_MPEG_DVB,
496 .num_fds_portb = 2,
497 .num_fds_portc = 2,
498 .tuner_type = TUNER_XC5000,
499 .tuner_addr = 0x64,
500 .input = { {
501 .type = CX23885_VMUX_TELEVISION,
502 .vmux = CX25840_COMPOSITE1,
503 } },
504 },
505 [CX23885_BOARD_MPX885] = {
506 .name = "MPX-885",
507 .porta = CX23885_ANALOG_VIDEO,
508 .input = {{
509 .type = CX23885_VMUX_COMPOSITE1,
510 .vmux = CX25840_COMPOSITE1,
511 .amux = CX25840_AUDIO6,
512 .gpio0 = 0,
513 }, {
514 .type = CX23885_VMUX_COMPOSITE2,
515 .vmux = CX25840_COMPOSITE2,
516 .amux = CX25840_AUDIO6,
517 .gpio0 = 0,
518 }, {
519 .type = CX23885_VMUX_COMPOSITE3,
520 .vmux = CX25840_COMPOSITE3,
521 .amux = CX25840_AUDIO7,
522 .gpio0 = 0,
523 }, {
524 .type = CX23885_VMUX_COMPOSITE4,
525 .vmux = CX25840_COMPOSITE4,
526 .amux = CX25840_AUDIO7,
527 .gpio0 = 0,
528 } },
529 },
530 [CX23885_BOARD_MYGICA_X8507] = {
531 .name = "Mygica X8507",
532 .tuner_type = TUNER_XC5000,
533 .tuner_addr = 0x61,
534 .tuner_bus = 1,
535 .porta = CX23885_ANALOG_VIDEO,
536 .input = {
537 {
538 .type = CX23885_VMUX_TELEVISION,
539 .vmux = CX25840_COMPOSITE2,
540 .amux = CX25840_AUDIO8,
541 },
542 {
543 .type = CX23885_VMUX_COMPOSITE1,
544 .vmux = CX25840_COMPOSITE8,
545 .amux = CX25840_AUDIO7,
546 },
547 {
548 .type = CX23885_VMUX_SVIDEO,
549 .vmux = CX25840_SVIDEO_LUMA3 |
550 CX25840_SVIDEO_CHROMA4,
551 .amux = CX25840_AUDIO7,
552 },
553 {
554 .type = CX23885_VMUX_COMPONENT,
555 .vmux = CX25840_COMPONENT_ON |
556 CX25840_VIN1_CH1 |
557 CX25840_VIN6_CH2 |
558 CX25840_VIN7_CH3,
559 .amux = CX25840_AUDIO7,
560 },
561 },
562 },
563 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
564 .name = "TerraTec Cinergy T PCIe Dual",
565 .portb = CX23885_MPEG_DVB,
566 .portc = CX23885_MPEG_DVB,
567 },
568 [CX23885_BOARD_TEVII_S471] = {
569 .name = "TeVii S471",
570 .portb = CX23885_MPEG_DVB,
571 },
572 [CX23885_BOARD_PROF_8000] = {
573 .name = "Prof Revolution DVB-S2 8000",
574 .portb = CX23885_MPEG_DVB,
575 },
576 [CX23885_BOARD_HAUPPAUGE_HVR4400] = {
577 .name = "Hauppauge WinTV-HVR4400",
578 .portb = CX23885_MPEG_DVB,
579 },
580 };
581 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
582
583 /* ------------------------------------------------------------------ */
584 /* PCI subsystem IDs */
585
586 struct cx23885_subid cx23885_subids[] = {
587 {
588 .subvendor = 0x0070,
589 .subdevice = 0x3400,
590 .card = CX23885_BOARD_UNKNOWN,
591 }, {
592 .subvendor = 0x0070,
593 .subdevice = 0x7600,
594 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
595 }, {
596 .subvendor = 0x0070,
597 .subdevice = 0x7800,
598 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
599 }, {
600 .subvendor = 0x0070,
601 .subdevice = 0x7801,
602 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
603 }, {
604 .subvendor = 0x0070,
605 .subdevice = 0x7809,
606 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
607 }, {
608 .subvendor = 0x0070,
609 .subdevice = 0x7911,
610 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
611 }, {
612 .subvendor = 0x18ac,
613 .subdevice = 0xd500,
614 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
615 }, {
616 .subvendor = 0x0070,
617 .subdevice = 0x7790,
618 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
619 }, {
620 .subvendor = 0x0070,
621 .subdevice = 0x7797,
622 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
623 }, {
624 .subvendor = 0x0070,
625 .subdevice = 0x7710,
626 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
627 }, {
628 .subvendor = 0x0070,
629 .subdevice = 0x7717,
630 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
631 }, {
632 .subvendor = 0x0070,
633 .subdevice = 0x71d1,
634 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
635 }, {
636 .subvendor = 0x0070,
637 .subdevice = 0x71d3,
638 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
639 }, {
640 .subvendor = 0x0070,
641 .subdevice = 0x8101,
642 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
643 }, {
644 .subvendor = 0x0070,
645 .subdevice = 0x8010,
646 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
647 }, {
648 .subvendor = 0x18ac,
649 .subdevice = 0xd618,
650 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
651 }, {
652 .subvendor = 0x18ac,
653 .subdevice = 0xdb78,
654 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
655 }, {
656 .subvendor = 0x107d,
657 .subdevice = 0x6681,
658 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
659 }, {
660 .subvendor = 0x107d,
661 .subdevice = 0x6f39,
662 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
663 }, {
664 .subvendor = 0x185b,
665 .subdevice = 0xe800,
666 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
667 }, {
668 .subvendor = 0x6920,
669 .subdevice = 0x8888,
670 .card = CX23885_BOARD_TBS_6920,
671 }, {
672 .subvendor = 0xd470,
673 .subdevice = 0x9022,
674 .card = CX23885_BOARD_TEVII_S470,
675 }, {
676 .subvendor = 0x0001,
677 .subdevice = 0x2005,
678 .card = CX23885_BOARD_DVBWORLD_2005,
679 }, {
680 .subvendor = 0x1b55,
681 .subdevice = 0x2a2c,
682 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
683 }, {
684 .subvendor = 0x0070,
685 .subdevice = 0x2211,
686 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
687 }, {
688 .subvendor = 0x0070,
689 .subdevice = 0x2215,
690 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
691 }, {
692 .subvendor = 0x0070,
693 .subdevice = 0x221d,
694 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
695 }, {
696 .subvendor = 0x0070,
697 .subdevice = 0x2251,
698 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
699 }, {
700 .subvendor = 0x0070,
701 .subdevice = 0x2259,
702 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
703 }, {
704 .subvendor = 0x0070,
705 .subdevice = 0x2291,
706 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
707 }, {
708 .subvendor = 0x0070,
709 .subdevice = 0x2295,
710 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
711 }, {
712 .subvendor = 0x0070,
713 .subdevice = 0x2299,
714 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
715 }, {
716 .subvendor = 0x0070,
717 .subdevice = 0x229d,
718 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
719 }, {
720 .subvendor = 0x0070,
721 .subdevice = 0x22f0,
722 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
723 }, {
724 .subvendor = 0x0070,
725 .subdevice = 0x22f1,
726 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
727 }, {
728 .subvendor = 0x0070,
729 .subdevice = 0x22f2,
730 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
731 }, {
732 .subvendor = 0x0070,
733 .subdevice = 0x22f3,
734 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
735 }, {
736 .subvendor = 0x0070,
737 .subdevice = 0x22f4,
738 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
739 }, {
740 .subvendor = 0x0070,
741 .subdevice = 0x22f5,
742 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
743 }, {
744 .subvendor = 0x14f1,
745 .subdevice = 0x8651,
746 .card = CX23885_BOARD_MYGICA_X8506,
747 }, {
748 .subvendor = 0x14f1,
749 .subdevice = 0x8657,
750 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
751 }, {
752 .subvendor = 0x0070,
753 .subdevice = 0x8541,
754 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
755 }, {
756 .subvendor = 0x1858,
757 .subdevice = 0xe800,
758 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
759 }, {
760 .subvendor = 0x0070,
761 .subdevice = 0x8551,
762 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
763 }, {
764 .subvendor = 0x14f1,
765 .subdevice = 0x8578,
766 .card = CX23885_BOARD_MYGICA_X8558PRO,
767 }, {
768 .subvendor = 0x107d,
769 .subdevice = 0x6f22,
770 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
771 }, {
772 .subvendor = 0x5654,
773 .subdevice = 0x2390,
774 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
775 }, {
776 .subvendor = 0x1b55,
777 .subdevice = 0xe2e4,
778 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
779 }, {
780 .subvendor = 0x14f1,
781 .subdevice = 0x8502,
782 .card = CX23885_BOARD_MYGICA_X8507,
783 }, {
784 .subvendor = 0x153b,
785 .subdevice = 0x117e,
786 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
787 }, {
788 .subvendor = 0xd471,
789 .subdevice = 0x9022,
790 .card = CX23885_BOARD_TEVII_S471,
791 }, {
792 .subvendor = 0x8000,
793 .subdevice = 0x3034,
794 .card = CX23885_BOARD_PROF_8000,
795 }, {
796 .subvendor = 0x0070,
797 .subdevice = 0xc108,
798 .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
799 }, {
800 .subvendor = 0x0070,
801 .subdevice = 0xc138,
802 .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
803 }, {
804 .subvendor = 0x0070,
805 .subdevice = 0xc12a,
806 .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
807 }, {
808 .subvendor = 0x0070,
809 .subdevice = 0xc1f8,
810 .card = CX23885_BOARD_HAUPPAUGE_HVR4400,
811 },
812 };
813 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
814
815 void cx23885_card_list(struct cx23885_dev *dev)
816 {
817 int i;
818
819 if (0 == dev->pci->subsystem_vendor &&
820 0 == dev->pci->subsystem_device) {
821 printk(KERN_INFO
822 "%s: Board has no valid PCIe Subsystem ID and can't\n"
823 "%s: be autodetected. Pass card=<n> insmod option\n"
824 "%s: to workaround that. Redirect complaints to the\n"
825 "%s: vendor of the TV card. Best regards,\n"
826 "%s: -- tux\n",
827 dev->name, dev->name, dev->name, dev->name, dev->name);
828 } else {
829 printk(KERN_INFO
830 "%s: Your board isn't known (yet) to the driver.\n"
831 "%s: Try to pick one of the existing card configs via\n"
832 "%s: card=<n> insmod option. Updating to the latest\n"
833 "%s: version might help as well.\n",
834 dev->name, dev->name, dev->name, dev->name);
835 }
836 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
837 dev->name);
838 for (i = 0; i < cx23885_bcount; i++)
839 printk(KERN_INFO "%s: card=%d -> %s\n",
840 dev->name, i, cx23885_boards[i].name);
841 }
842
843 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
844 {
845 struct tveeprom tv;
846
847 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
848 eeprom_data);
849
850 /* Make sure we support the board model */
851 switch (tv.model) {
852 case 22001:
853 /* WinTV-HVR1270 (PCIe, Retail, half height)
854 * ATSC/QAM and basic analog, IR Blast */
855 case 22009:
856 /* WinTV-HVR1210 (PCIe, Retail, half height)
857 * DVB-T and basic analog, IR Blast */
858 case 22011:
859 /* WinTV-HVR1270 (PCIe, Retail, half height)
860 * ATSC/QAM and basic analog, IR Recv */
861 case 22019:
862 /* WinTV-HVR1210 (PCIe, Retail, half height)
863 * DVB-T and basic analog, IR Recv */
864 case 22021:
865 /* WinTV-HVR1275 (PCIe, Retail, half height)
866 * ATSC/QAM and basic analog, IR Recv */
867 case 22029:
868 /* WinTV-HVR1210 (PCIe, Retail, half height)
869 * DVB-T and basic analog, IR Recv */
870 case 22101:
871 /* WinTV-HVR1270 (PCIe, Retail, full height)
872 * ATSC/QAM and basic analog, IR Blast */
873 case 22109:
874 /* WinTV-HVR1210 (PCIe, Retail, full height)
875 * DVB-T and basic analog, IR Blast */
876 case 22111:
877 /* WinTV-HVR1270 (PCIe, Retail, full height)
878 * ATSC/QAM and basic analog, IR Recv */
879 case 22119:
880 /* WinTV-HVR1210 (PCIe, Retail, full height)
881 * DVB-T and basic analog, IR Recv */
882 case 22121:
883 /* WinTV-HVR1275 (PCIe, Retail, full height)
884 * ATSC/QAM and basic analog, IR Recv */
885 case 22129:
886 /* WinTV-HVR1210 (PCIe, Retail, full height)
887 * DVB-T and basic analog, IR Recv */
888 case 71009:
889 /* WinTV-HVR1200 (PCIe, Retail, full height)
890 * DVB-T and basic analog */
891 case 71359:
892 /* WinTV-HVR1200 (PCIe, OEM, half height)
893 * DVB-T and basic analog */
894 case 71439:
895 /* WinTV-HVR1200 (PCIe, OEM, half height)
896 * DVB-T and basic analog */
897 case 71449:
898 /* WinTV-HVR1200 (PCIe, OEM, full height)
899 * DVB-T and basic analog */
900 case 71939:
901 /* WinTV-HVR1200 (PCIe, OEM, half height)
902 * DVB-T and basic analog */
903 case 71949:
904 /* WinTV-HVR1200 (PCIe, OEM, full height)
905 * DVB-T and basic analog */
906 case 71959:
907 /* WinTV-HVR1200 (PCIe, OEM, full height)
908 * DVB-T and basic analog */
909 case 71979:
910 /* WinTV-HVR1200 (PCIe, OEM, half height)
911 * DVB-T and basic analog */
912 case 71999:
913 /* WinTV-HVR1200 (PCIe, OEM, full height)
914 * DVB-T and basic analog */
915 case 76601:
916 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
917 channel ATSC and MPEG2 HW Encoder */
918 case 77001:
919 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
920 and Basic analog */
921 case 77011:
922 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
923 and Basic analog */
924 case 77041:
925 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
926 and Basic analog */
927 case 77051:
928 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
929 and Basic analog */
930 case 78011:
931 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
932 Dual channel ATSC and MPEG2 HW Encoder */
933 case 78501:
934 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
935 Dual channel ATSC and MPEG2 HW Encoder */
936 case 78521:
937 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
938 Dual channel ATSC and MPEG2 HW Encoder */
939 case 78531:
940 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
941 Dual channel ATSC and MPEG2 HW Encoder */
942 case 78631:
943 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
944 Dual channel ATSC and MPEG2 HW Encoder */
945 case 79001:
946 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
947 ATSC and Basic analog */
948 case 79101:
949 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
950 ATSC and Basic analog */
951 case 79501:
952 /* WinTV-HVR1250 (PCIe, No IR, half height,
953 ATSC [at least] and Basic analog) */
954 case 79561:
955 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
956 ATSC and Basic analog */
957 case 79571:
958 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
959 ATSC and Basic analog */
960 case 79671:
961 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
962 ATSC and Basic analog */
963 case 80019:
964 /* WinTV-HVR1400 (Express Card, Retail, IR,
965 * DVB-T and Basic analog */
966 case 81509:
967 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
968 * DVB-T and MPEG2 HW Encoder */
969 case 81519:
970 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
971 * DVB-T and MPEG2 HW Encoder */
972 break;
973 case 85021:
974 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
975 Dual channel ATSC and MPEG2 HW Encoder */
976 break;
977 case 85721:
978 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
979 Dual channel ATSC and Basic analog */
980 break;
981 default:
982 printk(KERN_WARNING "%s: warning: "
983 "unknown hauppauge model #%d\n",
984 dev->name, tv.model);
985 break;
986 }
987
988 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
989 dev->name, tv.model);
990 }
991
992 int cx23885_tuner_callback(void *priv, int component, int command, int arg)
993 {
994 struct cx23885_tsport *port = priv;
995 struct cx23885_dev *dev = port->dev;
996 u32 bitmask = 0;
997
998 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
999 return 0;
1000
1001 if (command != 0) {
1002 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
1003 __func__, command);
1004 return -EINVAL;
1005 }
1006
1007 switch (dev->board) {
1008 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1009 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1010 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1011 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1012 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1013 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1014 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1015 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1016 /* Tuner Reset Command */
1017 bitmask = 0x04;
1018 break;
1019 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1020 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1021 /* Two identical tuners on two different i2c buses,
1022 * we need to reset the correct gpio. */
1023 if (port->nr == 1)
1024 bitmask = 0x01;
1025 else if (port->nr == 2)
1026 bitmask = 0x04;
1027 break;
1028 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1029 /* Tuner Reset Command */
1030 bitmask = 0x02;
1031 break;
1032 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1033 altera_ci_tuner_reset(dev, port->nr);
1034 break;
1035 }
1036
1037 if (bitmask) {
1038 /* Drive the tuner into reset and back out */
1039 cx_clear(GP0_IO, bitmask);
1040 mdelay(200);
1041 cx_set(GP0_IO, bitmask);
1042 }
1043
1044 return 0;
1045 }
1046
1047 void cx23885_gpio_setup(struct cx23885_dev *dev)
1048 {
1049 switch (dev->board) {
1050 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1051 /* GPIO-0 cx24227 demodulator reset */
1052 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1053 break;
1054 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1055 /* GPIO-0 cx24227 demodulator */
1056 /* GPIO-2 xc3028 tuner */
1057
1058 /* Put the parts into reset */
1059 cx_set(GP0_IO, 0x00050000);
1060 cx_clear(GP0_IO, 0x00000005);
1061 msleep(5);
1062
1063 /* Bring the parts out of reset */
1064 cx_set(GP0_IO, 0x00050005);
1065 break;
1066 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1067 /* GPIO-0 cx24227 demodulator reset */
1068 /* GPIO-2 xc5000 tuner reset */
1069 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
1070 break;
1071 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1072 /* GPIO-0 656_CLK */
1073 /* GPIO-1 656_D0 */
1074 /* GPIO-2 8295A Reset */
1075 /* GPIO-3-10 cx23417 data0-7 */
1076 /* GPIO-11-14 cx23417 addr0-3 */
1077 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1078 /* GPIO-19 IR_RX */
1079
1080 /* CX23417 GPIO's */
1081 /* EIO15 Zilog Reset */
1082 /* EIO14 S5H1409/CX24227 Reset */
1083 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
1084
1085 /* Put the demod into reset and protect the eeprom */
1086 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
1087 mdelay(100);
1088
1089 /* Bring the demod and blaster out of reset */
1090 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
1091 mdelay(100);
1092
1093 /* Force the TDA8295A into reset and back */
1094 cx23885_gpio_enable(dev, GPIO_2, 1);
1095 cx23885_gpio_set(dev, GPIO_2);
1096 mdelay(20);
1097 cx23885_gpio_clear(dev, GPIO_2);
1098 mdelay(20);
1099 cx23885_gpio_set(dev, GPIO_2);
1100 mdelay(20);
1101 break;
1102 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1103 /* GPIO-0 tda10048 demodulator reset */
1104 /* GPIO-2 tda18271 tuner reset */
1105
1106 /* Put the parts into reset and back */
1107 cx_set(GP0_IO, 0x00050000);
1108 mdelay(20);
1109 cx_clear(GP0_IO, 0x00000005);
1110 mdelay(20);
1111 cx_set(GP0_IO, 0x00050005);
1112 break;
1113 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1114 /* GPIO-0 TDA10048 demodulator reset */
1115 /* GPIO-2 TDA8295A Reset */
1116 /* GPIO-3-10 cx23417 data0-7 */
1117 /* GPIO-11-14 cx23417 addr0-3 */
1118 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1119
1120 /* The following GPIO's are on the interna AVCore (cx25840) */
1121 /* GPIO-19 IR_RX */
1122 /* GPIO-20 IR_TX 416/DVBT Select */
1123 /* GPIO-21 IIS DAT */
1124 /* GPIO-22 IIS WCLK */
1125 /* GPIO-23 IIS BCLK */
1126
1127 /* Put the parts into reset and back */
1128 cx_set(GP0_IO, 0x00050000);
1129 mdelay(20);
1130 cx_clear(GP0_IO, 0x00000005);
1131 mdelay(20);
1132 cx_set(GP0_IO, 0x00050005);
1133 break;
1134 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1135 /* GPIO-0 Dibcom7000p demodulator reset */
1136 /* GPIO-2 xc3028L tuner reset */
1137 /* GPIO-13 LED */
1138
1139 /* Put the parts into reset and back */
1140 cx_set(GP0_IO, 0x00050000);
1141 mdelay(20);
1142 cx_clear(GP0_IO, 0x00000005);
1143 mdelay(20);
1144 cx_set(GP0_IO, 0x00050005);
1145 break;
1146 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1147 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
1148 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
1149 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
1150 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
1151
1152 /* Put the parts into reset and back */
1153 cx_set(GP0_IO, 0x000f0000);
1154 mdelay(20);
1155 cx_clear(GP0_IO, 0x0000000f);
1156 mdelay(20);
1157 cx_set(GP0_IO, 0x000f000f);
1158 break;
1159 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1160 /* GPIO-0 portb xc3028 reset */
1161 /* GPIO-1 portb zl10353 reset */
1162 /* GPIO-2 portc xc3028 reset */
1163 /* GPIO-3 portc zl10353 reset */
1164
1165 /* Put the parts into reset and back */
1166 cx_set(GP0_IO, 0x000f0000);
1167 mdelay(20);
1168 cx_clear(GP0_IO, 0x0000000f);
1169 mdelay(20);
1170 cx_set(GP0_IO, 0x000f000f);
1171 break;
1172 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1173 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1174 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1175 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1176 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1177 /* GPIO-2 xc3028 tuner reset */
1178
1179 /* The following GPIO's are on the internal AVCore (cx25840) */
1180 /* GPIO-? zl10353 demod reset */
1181
1182 /* Put the parts into reset and back */
1183 cx_set(GP0_IO, 0x00040000);
1184 mdelay(20);
1185 cx_clear(GP0_IO, 0x00000004);
1186 mdelay(20);
1187 cx_set(GP0_IO, 0x00040004);
1188 break;
1189 case CX23885_BOARD_TBS_6920:
1190 case CX23885_BOARD_PROF_8000:
1191 cx_write(MC417_CTL, 0x00000036);
1192 cx_write(MC417_OEN, 0x00001000);
1193 cx_set(MC417_RWD, 0x00000002);
1194 mdelay(200);
1195 cx_clear(MC417_RWD, 0x00000800);
1196 mdelay(200);
1197 cx_set(MC417_RWD, 0x00000800);
1198 mdelay(200);
1199 break;
1200 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1201 /* GPIO-0 INTA from CiMax1
1202 GPIO-1 INTB from CiMax2
1203 GPIO-2 reset chips
1204 GPIO-3 to GPIO-10 data/addr for CA
1205 GPIO-11 ~CS0 to CiMax1
1206 GPIO-12 ~CS1 to CiMax2
1207 GPIO-13 ADL0 load LSB addr
1208 GPIO-14 ADL1 load MSB addr
1209 GPIO-15 ~RDY from CiMax
1210 GPIO-17 ~RD to CiMax
1211 GPIO-18 ~WR to CiMax
1212 */
1213 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
1214 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
1215 cx_clear(GP0_IO, 0x00030004);
1216 mdelay(100);/* reset delay */
1217 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
1218 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
1219 /* GPIO-15 IN as ~ACK, rest as OUT */
1220 cx_write(MC417_OEN, 0x00001000);
1221 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1222 cx_write(MC417_RWD, 0x0000c300);
1223 /* enable irq */
1224 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1225 break;
1226 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1227 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1228 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1229 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1230 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1231 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
1232 /* GPIO-6 I2C Gate which can isolate the demod from the bus */
1233 /* GPIO-9 Demod reset */
1234
1235 /* Put the parts into reset and back */
1236 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
1237 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
1238 cx23885_gpio_clear(dev, GPIO_9);
1239 mdelay(20);
1240 cx23885_gpio_set(dev, GPIO_9);
1241 break;
1242 case CX23885_BOARD_MYGICA_X8506:
1243 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1244 case CX23885_BOARD_MYGICA_X8507:
1245 /* GPIO-0 (0)Analog / (1)Digital TV */
1246 /* GPIO-1 reset XC5000 */
1247 /* GPIO-2 reset LGS8GL5 / LGS8G75 */
1248 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
1249 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
1250 mdelay(100);
1251 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
1252 mdelay(100);
1253 break;
1254 case CX23885_BOARD_MYGICA_X8558PRO:
1255 /* GPIO-0 reset first ATBM8830 */
1256 /* GPIO-1 reset second ATBM8830 */
1257 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
1258 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
1259 mdelay(100);
1260 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
1261 mdelay(100);
1262 break;
1263 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1264 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1265 /* GPIO-0 656_CLK */
1266 /* GPIO-1 656_D0 */
1267 /* GPIO-2 Wake# */
1268 /* GPIO-3-10 cx23417 data0-7 */
1269 /* GPIO-11-14 cx23417 addr0-3 */
1270 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1271 /* GPIO-19 IR_RX */
1272 /* GPIO-20 C_IR_TX */
1273 /* GPIO-21 I2S DAT */
1274 /* GPIO-22 I2S WCLK */
1275 /* GPIO-23 I2S BCLK */
1276 /* ALT GPIO: EXP GPIO LATCH */
1277
1278 /* CX23417 GPIO's */
1279 /* GPIO-14 S5H1411/CX24228 Reset */
1280 /* GPIO-13 EEPROM write protect */
1281 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
1282
1283 /* Put the demod into reset and protect the eeprom */
1284 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
1285 mdelay(100);
1286
1287 /* Bring the demod out of reset */
1288 mc417_gpio_set(dev, GPIO_14);
1289 mdelay(100);
1290
1291 /* CX24228 GPIO */
1292 /* Connected to IF / Mux */
1293 break;
1294 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1295 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1296 break;
1297 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1298 /* GPIO-0 ~INT in
1299 GPIO-1 TMS out
1300 GPIO-2 ~reset chips out
1301 GPIO-3 to GPIO-10 data/addr for CA in/out
1302 GPIO-11 ~CS out
1303 GPIO-12 ADDR out
1304 GPIO-13 ~WR out
1305 GPIO-14 ~RD out
1306 GPIO-15 ~RDY in
1307 GPIO-16 TCK out
1308 GPIO-17 TDO in
1309 GPIO-18 TDI out
1310 */
1311 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
1312 /* GPIO-0 as INT, reset & TMS low */
1313 cx_clear(GP0_IO, 0x00010006);
1314 mdelay(100);/* reset delay */
1315 cx_set(GP0_IO, 0x00000004); /* reset high */
1316 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
1317 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
1318 cx_write(MC417_OEN, 0x00005000);
1319 /* ~RD, ~WR high; ADDR low; ~CS high */
1320 cx_write(MC417_RWD, 0x00000d00);
1321 /* enable irq */
1322 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1323 break;
1324 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1325 /* GPIO-8 tda10071 demod reset */
1326
1327 /* Put the parts into reset and back */
1328 cx23885_gpio_enable(dev, GPIO_8, 1);
1329 cx23885_gpio_clear(dev, GPIO_8);
1330 mdelay(100);
1331 cx23885_gpio_set(dev, GPIO_8);
1332 mdelay(100);
1333 break;
1334 }
1335 }
1336
1337 int cx23885_ir_init(struct cx23885_dev *dev)
1338 {
1339 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
1340 {
1341 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1342 .pin = CX23885_PIN_IR_RX_GPIO19,
1343 .function = CX23885_PAD_IR_RX,
1344 .value = 0,
1345 .strength = CX25840_PIN_DRIVE_MEDIUM,
1346 }, {
1347 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
1348 .pin = CX23885_PIN_IR_TX_GPIO20,
1349 .function = CX23885_PAD_IR_TX,
1350 .value = 0,
1351 .strength = CX25840_PIN_DRIVE_MEDIUM,
1352 }
1353 };
1354 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1355
1356 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1357 {
1358 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1359 .pin = CX23885_PIN_IR_RX_GPIO19,
1360 .function = CX23885_PAD_IR_RX,
1361 .value = 0,
1362 .strength = CX25840_PIN_DRIVE_MEDIUM,
1363 }
1364 };
1365 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
1366
1367 struct v4l2_subdev_ir_parameters params;
1368 int ret = 0;
1369 switch (dev->board) {
1370 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1371 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1372 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1373 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1374 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1375 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1376 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1377 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1378 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1379 /* FIXME: Implement me */
1380 break;
1381 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1382 ret = cx23888_ir_probe(dev);
1383 if (ret)
1384 break;
1385 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1386 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1387 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1388 break;
1389 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1390 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1391 ret = cx23888_ir_probe(dev);
1392 if (ret)
1393 break;
1394 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1395 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1396 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1397 /*
1398 * For these boards we need to invert the Tx output via the
1399 * IR controller to have the LED off while idle
1400 */
1401 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
1402 params.enable = false;
1403 params.shutdown = false;
1404 params.invert_level = true;
1405 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1406 params.shutdown = true;
1407 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1408 break;
1409 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1410 case CX23885_BOARD_TEVII_S470:
1411 if (!enable_885_ir)
1412 break;
1413 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1414 if (dev->sd_ir == NULL) {
1415 ret = -ENODEV;
1416 break;
1417 }
1418 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1419 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1420 break;
1421 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1422 if (!enable_885_ir)
1423 break;
1424 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1425 if (dev->sd_ir == NULL) {
1426 ret = -ENODEV;
1427 break;
1428 }
1429 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1430 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1431 break;
1432 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1433 request_module("ir-kbd-i2c");
1434 break;
1435 }
1436
1437 return ret;
1438 }
1439
1440 void cx23885_ir_fini(struct cx23885_dev *dev)
1441 {
1442 switch (dev->board) {
1443 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1444 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1445 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1446 cx23885_irq_remove(dev, PCI_MSK_IR);
1447 cx23888_ir_remove(dev);
1448 dev->sd_ir = NULL;
1449 break;
1450 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1451 case CX23885_BOARD_TEVII_S470:
1452 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1453 cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
1454 /* sd_ir is a duplicate pointer to the AV Core, just clear it */
1455 dev->sd_ir = NULL;
1456 break;
1457 }
1458 }
1459
1460 static int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
1461 {
1462 int data;
1463 int tdo = 0;
1464 struct cx23885_dev *dev = (struct cx23885_dev *)device;
1465 /*TMS*/
1466 data = ((cx_read(GP0_IO)) & (~0x00000002));
1467 data |= (tms ? 0x00020002 : 0x00020000);
1468 cx_write(GP0_IO, data);
1469
1470 /*TDI*/
1471 data = ((cx_read(MC417_RWD)) & (~0x0000a000));
1472 data |= (tdi ? 0x00008000 : 0);
1473 cx_write(MC417_RWD, data);
1474 if (read_tdo)
1475 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
1476
1477 cx_write(MC417_RWD, data | 0x00002000);
1478 udelay(1);
1479 /*TCK*/
1480 cx_write(MC417_RWD, data);
1481
1482 return tdo;
1483 }
1484
1485 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1486 {
1487 switch (dev->board) {
1488 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1489 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1490 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1491 if (dev->sd_ir)
1492 cx23885_irq_add_enable(dev, PCI_MSK_IR);
1493 break;
1494 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1495 case CX23885_BOARD_TEVII_S470:
1496 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1497 if (dev->sd_ir)
1498 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
1499 break;
1500 }
1501 }
1502
1503 void cx23885_card_setup(struct cx23885_dev *dev)
1504 {
1505 struct cx23885_tsport *ts1 = &dev->ts1;
1506 struct cx23885_tsport *ts2 = &dev->ts2;
1507
1508 static u8 eeprom[256];
1509
1510 if (dev->i2c_bus[0].i2c_rc == 0) {
1511 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1512 tveeprom_read(&dev->i2c_bus[0].i2c_client,
1513 eeprom, sizeof(eeprom));
1514 }
1515
1516 switch (dev->board) {
1517 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1518 if (dev->i2c_bus[0].i2c_rc == 0) {
1519 if (eeprom[0x80] != 0x84)
1520 hauppauge_eeprom(dev, eeprom+0xc0);
1521 else
1522 hauppauge_eeprom(dev, eeprom+0x80);
1523 }
1524 break;
1525 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1526 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1527 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1528 if (dev->i2c_bus[0].i2c_rc == 0)
1529 hauppauge_eeprom(dev, eeprom+0x80);
1530 break;
1531 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1532 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1533 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1534 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1535 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1536 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1537 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1538 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1539 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1540 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1541 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1542 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1543 if (dev->i2c_bus[0].i2c_rc == 0)
1544 hauppauge_eeprom(dev, eeprom+0xc0);
1545 break;
1546 }
1547
1548 switch (dev->board) {
1549 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1550 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1551 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1552 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1553 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1554 /* break omitted intentionally */
1555 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
1556 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1557 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1558 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1559 break;
1560 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1561 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1562 /* Defaults for VID B - Analog encoder */
1563 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1564 ts1->gen_ctrl_val = 0x10e;
1565 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1566 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1567
1568 /* APB_TSVALERR_POL (active low)*/
1569 ts1->vld_misc_val = 0x2000;
1570 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
1571 cx_write(0x130184, 0xc);
1572
1573 /* Defaults for VID C */
1574 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1575 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1576 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1577 break;
1578 case CX23885_BOARD_TBS_6920:
1579 ts1->gen_ctrl_val = 0x4; /* Parallel */
1580 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1581 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1582 break;
1583 case CX23885_BOARD_TEVII_S470:
1584 case CX23885_BOARD_TEVII_S471:
1585 case CX23885_BOARD_DVBWORLD_2005:
1586 case CX23885_BOARD_PROF_8000:
1587 ts1->gen_ctrl_val = 0x5; /* Parallel */
1588 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1589 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1590 break;
1591 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1592 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1593 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1594 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1595 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1596 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1597 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1598 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1599 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1600 break;
1601 case CX23885_BOARD_MYGICA_X8506:
1602 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1603 ts1->gen_ctrl_val = 0x5; /* Parallel */
1604 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1605 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1606 break;
1607 case CX23885_BOARD_MYGICA_X8558PRO:
1608 ts1->gen_ctrl_val = 0x5; /* Parallel */
1609 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1610 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1611 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1612 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1613 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1614 break;
1615 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1616 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1617 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1618 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1619 break;
1620 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1621 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1622 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1623 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1624 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1625 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1626 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1627 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1628 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1629 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1630 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1631 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1632 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1633 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1634 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1635 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1636 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1637 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1638 default:
1639 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1640 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1641 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1642 }
1643
1644 /* Certain boards support analog, or require the avcore to be
1645 * loaded, ensure this happens.
1646 */
1647 switch (dev->board) {
1648 case CX23885_BOARD_TEVII_S470:
1649 /* Currently only enabled for the integrated IR controller */
1650 if (!enable_885_ir)
1651 break;
1652 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1653 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1654 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1655 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1656 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1657 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1658 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1659 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1660 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1661 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1662 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1663 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1664 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1665 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1666 case CX23885_BOARD_MYGICA_X8506:
1667 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1668 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1669 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1670 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1671 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1672 case CX23885_BOARD_MPX885:
1673 case CX23885_BOARD_MYGICA_X8507:
1674 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1675 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
1676 &dev->i2c_bus[2].i2c_adap,
1677 "cx25840", 0x88 >> 1, NULL);
1678 if (dev->sd_cx25840) {
1679 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
1680 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
1681 }
1682 break;
1683 }
1684
1685 /* AUX-PLL 27MHz CLK */
1686 switch (dev->board) {
1687 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1688 netup_initialize(dev);
1689 break;
1690 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1691 int ret;
1692 const struct firmware *fw;
1693 const char *filename = "dvb-netup-altera-01.fw";
1694 char *action = "configure";
1695 static struct netup_card_info cinfo;
1696 struct altera_config netup_config = {
1697 .dev = dev,
1698 .action = action,
1699 .jtag_io = netup_jtag_io,
1700 };
1701
1702 netup_initialize(dev);
1703
1704 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1705 if (netup_card_rev)
1706 cinfo.rev = netup_card_rev;
1707
1708 switch (cinfo.rev) {
1709 case 0x4:
1710 filename = "dvb-netup-altera-04.fw";
1711 break;
1712 default:
1713 filename = "dvb-netup-altera-01.fw";
1714 break;
1715 }
1716 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
1717 cinfo.rev, filename);
1718
1719 ret = request_firmware(&fw, filename, &dev->pci->dev);
1720 if (ret != 0)
1721 printk(KERN_ERR "did not find the firmware file. (%s) "
1722 "Please see linux/Documentation/dvb/ for more details "
1723 "on firmware-problems.", filename);
1724 else
1725 altera_init(&netup_config, fw);
1726
1727 release_firmware(fw);
1728 break;
1729 }
1730 }
1731 }
1732
1733 /* ------------------------------------------------------------------ */
Linux kernel - Deliverables
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