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[media] cx23885-cards: fix netup card default revision
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885-cards.c
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <media/cx25840.h>
27 #include <linux/firmware.h>
28 #include <misc/altera.h>
29
30 #include "cx23885.h"
31 #include "tuner-xc2028.h"
32 #include "netup-eeprom.h"
33 #include "netup-init.h"
34 #include "altera-ci.h"
35 #include "xc4000.h"
36 #include "xc5000.h"
37 #include "cx23888-ir.h"
38
39 static unsigned int netup_card_rev = 4;
40 module_param(netup_card_rev, int, 0644);
41 MODULE_PARM_DESC(netup_card_rev,
42 "NetUP Dual DVB-T/C CI card revision");
43 static unsigned int enable_885_ir;
44 module_param(enable_885_ir, int, 0644);
45 MODULE_PARM_DESC(enable_885_ir,
46 "Enable integrated IR controller for supported\n"
47 "\t\t CX2388[57] boards that are wired for it:\n"
48 "\t\t\tHVR-1250 (reported safe)\n"
49 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n"
50 "\t\t\tTeVii S470 (reported unsafe)\n"
51 "\t\t This can cause an interrupt storm with some cards.\n"
52 "\t\t Default: 0 [Disabled]");
53
54 /* ------------------------------------------------------------------ */
55 /* board config info */
56
57 struct cx23885_board cx23885_boards[] = {
58 [CX23885_BOARD_UNKNOWN] = {
59 .name = "UNKNOWN/GENERIC",
60 /* Ensure safe default for unknown boards */
61 .clk_freq = 0,
62 .input = {{
63 .type = CX23885_VMUX_COMPOSITE1,
64 .vmux = 0,
65 }, {
66 .type = CX23885_VMUX_COMPOSITE2,
67 .vmux = 1,
68 }, {
69 .type = CX23885_VMUX_COMPOSITE3,
70 .vmux = 2,
71 }, {
72 .type = CX23885_VMUX_COMPOSITE4,
73 .vmux = 3,
74 } },
75 },
76 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
77 .name = "Hauppauge WinTV-HVR1800lp",
78 .portc = CX23885_MPEG_DVB,
79 .input = {{
80 .type = CX23885_VMUX_TELEVISION,
81 .vmux = 0,
82 .gpio0 = 0xff00,
83 }, {
84 .type = CX23885_VMUX_DEBUG,
85 .vmux = 0,
86 .gpio0 = 0xff01,
87 }, {
88 .type = CX23885_VMUX_COMPOSITE1,
89 .vmux = 1,
90 .gpio0 = 0xff02,
91 }, {
92 .type = CX23885_VMUX_SVIDEO,
93 .vmux = 2,
94 .gpio0 = 0xff02,
95 } },
96 },
97 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
98 .name = "Hauppauge WinTV-HVR1800",
99 .porta = CX23885_ANALOG_VIDEO,
100 .portb = CX23885_MPEG_ENCODER,
101 .portc = CX23885_MPEG_DVB,
102 .tuner_type = TUNER_PHILIPS_TDA8290,
103 .tuner_addr = 0x42, /* 0x84 >> 1 */
104 .tuner_bus = 1,
105 .input = {{
106 .type = CX23885_VMUX_TELEVISION,
107 .vmux = CX25840_VIN7_CH3 |
108 CX25840_VIN5_CH2 |
109 CX25840_VIN2_CH1,
110 .amux = CX25840_AUDIO8,
111 .gpio0 = 0,
112 }, {
113 .type = CX23885_VMUX_COMPOSITE1,
114 .vmux = CX25840_VIN7_CH3 |
115 CX25840_VIN4_CH2 |
116 CX25840_VIN6_CH1,
117 .amux = CX25840_AUDIO7,
118 .gpio0 = 0,
119 }, {
120 .type = CX23885_VMUX_SVIDEO,
121 .vmux = CX25840_VIN7_CH3 |
122 CX25840_VIN4_CH2 |
123 CX25840_VIN8_CH1 |
124 CX25840_SVIDEO_ON,
125 .amux = CX25840_AUDIO7,
126 .gpio0 = 0,
127 } },
128 },
129 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
130 .name = "Hauppauge WinTV-HVR1250",
131 .porta = CX23885_ANALOG_VIDEO,
132 .portc = CX23885_MPEG_DVB,
133 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
134 .tuner_type = TUNER_PHILIPS_TDA8290,
135 .tuner_addr = 0x42, /* 0x84 >> 1 */
136 .tuner_bus = 1,
137 #endif
138 .force_bff = 1,
139 .input = {{
140 #ifdef MT2131_NO_ANALOG_SUPPORT_YET
141 .type = CX23885_VMUX_TELEVISION,
142 .vmux = CX25840_VIN7_CH3 |
143 CX25840_VIN5_CH2 |
144 CX25840_VIN2_CH1,
145 .amux = CX25840_AUDIO8,
146 .gpio0 = 0xff00,
147 }, {
148 #endif
149 .type = CX23885_VMUX_COMPOSITE1,
150 .vmux = CX25840_VIN7_CH3 |
151 CX25840_VIN4_CH2 |
152 CX25840_VIN6_CH1,
153 .amux = CX25840_AUDIO7,
154 .gpio0 = 0xff02,
155 }, {
156 .type = CX23885_VMUX_SVIDEO,
157 .vmux = CX25840_VIN7_CH3 |
158 CX25840_VIN4_CH2 |
159 CX25840_VIN8_CH1 |
160 CX25840_SVIDEO_ON,
161 .amux = CX25840_AUDIO7,
162 .gpio0 = 0xff02,
163 } },
164 },
165 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
166 .name = "DViCO FusionHDTV5 Express",
167 .portb = CX23885_MPEG_DVB,
168 },
169 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
170 .name = "Hauppauge WinTV-HVR1500Q",
171 .portc = CX23885_MPEG_DVB,
172 },
173 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
174 .name = "Hauppauge WinTV-HVR1500",
175 .porta = CX23885_ANALOG_VIDEO,
176 .portc = CX23885_MPEG_DVB,
177 .tuner_type = TUNER_XC2028,
178 .tuner_addr = 0x61, /* 0xc2 >> 1 */
179 .input = {{
180 .type = CX23885_VMUX_TELEVISION,
181 .vmux = CX25840_VIN7_CH3 |
182 CX25840_VIN5_CH2 |
183 CX25840_VIN2_CH1,
184 .gpio0 = 0,
185 }, {
186 .type = CX23885_VMUX_COMPOSITE1,
187 .vmux = CX25840_VIN7_CH3 |
188 CX25840_VIN4_CH2 |
189 CX25840_VIN6_CH1,
190 .gpio0 = 0,
191 }, {
192 .type = CX23885_VMUX_SVIDEO,
193 .vmux = CX25840_VIN7_CH3 |
194 CX25840_VIN4_CH2 |
195 CX25840_VIN8_CH1 |
196 CX25840_SVIDEO_ON,
197 .gpio0 = 0,
198 } },
199 },
200 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
201 .name = "Hauppauge WinTV-HVR1200",
202 .portc = CX23885_MPEG_DVB,
203 },
204 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
205 .name = "Hauppauge WinTV-HVR1700",
206 .portc = CX23885_MPEG_DVB,
207 },
208 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
209 .name = "Hauppauge WinTV-HVR1400",
210 .portc = CX23885_MPEG_DVB,
211 },
212 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
213 .name = "DViCO FusionHDTV7 Dual Express",
214 .portb = CX23885_MPEG_DVB,
215 .portc = CX23885_MPEG_DVB,
216 },
217 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
218 .name = "DViCO FusionHDTV DVB-T Dual Express",
219 .portb = CX23885_MPEG_DVB,
220 .portc = CX23885_MPEG_DVB,
221 },
222 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
223 .name = "Leadtek Winfast PxDVR3200 H",
224 .portc = CX23885_MPEG_DVB,
225 },
226 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
227 .name = "Leadtek Winfast PxDVR3200 H XC4000",
228 .porta = CX23885_ANALOG_VIDEO,
229 .portc = CX23885_MPEG_DVB,
230 .tuner_type = TUNER_XC4000,
231 .tuner_addr = 0x61,
232 .radio_type = UNSET,
233 .radio_addr = ADDR_UNSET,
234 .input = {{
235 .type = CX23885_VMUX_TELEVISION,
236 .vmux = CX25840_VIN2_CH1 |
237 CX25840_VIN5_CH2 |
238 CX25840_NONE0_CH3,
239 }, {
240 .type = CX23885_VMUX_COMPOSITE1,
241 .vmux = CX25840_COMPOSITE1,
242 }, {
243 .type = CX23885_VMUX_SVIDEO,
244 .vmux = CX25840_SVIDEO_LUMA3 |
245 CX25840_SVIDEO_CHROMA4,
246 }, {
247 .type = CX23885_VMUX_COMPONENT,
248 .vmux = CX25840_VIN7_CH1 |
249 CX25840_VIN6_CH2 |
250 CX25840_VIN8_CH3 |
251 CX25840_COMPONENT_ON,
252 } },
253 },
254 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
255 .name = "Compro VideoMate E650F",
256 .portc = CX23885_MPEG_DVB,
257 },
258 [CX23885_BOARD_TBS_6920] = {
259 .name = "TurboSight TBS 6920",
260 .portb = CX23885_MPEG_DVB,
261 },
262 [CX23885_BOARD_TEVII_S470] = {
263 .name = "TeVii S470",
264 .portb = CX23885_MPEG_DVB,
265 },
266 [CX23885_BOARD_DVBWORLD_2005] = {
267 .name = "DVBWorld DVB-S2 2005",
268 .portb = CX23885_MPEG_DVB,
269 },
270 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
271 .ci_type = 1,
272 .name = "NetUP Dual DVB-S2 CI",
273 .portb = CX23885_MPEG_DVB,
274 .portc = CX23885_MPEG_DVB,
275 },
276 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
277 .name = "Hauppauge WinTV-HVR1270",
278 .portc = CX23885_MPEG_DVB,
279 },
280 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
281 .name = "Hauppauge WinTV-HVR1275",
282 .portc = CX23885_MPEG_DVB,
283 },
284 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
285 .name = "Hauppauge WinTV-HVR1255",
286 .porta = CX23885_ANALOG_VIDEO,
287 .portc = CX23885_MPEG_DVB,
288 .tuner_type = TUNER_ABSENT,
289 .tuner_addr = 0x42, /* 0x84 >> 1 */
290 .force_bff = 1,
291 .input = {{
292 .type = CX23885_VMUX_TELEVISION,
293 .vmux = CX25840_VIN7_CH3 |
294 CX25840_VIN5_CH2 |
295 CX25840_VIN2_CH1 |
296 CX25840_DIF_ON,
297 .amux = CX25840_AUDIO8,
298 }, {
299 .type = CX23885_VMUX_COMPOSITE1,
300 .vmux = CX25840_VIN7_CH3 |
301 CX25840_VIN4_CH2 |
302 CX25840_VIN6_CH1,
303 .amux = CX25840_AUDIO7,
304 }, {
305 .type = CX23885_VMUX_SVIDEO,
306 .vmux = CX25840_VIN7_CH3 |
307 CX25840_VIN4_CH2 |
308 CX25840_VIN8_CH1 |
309 CX25840_SVIDEO_ON,
310 .amux = CX25840_AUDIO7,
311 } },
312 },
313 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
314 .name = "Hauppauge WinTV-HVR1255",
315 .porta = CX23885_ANALOG_VIDEO,
316 .portc = CX23885_MPEG_DVB,
317 .tuner_type = TUNER_ABSENT,
318 .tuner_addr = 0x42, /* 0x84 >> 1 */
319 .force_bff = 1,
320 .input = {{
321 .type = CX23885_VMUX_TELEVISION,
322 .vmux = CX25840_VIN7_CH3 |
323 CX25840_VIN5_CH2 |
324 CX25840_VIN2_CH1 |
325 CX25840_DIF_ON,
326 .amux = CX25840_AUDIO8,
327 }, {
328 .type = CX23885_VMUX_SVIDEO,
329 .vmux = CX25840_VIN7_CH3 |
330 CX25840_VIN4_CH2 |
331 CX25840_VIN8_CH1 |
332 CX25840_SVIDEO_ON,
333 .amux = CX25840_AUDIO7,
334 } },
335 },
336 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
337 .name = "Hauppauge WinTV-HVR1210",
338 .portc = CX23885_MPEG_DVB,
339 },
340 [CX23885_BOARD_MYGICA_X8506] = {
341 .name = "Mygica X8506 DMB-TH",
342 .tuner_type = TUNER_XC5000,
343 .tuner_addr = 0x61,
344 .tuner_bus = 1,
345 .porta = CX23885_ANALOG_VIDEO,
346 .portb = CX23885_MPEG_DVB,
347 .input = {
348 {
349 .type = CX23885_VMUX_TELEVISION,
350 .vmux = CX25840_COMPOSITE2,
351 },
352 {
353 .type = CX23885_VMUX_COMPOSITE1,
354 .vmux = CX25840_COMPOSITE8,
355 },
356 {
357 .type = CX23885_VMUX_SVIDEO,
358 .vmux = CX25840_SVIDEO_LUMA3 |
359 CX25840_SVIDEO_CHROMA4,
360 },
361 {
362 .type = CX23885_VMUX_COMPONENT,
363 .vmux = CX25840_COMPONENT_ON |
364 CX25840_VIN1_CH1 |
365 CX25840_VIN6_CH2 |
366 CX25840_VIN7_CH3,
367 },
368 },
369 },
370 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
371 .name = "Magic-Pro ProHDTV Extreme 2",
372 .tuner_type = TUNER_XC5000,
373 .tuner_addr = 0x61,
374 .tuner_bus = 1,
375 .porta = CX23885_ANALOG_VIDEO,
376 .portb = CX23885_MPEG_DVB,
377 .input = {
378 {
379 .type = CX23885_VMUX_TELEVISION,
380 .vmux = CX25840_COMPOSITE2,
381 },
382 {
383 .type = CX23885_VMUX_COMPOSITE1,
384 .vmux = CX25840_COMPOSITE8,
385 },
386 {
387 .type = CX23885_VMUX_SVIDEO,
388 .vmux = CX25840_SVIDEO_LUMA3 |
389 CX25840_SVIDEO_CHROMA4,
390 },
391 {
392 .type = CX23885_VMUX_COMPONENT,
393 .vmux = CX25840_COMPONENT_ON |
394 CX25840_VIN1_CH1 |
395 CX25840_VIN6_CH2 |
396 CX25840_VIN7_CH3,
397 },
398 },
399 },
400 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
401 .name = "Hauppauge WinTV-HVR1850",
402 .porta = CX23885_ANALOG_VIDEO,
403 .portb = CX23885_MPEG_ENCODER,
404 .portc = CX23885_MPEG_DVB,
405 .tuner_type = TUNER_ABSENT,
406 .tuner_addr = 0x42, /* 0x84 >> 1 */
407 .force_bff = 1,
408 .input = {{
409 .type = CX23885_VMUX_TELEVISION,
410 .vmux = CX25840_VIN7_CH3 |
411 CX25840_VIN5_CH2 |
412 CX25840_VIN2_CH1 |
413 CX25840_DIF_ON,
414 .amux = CX25840_AUDIO8,
415 }, {
416 .type = CX23885_VMUX_COMPOSITE1,
417 .vmux = CX25840_VIN7_CH3 |
418 CX25840_VIN4_CH2 |
419 CX25840_VIN6_CH1,
420 .amux = CX25840_AUDIO7,
421 }, {
422 .type = CX23885_VMUX_SVIDEO,
423 .vmux = CX25840_VIN7_CH3 |
424 CX25840_VIN4_CH2 |
425 CX25840_VIN8_CH1 |
426 CX25840_SVIDEO_ON,
427 .amux = CX25840_AUDIO7,
428 } },
429 },
430 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
431 .name = "Compro VideoMate E800",
432 .portc = CX23885_MPEG_DVB,
433 },
434 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
435 .name = "Hauppauge WinTV-HVR1290",
436 .portc = CX23885_MPEG_DVB,
437 },
438 [CX23885_BOARD_MYGICA_X8558PRO] = {
439 .name = "Mygica X8558 PRO DMB-TH",
440 .portb = CX23885_MPEG_DVB,
441 .portc = CX23885_MPEG_DVB,
442 },
443 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
444 .name = "LEADTEK WinFast PxTV1200",
445 .porta = CX23885_ANALOG_VIDEO,
446 .tuner_type = TUNER_XC2028,
447 .tuner_addr = 0x61,
448 .tuner_bus = 1,
449 .input = {{
450 .type = CX23885_VMUX_TELEVISION,
451 .vmux = CX25840_VIN2_CH1 |
452 CX25840_VIN5_CH2 |
453 CX25840_NONE0_CH3,
454 }, {
455 .type = CX23885_VMUX_COMPOSITE1,
456 .vmux = CX25840_COMPOSITE1,
457 }, {
458 .type = CX23885_VMUX_SVIDEO,
459 .vmux = CX25840_SVIDEO_LUMA3 |
460 CX25840_SVIDEO_CHROMA4,
461 }, {
462 .type = CX23885_VMUX_COMPONENT,
463 .vmux = CX25840_VIN7_CH1 |
464 CX25840_VIN6_CH2 |
465 CX25840_VIN8_CH3 |
466 CX25840_COMPONENT_ON,
467 } },
468 },
469 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
470 .name = "GoTView X5 3D Hybrid",
471 .tuner_type = TUNER_XC5000,
472 .tuner_addr = 0x64,
473 .tuner_bus = 1,
474 .porta = CX23885_ANALOG_VIDEO,
475 .portb = CX23885_MPEG_DVB,
476 .input = {{
477 .type = CX23885_VMUX_TELEVISION,
478 .vmux = CX25840_VIN2_CH1 |
479 CX25840_VIN5_CH2,
480 .gpio0 = 0x02,
481 }, {
482 .type = CX23885_VMUX_COMPOSITE1,
483 .vmux = CX23885_VMUX_COMPOSITE1,
484 }, {
485 .type = CX23885_VMUX_SVIDEO,
486 .vmux = CX25840_SVIDEO_LUMA3 |
487 CX25840_SVIDEO_CHROMA4,
488 } },
489 },
490 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
491 .ci_type = 2,
492 .name = "NetUP Dual DVB-T/C-CI RF",
493 .porta = CX23885_ANALOG_VIDEO,
494 .portb = CX23885_MPEG_DVB,
495 .portc = CX23885_MPEG_DVB,
496 .num_fds_portb = 2,
497 .num_fds_portc = 2,
498 .tuner_type = TUNER_XC5000,
499 .tuner_addr = 0x64,
500 .input = { {
501 .type = CX23885_VMUX_TELEVISION,
502 .vmux = CX25840_COMPOSITE1,
503 } },
504 },
505 [CX23885_BOARD_MPX885] = {
506 .name = "MPX-885",
507 .porta = CX23885_ANALOG_VIDEO,
508 .input = {{
509 .type = CX23885_VMUX_COMPOSITE1,
510 .vmux = CX25840_COMPOSITE1,
511 .amux = CX25840_AUDIO6,
512 .gpio0 = 0,
513 }, {
514 .type = CX23885_VMUX_COMPOSITE2,
515 .vmux = CX25840_COMPOSITE2,
516 .amux = CX25840_AUDIO6,
517 .gpio0 = 0,
518 }, {
519 .type = CX23885_VMUX_COMPOSITE3,
520 .vmux = CX25840_COMPOSITE3,
521 .amux = CX25840_AUDIO7,
522 .gpio0 = 0,
523 }, {
524 .type = CX23885_VMUX_COMPOSITE4,
525 .vmux = CX25840_COMPOSITE4,
526 .amux = CX25840_AUDIO7,
527 .gpio0 = 0,
528 } },
529 },
530 [CX23885_BOARD_MYGICA_X8507] = {
531 .name = "Mygica X8507",
532 .tuner_type = TUNER_XC5000,
533 .tuner_addr = 0x61,
534 .tuner_bus = 1,
535 .porta = CX23885_ANALOG_VIDEO,
536 .input = {
537 {
538 .type = CX23885_VMUX_TELEVISION,
539 .vmux = CX25840_COMPOSITE2,
540 .amux = CX25840_AUDIO8,
541 },
542 {
543 .type = CX23885_VMUX_COMPOSITE1,
544 .vmux = CX25840_COMPOSITE8,
545 },
546 {
547 .type = CX23885_VMUX_SVIDEO,
548 .vmux = CX25840_SVIDEO_LUMA3 |
549 CX25840_SVIDEO_CHROMA4,
550 },
551 {
552 .type = CX23885_VMUX_COMPONENT,
553 .vmux = CX25840_COMPONENT_ON |
554 CX25840_VIN1_CH1 |
555 CX25840_VIN6_CH2 |
556 CX25840_VIN7_CH3,
557 },
558 },
559 },
560 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
561 .name = "TerraTec Cinergy T PCIe Dual",
562 .portb = CX23885_MPEG_DVB,
563 .portc = CX23885_MPEG_DVB,
564 },
565 [CX23885_BOARD_TEVII_S471] = {
566 .name = "TeVii S471",
567 .portb = CX23885_MPEG_DVB,
568 }
569 };
570 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
571
572 /* ------------------------------------------------------------------ */
573 /* PCI subsystem IDs */
574
575 struct cx23885_subid cx23885_subids[] = {
576 {
577 .subvendor = 0x0070,
578 .subdevice = 0x3400,
579 .card = CX23885_BOARD_UNKNOWN,
580 }, {
581 .subvendor = 0x0070,
582 .subdevice = 0x7600,
583 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
584 }, {
585 .subvendor = 0x0070,
586 .subdevice = 0x7800,
587 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
588 }, {
589 .subvendor = 0x0070,
590 .subdevice = 0x7801,
591 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
592 }, {
593 .subvendor = 0x0070,
594 .subdevice = 0x7809,
595 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
596 }, {
597 .subvendor = 0x0070,
598 .subdevice = 0x7911,
599 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
600 }, {
601 .subvendor = 0x18ac,
602 .subdevice = 0xd500,
603 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
604 }, {
605 .subvendor = 0x0070,
606 .subdevice = 0x7790,
607 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
608 }, {
609 .subvendor = 0x0070,
610 .subdevice = 0x7797,
611 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
612 }, {
613 .subvendor = 0x0070,
614 .subdevice = 0x7710,
615 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
616 }, {
617 .subvendor = 0x0070,
618 .subdevice = 0x7717,
619 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
620 }, {
621 .subvendor = 0x0070,
622 .subdevice = 0x71d1,
623 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
624 }, {
625 .subvendor = 0x0070,
626 .subdevice = 0x71d3,
627 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
628 }, {
629 .subvendor = 0x0070,
630 .subdevice = 0x8101,
631 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
632 }, {
633 .subvendor = 0x0070,
634 .subdevice = 0x8010,
635 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
636 }, {
637 .subvendor = 0x18ac,
638 .subdevice = 0xd618,
639 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
640 }, {
641 .subvendor = 0x18ac,
642 .subdevice = 0xdb78,
643 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
644 }, {
645 .subvendor = 0x107d,
646 .subdevice = 0x6681,
647 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
648 }, {
649 .subvendor = 0x107d,
650 .subdevice = 0x6f39,
651 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
652 }, {
653 .subvendor = 0x185b,
654 .subdevice = 0xe800,
655 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
656 }, {
657 .subvendor = 0x6920,
658 .subdevice = 0x8888,
659 .card = CX23885_BOARD_TBS_6920,
660 }, {
661 .subvendor = 0xd470,
662 .subdevice = 0x9022,
663 .card = CX23885_BOARD_TEVII_S470,
664 }, {
665 .subvendor = 0x0001,
666 .subdevice = 0x2005,
667 .card = CX23885_BOARD_DVBWORLD_2005,
668 }, {
669 .subvendor = 0x1b55,
670 .subdevice = 0x2a2c,
671 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
672 }, {
673 .subvendor = 0x0070,
674 .subdevice = 0x2211,
675 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
676 }, {
677 .subvendor = 0x0070,
678 .subdevice = 0x2215,
679 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
680 }, {
681 .subvendor = 0x0070,
682 .subdevice = 0x221d,
683 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
684 }, {
685 .subvendor = 0x0070,
686 .subdevice = 0x2251,
687 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
688 }, {
689 .subvendor = 0x0070,
690 .subdevice = 0x2259,
691 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
692 }, {
693 .subvendor = 0x0070,
694 .subdevice = 0x2291,
695 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
696 }, {
697 .subvendor = 0x0070,
698 .subdevice = 0x2295,
699 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
700 }, {
701 .subvendor = 0x0070,
702 .subdevice = 0x2299,
703 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
704 }, {
705 .subvendor = 0x0070,
706 .subdevice = 0x229d,
707 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
708 }, {
709 .subvendor = 0x0070,
710 .subdevice = 0x22f0,
711 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
712 }, {
713 .subvendor = 0x0070,
714 .subdevice = 0x22f1,
715 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
716 }, {
717 .subvendor = 0x0070,
718 .subdevice = 0x22f2,
719 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
720 }, {
721 .subvendor = 0x0070,
722 .subdevice = 0x22f3,
723 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
724 }, {
725 .subvendor = 0x0070,
726 .subdevice = 0x22f4,
727 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
728 }, {
729 .subvendor = 0x0070,
730 .subdevice = 0x22f5,
731 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
732 }, {
733 .subvendor = 0x14f1,
734 .subdevice = 0x8651,
735 .card = CX23885_BOARD_MYGICA_X8506,
736 }, {
737 .subvendor = 0x14f1,
738 .subdevice = 0x8657,
739 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
740 }, {
741 .subvendor = 0x0070,
742 .subdevice = 0x8541,
743 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
744 }, {
745 .subvendor = 0x1858,
746 .subdevice = 0xe800,
747 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
748 }, {
749 .subvendor = 0x0070,
750 .subdevice = 0x8551,
751 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
752 }, {
753 .subvendor = 0x14f1,
754 .subdevice = 0x8578,
755 .card = CX23885_BOARD_MYGICA_X8558PRO,
756 }, {
757 .subvendor = 0x107d,
758 .subdevice = 0x6f22,
759 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
760 }, {
761 .subvendor = 0x5654,
762 .subdevice = 0x2390,
763 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
764 }, {
765 .subvendor = 0x1b55,
766 .subdevice = 0xe2e4,
767 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
768 }, {
769 .subvendor = 0x14f1,
770 .subdevice = 0x8502,
771 .card = CX23885_BOARD_MYGICA_X8507,
772 }, {
773 .subvendor = 0x153b,
774 .subdevice = 0x117e,
775 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
776 }, {
777 .subvendor = 0xd471,
778 .subdevice = 0x9022,
779 .card = CX23885_BOARD_TEVII_S471,
780 },
781 };
782 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
783
784 void cx23885_card_list(struct cx23885_dev *dev)
785 {
786 int i;
787
788 if (0 == dev->pci->subsystem_vendor &&
789 0 == dev->pci->subsystem_device) {
790 printk(KERN_INFO
791 "%s: Board has no valid PCIe Subsystem ID and can't\n"
792 "%s: be autodetected. Pass card=<n> insmod option\n"
793 "%s: to workaround that. Redirect complaints to the\n"
794 "%s: vendor of the TV card. Best regards,\n"
795 "%s: -- tux\n",
796 dev->name, dev->name, dev->name, dev->name, dev->name);
797 } else {
798 printk(KERN_INFO
799 "%s: Your board isn't known (yet) to the driver.\n"
800 "%s: Try to pick one of the existing card configs via\n"
801 "%s: card=<n> insmod option. Updating to the latest\n"
802 "%s: version might help as well.\n",
803 dev->name, dev->name, dev->name, dev->name);
804 }
805 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
806 dev->name);
807 for (i = 0; i < cx23885_bcount; i++)
808 printk(KERN_INFO "%s: card=%d -> %s\n",
809 dev->name, i, cx23885_boards[i].name);
810 }
811
812 static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
813 {
814 struct tveeprom tv;
815
816 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
817 eeprom_data);
818
819 /* Make sure we support the board model */
820 switch (tv.model) {
821 case 22001:
822 /* WinTV-HVR1270 (PCIe, Retail, half height)
823 * ATSC/QAM and basic analog, IR Blast */
824 case 22009:
825 /* WinTV-HVR1210 (PCIe, Retail, half height)
826 * DVB-T and basic analog, IR Blast */
827 case 22011:
828 /* WinTV-HVR1270 (PCIe, Retail, half height)
829 * ATSC/QAM and basic analog, IR Recv */
830 case 22019:
831 /* WinTV-HVR1210 (PCIe, Retail, half height)
832 * DVB-T and basic analog, IR Recv */
833 case 22021:
834 /* WinTV-HVR1275 (PCIe, Retail, half height)
835 * ATSC/QAM and basic analog, IR Recv */
836 case 22029:
837 /* WinTV-HVR1210 (PCIe, Retail, half height)
838 * DVB-T and basic analog, IR Recv */
839 case 22101:
840 /* WinTV-HVR1270 (PCIe, Retail, full height)
841 * ATSC/QAM and basic analog, IR Blast */
842 case 22109:
843 /* WinTV-HVR1210 (PCIe, Retail, full height)
844 * DVB-T and basic analog, IR Blast */
845 case 22111:
846 /* WinTV-HVR1270 (PCIe, Retail, full height)
847 * ATSC/QAM and basic analog, IR Recv */
848 case 22119:
849 /* WinTV-HVR1210 (PCIe, Retail, full height)
850 * DVB-T and basic analog, IR Recv */
851 case 22121:
852 /* WinTV-HVR1275 (PCIe, Retail, full height)
853 * ATSC/QAM and basic analog, IR Recv */
854 case 22129:
855 /* WinTV-HVR1210 (PCIe, Retail, full height)
856 * DVB-T and basic analog, IR Recv */
857 case 71009:
858 /* WinTV-HVR1200 (PCIe, Retail, full height)
859 * DVB-T and basic analog */
860 case 71359:
861 /* WinTV-HVR1200 (PCIe, OEM, half height)
862 * DVB-T and basic analog */
863 case 71439:
864 /* WinTV-HVR1200 (PCIe, OEM, half height)
865 * DVB-T and basic analog */
866 case 71449:
867 /* WinTV-HVR1200 (PCIe, OEM, full height)
868 * DVB-T and basic analog */
869 case 71939:
870 /* WinTV-HVR1200 (PCIe, OEM, half height)
871 * DVB-T and basic analog */
872 case 71949:
873 /* WinTV-HVR1200 (PCIe, OEM, full height)
874 * DVB-T and basic analog */
875 case 71959:
876 /* WinTV-HVR1200 (PCIe, OEM, full height)
877 * DVB-T and basic analog */
878 case 71979:
879 /* WinTV-HVR1200 (PCIe, OEM, half height)
880 * DVB-T and basic analog */
881 case 71999:
882 /* WinTV-HVR1200 (PCIe, OEM, full height)
883 * DVB-T and basic analog */
884 case 76601:
885 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
886 channel ATSC and MPEG2 HW Encoder */
887 case 77001:
888 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
889 and Basic analog */
890 case 77011:
891 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
892 and Basic analog */
893 case 77041:
894 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
895 and Basic analog */
896 case 77051:
897 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
898 and Basic analog */
899 case 78011:
900 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
901 Dual channel ATSC and MPEG2 HW Encoder */
902 case 78501:
903 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
904 Dual channel ATSC and MPEG2 HW Encoder */
905 case 78521:
906 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
907 Dual channel ATSC and MPEG2 HW Encoder */
908 case 78531:
909 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
910 Dual channel ATSC and MPEG2 HW Encoder */
911 case 78631:
912 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
913 Dual channel ATSC and MPEG2 HW Encoder */
914 case 79001:
915 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
916 ATSC and Basic analog */
917 case 79101:
918 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
919 ATSC and Basic analog */
920 case 79501:
921 /* WinTV-HVR1250 (PCIe, No IR, half height,
922 ATSC [at least] and Basic analog) */
923 case 79561:
924 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
925 ATSC and Basic analog */
926 case 79571:
927 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
928 ATSC and Basic analog */
929 case 79671:
930 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
931 ATSC and Basic analog */
932 case 80019:
933 /* WinTV-HVR1400 (Express Card, Retail, IR,
934 * DVB-T and Basic analog */
935 case 81509:
936 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
937 * DVB-T and MPEG2 HW Encoder */
938 case 81519:
939 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
940 * DVB-T and MPEG2 HW Encoder */
941 break;
942 case 85021:
943 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
944 Dual channel ATSC and MPEG2 HW Encoder */
945 break;
946 case 85721:
947 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
948 Dual channel ATSC and Basic analog */
949 break;
950 default:
951 printk(KERN_WARNING "%s: warning: "
952 "unknown hauppauge model #%d\n",
953 dev->name, tv.model);
954 break;
955 }
956
957 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
958 dev->name, tv.model);
959 }
960
961 int cx23885_tuner_callback(void *priv, int component, int command, int arg)
962 {
963 struct cx23885_tsport *port = priv;
964 struct cx23885_dev *dev = port->dev;
965 u32 bitmask = 0;
966
967 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
968 return 0;
969
970 if (command != 0) {
971 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
972 __func__, command);
973 return -EINVAL;
974 }
975
976 switch (dev->board) {
977 case CX23885_BOARD_HAUPPAUGE_HVR1400:
978 case CX23885_BOARD_HAUPPAUGE_HVR1500:
979 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
980 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
981 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
982 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
983 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
984 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
985 /* Tuner Reset Command */
986 bitmask = 0x04;
987 break;
988 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
989 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
990 /* Two identical tuners on two different i2c buses,
991 * we need to reset the correct gpio. */
992 if (port->nr == 1)
993 bitmask = 0x01;
994 else if (port->nr == 2)
995 bitmask = 0x04;
996 break;
997 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
998 /* Tuner Reset Command */
999 bitmask = 0x02;
1000 break;
1001 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1002 altera_ci_tuner_reset(dev, port->nr);
1003 break;
1004 }
1005
1006 if (bitmask) {
1007 /* Drive the tuner into reset and back out */
1008 cx_clear(GP0_IO, bitmask);
1009 mdelay(200);
1010 cx_set(GP0_IO, bitmask);
1011 }
1012
1013 return 0;
1014 }
1015
1016 void cx23885_gpio_setup(struct cx23885_dev *dev)
1017 {
1018 switch (dev->board) {
1019 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1020 /* GPIO-0 cx24227 demodulator reset */
1021 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1022 break;
1023 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1024 /* GPIO-0 cx24227 demodulator */
1025 /* GPIO-2 xc3028 tuner */
1026
1027 /* Put the parts into reset */
1028 cx_set(GP0_IO, 0x00050000);
1029 cx_clear(GP0_IO, 0x00000005);
1030 msleep(5);
1031
1032 /* Bring the parts out of reset */
1033 cx_set(GP0_IO, 0x00050005);
1034 break;
1035 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1036 /* GPIO-0 cx24227 demodulator reset */
1037 /* GPIO-2 xc5000 tuner reset */
1038 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
1039 break;
1040 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1041 /* GPIO-0 656_CLK */
1042 /* GPIO-1 656_D0 */
1043 /* GPIO-2 8295A Reset */
1044 /* GPIO-3-10 cx23417 data0-7 */
1045 /* GPIO-11-14 cx23417 addr0-3 */
1046 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1047 /* GPIO-19 IR_RX */
1048
1049 /* CX23417 GPIO's */
1050 /* EIO15 Zilog Reset */
1051 /* EIO14 S5H1409/CX24227 Reset */
1052 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
1053
1054 /* Put the demod into reset and protect the eeprom */
1055 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
1056 mdelay(100);
1057
1058 /* Bring the demod and blaster out of reset */
1059 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
1060 mdelay(100);
1061
1062 /* Force the TDA8295A into reset and back */
1063 cx23885_gpio_enable(dev, GPIO_2, 1);
1064 cx23885_gpio_set(dev, GPIO_2);
1065 mdelay(20);
1066 cx23885_gpio_clear(dev, GPIO_2);
1067 mdelay(20);
1068 cx23885_gpio_set(dev, GPIO_2);
1069 mdelay(20);
1070 break;
1071 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1072 /* GPIO-0 tda10048 demodulator reset */
1073 /* GPIO-2 tda18271 tuner reset */
1074
1075 /* Put the parts into reset and back */
1076 cx_set(GP0_IO, 0x00050000);
1077 mdelay(20);
1078 cx_clear(GP0_IO, 0x00000005);
1079 mdelay(20);
1080 cx_set(GP0_IO, 0x00050005);
1081 break;
1082 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1083 /* GPIO-0 TDA10048 demodulator reset */
1084 /* GPIO-2 TDA8295A Reset */
1085 /* GPIO-3-10 cx23417 data0-7 */
1086 /* GPIO-11-14 cx23417 addr0-3 */
1087 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1088
1089 /* The following GPIO's are on the interna AVCore (cx25840) */
1090 /* GPIO-19 IR_RX */
1091 /* GPIO-20 IR_TX 416/DVBT Select */
1092 /* GPIO-21 IIS DAT */
1093 /* GPIO-22 IIS WCLK */
1094 /* GPIO-23 IIS BCLK */
1095
1096 /* Put the parts into reset and back */
1097 cx_set(GP0_IO, 0x00050000);
1098 mdelay(20);
1099 cx_clear(GP0_IO, 0x00000005);
1100 mdelay(20);
1101 cx_set(GP0_IO, 0x00050005);
1102 break;
1103 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1104 /* GPIO-0 Dibcom7000p demodulator reset */
1105 /* GPIO-2 xc3028L tuner reset */
1106 /* GPIO-13 LED */
1107
1108 /* Put the parts into reset and back */
1109 cx_set(GP0_IO, 0x00050000);
1110 mdelay(20);
1111 cx_clear(GP0_IO, 0x00000005);
1112 mdelay(20);
1113 cx_set(GP0_IO, 0x00050005);
1114 break;
1115 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1116 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
1117 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
1118 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
1119 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
1120
1121 /* Put the parts into reset and back */
1122 cx_set(GP0_IO, 0x000f0000);
1123 mdelay(20);
1124 cx_clear(GP0_IO, 0x0000000f);
1125 mdelay(20);
1126 cx_set(GP0_IO, 0x000f000f);
1127 break;
1128 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1129 /* GPIO-0 portb xc3028 reset */
1130 /* GPIO-1 portb zl10353 reset */
1131 /* GPIO-2 portc xc3028 reset */
1132 /* GPIO-3 portc zl10353 reset */
1133
1134 /* Put the parts into reset and back */
1135 cx_set(GP0_IO, 0x000f0000);
1136 mdelay(20);
1137 cx_clear(GP0_IO, 0x0000000f);
1138 mdelay(20);
1139 cx_set(GP0_IO, 0x000f000f);
1140 break;
1141 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1142 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1143 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1144 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1145 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1146 /* GPIO-2 xc3028 tuner reset */
1147
1148 /* The following GPIO's are on the internal AVCore (cx25840) */
1149 /* GPIO-? zl10353 demod reset */
1150
1151 /* Put the parts into reset and back */
1152 cx_set(GP0_IO, 0x00040000);
1153 mdelay(20);
1154 cx_clear(GP0_IO, 0x00000004);
1155 mdelay(20);
1156 cx_set(GP0_IO, 0x00040004);
1157 break;
1158 case CX23885_BOARD_TBS_6920:
1159 cx_write(MC417_CTL, 0x00000036);
1160 cx_write(MC417_OEN, 0x00001000);
1161 cx_set(MC417_RWD, 0x00000002);
1162 mdelay(200);
1163 cx_clear(MC417_RWD, 0x00000800);
1164 mdelay(200);
1165 cx_set(MC417_RWD, 0x00000800);
1166 mdelay(200);
1167 break;
1168 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1169 /* GPIO-0 INTA from CiMax1
1170 GPIO-1 INTB from CiMax2
1171 GPIO-2 reset chips
1172 GPIO-3 to GPIO-10 data/addr for CA
1173 GPIO-11 ~CS0 to CiMax1
1174 GPIO-12 ~CS1 to CiMax2
1175 GPIO-13 ADL0 load LSB addr
1176 GPIO-14 ADL1 load MSB addr
1177 GPIO-15 ~RDY from CiMax
1178 GPIO-17 ~RD to CiMax
1179 GPIO-18 ~WR to CiMax
1180 */
1181 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
1182 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
1183 cx_clear(GP0_IO, 0x00030004);
1184 mdelay(100);/* reset delay */
1185 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
1186 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
1187 /* GPIO-15 IN as ~ACK, rest as OUT */
1188 cx_write(MC417_OEN, 0x00001000);
1189 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1190 cx_write(MC417_RWD, 0x0000c300);
1191 /* enable irq */
1192 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1193 break;
1194 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1195 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1196 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1197 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1198 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1199 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
1200 /* GPIO-6 I2C Gate which can isolate the demod from the bus */
1201 /* GPIO-9 Demod reset */
1202
1203 /* Put the parts into reset and back */
1204 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
1205 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
1206 cx23885_gpio_clear(dev, GPIO_9);
1207 mdelay(20);
1208 cx23885_gpio_set(dev, GPIO_9);
1209 break;
1210 case CX23885_BOARD_MYGICA_X8506:
1211 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1212 case CX23885_BOARD_MYGICA_X8507:
1213 /* GPIO-0 (0)Analog / (1)Digital TV */
1214 /* GPIO-1 reset XC5000 */
1215 /* GPIO-2 reset LGS8GL5 / LGS8G75 */
1216 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
1217 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
1218 mdelay(100);
1219 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
1220 mdelay(100);
1221 break;
1222 case CX23885_BOARD_MYGICA_X8558PRO:
1223 /* GPIO-0 reset first ATBM8830 */
1224 /* GPIO-1 reset second ATBM8830 */
1225 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
1226 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
1227 mdelay(100);
1228 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
1229 mdelay(100);
1230 break;
1231 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1232 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1233 /* GPIO-0 656_CLK */
1234 /* GPIO-1 656_D0 */
1235 /* GPIO-2 Wake# */
1236 /* GPIO-3-10 cx23417 data0-7 */
1237 /* GPIO-11-14 cx23417 addr0-3 */
1238 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1239 /* GPIO-19 IR_RX */
1240 /* GPIO-20 C_IR_TX */
1241 /* GPIO-21 I2S DAT */
1242 /* GPIO-22 I2S WCLK */
1243 /* GPIO-23 I2S BCLK */
1244 /* ALT GPIO: EXP GPIO LATCH */
1245
1246 /* CX23417 GPIO's */
1247 /* GPIO-14 S5H1411/CX24228 Reset */
1248 /* GPIO-13 EEPROM write protect */
1249 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
1250
1251 /* Put the demod into reset and protect the eeprom */
1252 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
1253 mdelay(100);
1254
1255 /* Bring the demod out of reset */
1256 mc417_gpio_set(dev, GPIO_14);
1257 mdelay(100);
1258
1259 /* CX24228 GPIO */
1260 /* Connected to IF / Mux */
1261 break;
1262 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1263 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1264 break;
1265 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1266 /* GPIO-0 ~INT in
1267 GPIO-1 TMS out
1268 GPIO-2 ~reset chips out
1269 GPIO-3 to GPIO-10 data/addr for CA in/out
1270 GPIO-11 ~CS out
1271 GPIO-12 ADDR out
1272 GPIO-13 ~WR out
1273 GPIO-14 ~RD out
1274 GPIO-15 ~RDY in
1275 GPIO-16 TCK out
1276 GPIO-17 TDO in
1277 GPIO-18 TDI out
1278 */
1279 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
1280 /* GPIO-0 as INT, reset & TMS low */
1281 cx_clear(GP0_IO, 0x00010006);
1282 mdelay(100);/* reset delay */
1283 cx_set(GP0_IO, 0x00000004); /* reset high */
1284 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
1285 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
1286 cx_write(MC417_OEN, 0x00005000);
1287 /* ~RD, ~WR high; ADDR low; ~CS high */
1288 cx_write(MC417_RWD, 0x00000d00);
1289 /* enable irq */
1290 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1291 break;
1292 }
1293 }
1294
1295 int cx23885_ir_init(struct cx23885_dev *dev)
1296 {
1297 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
1298 {
1299 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1300 .pin = CX23885_PIN_IR_RX_GPIO19,
1301 .function = CX23885_PAD_IR_RX,
1302 .value = 0,
1303 .strength = CX25840_PIN_DRIVE_MEDIUM,
1304 }, {
1305 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
1306 .pin = CX23885_PIN_IR_TX_GPIO20,
1307 .function = CX23885_PAD_IR_TX,
1308 .value = 0,
1309 .strength = CX25840_PIN_DRIVE_MEDIUM,
1310 }
1311 };
1312 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1313
1314 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1315 {
1316 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1317 .pin = CX23885_PIN_IR_RX_GPIO19,
1318 .function = CX23885_PAD_IR_RX,
1319 .value = 0,
1320 .strength = CX25840_PIN_DRIVE_MEDIUM,
1321 }
1322 };
1323 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
1324
1325 struct v4l2_subdev_ir_parameters params;
1326 int ret = 0;
1327 switch (dev->board) {
1328 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1329 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1330 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1331 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1332 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1333 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1334 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1335 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1336 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1337 /* FIXME: Implement me */
1338 break;
1339 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1340 ret = cx23888_ir_probe(dev);
1341 if (ret)
1342 break;
1343 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1344 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1345 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1346 break;
1347 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1348 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1349 ret = cx23888_ir_probe(dev);
1350 if (ret)
1351 break;
1352 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1353 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1354 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1355 /*
1356 * For these boards we need to invert the Tx output via the
1357 * IR controller to have the LED off while idle
1358 */
1359 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
1360 params.enable = false;
1361 params.shutdown = false;
1362 params.invert_level = true;
1363 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1364 params.shutdown = true;
1365 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1366 break;
1367 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1368 case CX23885_BOARD_TEVII_S470:
1369 if (!enable_885_ir)
1370 break;
1371 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1372 if (dev->sd_ir == NULL) {
1373 ret = -ENODEV;
1374 break;
1375 }
1376 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1377 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1378 break;
1379 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1380 if (!enable_885_ir)
1381 break;
1382 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1383 if (dev->sd_ir == NULL) {
1384 ret = -ENODEV;
1385 break;
1386 }
1387 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1388 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
1389 break;
1390 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1391 request_module("ir-kbd-i2c");
1392 break;
1393 }
1394
1395 return ret;
1396 }
1397
1398 void cx23885_ir_fini(struct cx23885_dev *dev)
1399 {
1400 switch (dev->board) {
1401 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1402 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1403 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1404 cx23885_irq_remove(dev, PCI_MSK_IR);
1405 cx23888_ir_remove(dev);
1406 dev->sd_ir = NULL;
1407 break;
1408 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1409 case CX23885_BOARD_TEVII_S470:
1410 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1411 cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
1412 /* sd_ir is a duplicate pointer to the AV Core, just clear it */
1413 dev->sd_ir = NULL;
1414 break;
1415 }
1416 }
1417
1418 int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
1419 {
1420 int data;
1421 int tdo = 0;
1422 struct cx23885_dev *dev = (struct cx23885_dev *)device;
1423 /*TMS*/
1424 data = ((cx_read(GP0_IO)) & (~0x00000002));
1425 data |= (tms ? 0x00020002 : 0x00020000);
1426 cx_write(GP0_IO, data);
1427
1428 /*TDI*/
1429 data = ((cx_read(MC417_RWD)) & (~0x0000a000));
1430 data |= (tdi ? 0x00008000 : 0);
1431 cx_write(MC417_RWD, data);
1432 if (read_tdo)
1433 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
1434
1435 cx_write(MC417_RWD, data | 0x00002000);
1436 udelay(1);
1437 /*TCK*/
1438 cx_write(MC417_RWD, data);
1439
1440 return tdo;
1441 }
1442
1443 void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1444 {
1445 switch (dev->board) {
1446 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1447 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1448 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1449 if (dev->sd_ir)
1450 cx23885_irq_add_enable(dev, PCI_MSK_IR);
1451 break;
1452 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1453 case CX23885_BOARD_TEVII_S470:
1454 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1455 if (dev->sd_ir)
1456 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
1457 break;
1458 }
1459 }
1460
1461 void cx23885_card_setup(struct cx23885_dev *dev)
1462 {
1463 struct cx23885_tsport *ts1 = &dev->ts1;
1464 struct cx23885_tsport *ts2 = &dev->ts2;
1465
1466 static u8 eeprom[256];
1467
1468 if (dev->i2c_bus[0].i2c_rc == 0) {
1469 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1470 tveeprom_read(&dev->i2c_bus[0].i2c_client,
1471 eeprom, sizeof(eeprom));
1472 }
1473
1474 switch (dev->board) {
1475 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1476 if (dev->i2c_bus[0].i2c_rc == 0) {
1477 if (eeprom[0x80] != 0x84)
1478 hauppauge_eeprom(dev, eeprom+0xc0);
1479 else
1480 hauppauge_eeprom(dev, eeprom+0x80);
1481 }
1482 break;
1483 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1484 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1485 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1486 if (dev->i2c_bus[0].i2c_rc == 0)
1487 hauppauge_eeprom(dev, eeprom+0x80);
1488 break;
1489 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1490 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1491 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1492 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1493 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1494 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1495 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1496 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1497 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1498 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1499 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1500 if (dev->i2c_bus[0].i2c_rc == 0)
1501 hauppauge_eeprom(dev, eeprom+0xc0);
1502 break;
1503 }
1504
1505 switch (dev->board) {
1506 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1507 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1508 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1509 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1510 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1511 /* break omitted intentionally */
1512 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
1513 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1514 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1515 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1516 break;
1517 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1518 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1519 /* Defaults for VID B - Analog encoder */
1520 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1521 ts1->gen_ctrl_val = 0x10e;
1522 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1523 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1524
1525 /* APB_TSVALERR_POL (active low)*/
1526 ts1->vld_misc_val = 0x2000;
1527 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
1528 cx_write(0x130184, 0xc);
1529
1530 /* Defaults for VID C */
1531 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1532 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1533 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1534 break;
1535 case CX23885_BOARD_TBS_6920:
1536 ts1->gen_ctrl_val = 0x4; /* Parallel */
1537 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1538 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1539 break;
1540 case CX23885_BOARD_TEVII_S470:
1541 case CX23885_BOARD_TEVII_S471:
1542 case CX23885_BOARD_DVBWORLD_2005:
1543 ts1->gen_ctrl_val = 0x5; /* Parallel */
1544 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1545 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1546 break;
1547 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1548 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1549 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1550 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1551 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1552 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1553 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1554 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1555 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1556 break;
1557 case CX23885_BOARD_MYGICA_X8506:
1558 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1559 ts1->gen_ctrl_val = 0x5; /* Parallel */
1560 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1561 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1562 break;
1563 case CX23885_BOARD_MYGICA_X8558PRO:
1564 ts1->gen_ctrl_val = 0x5; /* Parallel */
1565 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1566 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1567 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1568 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1569 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1570 break;
1571 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1572 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1573 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1574 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1575 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1576 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1577 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1578 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1579 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1580 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1581 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1582 case CX23885_BOARD_HAUPPAUGE_HVR1275:
1583 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1584 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1585 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1586 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1587 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1588 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1589 default:
1590 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1591 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1592 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1593 }
1594
1595 /* Certain boards support analog, or require the avcore to be
1596 * loaded, ensure this happens.
1597 */
1598 switch (dev->board) {
1599 case CX23885_BOARD_TEVII_S470:
1600 /* Currently only enabled for the integrated IR controller */
1601 if (!enable_885_ir)
1602 break;
1603 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1604 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1605 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1606 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1607 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
1608 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1609 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
1610 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1611 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1612 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
1613 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1614 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
1615 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1616 case CX23885_BOARD_HAUPPAUGE_HVR1850:
1617 case CX23885_BOARD_MYGICA_X8506:
1618 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1619 case CX23885_BOARD_HAUPPAUGE_HVR1290:
1620 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
1621 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1622 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1623 case CX23885_BOARD_MPX885:
1624 case CX23885_BOARD_MYGICA_X8507:
1625 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1626 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
1627 &dev->i2c_bus[2].i2c_adap,
1628 "cx25840", 0x88 >> 1, NULL);
1629 if (dev->sd_cx25840) {
1630 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
1631 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
1632 }
1633 break;
1634 }
1635
1636 /* AUX-PLL 27MHz CLK */
1637 switch (dev->board) {
1638 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1639 netup_initialize(dev);
1640 break;
1641 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1642 int ret;
1643 const struct firmware *fw;
1644 const char *filename = "dvb-netup-altera-01.fw";
1645 char *action = "configure";
1646 static struct netup_card_info cinfo;
1647 struct altera_config netup_config = {
1648 .dev = dev,
1649 .action = action,
1650 .jtag_io = netup_jtag_io,
1651 };
1652
1653 netup_initialize(dev);
1654
1655 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1656 if (netup_card_rev)
1657 cinfo.rev = netup_card_rev;
1658
1659 switch (cinfo.rev) {
1660 case 0x4:
1661 filename = "dvb-netup-altera-04.fw";
1662 break;
1663 default:
1664 filename = "dvb-netup-altera-01.fw";
1665 break;
1666 }
1667 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
1668 cinfo.rev, filename);
1669
1670 ret = request_firmware(&fw, filename, &dev->pci->dev);
1671 if (ret != 0)
1672 printk(KERN_ERR "did not find the firmware file. (%s) "
1673 "Please see linux/Documentation/dvb/ for more details "
1674 "on firmware-problems.", filename);
1675 else
1676 altera_init(&netup_config, fw);
1677
1678 release_firmware(fw);
1679 break;
1680 }
1681 }
1682 }
1683
1684 /* ------------------------------------------------------------------ */
Linux kernel - Deliverables
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