2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
6 * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include <linux/i2c.h>
27 #include <linux/slab.h>
29 #include "cx25821-sram.h"
30 #include "cx25821-video.h"
32 MODULE_DESCRIPTION("Driver for Athena cards");
33 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
34 MODULE_LICENSE("GPL");
36 static unsigned int debug
;
37 module_param(debug
, int, 0644);
38 MODULE_PARM_DESC(debug
, "enable debug messages");
40 static unsigned int card
[] = {[0 ... (CX25821_MAXBOARDS
- 1)] = UNSET
};
41 module_param_array(card
, int, NULL
, 0444);
42 MODULE_PARM_DESC(card
, "card type");
44 static unsigned int cx25821_devcount
;
46 DEFINE_MUTEX(cx25821_devlist_mutex
);
47 EXPORT_SYMBOL(cx25821_devlist_mutex
);
48 LIST_HEAD(cx25821_devlist
);
49 EXPORT_SYMBOL(cx25821_devlist
);
51 struct sram_channel cx25821_sram_channels
[] = {
55 .cmds_start
= VID_A_DOWN_CMDS
,
56 .ctrl_start
= VID_A_IQ
,
58 .fifo_start
= VID_A_DOWN_CLUSTER_1
,
59 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
60 .ptr1_reg
= DMA1_PTR1
,
61 .ptr2_reg
= DMA1_PTR2
,
62 .cnt1_reg
= DMA1_CNT1
,
63 .cnt2_reg
= DMA1_CNT2
,
64 .int_msk
= VID_A_INT_MSK
,
65 .int_stat
= VID_A_INT_STAT
,
66 .int_mstat
= VID_A_INT_MSTAT
,
67 .dma_ctl
= VID_DST_A_DMA_CTL
,
68 .gpcnt_ctl
= VID_DST_A_GPCNT_CTL
,
69 .gpcnt
= VID_DST_A_GPCNT
,
70 .vip_ctl
= VID_DST_A_VIP_CTL
,
71 .pix_frmt
= VID_DST_A_PIX_FRMT
,
77 .cmds_start
= VID_B_DOWN_CMDS
,
78 .ctrl_start
= VID_B_IQ
,
80 .fifo_start
= VID_B_DOWN_CLUSTER_1
,
81 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
82 .ptr1_reg
= DMA2_PTR1
,
83 .ptr2_reg
= DMA2_PTR2
,
84 .cnt1_reg
= DMA2_CNT1
,
85 .cnt2_reg
= DMA2_CNT2
,
86 .int_msk
= VID_B_INT_MSK
,
87 .int_stat
= VID_B_INT_STAT
,
88 .int_mstat
= VID_B_INT_MSTAT
,
89 .dma_ctl
= VID_DST_B_DMA_CTL
,
90 .gpcnt_ctl
= VID_DST_B_GPCNT_CTL
,
91 .gpcnt
= VID_DST_B_GPCNT
,
92 .vip_ctl
= VID_DST_B_VIP_CTL
,
93 .pix_frmt
= VID_DST_B_PIX_FRMT
,
99 .cmds_start
= VID_C_DOWN_CMDS
,
100 .ctrl_start
= VID_C_IQ
,
102 .fifo_start
= VID_C_DOWN_CLUSTER_1
,
103 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
104 .ptr1_reg
= DMA3_PTR1
,
105 .ptr2_reg
= DMA3_PTR2
,
106 .cnt1_reg
= DMA3_CNT1
,
107 .cnt2_reg
= DMA3_CNT2
,
108 .int_msk
= VID_C_INT_MSK
,
109 .int_stat
= VID_C_INT_STAT
,
110 .int_mstat
= VID_C_INT_MSTAT
,
111 .dma_ctl
= VID_DST_C_DMA_CTL
,
112 .gpcnt_ctl
= VID_DST_C_GPCNT_CTL
,
113 .gpcnt
= VID_DST_C_GPCNT
,
114 .vip_ctl
= VID_DST_C_VIP_CTL
,
115 .pix_frmt
= VID_DST_C_PIX_FRMT
,
121 .cmds_start
= VID_D_DOWN_CMDS
,
122 .ctrl_start
= VID_D_IQ
,
124 .fifo_start
= VID_D_DOWN_CLUSTER_1
,
125 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
126 .ptr1_reg
= DMA4_PTR1
,
127 .ptr2_reg
= DMA4_PTR2
,
128 .cnt1_reg
= DMA4_CNT1
,
129 .cnt2_reg
= DMA4_CNT2
,
130 .int_msk
= VID_D_INT_MSK
,
131 .int_stat
= VID_D_INT_STAT
,
132 .int_mstat
= VID_D_INT_MSTAT
,
133 .dma_ctl
= VID_DST_D_DMA_CTL
,
134 .gpcnt_ctl
= VID_DST_D_GPCNT_CTL
,
135 .gpcnt
= VID_DST_D_GPCNT
,
136 .vip_ctl
= VID_DST_D_VIP_CTL
,
137 .pix_frmt
= VID_DST_D_PIX_FRMT
,
143 .cmds_start
= VID_E_DOWN_CMDS
,
144 .ctrl_start
= VID_E_IQ
,
146 .fifo_start
= VID_E_DOWN_CLUSTER_1
,
147 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
148 .ptr1_reg
= DMA5_PTR1
,
149 .ptr2_reg
= DMA5_PTR2
,
150 .cnt1_reg
= DMA5_CNT1
,
151 .cnt2_reg
= DMA5_CNT2
,
152 .int_msk
= VID_E_INT_MSK
,
153 .int_stat
= VID_E_INT_STAT
,
154 .int_mstat
= VID_E_INT_MSTAT
,
155 .dma_ctl
= VID_DST_E_DMA_CTL
,
156 .gpcnt_ctl
= VID_DST_E_GPCNT_CTL
,
157 .gpcnt
= VID_DST_E_GPCNT
,
158 .vip_ctl
= VID_DST_E_VIP_CTL
,
159 .pix_frmt
= VID_DST_E_PIX_FRMT
,
165 .cmds_start
= VID_F_DOWN_CMDS
,
166 .ctrl_start
= VID_F_IQ
,
168 .fifo_start
= VID_F_DOWN_CLUSTER_1
,
169 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
170 .ptr1_reg
= DMA6_PTR1
,
171 .ptr2_reg
= DMA6_PTR2
,
172 .cnt1_reg
= DMA6_CNT1
,
173 .cnt2_reg
= DMA6_CNT2
,
174 .int_msk
= VID_F_INT_MSK
,
175 .int_stat
= VID_F_INT_STAT
,
176 .int_mstat
= VID_F_INT_MSTAT
,
177 .dma_ctl
= VID_DST_F_DMA_CTL
,
178 .gpcnt_ctl
= VID_DST_F_GPCNT_CTL
,
179 .gpcnt
= VID_DST_F_GPCNT
,
180 .vip_ctl
= VID_DST_F_VIP_CTL
,
181 .pix_frmt
= VID_DST_F_PIX_FRMT
,
187 .cmds_start
= VID_G_DOWN_CMDS
,
188 .ctrl_start
= VID_G_IQ
,
190 .fifo_start
= VID_G_DOWN_CLUSTER_1
,
191 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
192 .ptr1_reg
= DMA7_PTR1
,
193 .ptr2_reg
= DMA7_PTR2
,
194 .cnt1_reg
= DMA7_CNT1
,
195 .cnt2_reg
= DMA7_CNT2
,
196 .int_msk
= VID_G_INT_MSK
,
197 .int_stat
= VID_G_INT_STAT
,
198 .int_mstat
= VID_G_INT_MSTAT
,
199 .dma_ctl
= VID_DST_G_DMA_CTL
,
200 .gpcnt_ctl
= VID_DST_G_GPCNT_CTL
,
201 .gpcnt
= VID_DST_G_GPCNT
,
202 .vip_ctl
= VID_DST_G_VIP_CTL
,
203 .pix_frmt
= VID_DST_G_PIX_FRMT
,
209 .cmds_start
= VID_H_DOWN_CMDS
,
210 .ctrl_start
= VID_H_IQ
,
212 .fifo_start
= VID_H_DOWN_CLUSTER_1
,
213 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
214 .ptr1_reg
= DMA8_PTR1
,
215 .ptr2_reg
= DMA8_PTR2
,
216 .cnt1_reg
= DMA8_CNT1
,
217 .cnt2_reg
= DMA8_CNT2
,
218 .int_msk
= VID_H_INT_MSK
,
219 .int_stat
= VID_H_INT_STAT
,
220 .int_mstat
= VID_H_INT_MSTAT
,
221 .dma_ctl
= VID_DST_H_DMA_CTL
,
222 .gpcnt_ctl
= VID_DST_H_GPCNT_CTL
,
223 .gpcnt
= VID_DST_H_GPCNT
,
224 .vip_ctl
= VID_DST_H_VIP_CTL
,
225 .pix_frmt
= VID_DST_H_PIX_FRMT
,
229 .name
= "audio from",
230 .cmds_start
= AUD_A_DOWN_CMDS
,
231 .ctrl_start
= AUD_A_IQ
,
233 .fifo_start
= AUD_A_DOWN_CLUSTER_1
,
234 .fifo_size
= AUDIO_CLUSTER_SIZE
* 3,
235 .ptr1_reg
= DMA17_PTR1
,
236 .ptr2_reg
= DMA17_PTR2
,
237 .cnt1_reg
= DMA17_CNT1
,
238 .cnt2_reg
= DMA17_CNT2
,
243 .name
= "VID Upstream I",
244 .cmds_start
= VID_I_UP_CMDS
,
245 .ctrl_start
= VID_I_IQ
,
247 .fifo_start
= VID_I_UP_CLUSTER_1
,
248 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
249 .ptr1_reg
= DMA15_PTR1
,
250 .ptr2_reg
= DMA15_PTR2
,
251 .cnt1_reg
= DMA15_CNT1
,
252 .cnt2_reg
= DMA15_CNT2
,
253 .int_msk
= VID_I_INT_MSK
,
254 .int_stat
= VID_I_INT_STAT
,
255 .int_mstat
= VID_I_INT_MSTAT
,
256 .dma_ctl
= VID_SRC_I_DMA_CTL
,
257 .gpcnt_ctl
= VID_SRC_I_GPCNT_CTL
,
258 .gpcnt
= VID_SRC_I_GPCNT
,
260 .vid_fmt_ctl
= VID_SRC_I_FMT_CTL
,
261 .vid_active_ctl1
= VID_SRC_I_ACTIVE_CTL1
,
262 .vid_active_ctl2
= VID_SRC_I_ACTIVE_CTL2
,
263 .vid_cdt_size
= VID_SRC_I_CDT_SZ
,
269 .name
= "VID Upstream J",
270 .cmds_start
= VID_J_UP_CMDS
,
271 .ctrl_start
= VID_J_IQ
,
273 .fifo_start
= VID_J_UP_CLUSTER_1
,
274 .fifo_size
= (VID_CLUSTER_SIZE
<< 2),
275 .ptr1_reg
= DMA16_PTR1
,
276 .ptr2_reg
= DMA16_PTR2
,
277 .cnt1_reg
= DMA16_CNT1
,
278 .cnt2_reg
= DMA16_CNT2
,
279 .int_msk
= VID_J_INT_MSK
,
280 .int_stat
= VID_J_INT_STAT
,
281 .int_mstat
= VID_J_INT_MSTAT
,
282 .dma_ctl
= VID_SRC_J_DMA_CTL
,
283 .gpcnt_ctl
= VID_SRC_J_GPCNT_CTL
,
284 .gpcnt
= VID_SRC_J_GPCNT
,
286 .vid_fmt_ctl
= VID_SRC_J_FMT_CTL
,
287 .vid_active_ctl1
= VID_SRC_J_ACTIVE_CTL1
,
288 .vid_active_ctl2
= VID_SRC_J_ACTIVE_CTL2
,
289 .vid_cdt_size
= VID_SRC_J_CDT_SZ
,
295 .name
= "Audio Upstream Channel B",
296 .cmds_start
= AUD_B_UP_CMDS
,
297 .ctrl_start
= AUD_B_IQ
,
299 .fifo_start
= AUD_B_UP_CLUSTER_1
,
300 .fifo_size
= (AUDIO_CLUSTER_SIZE
* 3),
301 .ptr1_reg
= DMA22_PTR1
,
302 .ptr2_reg
= DMA22_PTR2
,
303 .cnt1_reg
= DMA22_CNT1
,
304 .cnt2_reg
= DMA22_CNT2
,
305 .int_msk
= AUD_B_INT_MSK
,
306 .int_stat
= AUD_B_INT_STAT
,
307 .int_mstat
= AUD_B_INT_MSTAT
,
308 .dma_ctl
= AUD_INT_DMA_CTL
,
309 .gpcnt_ctl
= AUD_B_GPCNT_CTL
,
310 .gpcnt
= AUD_B_GPCNT
,
311 .aud_length
= AUD_B_LNGTH
,
312 .aud_cfg
= AUD_B_CFG
,
313 .fld_aud_fifo_en
= FLD_AUD_SRC_B_FIFO_EN
,
314 .fld_aud_risc_en
= FLD_AUD_SRC_B_RISC_EN
,
318 EXPORT_SYMBOL(cx25821_sram_channels
);
320 struct sram_channel
*channel0
= &cx25821_sram_channels
[SRAM_CH00
];
321 struct sram_channel
*channel1
= &cx25821_sram_channels
[SRAM_CH01
];
322 struct sram_channel
*channel2
= &cx25821_sram_channels
[SRAM_CH02
];
323 struct sram_channel
*channel3
= &cx25821_sram_channels
[SRAM_CH03
];
324 struct sram_channel
*channel4
= &cx25821_sram_channels
[SRAM_CH04
];
325 struct sram_channel
*channel5
= &cx25821_sram_channels
[SRAM_CH05
];
326 struct sram_channel
*channel6
= &cx25821_sram_channels
[SRAM_CH06
];
327 struct sram_channel
*channel7
= &cx25821_sram_channels
[SRAM_CH07
];
328 struct sram_channel
*channel9
= &cx25821_sram_channels
[SRAM_CH09
];
329 struct sram_channel
*channel10
= &cx25821_sram_channels
[SRAM_CH10
];
330 struct sram_channel
*channel11
= &cx25821_sram_channels
[SRAM_CH11
];
332 struct cx25821_dmaqueue mpegq
;
334 static int cx25821_risc_decode(u32 risc
)
336 static const char * const instr
[16] = {
337 [RISC_SYNC
>> 28] = "sync",
338 [RISC_WRITE
>> 28] = "write",
339 [RISC_WRITEC
>> 28] = "writec",
340 [RISC_READ
>> 28] = "read",
341 [RISC_READC
>> 28] = "readc",
342 [RISC_JUMP
>> 28] = "jump",
343 [RISC_SKIP
>> 28] = "skip",
344 [RISC_WRITERM
>> 28] = "writerm",
345 [RISC_WRITECM
>> 28] = "writecm",
346 [RISC_WRITECR
>> 28] = "writecr",
348 static const int incr
[16] = {
349 [RISC_WRITE
>> 28] = 3,
350 [RISC_JUMP
>> 28] = 3,
351 [RISC_SKIP
>> 28] = 1,
352 [RISC_SYNC
>> 28] = 1,
353 [RISC_WRITERM
>> 28] = 3,
354 [RISC_WRITECM
>> 28] = 3,
355 [RISC_WRITECR
>> 28] = 4,
357 static const char * const bits
[] = {
358 "12", "13", "14", "resync",
359 "cnt0", "cnt1", "18", "19",
360 "20", "21", "22", "23",
361 "irq1", "irq2", "eol", "sol",
365 pr_cont("0x%08x [ %s",
366 risc
, instr
[risc
>> 28] ? instr
[risc
>> 28] : "INVALID");
367 for (i
= ARRAY_SIZE(bits
) - 1; i
>= 0; i
--) {
368 if (risc
& (1 << (i
+ 12)))
369 pr_cont(" %s", bits
[i
]);
371 pr_cont(" count=%d ]\n", risc
& 0xfff);
372 return incr
[risc
>> 28] ? incr
[risc
>> 28] : 1;
375 static inline int i2c_slave_did_ack(struct i2c_adapter
*i2c_adap
)
377 struct cx25821_i2c
*bus
= i2c_adap
->algo_data
;
378 struct cx25821_dev
*dev
= bus
->dev
;
379 return cx_read(bus
->reg_stat
) & 0x01;
382 static void cx25821_registers_init(struct cx25821_dev
*dev
)
386 /* enable RUN_RISC in Pecos */
387 cx_write(DEV_CNTRL2
, 0x20);
389 /* Set the master PCI interrupt masks to enable video, audio, MBIF,
390 * and GPIO interrupts
391 * I2C interrupt masking is handled by the I2C objects themselves. */
392 cx_write(PCI_INT_MSK
, 0x2001FFFF);
394 tmp
= cx_read(RDR_TLCTL0
);
395 tmp
&= ~FLD_CFG_RCB_CK_EN
; /* Clear the RCB_CK_EN bit */
396 cx_write(RDR_TLCTL0
, tmp
);
398 /* PLL-A setting for the Audio Master Clock */
399 cx_write(PLL_A_INT_FRAC
, 0x9807A58B);
401 /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */
402 cx_write(PLL_A_POST_STAT_BIST
, 0x8000019C);
404 /* clear reset bit [31] */
405 tmp
= cx_read(PLL_A_INT_FRAC
);
406 cx_write(PLL_A_INT_FRAC
, tmp
& 0x7FFFFFFF);
408 /* PLL-B setting for Mobilygen Host Bus Interface */
409 cx_write(PLL_B_INT_FRAC
, 0x9883A86F);
411 /* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */
412 cx_write(PLL_B_POST_STAT_BIST
, 0x8000018D);
414 /* clear reset bit [31] */
415 tmp
= cx_read(PLL_B_INT_FRAC
);
416 cx_write(PLL_B_INT_FRAC
, tmp
& 0x7FFFFFFF);
418 /* PLL-C setting for video upstream channel */
419 cx_write(PLL_C_INT_FRAC
, 0x96A0EA3F);
421 /* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */
422 cx_write(PLL_C_POST_STAT_BIST
, 0x80000103);
424 /* clear reset bit [31] */
425 tmp
= cx_read(PLL_C_INT_FRAC
);
426 cx_write(PLL_C_INT_FRAC
, tmp
& 0x7FFFFFFF);
428 /* PLL-D setting for audio upstream channel */
429 cx_write(PLL_D_INT_FRAC
, 0x98757F5B);
431 /* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */
432 cx_write(PLL_D_POST_STAT_BIST
, 0x80000113);
434 /* clear reset bit [31] */
435 tmp
= cx_read(PLL_D_INT_FRAC
);
436 cx_write(PLL_D_INT_FRAC
, tmp
& 0x7FFFFFFF);
438 /* This selects the PLL C clock source for the video upstream channel
440 tmp
= cx_read(VID_CH_CLK_SEL
);
441 cx_write(VID_CH_CLK_SEL
, (tmp
& 0x00FFFFFF) | 0x24000000);
443 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
445 * select 656/VIP DST for downstream Channel A - C */
446 tmp
= cx_read(VID_CH_MODE_SEL
);
447 /* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */
448 cx_write(VID_CH_MODE_SEL
, tmp
& 0xFFFFFE00);
450 /* enables 656 port I and J as output */
451 tmp
= cx_read(CLK_RST
);
452 /* use external ALT_PLL_REF pin as its reference clock instead */
453 tmp
|= FLD_USE_ALT_PLL_REF
;
454 cx_write(CLK_RST
, tmp
& ~(FLD_VID_I_CLK_NOE
| FLD_VID_J_CLK_NOE
));
459 int cx25821_sram_channel_setup(struct cx25821_dev
*dev
,
460 struct sram_channel
*ch
,
461 unsigned int bpl
, u32 risc
)
463 unsigned int i
, lines
;
466 if (ch
->cmds_start
== 0) {
467 cx_write(ch
->ptr1_reg
, 0);
468 cx_write(ch
->ptr2_reg
, 0);
469 cx_write(ch
->cnt2_reg
, 0);
470 cx_write(ch
->cnt1_reg
, 0);
474 bpl
= (bpl
+ 7) & ~7; /* alignment */
476 lines
= ch
->fifo_size
/ bpl
;
483 cx_write(8 + 0, RISC_JUMP
| RISC_IRQ1
| RISC_CNT_INC
);
488 for (i
= 0; i
< lines
; i
++) {
489 cx_write(cdt
+ 16 * i
, ch
->fifo_start
+ bpl
* i
);
490 cx_write(cdt
+ 16 * i
+ 4, 0);
491 cx_write(cdt
+ 16 * i
+ 8, 0);
492 cx_write(cdt
+ 16 * i
+ 12, 0);
495 /* init the first cdt buffer */
496 for (i
= 0; i
< 128; i
++)
497 cx_write(ch
->fifo_start
+ 4 * i
, i
);
501 cx_write(ch
->cmds_start
+ 0, 8);
503 cx_write(ch
->cmds_start
+ 0, risc
);
505 cx_write(ch
->cmds_start
+ 4, 0); /* 64 bits 63-32 */
506 cx_write(ch
->cmds_start
+ 8, cdt
);
507 cx_write(ch
->cmds_start
+ 12, (lines
* 16) >> 3);
508 cx_write(ch
->cmds_start
+ 16, ch
->ctrl_start
);
511 cx_write(ch
->cmds_start
+ 20, 0x80000000 | (64 >> 2));
513 cx_write(ch
->cmds_start
+ 20, 64 >> 2);
515 for (i
= 24; i
< 80; i
+= 4)
516 cx_write(ch
->cmds_start
+ i
, 0);
519 cx_write(ch
->ptr1_reg
, ch
->fifo_start
);
520 cx_write(ch
->ptr2_reg
, cdt
);
521 cx_write(ch
->cnt2_reg
, (lines
* 16) >> 3);
522 cx_write(ch
->cnt1_reg
, (bpl
>> 3) - 1);
526 EXPORT_SYMBOL(cx25821_sram_channel_setup
);
528 int cx25821_sram_channel_setup_audio(struct cx25821_dev
*dev
,
529 struct sram_channel
*ch
,
530 unsigned int bpl
, u32 risc
)
532 unsigned int i
, lines
;
535 if (ch
->cmds_start
== 0) {
536 cx_write(ch
->ptr1_reg
, 0);
537 cx_write(ch
->ptr2_reg
, 0);
538 cx_write(ch
->cnt2_reg
, 0);
539 cx_write(ch
->cnt1_reg
, 0);
543 bpl
= (bpl
+ 7) & ~7; /* alignment */
545 lines
= ch
->fifo_size
/ bpl
;
548 lines
= 3; /* for AUDIO */
552 cx_write(8 + 0, RISC_JUMP
| RISC_IRQ1
| RISC_CNT_INC
);
557 for (i
= 0; i
< lines
; i
++) {
558 cx_write(cdt
+ 16 * i
, ch
->fifo_start
+ bpl
* i
);
559 cx_write(cdt
+ 16 * i
+ 4, 0);
560 cx_write(cdt
+ 16 * i
+ 8, 0);
561 cx_write(cdt
+ 16 * i
+ 12, 0);
566 cx_write(ch
->cmds_start
+ 0, 8);
568 cx_write(ch
->cmds_start
+ 0, risc
);
570 cx_write(ch
->cmds_start
+ 4, 0); /* 64 bits 63-32 */
571 cx_write(ch
->cmds_start
+ 8, cdt
);
572 cx_write(ch
->cmds_start
+ 12, (lines
* 16) >> 3);
573 cx_write(ch
->cmds_start
+ 16, ch
->ctrl_start
);
577 cx_write(ch
->cmds_start
+ 20, 0x80000000 | (64 >> 2));
579 cx_write(ch
->cmds_start
+ 20, 64 >> 2);
582 for (i
= 24; i
< 80; i
+= 4)
583 cx_write(ch
->cmds_start
+ i
, 0);
586 cx_write(ch
->ptr1_reg
, ch
->fifo_start
);
587 cx_write(ch
->ptr2_reg
, cdt
);
588 cx_write(ch
->cnt2_reg
, (lines
* 16) >> 3);
589 cx_write(ch
->cnt1_reg
, (bpl
>> 3) - 1);
593 EXPORT_SYMBOL(cx25821_sram_channel_setup_audio
);
595 void cx25821_sram_channel_dump(struct cx25821_dev
*dev
, struct sram_channel
*ch
)
597 static char *name
[] = {
614 unsigned int i
, j
, n
;
616 pr_warn("%s: %s - dma channel status dump\n", dev
->name
, ch
->name
);
617 for (i
= 0; i
< ARRAY_SIZE(name
); i
++)
618 pr_warn("cmds + 0x%2x: %-15s: 0x%08x\n",
619 i
* 4, name
[i
], cx_read(ch
->cmds_start
+ 4 * i
));
622 for (i
= 0; i
< 4;) {
623 risc
= cx_read(ch
->cmds_start
+ 4 * (i
+ 14));
624 pr_warn("cmds + 0x%2x: risc%d: ", j
+ i
* 4, i
);
625 i
+= cx25821_risc_decode(risc
);
628 for (i
= 0; i
< (64 >> 2); i
+= n
) {
629 risc
= cx_read(ch
->ctrl_start
+ 4 * i
);
630 /* No consideration for bits 63-32 */
632 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
633 i
* 4, ch
->ctrl_start
+ 4 * i
, i
);
634 n
= cx25821_risc_decode(risc
);
635 for (j
= 1; j
< n
; j
++) {
636 risc
= cx_read(ch
->ctrl_start
+ 4 * (i
+ j
));
637 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
638 4 * (i
+ j
), i
+ j
, risc
, j
);
642 pr_warn(" : fifo: 0x%08x -> 0x%x\n",
643 ch
->fifo_start
, ch
->fifo_start
+ ch
->fifo_size
);
644 pr_warn(" : ctrl: 0x%08x -> 0x%x\n",
645 ch
->ctrl_start
, ch
->ctrl_start
+ 6 * 16);
646 pr_warn(" : ptr1_reg: 0x%08x\n",
647 cx_read(ch
->ptr1_reg
));
648 pr_warn(" : ptr2_reg: 0x%08x\n",
649 cx_read(ch
->ptr2_reg
));
650 pr_warn(" : cnt1_reg: 0x%08x\n",
651 cx_read(ch
->cnt1_reg
));
652 pr_warn(" : cnt2_reg: 0x%08x\n",
653 cx_read(ch
->cnt2_reg
));
655 EXPORT_SYMBOL(cx25821_sram_channel_dump
);
657 void cx25821_sram_channel_dump_audio(struct cx25821_dev
*dev
,
658 struct sram_channel
*ch
)
660 static const char * const name
[] = {
677 u32 risc
, value
, tmp
;
678 unsigned int i
, j
, n
;
680 pr_info("\n%s: %s - dma Audio channel status dump\n",
681 dev
->name
, ch
->name
);
683 for (i
= 0; i
< ARRAY_SIZE(name
); i
++)
684 pr_info("%s: cmds + 0x%2x: %-15s: 0x%08x\n",
685 dev
->name
, i
* 4, name
[i
],
686 cx_read(ch
->cmds_start
+ 4 * i
));
689 for (i
= 0; i
< 4;) {
690 risc
= cx_read(ch
->cmds_start
+ 4 * (i
+ 14));
691 pr_warn("cmds + 0x%2x: risc%d: ", j
+ i
* 4, i
);
692 i
+= cx25821_risc_decode(risc
);
695 for (i
= 0; i
< (64 >> 2); i
+= n
) {
696 risc
= cx_read(ch
->ctrl_start
+ 4 * i
);
697 /* No consideration for bits 63-32 */
699 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
700 i
* 4, ch
->ctrl_start
+ 4 * i
, i
);
701 n
= cx25821_risc_decode(risc
);
703 for (j
= 1; j
< n
; j
++) {
704 risc
= cx_read(ch
->ctrl_start
+ 4 * (i
+ j
));
705 pr_warn("ctrl + 0x%2x : iq %x: 0x%08x [ arg #%d ]\n",
706 4 * (i
+ j
), i
+ j
, risc
, j
);
710 pr_warn(" : fifo: 0x%08x -> 0x%x\n",
711 ch
->fifo_start
, ch
->fifo_start
+ ch
->fifo_size
);
712 pr_warn(" : ctrl: 0x%08x -> 0x%x\n",
713 ch
->ctrl_start
, ch
->ctrl_start
+ 6 * 16);
714 pr_warn(" : ptr1_reg: 0x%08x\n",
715 cx_read(ch
->ptr1_reg
));
716 pr_warn(" : ptr2_reg: 0x%08x\n",
717 cx_read(ch
->ptr2_reg
));
718 pr_warn(" : cnt1_reg: 0x%08x\n",
719 cx_read(ch
->cnt1_reg
));
720 pr_warn(" : cnt2_reg: 0x%08x\n",
721 cx_read(ch
->cnt2_reg
));
723 for (i
= 0; i
< 4; i
++) {
724 risc
= cx_read(ch
->cmds_start
+ 56 + (i
* 4));
725 pr_warn("instruction %d = 0x%x\n", i
, risc
);
728 /* read data from the first cdt buffer */
729 risc
= cx_read(AUD_A_CDT
);
730 pr_warn("\nread cdt loc=0x%x\n", risc
);
731 for (i
= 0; i
< 8; i
++) {
732 n
= cx_read(risc
+ i
* 4);
737 value
= cx_read(CLK_RST
);
738 CX25821_INFO(" CLK_RST = 0x%x\n\n", value
);
740 value
= cx_read(PLL_A_POST_STAT_BIST
);
741 CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value
);
742 value
= cx_read(PLL_A_INT_FRAC
);
743 CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value
);
745 value
= cx_read(PLL_B_POST_STAT_BIST
);
746 CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value
);
747 value
= cx_read(PLL_B_INT_FRAC
);
748 CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value
);
750 value
= cx_read(PLL_C_POST_STAT_BIST
);
751 CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value
);
752 value
= cx_read(PLL_C_INT_FRAC
);
753 CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value
);
755 value
= cx_read(PLL_D_POST_STAT_BIST
);
756 CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value
);
757 value
= cx_read(PLL_D_INT_FRAC
);
758 CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value
);
760 value
= cx25821_i2c_read(&dev
->i2c_bus
[0], AFE_AB_DIAG_CTRL
, &tmp
);
761 CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value
);
763 EXPORT_SYMBOL(cx25821_sram_channel_dump_audio
);
765 static void cx25821_shutdown(struct cx25821_dev
*dev
)
769 /* disable RISC controller */
770 cx_write(DEV_CNTRL2
, 0);
772 /* Disable Video A/B activity */
773 for (i
= 0; i
< VID_CHANNEL_NUM
; i
++) {
774 cx_write(dev
->channels
[i
].sram_channels
->dma_ctl
, 0);
775 cx_write(dev
->channels
[i
].sram_channels
->int_msk
, 0);
778 for (i
= VID_UPSTREAM_SRAM_CHANNEL_I
;
779 i
<= VID_UPSTREAM_SRAM_CHANNEL_J
; i
++) {
780 cx_write(dev
->channels
[i
].sram_channels
->dma_ctl
, 0);
781 cx_write(dev
->channels
[i
].sram_channels
->int_msk
, 0);
784 /* Disable Audio activity */
785 cx_write(AUD_INT_DMA_CTL
, 0);
787 /* Disable Serial port */
788 cx_write(UART_CTL
, 0);
790 /* Disable Interrupts */
791 cx_write(PCI_INT_MSK
, 0);
792 cx_write(AUD_A_INT_MSK
, 0);
795 void cx25821_set_pixel_format(struct cx25821_dev
*dev
, int channel_select
,
798 if (channel_select
<= 7 && channel_select
>= 0) {
799 cx_write(dev
->channels
[channel_select
].sram_channels
->pix_frmt
,
801 dev
->channels
[channel_select
].pixel_formats
= format
;
805 static void cx25821_set_vip_mode(struct cx25821_dev
*dev
,
806 struct sram_channel
*ch
)
808 cx_write(ch
->pix_frmt
, PIXEL_FRMT_422
);
809 cx_write(ch
->vip_ctl
, PIXEL_ENGINE_VIP1
);
812 static void cx25821_initialize(struct cx25821_dev
*dev
)
816 dprintk(1, "%s()\n", __func__
);
818 cx25821_shutdown(dev
);
819 cx_write(PCI_INT_STAT
, 0xffffffff);
821 for (i
= 0; i
< VID_CHANNEL_NUM
; i
++)
822 cx_write(dev
->channels
[i
].sram_channels
->int_stat
, 0xffffffff);
824 cx_write(AUD_A_INT_STAT
, 0xffffffff);
825 cx_write(AUD_B_INT_STAT
, 0xffffffff);
826 cx_write(AUD_C_INT_STAT
, 0xffffffff);
827 cx_write(AUD_D_INT_STAT
, 0xffffffff);
828 cx_write(AUD_E_INT_STAT
, 0xffffffff);
830 cx_write(CLK_DELAY
, cx_read(CLK_DELAY
) & 0x80000000);
831 cx_write(PAD_CTRL
, 0x12); /* for I2C */
832 cx25821_registers_init(dev
); /* init Pecos registers */
835 for (i
= 0; i
< VID_CHANNEL_NUM
; i
++) {
836 cx25821_set_vip_mode(dev
, dev
->channels
[i
].sram_channels
);
837 cx25821_sram_channel_setup(dev
, dev
->channels
[i
].sram_channels
,
839 dev
->channels
[i
].pixel_formats
= PIXEL_FRMT_422
;
840 dev
->channels
[i
].use_cif_resolution
= FALSE
;
843 /* Probably only affect Downstream */
844 for (i
= VID_UPSTREAM_SRAM_CHANNEL_I
;
845 i
<= VID_UPSTREAM_SRAM_CHANNEL_J
; i
++) {
846 cx25821_set_vip_mode(dev
, dev
->channels
[i
].sram_channels
);
849 cx25821_sram_channel_setup_audio(dev
,
850 dev
->channels
[SRAM_CH08
].sram_channels
, 128, 0);
852 cx25821_gpio_init(dev
);
855 static int cx25821_get_resources(struct cx25821_dev
*dev
)
857 if (request_mem_region(pci_resource_start(dev
->pci
, 0),
858 pci_resource_len(dev
->pci
, 0), dev
->name
))
861 pr_err("%s: can't get MMIO memory @ 0x%llx\n",
862 dev
->name
, (unsigned long long)pci_resource_start(dev
->pci
, 0));
867 static void cx25821_dev_checkrevision(struct cx25821_dev
*dev
)
869 dev
->hwrevision
= cx_read(RDR_CFG2
) & 0xff;
871 pr_info("%s(): Hardware revision = 0x%02x\n",
872 __func__
, dev
->hwrevision
);
875 static void cx25821_iounmap(struct cx25821_dev
*dev
)
880 /* Releasing IO memory */
881 if (dev
->lmmio
!= NULL
) {
882 CX25821_INFO("Releasing lmmio.\n");
888 static int cx25821_dev_setup(struct cx25821_dev
*dev
)
892 pr_info("\n***********************************\n");
893 pr_info("cx25821 set up\n");
894 pr_info("***********************************\n\n");
896 mutex_init(&dev
->lock
);
898 atomic_inc(&dev
->refcount
);
900 dev
->nr
= ++cx25821_devcount
;
901 sprintf(dev
->name
, "cx25821[%d]", dev
->nr
);
903 mutex_lock(&cx25821_devlist_mutex
);
904 list_add_tail(&dev
->devlist
, &cx25821_devlist
);
905 mutex_unlock(&cx25821_devlist_mutex
);
907 if (dev
->pci
->device
!= 0x8210) {
908 pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n",
909 __func__
, dev
->pci
->device
);
912 pr_info("Athena Hardware device = 0x%02x\n", dev
->pci
->device
);
915 /* Apply a sensible clock frequency for the PCIe bridge */
916 dev
->clk_freq
= 28000000;
917 for (i
= 0; i
< MAX_VID_CHANNEL_NUM
; i
++)
918 dev
->channels
[i
].sram_channels
= &cx25821_sram_channels
[i
];
921 CX25821_INFO("dev->nr > 1!");
924 dev
->board
= 1; /* card[dev->nr]; */
925 dev
->_max_num_decoders
= MAX_DECODERS
;
927 dev
->pci_bus
= dev
->pci
->bus
->number
;
928 dev
->pci_slot
= PCI_SLOT(dev
->pci
->devfn
);
929 dev
->pci_irqmask
= 0x001f00;
931 /* External Master 1 Bus */
932 dev
->i2c_bus
[0].nr
= 0;
933 dev
->i2c_bus
[0].dev
= dev
;
934 dev
->i2c_bus
[0].reg_stat
= I2C1_STAT
;
935 dev
->i2c_bus
[0].reg_ctrl
= I2C1_CTRL
;
936 dev
->i2c_bus
[0].reg_addr
= I2C1_ADDR
;
937 dev
->i2c_bus
[0].reg_rdata
= I2C1_RDATA
;
938 dev
->i2c_bus
[0].reg_wdata
= I2C1_WDATA
;
939 dev
->i2c_bus
[0].i2c_period
= (0x07 << 24); /* 1.95MHz */
941 if (cx25821_get_resources(dev
) < 0) {
942 pr_err("%s: No more PCIe resources for subsystem: %04x:%04x\n",
943 dev
->name
, dev
->pci
->subsystem_vendor
,
944 dev
->pci
->subsystem_device
);
951 dev
->base_io_addr
= pci_resource_start(dev
->pci
, 0);
953 if (!dev
->base_io_addr
) {
954 CX25821_ERR("No PCI Memory resources, exiting!\n");
958 dev
->lmmio
= ioremap(dev
->base_io_addr
, pci_resource_len(dev
->pci
, 0));
961 CX25821_ERR("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n");
962 cx25821_iounmap(dev
);
966 dev
->bmmio
= (u8 __iomem
*) dev
->lmmio
;
968 pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
969 dev
->name
, dev
->pci
->subsystem_vendor
,
970 dev
->pci
->subsystem_device
, cx25821_boards
[dev
->board
].name
,
971 dev
->board
, card
[dev
->nr
] == dev
->board
?
972 "insmod option" : "autodetected");
975 cx25821_initialize(dev
);
977 cx25821_i2c_register(&dev
->i2c_bus
[0]);
978 /* cx25821_i2c_register(&dev->i2c_bus[1]);
979 * cx25821_i2c_register(&dev->i2c_bus[2]); */
981 CX25821_INFO("i2c register! bus->i2c_rc = %d\n",
982 dev
->i2c_bus
[0].i2c_rc
);
984 cx25821_card_setup(dev
);
986 if (medusa_video_init(dev
) < 0)
987 CX25821_ERR("%s(): Failed to initialize medusa!\n", __func__
);
989 cx25821_video_register(dev
);
991 /* register IOCTL device */
992 dev
->ioctl_dev
= cx25821_vdev_init(dev
, dev
->pci
,
993 &cx25821_videoioctl_template
, "video");
995 if (video_register_device
996 (dev
->ioctl_dev
, VFL_TYPE_GRABBER
, VIDEO_IOCTL_CH
) < 0) {
997 cx25821_videoioctl_unregister(dev
);
998 pr_err("%s(): Failed to register video adapter for IOCTL, so unregistering videoioctl device\n",
1002 cx25821_dev_checkrevision(dev
);
1003 CX25821_INFO("setup done!\n");
1008 void cx25821_start_upstream_video_ch1(struct cx25821_dev
*dev
,
1009 struct upstream_user_struct
*up_data
)
1011 dev
->_isNTSC
= !strcmp(dev
->vid_stdname
, "NTSC") ? 1 : 0;
1013 dev
->tvnorm
= !dev
->_isNTSC
? V4L2_STD_PAL_BG
: V4L2_STD_NTSC_M
;
1014 medusa_set_videostandard(dev
);
1016 cx25821_vidupstream_init_ch1(dev
, dev
->channel_select
,
1020 void cx25821_start_upstream_video_ch2(struct cx25821_dev
*dev
,
1021 struct upstream_user_struct
*up_data
)
1023 dev
->_isNTSC_ch2
= !strcmp(dev
->vid_stdname_ch2
, "NTSC") ? 1 : 0;
1025 dev
->tvnorm
= !dev
->_isNTSC_ch2
? V4L2_STD_PAL_BG
: V4L2_STD_NTSC_M
;
1026 medusa_set_videostandard(dev
);
1028 cx25821_vidupstream_init_ch2(dev
, dev
->channel_select_ch2
,
1029 dev
->pixel_format_ch2
);
1032 void cx25821_start_upstream_audio(struct cx25821_dev
*dev
,
1033 struct upstream_user_struct
*up_data
)
1035 cx25821_audio_upstream_init(dev
, AUDIO_UPSTREAM_SRAM_CHANNEL_B
);
1038 void cx25821_dev_unregister(struct cx25821_dev
*dev
)
1042 if (!dev
->base_io_addr
)
1045 cx25821_free_mem_upstream_ch1(dev
);
1046 cx25821_free_mem_upstream_ch2(dev
);
1047 cx25821_free_mem_upstream_audio(dev
);
1049 release_mem_region(dev
->base_io_addr
, pci_resource_len(dev
->pci
, 0));
1051 if (!atomic_dec_and_test(&dev
->refcount
))
1054 for (i
= 0; i
< VID_CHANNEL_NUM
; i
++)
1055 cx25821_video_unregister(dev
, i
);
1057 for (i
= VID_UPSTREAM_SRAM_CHANNEL_I
;
1058 i
<= AUDIO_UPSTREAM_SRAM_CHANNEL_B
; i
++) {
1059 cx25821_video_unregister(dev
, i
);
1062 cx25821_videoioctl_unregister(dev
);
1064 cx25821_i2c_unregister(&dev
->i2c_bus
[0]);
1065 cx25821_iounmap(dev
);
1067 EXPORT_SYMBOL(cx25821_dev_unregister
);
1069 static __le32
*cx25821_risc_field(__le32
* rp
, struct scatterlist
*sglist
,
1070 unsigned int offset
, u32 sync_line
,
1071 unsigned int bpl
, unsigned int padding
,
1074 struct scatterlist
*sg
;
1075 unsigned int line
, todo
;
1077 /* sync instruction */
1078 if (sync_line
!= NO_SYNC_LINE
)
1079 *(rp
++) = cpu_to_le32(RISC_RESYNC
| sync_line
);
1083 for (line
= 0; line
< lines
; line
++) {
1084 while (offset
&& offset
>= sg_dma_len(sg
)) {
1085 offset
-= sg_dma_len(sg
);
1088 if (bpl
<= sg_dma_len(sg
) - offset
) {
1089 /* fits into current chunk */
1090 *(rp
++) = cpu_to_le32(RISC_WRITE
| RISC_SOL
| RISC_EOL
|
1092 *(rp
++) = cpu_to_le32(sg_dma_address(sg
) + offset
);
1093 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1096 /* scanline needs to be split */
1098 *(rp
++) = cpu_to_le32(RISC_WRITE
| RISC_SOL
|
1099 (sg_dma_len(sg
) - offset
));
1100 *(rp
++) = cpu_to_le32(sg_dma_address(sg
) + offset
);
1101 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1102 todo
-= (sg_dma_len(sg
) - offset
);
1105 while (todo
> sg_dma_len(sg
)) {
1106 *(rp
++) = cpu_to_le32(RISC_WRITE
|
1108 *(rp
++) = cpu_to_le32(sg_dma_address(sg
));
1109 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1110 todo
-= sg_dma_len(sg
);
1113 *(rp
++) = cpu_to_le32(RISC_WRITE
| RISC_EOL
| todo
);
1114 *(rp
++) = cpu_to_le32(sg_dma_address(sg
));
1115 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1125 int cx25821_risc_buffer(struct pci_dev
*pci
, struct btcx_riscmem
*risc
,
1126 struct scatterlist
*sglist
, unsigned int top_offset
,
1127 unsigned int bottom_offset
, unsigned int bpl
,
1128 unsigned int padding
, unsigned int lines
)
1136 if (UNSET
!= top_offset
)
1138 if (UNSET
!= bottom_offset
)
1141 /* estimate risc mem: worst case is one write per page border +
1142 one write per scan line + syncs + jump (all 2 dwords). Padding
1143 can cause next bpl to start close to a page border. First DMA
1144 region may be smaller than PAGE_SIZE */
1145 /* write and jump need and extra dword */
1146 instructions
= fields
* (1 + ((bpl
+ padding
) * lines
) / PAGE_SIZE
+
1149 rc
= btcx_riscmem_alloc(pci
, risc
, instructions
* 12);
1154 /* write risc instructions */
1157 if (UNSET
!= top_offset
) {
1158 rp
= cx25821_risc_field(rp
, sglist
, top_offset
, 0, bpl
, padding
,
1162 if (UNSET
!= bottom_offset
) {
1163 rp
= cx25821_risc_field(rp
, sglist
, bottom_offset
, 0x200, bpl
,
1167 /* save pointer to jmp instruction address */
1169 BUG_ON((risc
->jmp
- risc
->cpu
+ 2) * sizeof(*risc
->cpu
) > risc
->size
);
1174 static __le32
*cx25821_risc_field_audio(__le32
* rp
, struct scatterlist
*sglist
,
1175 unsigned int offset
, u32 sync_line
,
1176 unsigned int bpl
, unsigned int padding
,
1177 unsigned int lines
, unsigned int lpi
)
1179 struct scatterlist
*sg
;
1180 unsigned int line
, todo
, sol
;
1182 /* sync instruction */
1183 if (sync_line
!= NO_SYNC_LINE
)
1184 *(rp
++) = cpu_to_le32(RISC_RESYNC
| sync_line
);
1188 for (line
= 0; line
< lines
; line
++) {
1189 while (offset
&& offset
>= sg_dma_len(sg
)) {
1190 offset
-= sg_dma_len(sg
);
1194 if (lpi
&& line
> 0 && !(line
% lpi
))
1195 sol
= RISC_SOL
| RISC_IRQ1
| RISC_CNT_INC
;
1199 if (bpl
<= sg_dma_len(sg
) - offset
) {
1200 /* fits into current chunk */
1201 *(rp
++) = cpu_to_le32(RISC_WRITE
| sol
| RISC_EOL
|
1203 *(rp
++) = cpu_to_le32(sg_dma_address(sg
) + offset
);
1204 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1207 /* scanline needs to be split */
1209 *(rp
++) = cpu_to_le32(RISC_WRITE
| sol
|
1210 (sg_dma_len(sg
) - offset
));
1211 *(rp
++) = cpu_to_le32(sg_dma_address(sg
) + offset
);
1212 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1213 todo
-= (sg_dma_len(sg
) - offset
);
1216 while (todo
> sg_dma_len(sg
)) {
1217 *(rp
++) = cpu_to_le32(RISC_WRITE
|
1219 *(rp
++) = cpu_to_le32(sg_dma_address(sg
));
1220 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1221 todo
-= sg_dma_len(sg
);
1224 *(rp
++) = cpu_to_le32(RISC_WRITE
| RISC_EOL
| todo
);
1225 *(rp
++) = cpu_to_le32(sg_dma_address(sg
));
1226 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1235 int cx25821_risc_databuffer_audio(struct pci_dev
*pci
,
1236 struct btcx_riscmem
*risc
,
1237 struct scatterlist
*sglist
,
1239 unsigned int lines
, unsigned int lpi
)
1245 /* estimate risc mem: worst case is one write per page border +
1246 one write per scan line + syncs + jump (all 2 dwords). Here
1247 there is no padding and no sync. First DMA region may be smaller
1249 /* Jump and write need an extra dword */
1250 instructions
= 1 + (bpl
* lines
) / PAGE_SIZE
+ lines
;
1253 rc
= btcx_riscmem_alloc(pci
, risc
, instructions
* 12);
1257 /* write risc instructions */
1259 rp
= cx25821_risc_field_audio(rp
, sglist
, 0, NO_SYNC_LINE
, bpl
, 0,
1262 /* save pointer to jmp instruction address */
1264 BUG_ON((risc
->jmp
- risc
->cpu
+ 2) * sizeof(*risc
->cpu
) > risc
->size
);
1267 EXPORT_SYMBOL(cx25821_risc_databuffer_audio
);
1269 int cx25821_risc_stopper(struct pci_dev
*pci
, struct btcx_riscmem
*risc
,
1270 u32 reg
, u32 mask
, u32 value
)
1275 rc
= btcx_riscmem_alloc(pci
, risc
, 4 * 16);
1280 /* write risc instructions */
1283 *(rp
++) = cpu_to_le32(RISC_WRITECR
| RISC_IRQ1
);
1284 *(rp
++) = cpu_to_le32(reg
);
1285 *(rp
++) = cpu_to_le32(value
);
1286 *(rp
++) = cpu_to_le32(mask
);
1287 *(rp
++) = cpu_to_le32(RISC_JUMP
);
1288 *(rp
++) = cpu_to_le32(risc
->dma
);
1289 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1293 void cx25821_free_buffer(struct videobuf_queue
*q
, struct cx25821_buffer
*buf
)
1295 struct videobuf_dmabuf
*dma
= videobuf_to_dma(&buf
->vb
);
1297 BUG_ON(in_interrupt());
1298 videobuf_waiton(q
, &buf
->vb
, 0, 0);
1299 videobuf_dma_unmap(q
->dev
, dma
);
1300 videobuf_dma_free(dma
);
1301 btcx_riscmem_free(to_pci_dev(q
->dev
), &buf
->risc
);
1302 buf
->vb
.state
= VIDEOBUF_NEEDS_INIT
;
1305 static irqreturn_t
cx25821_irq(int irq
, void *dev_id
)
1307 struct cx25821_dev
*dev
= dev_id
;
1311 u32 mask
[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
1313 pci_status
= cx_read(PCI_INT_STAT
);
1315 if (pci_status
== 0)
1318 for (i
= 0; i
< VID_CHANNEL_NUM
; i
++) {
1319 if (pci_status
& mask
[i
]) {
1320 vid_status
= cx_read(dev
->channels
[i
].
1321 sram_channels
->int_stat
);
1324 handled
+= cx25821_video_irq(dev
, i
,
1327 cx_write(PCI_INT_STAT
, mask
[i
]);
1332 return IRQ_RETVAL(handled
);
1335 void cx25821_print_irqbits(char *name
, char *tag
, char **strings
,
1336 int len
, u32 bits
, u32 mask
)
1340 printk(KERN_DEBUG
pr_fmt("%s: %s [0x%x]"), name
, tag
, bits
);
1342 for (i
= 0; i
< len
; i
++) {
1343 if (!(bits
& (1 << i
)))
1346 pr_cont(" %s", strings
[i
]);
1349 if (!(mask
& (1 << i
)))
1355 EXPORT_SYMBOL(cx25821_print_irqbits
);
1357 struct cx25821_dev
*cx25821_dev_get(struct pci_dev
*pci
)
1359 struct cx25821_dev
*dev
= pci_get_drvdata(pci
);
1362 EXPORT_SYMBOL(cx25821_dev_get
);
1364 static int __devinit
cx25821_initdev(struct pci_dev
*pci_dev
,
1365 const struct pci_device_id
*pci_id
)
1367 struct cx25821_dev
*dev
;
1370 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1374 err
= v4l2_device_register(&pci_dev
->dev
, &dev
->v4l2_dev
);
1380 if (pci_enable_device(pci_dev
)) {
1383 pr_info("pci enable failed!\n");
1385 goto fail_unregister_device
;
1388 pr_info("Athena pci enable !\n");
1390 err
= cx25821_dev_setup(dev
);
1393 goto fail_unregister_device
;
1395 goto fail_unregister_pci
;
1398 /* print pci info */
1399 pci_read_config_byte(pci_dev
, PCI_CLASS_REVISION
, &dev
->pci_rev
);
1400 pci_read_config_byte(pci_dev
, PCI_LATENCY_TIMER
, &dev
->pci_lat
);
1401 pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
1402 dev
->name
, pci_name(pci_dev
), dev
->pci_rev
, pci_dev
->irq
,
1403 dev
->pci_lat
, (unsigned long long)dev
->base_io_addr
);
1405 pci_set_master(pci_dev
);
1406 if (!pci_dma_supported(pci_dev
, 0xffffffff)) {
1407 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev
->name
);
1412 err
= request_irq(pci_dev
->irq
, cx25821_irq
,
1413 IRQF_SHARED
, dev
->name
, dev
);
1416 pr_err("%s: can't get IRQ %d\n", dev
->name
, pci_dev
->irq
);
1423 pr_info("cx25821_initdev() can't get IRQ !\n");
1424 cx25821_dev_unregister(dev
);
1426 fail_unregister_pci
:
1427 pci_disable_device(pci_dev
);
1428 fail_unregister_device
:
1429 v4l2_device_unregister(&dev
->v4l2_dev
);
1436 static void __devexit
cx25821_finidev(struct pci_dev
*pci_dev
)
1438 struct v4l2_device
*v4l2_dev
= pci_get_drvdata(pci_dev
);
1439 struct cx25821_dev
*dev
= get_cx25821(v4l2_dev
);
1441 cx25821_shutdown(dev
);
1442 pci_disable_device(pci_dev
);
1444 /* unregister stuff */
1446 free_irq(pci_dev
->irq
, dev
);
1448 mutex_lock(&cx25821_devlist_mutex
);
1449 list_del(&dev
->devlist
);
1450 mutex_unlock(&cx25821_devlist_mutex
);
1452 cx25821_dev_unregister(dev
);
1453 v4l2_device_unregister(v4l2_dev
);
1457 static DEFINE_PCI_DEVICE_TABLE(cx25821_pci_tbl
) = {
1459 /* CX25821 Athena */
1462 .subvendor
= 0x14f1,
1463 .subdevice
= 0x0920,
1465 /* CX25821 No Brand */
1468 .subvendor
= 0x0000,
1469 .subdevice
= 0x0000,
1471 /* --- end of list --- */
1475 MODULE_DEVICE_TABLE(pci
, cx25821_pci_tbl
);
1477 static struct pci_driver cx25821_pci_driver
= {
1479 .id_table
= cx25821_pci_tbl
,
1480 .probe
= cx25821_initdev
,
1481 .remove
= __devexit_p(cx25821_finidev
),
1487 static int __init
cx25821_init(void)
1489 pr_info("driver version %d.%d.%d loaded\n",
1490 (CX25821_VERSION_CODE
>> 16) & 0xff,
1491 (CX25821_VERSION_CODE
>> 8) & 0xff,
1492 CX25821_VERSION_CODE
& 0xff);
1493 return pci_register_driver(&cx25821_pci_driver
);
1496 static void __exit
cx25821_fini(void)
1498 pci_unregister_driver(&cx25821_pci_driver
);
1501 module_init(cx25821_init
);
1502 module_exit(cx25821_fini
);