drivers/media/platform/marvell-ccic/mcam-core.h

   1 /*
   2  * Marvell camera core structures.
   3  *
   4  * Copyright 2011 Jonathan Corbet corbet@lwn.net
   5  */
   6 #ifndef _MCAM_CORE_H
   7 #define _MCAM_CORE_H
   8
   9 #include <linux/list.h>
  10 #include <media/v4l2-common.h>
  11 #include <media/v4l2-ctrls.h>
  12 #include <media/v4l2-dev.h>
  13 #include <media/videobuf2-core.h>
  14
  15 /*
  16  * Create our own symbols for the supported buffer modes, but, for now,
  17  * base them entirely on which videobuf2 options have been selected.
  18  */
  19 #if IS_ENABLED(CONFIG_VIDEOBUF2_VMALLOC)
  20 #define MCAM_MODE_VMALLOC 1
  21 #endif
  22
  23 #if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_CONTIG)
  24 #define MCAM_MODE_DMA_CONTIG 1
  25 #endif
  26
  27 #if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_SG)
  28 #define MCAM_MODE_DMA_SG 1
  29 #endif
  30
  31 #if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \
  32         !defined(MCAM_MODE_DMA_SG)
  33 #error One of the videobuf buffer modes must be selected in the config
  34 #endif
  35
  36
  37 enum mcam_state {
  38         S_NOTREADY,     /* Not yet initialized */
  39         S_IDLE,         /* Just hanging around */
  40         S_FLAKED,       /* Some sort of problem */
  41         S_STREAMING,    /* Streaming data */
  42         S_BUFWAIT       /* streaming requested but no buffers yet */
  43 };
  44 #define MAX_DMA_BUFS 3
  45
  46 /*
  47  * Different platforms work best with different buffer modes, so we
  48  * let the platform pick.
  49  */
  50 enum mcam_buffer_mode {
  51         B_vmalloc = 0,
  52         B_DMA_contig = 1,
  53         B_DMA_sg = 2
  54 };
  55
  56 enum mcam_chip_id {
  57         MCAM_CAFE,
  58         MCAM_ARMADA610,
  59 };
  60
  61 /*
  62  * Is a given buffer mode supported by the current kernel configuration?
  63  */
  64 static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode)
  65 {
  66         switch (mode) {
  67 #ifdef MCAM_MODE_VMALLOC
  68         case B_vmalloc:
  69 #endif
  70 #ifdef MCAM_MODE_DMA_CONTIG
  71         case B_DMA_contig:
  72 #endif
  73 #ifdef MCAM_MODE_DMA_SG
  74         case B_DMA_sg:
  75 #endif
  76                 return 1;
  77         default:
  78                 return 0;
  79         }
  80 }
  81
  82 /*
  83  * Basic frame states
  84  */
  85 struct mcam_frame_state {
  86         unsigned int frames;
  87         unsigned int singles;
  88         unsigned int delivered;
  89 };
  90
  91 #define NR_MCAM_CLK 3
  92
  93 /*
  94  * A description of one of our devices.
  95  * Locking: controlled by s_mutex.  Certain fields, however, require
  96  *          the dev_lock spinlock; they are marked as such by comments.
  97  *          dev_lock is also required for access to device registers.
  98  */
  99 struct mcam_camera {
 100         /*
 101          * These fields should be set by the platform code prior to
 102          * calling mcam_register().
 103          */
 104         struct i2c_adapter *i2c_adapter;
 105         unsigned char __iomem *regs;
 106         unsigned regs_size; /* size in bytes of the register space */
 107         spinlock_t dev_lock;
 108         struct device *dev; /* For messages, dma alloc */
 109         enum mcam_chip_id chip_id;
 110         short int clock_speed;  /* Sensor clock speed, default 30 */
 111         short int use_smbus;    /* SMBUS or straight I2c? */
 112         enum mcam_buffer_mode buffer_mode;
 113
 114         int mclk_min;   /* The minimal value of mclk */
 115         int mclk_src;   /* which clock source the mclk derives from */
 116         int mclk_div;   /* Clock Divider Value for MCLK */
 117
 118         int ccic_id;
 119         enum v4l2_mbus_type bus_type;
 120         /* MIPI support */
 121         /* The dphy config value, allocated in board file
 122          * dphy[0]: DPHY3
 123          * dphy[1]: DPHY5
 124          * dphy[2]: DPHY6
 125          */
 126         int *dphy;
 127         bool mipi_enabled;      /* flag whether mipi is enabled already */
 128         int lane;                       /* lane number */
 129
 130         /* clock tree support */
 131         struct clk *clk[NR_MCAM_CLK];
 132
 133         /*
 134          * Callbacks from the core to the platform code.
 135          */
 136         int (*plat_power_up) (struct mcam_camera *cam);
 137         void (*plat_power_down) (struct mcam_camera *cam);
 138         void (*calc_dphy) (struct mcam_camera *cam);
 139         void (*ctlr_reset) (struct mcam_camera *cam);
 140
 141         /*
 142          * Everything below here is private to the mcam core and
 143          * should not be touched by the platform code.
 144          */
 145         struct v4l2_device v4l2_dev;
 146         struct v4l2_ctrl_handler ctrl_handler;
 147         enum mcam_state state;
 148         unsigned long flags;            /* Buffer status, mainly (dev_lock) */
 149
 150         struct mcam_frame_state frame_state;    /* Frame state counter */
 151         /*
 152          * Subsystem structures.
 153          */
 154         struct video_device vdev;
 155         struct v4l2_subdev *sensor;
 156         unsigned short sensor_addr;
 157
 158         /* Videobuf2 stuff */
 159         struct vb2_queue vb_queue;
 160         struct list_head buffers;       /* Available frames */
 161
 162         unsigned int nbufs;             /* How many are alloc'd */
 163         int next_buf;                   /* Next to consume (dev_lock) */
 164
 165         char bus_info[32];              /* querycap bus_info */
 166
 167         /* DMA buffers - vmalloc mode */
 168 #ifdef MCAM_MODE_VMALLOC
 169         unsigned int dma_buf_size;      /* allocated size */
 170         void *dma_bufs[MAX_DMA_BUFS];   /* Internal buffer addresses */
 171         dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */
 172         struct tasklet_struct s_tasklet;
 173 #endif
 174         unsigned int sequence;          /* Frame sequence number */
 175         unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual bufs */
 176
 177         /* DMA buffers - DMA modes */
 178         struct mcam_vb_buffer *vb_bufs[MAX_DMA_BUFS];
 179         struct vb2_alloc_ctx *vb_alloc_ctx;
 180         struct vb2_alloc_ctx *vb_alloc_ctx_sg;
 181
 182         /* Mode-specific ops, set at open time */
 183         void (*dma_setup)(struct mcam_camera *cam);
 184         void (*frame_complete)(struct mcam_camera *cam, int frame);
 185
 186         /* Current operating parameters */
 187         struct v4l2_pix_format pix_format;
 188         u32 mbus_code;
 189
 190         /* Locks */
 191         struct mutex s_mutex; /* Access to this structure */
 192 };
 193
 194
 195 /*
 196  * Register I/O functions.  These are here because the platform code
 197  * may legitimately need to mess with the register space.
 198  */
 199 /*
 200  * Device register I/O
 201  */
 202 static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg,
 203                 unsigned int val)
 204 {
 205         iowrite32(val, cam->regs + reg);
 206 }
 207
 208 static inline unsigned int mcam_reg_read(struct mcam_camera *cam,
 209                 unsigned int reg)
 210 {
 211         return ioread32(cam->regs + reg);
 212 }
 213
 214
 215 static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg,
 216                 unsigned int val, unsigned int mask)
 217 {
 218         unsigned int v = mcam_reg_read(cam, reg);
 219
 220         v = (v & ~mask) | (val & mask);
 221         mcam_reg_write(cam, reg, v);
 222 }
 223
 224 static inline void mcam_reg_clear_bit(struct mcam_camera *cam,
 225                 unsigned int reg, unsigned int val)
 226 {
 227         mcam_reg_write_mask(cam, reg, 0, val);
 228 }
 229
 230 static inline void mcam_reg_set_bit(struct mcam_camera *cam,
 231                 unsigned int reg, unsigned int val)
 232 {
 233         mcam_reg_write_mask(cam, reg, val, val);
 234 }
 235
 236 /*
 237  * Functions for use by platform code.
 238  */
 239 int mccic_register(struct mcam_camera *cam);
 240 int mccic_irq(struct mcam_camera *cam, unsigned int irqs);
 241 void mccic_shutdown(struct mcam_camera *cam);
 242 #ifdef CONFIG_PM
 243 void mccic_suspend(struct mcam_camera *cam);
 244 int mccic_resume(struct mcam_camera *cam);
 245 #endif
 246
 247 /*
 248  * Register definitions for the m88alp01 camera interface.  Offsets in bytes
 249  * as given in the spec.
 250  */
 251 #define REG_Y0BAR       0x00
 252 #define REG_Y1BAR       0x04
 253 #define REG_Y2BAR       0x08
 254 #define REG_U0BAR       0x0c
 255 #define REG_U1BAR       0x10
 256 #define REG_U2BAR       0x14
 257 #define REG_V0BAR       0x18
 258 #define REG_V1BAR       0x1C
 259 #define REG_V2BAR       0x20
 260
 261 /*
 262  * register definitions for MIPI support
 263  */
 264 #define REG_CSI2_CTRL0  0x100
 265 #define   CSI2_C0_MIPI_EN (0x1 << 0)
 266 #define   CSI2_C0_ACT_LANE(n) ((n-1) << 1)
 267 #define REG_CSI2_DPHY3  0x12c
 268 #define REG_CSI2_DPHY5  0x134
 269 #define REG_CSI2_DPHY6  0x138
 270
 271 /* ... */
 272
 273 #define REG_IMGPITCH    0x24    /* Image pitch register */
 274 #define   IMGP_YP_SHFT    2             /* Y pitch params */
 275 #define   IMGP_YP_MASK    0x00003ffc    /* Y pitch field */
 276 #define   IMGP_UVP_SHFT   18            /* UV pitch (planar) */
 277 #define   IMGP_UVP_MASK   0x3ffc0000
 278 #define REG_IRQSTATRAW  0x28    /* RAW IRQ Status */
 279 #define   IRQ_EOF0        0x00000001    /* End of frame 0 */
 280 #define   IRQ_EOF1        0x00000002    /* End of frame 1 */
 281 #define   IRQ_EOF2        0x00000004    /* End of frame 2 */
 282 #define   IRQ_SOF0        0x00000008    /* Start of frame 0 */
 283 #define   IRQ_SOF1        0x00000010    /* Start of frame 1 */
 284 #define   IRQ_SOF2        0x00000020    /* Start of frame 2 */
 285 #define   IRQ_OVERFLOW    0x00000040    /* FIFO overflow */
 286 #define   IRQ_TWSIW       0x00010000    /* TWSI (smbus) write */
 287 #define   IRQ_TWSIR       0x00020000    /* TWSI read */
 288 #define   IRQ_TWSIE       0x00040000    /* TWSI error */
 289 #define   TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
 290 #define   FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
 291 #define   ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
 292 #define REG_IRQMASK     0x2c    /* IRQ mask - same bits as IRQSTAT */
 293 #define REG_IRQSTAT     0x30    /* IRQ status / clear */
 294
 295 #define REG_IMGSIZE     0x34    /* Image size */
 296 #define  IMGSZ_V_MASK     0x1fff0000
 297 #define  IMGSZ_V_SHIFT    16
 298 #define  IMGSZ_H_MASK     0x00003fff
 299 #define REG_IMGOFFSET   0x38    /* IMage offset */
 300
 301 #define REG_CTRL0       0x3c    /* Control 0 */
 302 #define   C0_ENABLE       0x00000001    /* Makes the whole thing go */
 303
 304 /* Mask for all the format bits */
 305 #define   C0_DF_MASK      0x00fffffc    /* Bits 2-23 */
 306
 307 /* RGB ordering */
 308 #define   C0_RGB4_RGBX    0x00000000
 309 #define   C0_RGB4_XRGB    0x00000004
 310 #define   C0_RGB4_BGRX    0x00000008
 311 #define   C0_RGB4_XBGR    0x0000000c
 312 #define   C0_RGB5_RGGB    0x00000000
 313 #define   C0_RGB5_GRBG    0x00000004
 314 #define   C0_RGB5_GBRG    0x00000008
 315 #define   C0_RGB5_BGGR    0x0000000c
 316
 317 /* Spec has two fields for DIN and DOUT, but they must match, so
 318    combine them here. */
 319 #define   C0_DF_YUV       0x00000000    /* Data is YUV      */
 320 #define   C0_DF_RGB       0x000000a0    /* ... RGB                  */
 321 #define   C0_DF_BAYER     0x00000140    /* ... Bayer                */
 322 /* 8-8-8 must be missing from the below - ask */
 323 #define   C0_RGBF_565     0x00000000
 324 #define   C0_RGBF_444     0x00000800
 325 #define   C0_RGB_BGR      0x00001000    /* Blue comes first */
 326 #define   C0_YUV_PLANAR   0x00000000    /* YUV 422 planar format */
 327 #define   C0_YUV_PACKED   0x00008000    /* YUV 422 packed       */
 328 #define   C0_YUV_420PL    0x0000a000    /* YUV 420 planar       */
 329 /* Think that 420 packed must be 111 - ask */
 330 #define   C0_YUVE_YUYV    0x00000000    /* Y1CbY0Cr             */
 331 #define   C0_YUVE_YVYU    0x00010000    /* Y1CrY0Cb             */
 332 #define   C0_YUVE_VYUY    0x00020000    /* CrY1CbY0             */
 333 #define   C0_YUVE_UYVY    0x00030000    /* CbY1CrY0             */
 334 #define   C0_YUVE_XYUV    0x00000000    /* 420: .YUV            */
 335 #define   C0_YUVE_XYVU    0x00010000    /* 420: .YVU            */
 336 #define   C0_YUVE_XUVY    0x00020000    /* 420: .UVY            */
 337 #define   C0_YUVE_XVUY    0x00030000    /* 420: .VUY            */
 338 /* Bayer bits 18,19 if needed */
 339 #define   C0_EOF_VSYNC    0x00400000    /* Generate EOF by VSYNC */
 340 #define   C0_VEDGE_CTRL   0x00800000    /* Detect falling edge of VSYNC */
 341 #define   C0_HPOL_LOW     0x01000000    /* HSYNC polarity active low */
 342 #define   C0_VPOL_LOW     0x02000000    /* VSYNC polarity active low */
 343 #define   C0_VCLK_LOW     0x04000000    /* VCLK on falling edge */
 344 #define   C0_DOWNSCALE    0x08000000    /* Enable downscaler */
 345 /* SIFMODE */
 346 #define   C0_SIF_HVSYNC   0x00000000    /* Use H/VSYNC */
 347 #define   C0_SOF_NOSYNC   0x40000000    /* Use inband active signaling */
 348 #define   C0_SIFM_MASK    0xc0000000    /* SIF mode bits */
 349
 350 /* Bits below C1_444ALPHA are not present in Cafe */
 351 #define REG_CTRL1       0x40    /* Control 1 */
 352 #define   C1_CLKGATE      0x00000001    /* Sensor clock gate */
 353 #define   C1_DESC_ENA     0x00000100    /* DMA descriptor enable */
 354 #define   C1_DESC_3WORD   0x00000200    /* Three-word descriptors used */
 355 #define   C1_444ALPHA     0x00f00000    /* Alpha field in RGB444 */
 356 #define   C1_ALPHA_SHFT   20
 357 #define   C1_DMAB32       0x00000000    /* 32-byte DMA burst */
 358 #define   C1_DMAB16       0x02000000    /* 16-byte DMA burst */
 359 #define   C1_DMAB64       0x04000000    /* 64-byte DMA burst */
 360 #define   C1_DMAB_MASK    0x06000000
 361 #define   C1_TWOBUFS      0x08000000    /* Use only two DMA buffers */
 362 #define   C1_PWRDWN       0x10000000    /* Power down */
 363
 364 #define REG_CLKCTRL     0x88    /* Clock control */
 365 #define   CLK_DIV_MASK    0x0000ffff    /* Upper bits RW "reserved" */
 366
 367 /* This appears to be a Cafe-only register */
 368 #define REG_UBAR        0xc4    /* Upper base address register */
 369
 370 /* Armada 610 DMA descriptor registers */
 371 #define REG_DMA_DESC_Y  0x200
 372 #define REG_DMA_DESC_U  0x204
 373 #define REG_DMA_DESC_V  0x208
 374 #define REG_DESC_LEN_Y  0x20c   /* Lengths are in bytes */
 375 #define REG_DESC_LEN_U  0x210
 376 #define REG_DESC_LEN_V  0x214
 377
 378 /*
 379  * Useful stuff that probably belongs somewhere global.
 380  */
 381 #define VGA_WIDTH       640
 382 #define VGA_HEIGHT      480
 383
 384 #endif /* _MCAM_CORE_H */