4 * TI OMAP3 ISP - CSI2 module
6 * Copyright (C) 2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
16 #include <linux/delay.h>
17 #include <media/v4l2-common.h>
18 #include <linux/v4l2-mediabus.h>
26 * csi2_if_enable - Enable CSI2 Receiver interface.
27 * @enable: enable flag
30 static void csi2_if_enable(struct isp_device
*isp
,
31 struct isp_csi2_device
*csi2
, u8 enable
)
33 struct isp_csi2_ctrl_cfg
*currctrl
= &csi2
->ctrl
;
35 isp_reg_clr_set(isp
, csi2
->regs1
, ISPCSI2_CTRL
, ISPCSI2_CTRL_IF_EN
,
36 enable
? ISPCSI2_CTRL_IF_EN
: 0);
38 currctrl
->if_enable
= enable
;
42 * csi2_recv_config - CSI2 receiver module configuration.
43 * @currctrl: isp_csi2_ctrl_cfg structure
46 static void csi2_recv_config(struct isp_device
*isp
,
47 struct isp_csi2_device
*csi2
,
48 struct isp_csi2_ctrl_cfg
*currctrl
)
52 reg
= isp_reg_readl(isp
, csi2
->regs1
, ISPCSI2_CTRL
);
54 if (currctrl
->frame_mode
)
55 reg
|= ISPCSI2_CTRL_FRAME
;
57 reg
&= ~ISPCSI2_CTRL_FRAME
;
59 if (currctrl
->vp_clk_enable
)
60 reg
|= ISPCSI2_CTRL_VP_CLK_EN
;
62 reg
&= ~ISPCSI2_CTRL_VP_CLK_EN
;
64 if (currctrl
->vp_only_enable
)
65 reg
|= ISPCSI2_CTRL_VP_ONLY_EN
;
67 reg
&= ~ISPCSI2_CTRL_VP_ONLY_EN
;
69 reg
&= ~ISPCSI2_CTRL_VP_OUT_CTRL_MASK
;
70 reg
|= currctrl
->vp_out_ctrl
<< ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT
;
72 if (currctrl
->ecc_enable
)
73 reg
|= ISPCSI2_CTRL_ECC_EN
;
75 reg
&= ~ISPCSI2_CTRL_ECC_EN
;
77 isp_reg_writel(isp
, reg
, csi2
->regs1
, ISPCSI2_CTRL
);
80 static const unsigned int csi2_input_fmts
[] = {
81 V4L2_MBUS_FMT_SGRBG10_1X10
,
82 V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8
,
83 V4L2_MBUS_FMT_SRGGB10_1X10
,
84 V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8
,
85 V4L2_MBUS_FMT_SBGGR10_1X10
,
86 V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8
,
87 V4L2_MBUS_FMT_SGBRG10_1X10
,
88 V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8
,
89 V4L2_MBUS_FMT_YUYV8_2X8
,
92 /* To set the format on the CSI2 requires a mapping function that takes
93 * the following inputs:
94 * - 3 different formats (at this time)
95 * - 2 destinations (mem, vp+mem) (vp only handled separately)
96 * - 2 decompression options (on, off)
97 * - 2 isp revisions (certain format must be handled differently on OMAP3630)
98 * Output should be CSI2 frame format code
99 * Array indices as follows: [format][dest][decompr][is_3630]
100 * Not all combinations are valid. 0 means invalid.
102 static const u16 __csi2_fmt_map
[3][2][2][2] = {
105 /* Output to memory */
107 /* No DPCM decompression */
108 { CSI2_PIX_FMT_RAW10_EXP16
, CSI2_PIX_FMT_RAW10_EXP16
},
109 /* DPCM decompression */
114 /* No DPCM decompression */
115 { CSI2_PIX_FMT_RAW10_EXP16_VP
,
116 CSI2_PIX_FMT_RAW10_EXP16_VP
},
117 /* DPCM decompression */
121 /* RAW10 DPCM8 formats */
123 /* Output to memory */
125 /* No DPCM decompression */
126 { CSI2_PIX_FMT_RAW8
, CSI2_USERDEF_8BIT_DATA1
},
127 /* DPCM decompression */
128 { CSI2_PIX_FMT_RAW8_DPCM10_EXP16
,
129 CSI2_USERDEF_8BIT_DATA1_DPCM10
},
133 /* No DPCM decompression */
134 { CSI2_PIX_FMT_RAW8_VP
,
135 CSI2_PIX_FMT_RAW8_VP
},
136 /* DPCM decompression */
137 { CSI2_PIX_FMT_RAW8_DPCM10_VP
,
138 CSI2_USERDEF_8BIT_DATA1_DPCM10_VP
},
141 /* YUYV8 2X8 formats */
143 /* Output to memory */
145 /* No DPCM decompression */
146 { CSI2_PIX_FMT_YUV422_8BIT
,
147 CSI2_PIX_FMT_YUV422_8BIT
},
148 /* DPCM decompression */
153 /* No DPCM decompression */
154 { CSI2_PIX_FMT_YUV422_8BIT_VP
,
155 CSI2_PIX_FMT_YUV422_8BIT_VP
},
156 /* DPCM decompression */
163 * csi2_ctx_map_format - Map CSI2 sink media bus format to CSI2 format ID
164 * @csi2: ISP CSI2 device
166 * Returns CSI2 physical format id
168 static u16
csi2_ctx_map_format(struct isp_csi2_device
*csi2
)
170 const struct v4l2_mbus_framefmt
*fmt
= &csi2
->formats
[CSI2_PAD_SINK
];
171 int fmtidx
, destidx
, is_3630
;
174 case V4L2_MBUS_FMT_SGRBG10_1X10
:
175 case V4L2_MBUS_FMT_SRGGB10_1X10
:
176 case V4L2_MBUS_FMT_SBGGR10_1X10
:
177 case V4L2_MBUS_FMT_SGBRG10_1X10
:
180 case V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8
:
181 case V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8
:
182 case V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8
:
183 case V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8
:
186 case V4L2_MBUS_FMT_YUYV8_2X8
:
190 WARN(1, KERN_ERR
"CSI2: pixel format %08x unsupported!\n",
195 if (!(csi2
->output
& CSI2_OUTPUT_CCDC
) &&
196 !(csi2
->output
& CSI2_OUTPUT_MEMORY
)) {
197 /* Neither output enabled is a valid combination */
198 return CSI2_PIX_FMT_OTHERS
;
201 /* If we need to skip frames at the beginning of the stream disable the
202 * video port to avoid sending the skipped frames to the CCDC.
204 destidx
= csi2
->frame_skip
? 0 : !!(csi2
->output
& CSI2_OUTPUT_CCDC
);
205 is_3630
= csi2
->isp
->revision
== ISP_REVISION_15_0
;
207 return __csi2_fmt_map
[fmtidx
][destidx
][csi2
->dpcm_decompress
][is_3630
];
211 * csi2_set_outaddr - Set memory address to save output image
212 * @csi2: Pointer to ISP CSI2a device.
213 * @addr: ISP MMU Mapped 32-bit memory address aligned on 32 byte boundary.
215 * Sets the memory address where the output will be saved.
217 * Returns 0 if successful, or -EINVAL if the address is not in the 32 byte
220 static void csi2_set_outaddr(struct isp_csi2_device
*csi2
, u32 addr
)
222 struct isp_device
*isp
= csi2
->isp
;
223 struct isp_csi2_ctx_cfg
*ctx
= &csi2
->contexts
[0];
225 ctx
->ping_addr
= addr
;
226 ctx
->pong_addr
= addr
;
227 isp_reg_writel(isp
, ctx
->ping_addr
,
228 csi2
->regs1
, ISPCSI2_CTX_DAT_PING_ADDR(ctx
->ctxnum
));
229 isp_reg_writel(isp
, ctx
->pong_addr
,
230 csi2
->regs1
, ISPCSI2_CTX_DAT_PONG_ADDR(ctx
->ctxnum
));
234 * is_usr_def_mapping - Checks whether USER_DEF_MAPPING should
235 * be enabled by CSI2.
236 * @format_id: mapped format id
239 static inline int is_usr_def_mapping(u32 format_id
)
241 return (format_id
& 0x40) ? 1 : 0;
245 * csi2_ctx_enable - Enable specified CSI2 context
246 * @ctxnum: Context number, valid between 0 and 7 values.
250 static void csi2_ctx_enable(struct isp_device
*isp
,
251 struct isp_csi2_device
*csi2
, u8 ctxnum
, u8 enable
)
253 struct isp_csi2_ctx_cfg
*ctx
= &csi2
->contexts
[ctxnum
];
254 unsigned int skip
= 0;
257 reg
= isp_reg_readl(isp
, csi2
->regs1
, ISPCSI2_CTX_CTRL1(ctxnum
));
260 if (csi2
->frame_skip
)
261 skip
= csi2
->frame_skip
;
262 else if (csi2
->output
& CSI2_OUTPUT_MEMORY
)
265 reg
&= ~ISPCSI2_CTX_CTRL1_COUNT_MASK
;
266 reg
|= ISPCSI2_CTX_CTRL1_COUNT_UNLOCK
267 | (skip
<< ISPCSI2_CTX_CTRL1_COUNT_SHIFT
)
268 | ISPCSI2_CTX_CTRL1_CTX_EN
;
270 reg
&= ~ISPCSI2_CTX_CTRL1_CTX_EN
;
273 isp_reg_writel(isp
, reg
, csi2
->regs1
, ISPCSI2_CTX_CTRL1(ctxnum
));
274 ctx
->enabled
= enable
;
278 * csi2_ctx_config - CSI2 context configuration.
279 * @ctx: context configuration
282 static void csi2_ctx_config(struct isp_device
*isp
,
283 struct isp_csi2_device
*csi2
,
284 struct isp_csi2_ctx_cfg
*ctx
)
288 /* Set up CSI2_CTx_CTRL1 */
289 reg
= isp_reg_readl(isp
, csi2
->regs1
, ISPCSI2_CTX_CTRL1(ctx
->ctxnum
));
291 if (ctx
->eof_enabled
)
292 reg
|= ISPCSI2_CTX_CTRL1_EOF_EN
;
294 reg
&= ~ISPCSI2_CTX_CTRL1_EOF_EN
;
296 if (ctx
->eol_enabled
)
297 reg
|= ISPCSI2_CTX_CTRL1_EOL_EN
;
299 reg
&= ~ISPCSI2_CTX_CTRL1_EOL_EN
;
301 if (ctx
->checksum_enabled
)
302 reg
|= ISPCSI2_CTX_CTRL1_CS_EN
;
304 reg
&= ~ISPCSI2_CTX_CTRL1_CS_EN
;
306 isp_reg_writel(isp
, reg
, csi2
->regs1
, ISPCSI2_CTX_CTRL1(ctx
->ctxnum
));
308 /* Set up CSI2_CTx_CTRL2 */
309 reg
= isp_reg_readl(isp
, csi2
->regs1
, ISPCSI2_CTX_CTRL2(ctx
->ctxnum
));
311 reg
&= ~(ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK
);
312 reg
|= ctx
->virtual_id
<< ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT
;
314 reg
&= ~(ISPCSI2_CTX_CTRL2_FORMAT_MASK
);
315 reg
|= ctx
->format_id
<< ISPCSI2_CTX_CTRL2_FORMAT_SHIFT
;
317 if (ctx
->dpcm_decompress
) {
318 if (ctx
->dpcm_predictor
)
319 reg
|= ISPCSI2_CTX_CTRL2_DPCM_PRED
;
321 reg
&= ~ISPCSI2_CTX_CTRL2_DPCM_PRED
;
324 if (is_usr_def_mapping(ctx
->format_id
)) {
325 reg
&= ~ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK
;
326 reg
|= 2 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT
;
329 isp_reg_writel(isp
, reg
, csi2
->regs1
, ISPCSI2_CTX_CTRL2(ctx
->ctxnum
));
331 /* Set up CSI2_CTx_CTRL3 */
332 reg
= isp_reg_readl(isp
, csi2
->regs1
, ISPCSI2_CTX_CTRL3(ctx
->ctxnum
));
333 reg
&= ~(ISPCSI2_CTX_CTRL3_ALPHA_MASK
);
334 reg
|= (ctx
->alpha
<< ISPCSI2_CTX_CTRL3_ALPHA_SHIFT
);
336 isp_reg_writel(isp
, reg
, csi2
->regs1
, ISPCSI2_CTX_CTRL3(ctx
->ctxnum
));
338 /* Set up CSI2_CTx_DAT_OFST */
339 reg
= isp_reg_readl(isp
, csi2
->regs1
,
340 ISPCSI2_CTX_DAT_OFST(ctx
->ctxnum
));
341 reg
&= ~ISPCSI2_CTX_DAT_OFST_OFST_MASK
;
342 reg
|= ctx
->data_offset
<< ISPCSI2_CTX_DAT_OFST_OFST_SHIFT
;
343 isp_reg_writel(isp
, reg
, csi2
->regs1
,
344 ISPCSI2_CTX_DAT_OFST(ctx
->ctxnum
));
346 isp_reg_writel(isp
, ctx
->ping_addr
,
347 csi2
->regs1
, ISPCSI2_CTX_DAT_PING_ADDR(ctx
->ctxnum
));
349 isp_reg_writel(isp
, ctx
->pong_addr
,
350 csi2
->regs1
, ISPCSI2_CTX_DAT_PONG_ADDR(ctx
->ctxnum
));
354 * csi2_timing_config - CSI2 timing configuration.
355 * @timing: csi2_timing_cfg structure
357 static void csi2_timing_config(struct isp_device
*isp
,
358 struct isp_csi2_device
*csi2
,
359 struct isp_csi2_timing_cfg
*timing
)
363 reg
= isp_reg_readl(isp
, csi2
->regs1
, ISPCSI2_TIMING
);
365 if (timing
->force_rx_mode
)
366 reg
|= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing
->ionum
);
368 reg
&= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing
->ionum
);
370 if (timing
->stop_state_16x
)
371 reg
|= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing
->ionum
);
373 reg
&= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing
->ionum
);
375 if (timing
->stop_state_4x
)
376 reg
|= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing
->ionum
);
378 reg
&= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing
->ionum
);
380 reg
&= ~ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(timing
->ionum
);
381 reg
|= timing
->stop_state_counter
<<
382 ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(timing
->ionum
);
384 isp_reg_writel(isp
, reg
, csi2
->regs1
, ISPCSI2_TIMING
);
388 * csi2_irq_ctx_set - Enables CSI2 Context IRQs.
389 * @enable: Enable/disable CSI2 Context interrupts
391 static void csi2_irq_ctx_set(struct isp_device
*isp
,
392 struct isp_csi2_device
*csi2
, int enable
)
396 for (i
= 0; i
< 8; i
++) {
397 isp_reg_writel(isp
, ISPCSI2_CTX_IRQSTATUS_FE_IRQ
, csi2
->regs1
,
398 ISPCSI2_CTX_IRQSTATUS(i
));
400 isp_reg_set(isp
, csi2
->regs1
, ISPCSI2_CTX_IRQENABLE(i
),
401 ISPCSI2_CTX_IRQSTATUS_FE_IRQ
);
403 isp_reg_clr(isp
, csi2
->regs1
, ISPCSI2_CTX_IRQENABLE(i
),
404 ISPCSI2_CTX_IRQSTATUS_FE_IRQ
);
409 * csi2_irq_complexio1_set - Enables CSI2 ComplexIO IRQs.
410 * @enable: Enable/disable CSI2 ComplexIO #1 interrupts
412 static void csi2_irq_complexio1_set(struct isp_device
*isp
,
413 struct isp_csi2_device
*csi2
, int enable
)
416 reg
= ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT
|
417 ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER
|
418 ISPCSI2_PHY_IRQENABLE_STATEULPM5
|
419 ISPCSI2_PHY_IRQENABLE_ERRCONTROL5
|
420 ISPCSI2_PHY_IRQENABLE_ERRESC5
|
421 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5
|
422 ISPCSI2_PHY_IRQENABLE_ERRSOTHS5
|
423 ISPCSI2_PHY_IRQENABLE_STATEULPM4
|
424 ISPCSI2_PHY_IRQENABLE_ERRCONTROL4
|
425 ISPCSI2_PHY_IRQENABLE_ERRESC4
|
426 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4
|
427 ISPCSI2_PHY_IRQENABLE_ERRSOTHS4
|
428 ISPCSI2_PHY_IRQENABLE_STATEULPM3
|
429 ISPCSI2_PHY_IRQENABLE_ERRCONTROL3
|
430 ISPCSI2_PHY_IRQENABLE_ERRESC3
|
431 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3
|
432 ISPCSI2_PHY_IRQENABLE_ERRSOTHS3
|
433 ISPCSI2_PHY_IRQENABLE_STATEULPM2
|
434 ISPCSI2_PHY_IRQENABLE_ERRCONTROL2
|
435 ISPCSI2_PHY_IRQENABLE_ERRESC2
|
436 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2
|
437 ISPCSI2_PHY_IRQENABLE_ERRSOTHS2
|
438 ISPCSI2_PHY_IRQENABLE_STATEULPM1
|
439 ISPCSI2_PHY_IRQENABLE_ERRCONTROL1
|
440 ISPCSI2_PHY_IRQENABLE_ERRESC1
|
441 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1
|
442 ISPCSI2_PHY_IRQENABLE_ERRSOTHS1
;
443 isp_reg_writel(isp
, reg
, csi2
->regs1
, ISPCSI2_PHY_IRQSTATUS
);
445 reg
|= isp_reg_readl(isp
, csi2
->regs1
, ISPCSI2_PHY_IRQENABLE
);
448 isp_reg_writel(isp
, reg
, csi2
->regs1
, ISPCSI2_PHY_IRQENABLE
);
452 * csi2_irq_status_set - Enables CSI2 Status IRQs.
453 * @enable: Enable/disable CSI2 Status interrupts
455 static void csi2_irq_status_set(struct isp_device
*isp
,
456 struct isp_csi2_device
*csi2
, int enable
)
459 reg
= ISPCSI2_IRQSTATUS_OCP_ERR_IRQ
|
460 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ
|
461 ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ
|
462 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ
|
463 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ
|
464 ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ
|
465 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ
|
466 ISPCSI2_IRQSTATUS_CONTEXT(0);
467 isp_reg_writel(isp
, reg
, csi2
->regs1
, ISPCSI2_IRQSTATUS
);
469 reg
|= isp_reg_readl(isp
, csi2
->regs1
, ISPCSI2_IRQENABLE
);
473 isp_reg_writel(isp
, reg
, csi2
->regs1
, ISPCSI2_IRQENABLE
);
477 * omap3isp_csi2_reset - Resets the CSI2 module.
479 * Must be called with the phy lock held.
481 * Returns 0 if successful, or -EBUSY if power command didn't respond.
483 int omap3isp_csi2_reset(struct isp_csi2_device
*csi2
)
485 struct isp_device
*isp
= csi2
->isp
;
486 u8 soft_reset_retries
= 0;
490 if (!csi2
->available
)
493 if (csi2
->phy
->phy_in_use
)
496 isp_reg_set(isp
, csi2
->regs1
, ISPCSI2_SYSCONFIG
,
497 ISPCSI2_SYSCONFIG_SOFT_RESET
);
500 reg
= isp_reg_readl(isp
, csi2
->regs1
, ISPCSI2_SYSSTATUS
) &
501 ISPCSI2_SYSSTATUS_RESET_DONE
;
502 if (reg
== ISPCSI2_SYSSTATUS_RESET_DONE
)
504 soft_reset_retries
++;
505 if (soft_reset_retries
< 5)
507 } while (soft_reset_retries
< 5);
509 if (soft_reset_retries
== 5) {
510 dev_err(isp
->dev
, "CSI2: Soft reset try count exceeded!\n");
514 if (isp
->revision
== ISP_REVISION_15_0
)
515 isp_reg_set(isp
, csi2
->regs1
, ISPCSI2_PHY_CFG
,
516 ISPCSI2_PHY_CFG_RESET_CTRL
);
520 reg
= isp_reg_readl(isp
, csi2
->phy
->phy_regs
, ISPCSIPHY_REG1
)
521 & ISPCSIPHY_REG1_RESET_DONE_CTRLCLK
;
522 if (reg
== ISPCSIPHY_REG1_RESET_DONE_CTRLCLK
)
529 "CSI2: Reset for CSI2_96M_FCLK domain Failed!\n");
534 isp_reg_clr_set(isp
, csi2
->regs1
, ISPCSI2_SYSCONFIG
,
535 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK
|
536 ISPCSI2_SYSCONFIG_AUTO_IDLE
,
537 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART
|
538 ((isp
->revision
== ISP_REVISION_15_0
) ?
539 ISPCSI2_SYSCONFIG_AUTO_IDLE
: 0));
541 isp_reg_clr_set(isp
, csi2
->regs1
, ISPCSI2_SYSCONFIG
,
542 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK
|
543 ISPCSI2_SYSCONFIG_AUTO_IDLE
,
544 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO
);
549 static int csi2_configure(struct isp_csi2_device
*csi2
)
551 const struct isp_v4l2_subdevs_group
*pdata
;
552 struct isp_device
*isp
= csi2
->isp
;
553 struct isp_csi2_timing_cfg
*timing
= &csi2
->timing
[0];
554 struct v4l2_subdev
*sensor
;
555 struct media_pad
*pad
;
558 * CSI2 fields that can be updated while the context has
559 * been enabled or the interface has been enabled are not
560 * updated dynamically currently. So we do not allow to
561 * reconfigure if either has been enabled
563 if (csi2
->contexts
[0].enabled
|| csi2
->ctrl
.if_enable
)
566 pad
= media_entity_remote_pad(&csi2
->pads
[CSI2_PAD_SINK
]);
567 sensor
= media_entity_to_v4l2_subdev(pad
->entity
);
568 pdata
= sensor
->host_priv
;
570 csi2
->frame_skip
= 0;
571 v4l2_subdev_call(sensor
, sensor
, g_skip_frames
, &csi2
->frame_skip
);
573 csi2
->ctrl
.vp_out_ctrl
= pdata
->bus
.csi2
.vpclk_div
;
574 csi2
->ctrl
.frame_mode
= ISP_CSI2_FRAME_IMMEDIATE
;
575 csi2
->ctrl
.ecc_enable
= pdata
->bus
.csi2
.crc
;
578 timing
->force_rx_mode
= 1;
579 timing
->stop_state_16x
= 1;
580 timing
->stop_state_4x
= 1;
581 timing
->stop_state_counter
= 0x1FF;
584 * The CSI2 receiver can't do any format conversion except DPCM
585 * decompression, so every set_format call configures both pads
586 * and enables DPCM decompression as a special case:
588 if (csi2
->formats
[CSI2_PAD_SINK
].code
!=
589 csi2
->formats
[CSI2_PAD_SOURCE
].code
)
590 csi2
->dpcm_decompress
= true;
592 csi2
->dpcm_decompress
= false;
594 csi2
->contexts
[0].format_id
= csi2_ctx_map_format(csi2
);
596 if (csi2
->video_out
.bpl_padding
== 0)
597 csi2
->contexts
[0].data_offset
= 0;
599 csi2
->contexts
[0].data_offset
= csi2
->video_out
.bpl_value
;
602 * Enable end of frame and end of line signals generation for
603 * context 0. These signals are generated from CSI2 receiver to
604 * qualify the last pixel of a frame and the last pixel of a line.
605 * Without enabling the signals CSI2 receiver writes data to memory
606 * beyond buffer size and/or data line offset is not handled correctly.
608 csi2
->contexts
[0].eof_enabled
= 1;
609 csi2
->contexts
[0].eol_enabled
= 1;
611 csi2_irq_complexio1_set(isp
, csi2
, 1);
612 csi2_irq_ctx_set(isp
, csi2
, 1);
613 csi2_irq_status_set(isp
, csi2
, 1);
615 /* Set configuration (timings, format and links) */
616 csi2_timing_config(isp
, csi2
, timing
);
617 csi2_recv_config(isp
, csi2
, &csi2
->ctrl
);
618 csi2_ctx_config(isp
, csi2
, &csi2
->contexts
[0]);
624 * csi2_print_status - Prints CSI2 debug information.
626 #define CSI2_PRINT_REGISTER(isp, regs, name)\
627 dev_dbg(isp->dev, "###CSI2 " #name "=0x%08x\n", \
628 isp_reg_readl(isp, regs, ISPCSI2_##name))
630 static void csi2_print_status(struct isp_csi2_device
*csi2
)
632 struct isp_device
*isp
= csi2
->isp
;
634 if (!csi2
->available
)
637 dev_dbg(isp
->dev
, "-------------CSI2 Register dump-------------\n");
639 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, SYSCONFIG
);
640 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, SYSSTATUS
);
641 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, IRQENABLE
);
642 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, IRQSTATUS
);
643 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, CTRL
);
644 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, DBG_H
);
645 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, GNQ
);
646 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, PHY_CFG
);
647 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, PHY_IRQSTATUS
);
648 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, SHORT_PACKET
);
649 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, PHY_IRQENABLE
);
650 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, DBG_P
);
651 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, TIMING
);
652 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, CTX_CTRL1(0));
653 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, CTX_CTRL2(0));
654 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, CTX_DAT_OFST(0));
655 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, CTX_DAT_PING_ADDR(0));
656 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, CTX_DAT_PONG_ADDR(0));
657 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, CTX_IRQENABLE(0));
658 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, CTX_IRQSTATUS(0));
659 CSI2_PRINT_REGISTER(isp
, csi2
->regs1
, CTX_CTRL3(0));
661 dev_dbg(isp
->dev
, "--------------------------------------------\n");
664 /* -----------------------------------------------------------------------------
669 * csi2_isr_buffer - Does buffer handling at end-of-frame
670 * when writing to memory.
672 static void csi2_isr_buffer(struct isp_csi2_device
*csi2
)
674 struct isp_device
*isp
= csi2
->isp
;
675 struct isp_buffer
*buffer
;
677 csi2_ctx_enable(isp
, csi2
, 0, 0);
679 buffer
= omap3isp_video_buffer_next(&csi2
->video_out
);
682 * Let video queue operation restart engine if there is an underrun
688 csi2_set_outaddr(csi2
, buffer
->dma
);
689 csi2_ctx_enable(isp
, csi2
, 0, 1);
692 static void csi2_isr_ctx(struct isp_csi2_device
*csi2
,
693 struct isp_csi2_ctx_cfg
*ctx
)
695 struct isp_device
*isp
= csi2
->isp
;
696 unsigned int n
= ctx
->ctxnum
;
699 status
= isp_reg_readl(isp
, csi2
->regs1
, ISPCSI2_CTX_IRQSTATUS(n
));
700 isp_reg_writel(isp
, status
, csi2
->regs1
, ISPCSI2_CTX_IRQSTATUS(n
));
702 if (!(status
& ISPCSI2_CTX_IRQSTATUS_FE_IRQ
))
705 /* Skip interrupts until we reach the frame skip count. The CSI2 will be
706 * automatically disabled, as the frame skip count has been programmed
707 * in the CSI2_CTx_CTRL1::COUNT field, so reenable it.
709 * It would have been nice to rely on the FRAME_NUMBER interrupt instead
710 * but it turned out that the interrupt is only generated when the CSI2
711 * writes to memory (the CSI2_CTx_CTRL1::COUNT field is decreased
712 * correctly and reaches 0 when data is forwarded to the video port only
713 * but no interrupt arrives). Maybe a CSI2 hardware bug.
715 if (csi2
->frame_skip
) {
717 if (csi2
->frame_skip
== 0) {
718 ctx
->format_id
= csi2_ctx_map_format(csi2
);
719 csi2_ctx_config(isp
, csi2
, ctx
);
720 csi2_ctx_enable(isp
, csi2
, n
, 1);
725 if (csi2
->output
& CSI2_OUTPUT_MEMORY
)
726 csi2_isr_buffer(csi2
);
730 * omap3isp_csi2_isr - CSI2 interrupt handling.
732 void omap3isp_csi2_isr(struct isp_csi2_device
*csi2
)
734 struct isp_pipeline
*pipe
= to_isp_pipeline(&csi2
->subdev
.entity
);
735 u32 csi2_irqstatus
, cpxio1_irqstatus
;
736 struct isp_device
*isp
= csi2
->isp
;
738 if (!csi2
->available
)
741 csi2_irqstatus
= isp_reg_readl(isp
, csi2
->regs1
, ISPCSI2_IRQSTATUS
);
742 isp_reg_writel(isp
, csi2_irqstatus
, csi2
->regs1
, ISPCSI2_IRQSTATUS
);
745 if (csi2_irqstatus
& ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ
) {
746 cpxio1_irqstatus
= isp_reg_readl(isp
, csi2
->regs1
,
747 ISPCSI2_PHY_IRQSTATUS
);
748 isp_reg_writel(isp
, cpxio1_irqstatus
,
749 csi2
->regs1
, ISPCSI2_PHY_IRQSTATUS
);
750 dev_dbg(isp
->dev
, "CSI2: ComplexIO Error IRQ "
751 "%x\n", cpxio1_irqstatus
);
755 if (csi2_irqstatus
& (ISPCSI2_IRQSTATUS_OCP_ERR_IRQ
|
756 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ
|
757 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ
|
758 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ
|
759 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ
)) {
760 dev_dbg(isp
->dev
, "CSI2 Err:"
768 ISPCSI2_IRQSTATUS_OCP_ERR_IRQ
) ? 1 : 0,
770 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ
) ? 1 : 0,
772 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ
) ? 1 : 0,
774 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ
) ? 1 : 0,
776 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ
) ? 1 : 0);
780 if (omap3isp_module_sync_is_stopping(&csi2
->wait
, &csi2
->stopping
))
783 /* Successful cases */
784 if (csi2_irqstatus
& ISPCSI2_IRQSTATUS_CONTEXT(0))
785 csi2_isr_ctx(csi2
, &csi2
->contexts
[0]);
787 if (csi2_irqstatus
& ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ
)
788 dev_dbg(isp
->dev
, "CSI2: ECC correction done\n");
791 /* -----------------------------------------------------------------------------
792 * ISP video operations
796 * csi2_queue - Queues the first buffer when using memory output
797 * @video: The video node
798 * @buffer: buffer to queue
800 static int csi2_queue(struct isp_video
*video
, struct isp_buffer
*buffer
)
802 struct isp_device
*isp
= video
->isp
;
803 struct isp_csi2_device
*csi2
= &isp
->isp_csi2a
;
805 csi2_set_outaddr(csi2
, buffer
->dma
);
808 * If streaming was enabled before there was a buffer queued
809 * or underrun happened in the ISR, the hardware was not enabled
810 * and DMA queue flag ISP_VIDEO_DMAQUEUE_UNDERRUN is still set.
813 if (csi2
->video_out
.dmaqueue_flags
& ISP_VIDEO_DMAQUEUE_UNDERRUN
) {
814 /* Enable / disable context 0 and IRQs */
815 csi2_if_enable(isp
, csi2
, 1);
816 csi2_ctx_enable(isp
, csi2
, 0, 1);
817 isp_video_dmaqueue_flags_clr(&csi2
->video_out
);
823 static const struct isp_video_operations csi2_ispvideo_ops
= {
827 /* -----------------------------------------------------------------------------
828 * V4L2 subdev operations
831 static struct v4l2_mbus_framefmt
*
832 __csi2_get_format(struct isp_csi2_device
*csi2
, struct v4l2_subdev_fh
*fh
,
833 unsigned int pad
, enum v4l2_subdev_format_whence which
)
835 if (which
== V4L2_SUBDEV_FORMAT_TRY
)
836 return v4l2_subdev_get_try_format(fh
, pad
);
838 return &csi2
->formats
[pad
];
842 csi2_try_format(struct isp_csi2_device
*csi2
, struct v4l2_subdev_fh
*fh
,
843 unsigned int pad
, struct v4l2_mbus_framefmt
*fmt
,
844 enum v4l2_subdev_format_whence which
)
846 enum v4l2_mbus_pixelcode pixelcode
;
847 struct v4l2_mbus_framefmt
*format
;
848 const struct isp_format_info
*info
;
853 /* Clamp the width and height to valid range (1-8191). */
854 for (i
= 0; i
< ARRAY_SIZE(csi2_input_fmts
); i
++) {
855 if (fmt
->code
== csi2_input_fmts
[i
])
859 /* If not found, use SGRBG10 as default */
860 if (i
>= ARRAY_SIZE(csi2_input_fmts
))
861 fmt
->code
= V4L2_MBUS_FMT_SGRBG10_1X10
;
863 fmt
->width
= clamp_t(u32
, fmt
->width
, 1, 8191);
864 fmt
->height
= clamp_t(u32
, fmt
->height
, 1, 8191);
867 case CSI2_PAD_SOURCE
:
868 /* Source format same as sink format, except for DPCM
871 pixelcode
= fmt
->code
;
872 format
= __csi2_get_format(csi2
, fh
, CSI2_PAD_SINK
, which
);
873 memcpy(fmt
, format
, sizeof(*fmt
));
876 * Only Allow DPCM decompression, and check that the
877 * pattern is preserved
879 info
= omap3isp_video_format_info(fmt
->code
);
880 if (info
->uncompressed
== pixelcode
)
881 fmt
->code
= pixelcode
;
885 /* RGB, non-interlaced */
886 fmt
->colorspace
= V4L2_COLORSPACE_SRGB
;
887 fmt
->field
= V4L2_FIELD_NONE
;
891 * csi2_enum_mbus_code - Handle pixel format enumeration
892 * @sd : pointer to v4l2 subdev structure
893 * @fh : V4L2 subdev file handle
894 * @code : pointer to v4l2_subdev_mbus_code_enum structure
895 * return -EINVAL or zero on success
897 static int csi2_enum_mbus_code(struct v4l2_subdev
*sd
,
898 struct v4l2_subdev_fh
*fh
,
899 struct v4l2_subdev_mbus_code_enum
*code
)
901 struct isp_csi2_device
*csi2
= v4l2_get_subdevdata(sd
);
902 struct v4l2_mbus_framefmt
*format
;
903 const struct isp_format_info
*info
;
905 if (code
->pad
== CSI2_PAD_SINK
) {
906 if (code
->index
>= ARRAY_SIZE(csi2_input_fmts
))
909 code
->code
= csi2_input_fmts
[code
->index
];
911 format
= __csi2_get_format(csi2
, fh
, CSI2_PAD_SINK
,
912 V4L2_SUBDEV_FORMAT_TRY
);
913 switch (code
->index
) {
915 /* Passthrough sink pad code */
916 code
->code
= format
->code
;
919 /* Uncompressed code */
920 info
= omap3isp_video_format_info(format
->code
);
921 if (info
->uncompressed
== format
->code
)
924 code
->code
= info
->uncompressed
;
934 static int csi2_enum_frame_size(struct v4l2_subdev
*sd
,
935 struct v4l2_subdev_fh
*fh
,
936 struct v4l2_subdev_frame_size_enum
*fse
)
938 struct isp_csi2_device
*csi2
= v4l2_get_subdevdata(sd
);
939 struct v4l2_mbus_framefmt format
;
944 format
.code
= fse
->code
;
947 csi2_try_format(csi2
, fh
, fse
->pad
, &format
, V4L2_SUBDEV_FORMAT_TRY
);
948 fse
->min_width
= format
.width
;
949 fse
->min_height
= format
.height
;
951 if (format
.code
!= fse
->code
)
954 format
.code
= fse
->code
;
957 csi2_try_format(csi2
, fh
, fse
->pad
, &format
, V4L2_SUBDEV_FORMAT_TRY
);
958 fse
->max_width
= format
.width
;
959 fse
->max_height
= format
.height
;
965 * csi2_get_format - Handle get format by pads subdev method
966 * @sd : pointer to v4l2 subdev structure
967 * @fh : V4L2 subdev file handle
968 * @fmt: pointer to v4l2 subdev format structure
969 * return -EINVAL or zero on success
971 static int csi2_get_format(struct v4l2_subdev
*sd
, struct v4l2_subdev_fh
*fh
,
972 struct v4l2_subdev_format
*fmt
)
974 struct isp_csi2_device
*csi2
= v4l2_get_subdevdata(sd
);
975 struct v4l2_mbus_framefmt
*format
;
977 format
= __csi2_get_format(csi2
, fh
, fmt
->pad
, fmt
->which
);
981 fmt
->format
= *format
;
986 * csi2_set_format - Handle set format by pads subdev method
987 * @sd : pointer to v4l2 subdev structure
988 * @fh : V4L2 subdev file handle
989 * @fmt: pointer to v4l2 subdev format structure
990 * return -EINVAL or zero on success
992 static int csi2_set_format(struct v4l2_subdev
*sd
, struct v4l2_subdev_fh
*fh
,
993 struct v4l2_subdev_format
*fmt
)
995 struct isp_csi2_device
*csi2
= v4l2_get_subdevdata(sd
);
996 struct v4l2_mbus_framefmt
*format
;
998 format
= __csi2_get_format(csi2
, fh
, fmt
->pad
, fmt
->which
);
1002 csi2_try_format(csi2
, fh
, fmt
->pad
, &fmt
->format
, fmt
->which
);
1003 *format
= fmt
->format
;
1005 /* Propagate the format from sink to source */
1006 if (fmt
->pad
== CSI2_PAD_SINK
) {
1007 format
= __csi2_get_format(csi2
, fh
, CSI2_PAD_SOURCE
,
1009 *format
= fmt
->format
;
1010 csi2_try_format(csi2
, fh
, CSI2_PAD_SOURCE
, format
, fmt
->which
);
1017 * csi2_init_formats - Initialize formats on all pads
1018 * @sd: ISP CSI2 V4L2 subdevice
1019 * @fh: V4L2 subdev file handle
1021 * Initialize all pad formats with default values. If fh is not NULL, try
1022 * formats are initialized on the file handle. Otherwise active formats are
1023 * initialized on the device.
1025 static int csi2_init_formats(struct v4l2_subdev
*sd
, struct v4l2_subdev_fh
*fh
)
1027 struct v4l2_subdev_format format
;
1029 memset(&format
, 0, sizeof(format
));
1030 format
.pad
= CSI2_PAD_SINK
;
1031 format
.which
= fh
? V4L2_SUBDEV_FORMAT_TRY
: V4L2_SUBDEV_FORMAT_ACTIVE
;
1032 format
.format
.code
= V4L2_MBUS_FMT_SGRBG10_1X10
;
1033 format
.format
.width
= 4096;
1034 format
.format
.height
= 4096;
1035 csi2_set_format(sd
, fh
, &format
);
1041 * csi2_set_stream - Enable/Disable streaming on the CSI2 module
1042 * @sd: ISP CSI2 V4L2 subdevice
1043 * @enable: ISP pipeline stream state
1045 * Return 0 on success or a negative error code otherwise.
1047 static int csi2_set_stream(struct v4l2_subdev
*sd
, int enable
)
1049 struct isp_csi2_device
*csi2
= v4l2_get_subdevdata(sd
);
1050 struct isp_device
*isp
= csi2
->isp
;
1051 struct isp_video
*video_out
= &csi2
->video_out
;
1054 case ISP_PIPELINE_STREAM_CONTINUOUS
:
1055 if (omap3isp_csiphy_acquire(csi2
->phy
) < 0)
1057 if (csi2
->output
& CSI2_OUTPUT_MEMORY
)
1058 omap3isp_sbl_enable(isp
, OMAP3_ISP_SBL_CSI2A_WRITE
);
1059 csi2_configure(csi2
);
1060 csi2_print_status(csi2
);
1063 * When outputting to memory with no buffer available, let the
1064 * buffer queue handler start the hardware. A DMA queue flag
1065 * ISP_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is
1066 * a buffer available.
1068 if (csi2
->output
& CSI2_OUTPUT_MEMORY
&&
1069 !(video_out
->dmaqueue_flags
& ISP_VIDEO_DMAQUEUE_QUEUED
))
1071 /* Enable context 0 and IRQs */
1072 atomic_set(&csi2
->stopping
, 0);
1073 csi2_ctx_enable(isp
, csi2
, 0, 1);
1074 csi2_if_enable(isp
, csi2
, 1);
1075 isp_video_dmaqueue_flags_clr(video_out
);
1078 case ISP_PIPELINE_STREAM_STOPPED
:
1079 if (csi2
->state
== ISP_PIPELINE_STREAM_STOPPED
)
1081 if (omap3isp_module_sync_idle(&sd
->entity
, &csi2
->wait
,
1083 dev_dbg(isp
->dev
, "%s: module stop timeout.\n",
1085 csi2_ctx_enable(isp
, csi2
, 0, 0);
1086 csi2_if_enable(isp
, csi2
, 0);
1087 csi2_irq_ctx_set(isp
, csi2
, 0);
1088 omap3isp_csiphy_release(csi2
->phy
);
1089 isp_video_dmaqueue_flags_clr(video_out
);
1090 omap3isp_sbl_disable(isp
, OMAP3_ISP_SBL_CSI2A_WRITE
);
1094 csi2
->state
= enable
;
1098 /* subdev video operations */
1099 static const struct v4l2_subdev_video_ops csi2_video_ops
= {
1100 .s_stream
= csi2_set_stream
,
1103 /* subdev pad operations */
1104 static const struct v4l2_subdev_pad_ops csi2_pad_ops
= {
1105 .enum_mbus_code
= csi2_enum_mbus_code
,
1106 .enum_frame_size
= csi2_enum_frame_size
,
1107 .get_fmt
= csi2_get_format
,
1108 .set_fmt
= csi2_set_format
,
1111 /* subdev operations */
1112 static const struct v4l2_subdev_ops csi2_ops
= {
1113 .video
= &csi2_video_ops
,
1114 .pad
= &csi2_pad_ops
,
1117 /* subdev internal operations */
1118 static const struct v4l2_subdev_internal_ops csi2_internal_ops
= {
1119 .open
= csi2_init_formats
,
1122 /* -----------------------------------------------------------------------------
1123 * Media entity operations
1127 * csi2_link_setup - Setup CSI2 connections.
1128 * @entity : Pointer to media entity structure
1129 * @local : Pointer to local pad array
1130 * @remote : Pointer to remote pad array
1131 * @flags : Link flags
1132 * return -EINVAL or zero on success
1134 static int csi2_link_setup(struct media_entity
*entity
,
1135 const struct media_pad
*local
,
1136 const struct media_pad
*remote
, u32 flags
)
1138 struct v4l2_subdev
*sd
= media_entity_to_v4l2_subdev(entity
);
1139 struct isp_csi2_device
*csi2
= v4l2_get_subdevdata(sd
);
1140 struct isp_csi2_ctrl_cfg
*ctrl
= &csi2
->ctrl
;
1143 * The ISP core doesn't support pipelines with multiple video outputs.
1144 * Revisit this when it will be implemented, and return -EBUSY for now.
1147 switch (local
->index
| media_entity_type(remote
->entity
)) {
1148 case CSI2_PAD_SOURCE
| MEDIA_ENT_T_DEVNODE
:
1149 if (flags
& MEDIA_LNK_FL_ENABLED
) {
1150 if (csi2
->output
& ~CSI2_OUTPUT_MEMORY
)
1152 csi2
->output
|= CSI2_OUTPUT_MEMORY
;
1154 csi2
->output
&= ~CSI2_OUTPUT_MEMORY
;
1158 case CSI2_PAD_SOURCE
| MEDIA_ENT_T_V4L2_SUBDEV
:
1159 if (flags
& MEDIA_LNK_FL_ENABLED
) {
1160 if (csi2
->output
& ~CSI2_OUTPUT_CCDC
)
1162 csi2
->output
|= CSI2_OUTPUT_CCDC
;
1164 csi2
->output
&= ~CSI2_OUTPUT_CCDC
;
1169 /* Link from camera to CSI2 is fixed... */
1173 ctrl
->vp_only_enable
=
1174 (csi2
->output
& CSI2_OUTPUT_MEMORY
) ? false : true;
1175 ctrl
->vp_clk_enable
= !!(csi2
->output
& CSI2_OUTPUT_CCDC
);
1180 /* media operations */
1181 static const struct media_entity_operations csi2_media_ops
= {
1182 .link_setup
= csi2_link_setup
,
1183 .link_validate
= v4l2_subdev_link_validate
,
1186 void omap3isp_csi2_unregister_entities(struct isp_csi2_device
*csi2
)
1188 v4l2_device_unregister_subdev(&csi2
->subdev
);
1189 omap3isp_video_unregister(&csi2
->video_out
);
1192 int omap3isp_csi2_register_entities(struct isp_csi2_device
*csi2
,
1193 struct v4l2_device
*vdev
)
1197 /* Register the subdev and video nodes. */
1198 ret
= v4l2_device_register_subdev(vdev
, &csi2
->subdev
);
1202 ret
= omap3isp_video_register(&csi2
->video_out
, vdev
);
1209 omap3isp_csi2_unregister_entities(csi2
);
1213 /* -----------------------------------------------------------------------------
1214 * ISP CSI2 initialisation and cleanup
1218 * csi2_init_entities - Initialize subdev and media entity.
1219 * @csi2: Pointer to csi2 structure.
1220 * return -ENOMEM or zero on success
1222 static int csi2_init_entities(struct isp_csi2_device
*csi2
)
1224 struct v4l2_subdev
*sd
= &csi2
->subdev
;
1225 struct media_pad
*pads
= csi2
->pads
;
1226 struct media_entity
*me
= &sd
->entity
;
1229 v4l2_subdev_init(sd
, &csi2_ops
);
1230 sd
->internal_ops
= &csi2_internal_ops
;
1231 strlcpy(sd
->name
, "OMAP3 ISP CSI2a", sizeof(sd
->name
));
1233 sd
->grp_id
= 1 << 16; /* group ID for isp subdevs */
1234 v4l2_set_subdevdata(sd
, csi2
);
1235 sd
->flags
|= V4L2_SUBDEV_FL_HAS_DEVNODE
;
1237 pads
[CSI2_PAD_SOURCE
].flags
= MEDIA_PAD_FL_SOURCE
;
1238 pads
[CSI2_PAD_SINK
].flags
= MEDIA_PAD_FL_SINK
1239 | MEDIA_PAD_FL_MUST_CONNECT
;
1241 me
->ops
= &csi2_media_ops
;
1242 ret
= media_entity_init(me
, CSI2_PADS_NUM
, pads
, 0);
1246 csi2_init_formats(sd
, NULL
);
1248 /* Video device node */
1249 csi2
->video_out
.type
= V4L2_BUF_TYPE_VIDEO_CAPTURE
;
1250 csi2
->video_out
.ops
= &csi2_ispvideo_ops
;
1251 csi2
->video_out
.bpl_alignment
= 32;
1252 csi2
->video_out
.bpl_zero_padding
= 1;
1253 csi2
->video_out
.bpl_max
= 0x1ffe0;
1254 csi2
->video_out
.isp
= csi2
->isp
;
1255 csi2
->video_out
.capture_mem
= PAGE_ALIGN(4096 * 4096) * 3;
1257 ret
= omap3isp_video_init(&csi2
->video_out
, "CSI2a");
1261 /* Connect the CSI2 subdev to the video node. */
1262 ret
= media_entity_create_link(&csi2
->subdev
.entity
, CSI2_PAD_SOURCE
,
1263 &csi2
->video_out
.video
.entity
, 0, 0);
1270 omap3isp_video_cleanup(&csi2
->video_out
);
1272 media_entity_cleanup(&csi2
->subdev
.entity
);
1277 * omap3isp_csi2_init - Routine for module driver init
1279 int omap3isp_csi2_init(struct isp_device
*isp
)
1281 struct isp_csi2_device
*csi2a
= &isp
->isp_csi2a
;
1282 struct isp_csi2_device
*csi2c
= &isp
->isp_csi2c
;
1286 csi2a
->available
= 1;
1287 csi2a
->regs1
= OMAP3_ISP_IOMEM_CSI2A_REGS1
;
1288 csi2a
->regs2
= OMAP3_ISP_IOMEM_CSI2A_REGS2
;
1289 csi2a
->phy
= &isp
->isp_csiphy2
;
1290 csi2a
->state
= ISP_PIPELINE_STREAM_STOPPED
;
1291 init_waitqueue_head(&csi2a
->wait
);
1293 ret
= csi2_init_entities(csi2a
);
1297 if (isp
->revision
== ISP_REVISION_15_0
) {
1299 csi2c
->available
= 1;
1300 csi2c
->regs1
= OMAP3_ISP_IOMEM_CSI2C_REGS1
;
1301 csi2c
->regs2
= OMAP3_ISP_IOMEM_CSI2C_REGS2
;
1302 csi2c
->phy
= &isp
->isp_csiphy1
;
1303 csi2c
->state
= ISP_PIPELINE_STREAM_STOPPED
;
1304 init_waitqueue_head(&csi2c
->wait
);
1311 * omap3isp_csi2_cleanup - Routine for module driver cleanup
1313 void omap3isp_csi2_cleanup(struct isp_device
*isp
)
1315 struct isp_csi2_device
*csi2a
= &isp
->isp_csi2a
;
1317 omap3isp_video_cleanup(&csi2a
->video_out
);
1318 media_entity_cleanup(&csi2a
->subdev
.entity
);