2 * Samsung S5P/EXYNOS4 SoC series FIMC (CAMIF) driver
4 * Copyright (C) 2010-2012 Samsung Electronics Co., Ltd.
5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation, either version 2 of the License,
10 * or (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/errno.h>
17 #include <linux/bug.h>
18 #include <linux/interrupt.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/list.h>
24 #include <linux/slab.h>
25 #include <linux/clk.h>
26 #include <media/v4l2-ioctl.h>
27 #include <media/videobuf2-core.h>
28 #include <media/videobuf2-dma-contig.h>
30 #include "fimc-core.h"
32 #include "fimc-mdevice.h"
34 static char *fimc_clocks
[MAX_FIMC_CLOCKS
] = {
38 static struct fimc_fmt fimc_formats
[] = {
41 .fourcc
= V4L2_PIX_FMT_RGB565
,
43 .color
= FIMC_FMT_RGB565
,
46 .flags
= FMT_FLAGS_M2M
,
49 .fourcc
= V4L2_PIX_FMT_BGR666
,
51 .color
= FIMC_FMT_RGB666
,
54 .flags
= FMT_FLAGS_M2M
,
56 .name
= "ARGB8888, 32 bpp",
57 .fourcc
= V4L2_PIX_FMT_RGB32
,
59 .color
= FIMC_FMT_RGB888
,
62 .flags
= FMT_FLAGS_M2M
| FMT_HAS_ALPHA
,
65 .fourcc
= V4L2_PIX_FMT_RGB555
,
67 .color
= FIMC_FMT_RGB555
,
70 .flags
= FMT_FLAGS_M2M_OUT
| FMT_HAS_ALPHA
,
73 .fourcc
= V4L2_PIX_FMT_RGB444
,
75 .color
= FIMC_FMT_RGB444
,
78 .flags
= FMT_FLAGS_M2M_OUT
| FMT_HAS_ALPHA
,
80 .name
= "YUV 4:2:2 packed, YCbYCr",
81 .fourcc
= V4L2_PIX_FMT_YUYV
,
83 .color
= FIMC_FMT_YCBYCR422
,
86 .mbus_code
= V4L2_MBUS_FMT_YUYV8_2X8
,
87 .flags
= FMT_FLAGS_M2M
| FMT_FLAGS_CAM
,
89 .name
= "YUV 4:2:2 packed, CbYCrY",
90 .fourcc
= V4L2_PIX_FMT_UYVY
,
92 .color
= FIMC_FMT_CBYCRY422
,
95 .mbus_code
= V4L2_MBUS_FMT_UYVY8_2X8
,
96 .flags
= FMT_FLAGS_M2M
| FMT_FLAGS_CAM
,
98 .name
= "YUV 4:2:2 packed, CrYCbY",
99 .fourcc
= V4L2_PIX_FMT_VYUY
,
101 .color
= FIMC_FMT_CRYCBY422
,
104 .mbus_code
= V4L2_MBUS_FMT_VYUY8_2X8
,
105 .flags
= FMT_FLAGS_M2M
| FMT_FLAGS_CAM
,
107 .name
= "YUV 4:2:2 packed, YCrYCb",
108 .fourcc
= V4L2_PIX_FMT_YVYU
,
110 .color
= FIMC_FMT_YCRYCB422
,
113 .mbus_code
= V4L2_MBUS_FMT_YVYU8_2X8
,
114 .flags
= FMT_FLAGS_M2M
| FMT_FLAGS_CAM
,
116 .name
= "YUV 4:2:2 planar, Y/Cb/Cr",
117 .fourcc
= V4L2_PIX_FMT_YUV422P
,
119 .color
= FIMC_FMT_YCBYCR422
,
122 .flags
= FMT_FLAGS_M2M
,
124 .name
= "YUV 4:2:2 planar, Y/CbCr",
125 .fourcc
= V4L2_PIX_FMT_NV16
,
127 .color
= FIMC_FMT_YCBYCR422
,
130 .flags
= FMT_FLAGS_M2M
,
132 .name
= "YUV 4:2:2 planar, Y/CrCb",
133 .fourcc
= V4L2_PIX_FMT_NV61
,
135 .color
= FIMC_FMT_YCRYCB422
,
138 .flags
= FMT_FLAGS_M2M
,
140 .name
= "YUV 4:2:0 planar, YCbCr",
141 .fourcc
= V4L2_PIX_FMT_YUV420
,
143 .color
= FIMC_FMT_YCBCR420
,
146 .flags
= FMT_FLAGS_M2M
,
148 .name
= "YUV 4:2:0 planar, Y/CbCr",
149 .fourcc
= V4L2_PIX_FMT_NV12
,
151 .color
= FIMC_FMT_YCBCR420
,
154 .flags
= FMT_FLAGS_M2M
,
156 .name
= "YUV 4:2:0 non-contig. 2p, Y/CbCr",
157 .fourcc
= V4L2_PIX_FMT_NV12M
,
158 .color
= FIMC_FMT_YCBCR420
,
162 .flags
= FMT_FLAGS_M2M
,
164 .name
= "YUV 4:2:0 non-contig. 3p, Y/Cb/Cr",
165 .fourcc
= V4L2_PIX_FMT_YUV420M
,
166 .color
= FIMC_FMT_YCBCR420
,
167 .depth
= { 8, 2, 2 },
170 .flags
= FMT_FLAGS_M2M
,
172 .name
= "YUV 4:2:0 non-contig. 2p, tiled",
173 .fourcc
= V4L2_PIX_FMT_NV12MT
,
174 .color
= FIMC_FMT_YCBCR420
,
178 .flags
= FMT_FLAGS_M2M
,
180 .name
= "JPEG encoded data",
181 .fourcc
= V4L2_PIX_FMT_JPEG
,
182 .color
= FIMC_FMT_JPEG
,
186 .mbus_code
= V4L2_MBUS_FMT_JPEG_1X8
,
187 .flags
= FMT_FLAGS_CAM
| FMT_FLAGS_COMPRESSED
,
189 .name
= "S5C73MX interleaved UYVY/JPEG",
190 .fourcc
= V4L2_PIX_FMT_S5C_UYVY_JPG
,
191 .color
= FIMC_FMT_YUYV_JPEG
,
195 .mdataplanes
= 0x2, /* plane 1 holds frame meta data */
196 .mbus_code
= V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8
,
197 .flags
= FMT_FLAGS_CAM
| FMT_FLAGS_COMPRESSED
,
201 struct fimc_fmt
*fimc_get_format(unsigned int index
)
203 if (index
>= ARRAY_SIZE(fimc_formats
))
206 return &fimc_formats
[index
];
209 int fimc_check_scaler_ratio(struct fimc_ctx
*ctx
, int sw
, int sh
,
210 int dw
, int dh
, int rotation
)
212 if (rotation
== 90 || rotation
== 270)
215 if (!ctx
->scaler
.enabled
)
216 return (sw
== dw
&& sh
== dh
) ? 0 : -EINVAL
;
218 if ((sw
>= SCALER_MAX_HRATIO
* dw
) || (sh
>= SCALER_MAX_VRATIO
* dh
))
224 static int fimc_get_scaler_factor(u32 src
, u32 tar
, u32
*ratio
, u32
*shift
)
233 if (src
>= tar
* tmp
) {
234 *shift
= sh
, *ratio
= tmp
;
238 *shift
= 0, *ratio
= 1;
242 int fimc_set_scaler_info(struct fimc_ctx
*ctx
)
244 struct fimc_variant
*variant
= ctx
->fimc_dev
->variant
;
245 struct device
*dev
= &ctx
->fimc_dev
->pdev
->dev
;
246 struct fimc_scaler
*sc
= &ctx
->scaler
;
247 struct fimc_frame
*s_frame
= &ctx
->s_frame
;
248 struct fimc_frame
*d_frame
= &ctx
->d_frame
;
252 if (ctx
->rotation
== 90 || ctx
->rotation
== 270) {
254 tx
= d_frame
->height
;
257 ty
= d_frame
->height
;
259 if (tx
<= 0 || ty
<= 0) {
260 dev_err(dev
, "Invalid target size: %dx%d", tx
, ty
);
265 sy
= s_frame
->height
;
266 if (sx
<= 0 || sy
<= 0) {
267 dev_err(dev
, "Invalid source size: %dx%d", sx
, sy
);
271 sc
->real_height
= sy
;
273 ret
= fimc_get_scaler_factor(sx
, tx
, &sc
->pre_hratio
, &sc
->hfactor
);
277 ret
= fimc_get_scaler_factor(sy
, ty
, &sc
->pre_vratio
, &sc
->vfactor
);
281 sc
->pre_dst_width
= sx
/ sc
->pre_hratio
;
282 sc
->pre_dst_height
= sy
/ sc
->pre_vratio
;
284 if (variant
->has_mainscaler_ext
) {
285 sc
->main_hratio
= (sx
<< 14) / (tx
<< sc
->hfactor
);
286 sc
->main_vratio
= (sy
<< 14) / (ty
<< sc
->vfactor
);
288 sc
->main_hratio
= (sx
<< 8) / (tx
<< sc
->hfactor
);
289 sc
->main_vratio
= (sy
<< 8) / (ty
<< sc
->vfactor
);
293 sc
->scaleup_h
= (tx
>= sx
) ? 1 : 0;
294 sc
->scaleup_v
= (ty
>= sy
) ? 1 : 0;
296 /* check to see if input and output size/format differ */
297 if (s_frame
->fmt
->color
== d_frame
->fmt
->color
298 && s_frame
->width
== d_frame
->width
299 && s_frame
->height
== d_frame
->height
)
307 static irqreturn_t
fimc_irq_handler(int irq
, void *priv
)
309 struct fimc_dev
*fimc
= priv
;
310 struct fimc_ctx
*ctx
;
312 fimc_hw_clear_irq(fimc
);
314 spin_lock(&fimc
->slock
);
316 if (test_and_clear_bit(ST_M2M_PEND
, &fimc
->state
)) {
317 if (test_and_clear_bit(ST_M2M_SUSPENDING
, &fimc
->state
)) {
318 set_bit(ST_M2M_SUSPENDED
, &fimc
->state
);
319 wake_up(&fimc
->irq_queue
);
322 ctx
= v4l2_m2m_get_curr_priv(fimc
->m2m
.m2m_dev
);
324 spin_unlock(&fimc
->slock
);
325 fimc_m2m_job_finish(ctx
, VB2_BUF_STATE_DONE
);
327 if (ctx
->state
& FIMC_CTX_SHUT
) {
328 ctx
->state
&= ~FIMC_CTX_SHUT
;
329 wake_up(&fimc
->irq_queue
);
333 } else if (test_bit(ST_CAPT_PEND
, &fimc
->state
)) {
334 int last_buf
= test_bit(ST_CAPT_JPEG
, &fimc
->state
) &&
335 fimc
->vid_cap
.reqbufs_count
== 1;
336 fimc_capture_irq_handler(fimc
, !last_buf
);
339 spin_unlock(&fimc
->slock
);
343 /* The color format (colplanes, memplanes) must be already configured. */
344 int fimc_prepare_addr(struct fimc_ctx
*ctx
, struct vb2_buffer
*vb
,
345 struct fimc_frame
*frame
, struct fimc_addr
*paddr
)
350 if (vb
== NULL
|| frame
== NULL
)
353 pix_size
= frame
->width
* frame
->height
;
355 dbg("memplanes= %d, colplanes= %d, pix_size= %d",
356 frame
->fmt
->memplanes
, frame
->fmt
->colplanes
, pix_size
);
358 paddr
->y
= vb2_dma_contig_plane_dma_addr(vb
, 0);
360 if (frame
->fmt
->memplanes
== 1) {
361 switch (frame
->fmt
->colplanes
) {
367 /* decompose Y into Y/Cb */
368 paddr
->cb
= (u32
)(paddr
->y
+ pix_size
);
372 paddr
->cb
= (u32
)(paddr
->y
+ pix_size
);
373 /* decompose Y into Y/Cb/Cr */
374 if (FIMC_FMT_YCBCR420
== frame
->fmt
->color
)
375 paddr
->cr
= (u32
)(paddr
->cb
378 paddr
->cr
= (u32
)(paddr
->cb
384 } else if (!frame
->fmt
->mdataplanes
) {
385 if (frame
->fmt
->memplanes
>= 2)
386 paddr
->cb
= vb2_dma_contig_plane_dma_addr(vb
, 1);
388 if (frame
->fmt
->memplanes
== 3)
389 paddr
->cr
= vb2_dma_contig_plane_dma_addr(vb
, 2);
392 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
393 paddr
->y
, paddr
->cb
, paddr
->cr
, ret
);
398 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
399 void fimc_set_yuv_order(struct fimc_ctx
*ctx
)
401 /* The one only mode supported in SoC. */
402 ctx
->in_order_2p
= FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB
;
403 ctx
->out_order_2p
= FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB
;
405 /* Set order for 1 plane input formats. */
406 switch (ctx
->s_frame
.fmt
->color
) {
407 case FIMC_FMT_YCRYCB422
:
408 ctx
->in_order_1p
= FIMC_REG_MSCTRL_ORDER422_CBYCRY
;
410 case FIMC_FMT_CBYCRY422
:
411 ctx
->in_order_1p
= FIMC_REG_MSCTRL_ORDER422_YCRYCB
;
413 case FIMC_FMT_CRYCBY422
:
414 ctx
->in_order_1p
= FIMC_REG_MSCTRL_ORDER422_YCBYCR
;
416 case FIMC_FMT_YCBYCR422
:
418 ctx
->in_order_1p
= FIMC_REG_MSCTRL_ORDER422_CRYCBY
;
421 dbg("ctx->in_order_1p= %d", ctx
->in_order_1p
);
423 switch (ctx
->d_frame
.fmt
->color
) {
424 case FIMC_FMT_YCRYCB422
:
425 ctx
->out_order_1p
= FIMC_REG_CIOCTRL_ORDER422_CBYCRY
;
427 case FIMC_FMT_CBYCRY422
:
428 ctx
->out_order_1p
= FIMC_REG_CIOCTRL_ORDER422_YCRYCB
;
430 case FIMC_FMT_CRYCBY422
:
431 ctx
->out_order_1p
= FIMC_REG_CIOCTRL_ORDER422_YCBYCR
;
433 case FIMC_FMT_YCBYCR422
:
435 ctx
->out_order_1p
= FIMC_REG_CIOCTRL_ORDER422_CRYCBY
;
438 dbg("ctx->out_order_1p= %d", ctx
->out_order_1p
);
441 void fimc_prepare_dma_offset(struct fimc_ctx
*ctx
, struct fimc_frame
*f
)
443 struct fimc_variant
*variant
= ctx
->fimc_dev
->variant
;
446 for (i
= 0; i
< f
->fmt
->colplanes
; i
++)
447 depth
+= f
->fmt
->depth
[i
];
449 f
->dma_offset
.y_h
= f
->offs_h
;
450 if (!variant
->pix_hoff
)
451 f
->dma_offset
.y_h
*= (depth
>> 3);
453 f
->dma_offset
.y_v
= f
->offs_v
;
455 f
->dma_offset
.cb_h
= f
->offs_h
;
456 f
->dma_offset
.cb_v
= f
->offs_v
;
458 f
->dma_offset
.cr_h
= f
->offs_h
;
459 f
->dma_offset
.cr_v
= f
->offs_v
;
461 if (!variant
->pix_hoff
) {
462 if (f
->fmt
->colplanes
== 3) {
463 f
->dma_offset
.cb_h
>>= 1;
464 f
->dma_offset
.cr_h
>>= 1;
466 if (f
->fmt
->color
== FIMC_FMT_YCBCR420
) {
467 f
->dma_offset
.cb_v
>>= 1;
468 f
->dma_offset
.cr_v
>>= 1;
472 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
473 f
->fmt
->color
, f
->dma_offset
.y_h
, f
->dma_offset
.y_v
);
476 static int fimc_set_color_effect(struct fimc_ctx
*ctx
, enum v4l2_colorfx colorfx
)
478 struct fimc_effect
*effect
= &ctx
->effect
;
481 case V4L2_COLORFX_NONE
:
482 effect
->type
= FIMC_REG_CIIMGEFF_FIN_BYPASS
;
484 case V4L2_COLORFX_BW
:
485 effect
->type
= FIMC_REG_CIIMGEFF_FIN_ARBITRARY
;
486 effect
->pat_cb
= 128;
487 effect
->pat_cr
= 128;
489 case V4L2_COLORFX_SEPIA
:
490 effect
->type
= FIMC_REG_CIIMGEFF_FIN_ARBITRARY
;
491 effect
->pat_cb
= 115;
492 effect
->pat_cr
= 145;
494 case V4L2_COLORFX_NEGATIVE
:
495 effect
->type
= FIMC_REG_CIIMGEFF_FIN_NEGATIVE
;
497 case V4L2_COLORFX_EMBOSS
:
498 effect
->type
= FIMC_REG_CIIMGEFF_FIN_EMBOSSING
;
500 case V4L2_COLORFX_ART_FREEZE
:
501 effect
->type
= FIMC_REG_CIIMGEFF_FIN_ARTFREEZE
;
503 case V4L2_COLORFX_SILHOUETTE
:
504 effect
->type
= FIMC_REG_CIIMGEFF_FIN_SILHOUETTE
;
506 case V4L2_COLORFX_SET_CBCR
:
507 effect
->type
= FIMC_REG_CIIMGEFF_FIN_ARBITRARY
;
508 effect
->pat_cb
= ctx
->ctrls
.colorfx_cbcr
->val
>> 8;
509 effect
->pat_cr
= ctx
->ctrls
.colorfx_cbcr
->val
& 0xff;
519 * V4L2 controls handling
521 #define ctrl_to_ctx(__ctrl) \
522 container_of((__ctrl)->handler, struct fimc_ctx, ctrls.handler)
524 static int __fimc_s_ctrl(struct fimc_ctx
*ctx
, struct v4l2_ctrl
*ctrl
)
526 struct fimc_dev
*fimc
= ctx
->fimc_dev
;
527 struct fimc_variant
*variant
= fimc
->variant
;
528 unsigned int flags
= FIMC_DST_FMT
| FIMC_SRC_FMT
;
531 if (ctrl
->flags
& V4L2_CTRL_FLAG_INACTIVE
)
536 ctx
->hflip
= ctrl
->val
;
540 ctx
->vflip
= ctrl
->val
;
543 case V4L2_CID_ROTATE
:
544 if (fimc_capture_pending(fimc
) ||
545 (ctx
->state
& flags
) == flags
) {
546 ret
= fimc_check_scaler_ratio(ctx
, ctx
->s_frame
.width
,
547 ctx
->s_frame
.height
, ctx
->d_frame
.width
,
548 ctx
->d_frame
.height
, ctrl
->val
);
552 if ((ctrl
->val
== 90 || ctrl
->val
== 270) &&
553 !variant
->has_out_rot
)
556 ctx
->rotation
= ctrl
->val
;
559 case V4L2_CID_ALPHA_COMPONENT
:
560 ctx
->d_frame
.alpha
= ctrl
->val
;
563 case V4L2_CID_COLORFX
:
564 ret
= fimc_set_color_effect(ctx
, ctrl
->val
);
570 ctx
->state
|= FIMC_PARAMS
;
571 set_bit(ST_CAPT_APPLY_CFG
, &fimc
->state
);
575 static int fimc_s_ctrl(struct v4l2_ctrl
*ctrl
)
577 struct fimc_ctx
*ctx
= ctrl_to_ctx(ctrl
);
581 spin_lock_irqsave(&ctx
->fimc_dev
->slock
, flags
);
582 ret
= __fimc_s_ctrl(ctx
, ctrl
);
583 spin_unlock_irqrestore(&ctx
->fimc_dev
->slock
, flags
);
588 static const struct v4l2_ctrl_ops fimc_ctrl_ops
= {
589 .s_ctrl
= fimc_s_ctrl
,
592 int fimc_ctrls_create(struct fimc_ctx
*ctx
)
594 struct fimc_variant
*variant
= ctx
->fimc_dev
->variant
;
595 unsigned int max_alpha
= fimc_get_alpha_mask(ctx
->d_frame
.fmt
);
596 struct fimc_ctrls
*ctrls
= &ctx
->ctrls
;
597 struct v4l2_ctrl_handler
*handler
= &ctrls
->handler
;
599 if (ctx
->ctrls
.ready
)
602 v4l2_ctrl_handler_init(handler
, 6);
604 ctrls
->rotate
= v4l2_ctrl_new_std(handler
, &fimc_ctrl_ops
,
605 V4L2_CID_ROTATE
, 0, 270, 90, 0);
606 ctrls
->hflip
= v4l2_ctrl_new_std(handler
, &fimc_ctrl_ops
,
607 V4L2_CID_HFLIP
, 0, 1, 1, 0);
608 ctrls
->vflip
= v4l2_ctrl_new_std(handler
, &fimc_ctrl_ops
,
609 V4L2_CID_VFLIP
, 0, 1, 1, 0);
611 if (variant
->has_alpha
)
612 ctrls
->alpha
= v4l2_ctrl_new_std(handler
, &fimc_ctrl_ops
,
613 V4L2_CID_ALPHA_COMPONENT
,
618 ctrls
->colorfx
= v4l2_ctrl_new_std_menu(handler
, &fimc_ctrl_ops
,
619 V4L2_CID_COLORFX
, V4L2_COLORFX_SET_CBCR
,
620 ~0x983f, V4L2_COLORFX_NONE
);
622 ctrls
->colorfx_cbcr
= v4l2_ctrl_new_std(handler
, &fimc_ctrl_ops
,
623 V4L2_CID_COLORFX_CBCR
, 0, 0xffff, 1, 0);
625 ctx
->effect
.type
= FIMC_REG_CIIMGEFF_FIN_BYPASS
;
627 if (!handler
->error
) {
628 v4l2_ctrl_cluster(2, &ctrls
->colorfx
);
632 return handler
->error
;
635 void fimc_ctrls_delete(struct fimc_ctx
*ctx
)
637 struct fimc_ctrls
*ctrls
= &ctx
->ctrls
;
640 v4l2_ctrl_handler_free(&ctrls
->handler
);
641 ctrls
->ready
= false;
646 void fimc_ctrls_activate(struct fimc_ctx
*ctx
, bool active
)
648 unsigned int has_alpha
= ctx
->d_frame
.fmt
->flags
& FMT_HAS_ALPHA
;
649 struct fimc_ctrls
*ctrls
= &ctx
->ctrls
;
654 mutex_lock(ctrls
->handler
.lock
);
655 v4l2_ctrl_activate(ctrls
->rotate
, active
);
656 v4l2_ctrl_activate(ctrls
->hflip
, active
);
657 v4l2_ctrl_activate(ctrls
->vflip
, active
);
658 v4l2_ctrl_activate(ctrls
->colorfx
, active
);
660 v4l2_ctrl_activate(ctrls
->alpha
, active
&& has_alpha
);
663 fimc_set_color_effect(ctx
, ctrls
->colorfx
->cur
.val
);
664 ctx
->rotation
= ctrls
->rotate
->val
;
665 ctx
->hflip
= ctrls
->hflip
->val
;
666 ctx
->vflip
= ctrls
->vflip
->val
;
668 ctx
->effect
.type
= FIMC_REG_CIIMGEFF_FIN_BYPASS
;
673 mutex_unlock(ctrls
->handler
.lock
);
676 /* Update maximum value of the alpha color control */
677 void fimc_alpha_ctrl_update(struct fimc_ctx
*ctx
)
679 struct fimc_dev
*fimc
= ctx
->fimc_dev
;
680 struct v4l2_ctrl
*ctrl
= ctx
->ctrls
.alpha
;
682 if (ctrl
== NULL
|| !fimc
->variant
->has_alpha
)
685 v4l2_ctrl_lock(ctrl
);
686 ctrl
->maximum
= fimc_get_alpha_mask(ctx
->d_frame
.fmt
);
688 if (ctrl
->cur
.val
> ctrl
->maximum
)
689 ctrl
->cur
.val
= ctrl
->maximum
;
691 v4l2_ctrl_unlock(ctrl
);
694 int fimc_fill_format(struct fimc_frame
*frame
, struct v4l2_format
*f
)
696 struct v4l2_pix_format_mplane
*pixm
= &f
->fmt
.pix_mp
;
699 pixm
->width
= frame
->o_width
;
700 pixm
->height
= frame
->o_height
;
701 pixm
->field
= V4L2_FIELD_NONE
;
702 pixm
->pixelformat
= frame
->fmt
->fourcc
;
703 pixm
->colorspace
= V4L2_COLORSPACE_JPEG
;
704 pixm
->num_planes
= frame
->fmt
->memplanes
;
706 for (i
= 0; i
< pixm
->num_planes
; ++i
) {
707 int bpl
= frame
->f_width
;
708 if (frame
->fmt
->colplanes
== 1) /* packed formats */
709 bpl
= (bpl
* frame
->fmt
->depth
[0]) / 8;
710 pixm
->plane_fmt
[i
].bytesperline
= bpl
;
712 if (frame
->fmt
->flags
& FMT_FLAGS_COMPRESSED
) {
713 pixm
->plane_fmt
[i
].sizeimage
= frame
->payload
[i
];
716 pixm
->plane_fmt
[i
].sizeimage
= (frame
->o_width
*
717 frame
->o_height
* frame
->fmt
->depth
[i
]) / 8;
722 void fimc_fill_frame(struct fimc_frame
*frame
, struct v4l2_format
*f
)
724 struct v4l2_pix_format_mplane
*pixm
= &f
->fmt
.pix_mp
;
726 frame
->f_width
= pixm
->plane_fmt
[0].bytesperline
;
727 if (frame
->fmt
->colplanes
== 1)
728 frame
->f_width
= (frame
->f_width
* 8) / frame
->fmt
->depth
[0];
729 frame
->f_height
= pixm
->height
;
730 frame
->width
= pixm
->width
;
731 frame
->height
= pixm
->height
;
732 frame
->o_width
= pixm
->width
;
733 frame
->o_height
= pixm
->height
;
739 * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
740 * @fmt: fimc pixel format description (input)
741 * @width: requested pixel width
742 * @height: requested pixel height
743 * @pix: multi-plane format to adjust
745 void fimc_adjust_mplane_format(struct fimc_fmt
*fmt
, u32 width
, u32 height
,
746 struct v4l2_pix_format_mplane
*pix
)
748 u32 bytesperline
= 0;
751 pix
->colorspace
= V4L2_COLORSPACE_JPEG
;
752 pix
->field
= V4L2_FIELD_NONE
;
753 pix
->num_planes
= fmt
->memplanes
;
754 pix
->pixelformat
= fmt
->fourcc
;
755 pix
->height
= height
;
758 for (i
= 0; i
< pix
->num_planes
; ++i
) {
759 struct v4l2_plane_pix_format
*plane_fmt
= &pix
->plane_fmt
[i
];
760 u32 bpl
= plane_fmt
->bytesperline
;
762 if (fmt
->colplanes
> 1 && (bpl
== 0 || bpl
< pix
->width
))
763 bpl
= pix
->width
; /* Planar */
765 if (fmt
->colplanes
== 1 && /* Packed */
766 (bpl
== 0 || ((bpl
* 8) / fmt
->depth
[i
]) < pix
->width
))
767 bpl
= (pix
->width
* fmt
->depth
[0]) / 8;
769 if (i
== 0) /* Same bytesperline for each plane. */
772 plane_fmt
->bytesperline
= bytesperline
;
773 plane_fmt
->sizeimage
= max((pix
->width
* pix
->height
*
774 fmt
->depth
[i
]) / 8, plane_fmt
->sizeimage
);
779 * fimc_find_format - lookup fimc color format by fourcc or media bus format
780 * @pixelformat: fourcc to match, ignored if null
781 * @mbus_code: media bus code to match, ignored if null
782 * @mask: the color flags to match
783 * @index: offset in the fimc_formats array, ignored if negative
785 struct fimc_fmt
*fimc_find_format(const u32
*pixelformat
, const u32
*mbus_code
,
786 unsigned int mask
, int index
)
788 struct fimc_fmt
*fmt
, *def_fmt
= NULL
;
792 if (index
>= (int)ARRAY_SIZE(fimc_formats
))
795 for (i
= 0; i
< ARRAY_SIZE(fimc_formats
); ++i
) {
796 fmt
= &fimc_formats
[i
];
797 if (!(fmt
->flags
& mask
))
799 if (pixelformat
&& fmt
->fourcc
== *pixelformat
)
801 if (mbus_code
&& fmt
->mbus_code
== *mbus_code
)
810 static void fimc_clk_put(struct fimc_dev
*fimc
)
813 for (i
= 0; i
< MAX_FIMC_CLOCKS
; i
++) {
814 if (IS_ERR_OR_NULL(fimc
->clock
[i
]))
816 clk_unprepare(fimc
->clock
[i
]);
817 clk_put(fimc
->clock
[i
]);
818 fimc
->clock
[i
] = NULL
;
822 static int fimc_clk_get(struct fimc_dev
*fimc
)
826 for (i
= 0; i
< MAX_FIMC_CLOCKS
; i
++) {
827 fimc
->clock
[i
] = clk_get(&fimc
->pdev
->dev
, fimc_clocks
[i
]);
828 if (IS_ERR(fimc
->clock
[i
]))
830 ret
= clk_prepare(fimc
->clock
[i
]);
832 clk_put(fimc
->clock
[i
]);
833 fimc
->clock
[i
] = NULL
;
840 dev_err(&fimc
->pdev
->dev
, "failed to get clock: %s\n",
845 static int fimc_m2m_suspend(struct fimc_dev
*fimc
)
850 spin_lock_irqsave(&fimc
->slock
, flags
);
851 if (!fimc_m2m_pending(fimc
)) {
852 spin_unlock_irqrestore(&fimc
->slock
, flags
);
855 clear_bit(ST_M2M_SUSPENDED
, &fimc
->state
);
856 set_bit(ST_M2M_SUSPENDING
, &fimc
->state
);
857 spin_unlock_irqrestore(&fimc
->slock
, flags
);
859 timeout
= wait_event_timeout(fimc
->irq_queue
,
860 test_bit(ST_M2M_SUSPENDED
, &fimc
->state
),
861 FIMC_SHUTDOWN_TIMEOUT
);
863 clear_bit(ST_M2M_SUSPENDING
, &fimc
->state
);
864 return timeout
== 0 ? -EAGAIN
: 0;
867 static int fimc_m2m_resume(struct fimc_dev
*fimc
)
871 spin_lock_irqsave(&fimc
->slock
, flags
);
872 /* Clear for full H/W setup in first run after resume */
873 fimc
->m2m
.ctx
= NULL
;
874 spin_unlock_irqrestore(&fimc
->slock
, flags
);
876 if (test_and_clear_bit(ST_M2M_SUSPENDED
, &fimc
->state
))
877 fimc_m2m_job_finish(fimc
->m2m
.ctx
,
878 VB2_BUF_STATE_ERROR
);
882 static int fimc_probe(struct platform_device
*pdev
)
884 struct fimc_drvdata
*drv_data
= fimc_get_drvdata(pdev
);
885 struct s5p_platform_fimc
*pdata
;
886 struct fimc_dev
*fimc
;
887 struct resource
*res
;
890 if (pdev
->id
>= drv_data
->num_entities
) {
891 dev_err(&pdev
->dev
, "Invalid platform device id: %d\n",
896 fimc
= devm_kzalloc(&pdev
->dev
, sizeof(*fimc
), GFP_KERNEL
);
902 fimc
->variant
= drv_data
->variant
[fimc
->id
];
904 pdata
= pdev
->dev
.platform_data
;
907 init_waitqueue_head(&fimc
->irq_queue
);
908 spin_lock_init(&fimc
->slock
);
909 mutex_init(&fimc
->lock
);
911 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
912 fimc
->regs
= devm_request_and_ioremap(&pdev
->dev
, res
);
913 if (fimc
->regs
== NULL
) {
914 dev_err(&pdev
->dev
, "Failed to obtain io memory\n");
918 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
920 dev_err(&pdev
->dev
, "Failed to get IRQ resource\n");
924 ret
= fimc_clk_get(fimc
);
927 clk_set_rate(fimc
->clock
[CLK_BUS
], drv_data
->lclk_frequency
);
928 clk_enable(fimc
->clock
[CLK_BUS
]);
930 ret
= devm_request_irq(&pdev
->dev
, res
->start
, fimc_irq_handler
,
931 0, dev_name(&pdev
->dev
), fimc
);
933 dev_err(&pdev
->dev
, "failed to install irq (%d)\n", ret
);
937 ret
= fimc_initialize_capture_subdev(fimc
);
941 platform_set_drvdata(pdev
, fimc
);
942 pm_runtime_enable(&pdev
->dev
);
943 ret
= pm_runtime_get_sync(&pdev
->dev
);
946 /* Initialize contiguous memory allocator */
947 fimc
->alloc_ctx
= vb2_dma_contig_init_ctx(&pdev
->dev
);
948 if (IS_ERR(fimc
->alloc_ctx
)) {
949 ret
= PTR_ERR(fimc
->alloc_ctx
);
953 dev_dbg(&pdev
->dev
, "FIMC.%d registered successfully\n", fimc
->id
);
955 pm_runtime_put(&pdev
->dev
);
958 pm_runtime_put(&pdev
->dev
);
960 fimc_unregister_capture_subdev(fimc
);
966 static int fimc_runtime_resume(struct device
*dev
)
968 struct fimc_dev
*fimc
= dev_get_drvdata(dev
);
970 dbg("fimc%d: state: 0x%lx", fimc
->id
, fimc
->state
);
972 /* Enable clocks and perform basic initalization */
973 clk_enable(fimc
->clock
[CLK_GATE
]);
976 /* Resume the capture or mem-to-mem device */
977 if (fimc_capture_busy(fimc
))
978 return fimc_capture_resume(fimc
);
980 return fimc_m2m_resume(fimc
);
983 static int fimc_runtime_suspend(struct device
*dev
)
985 struct fimc_dev
*fimc
= dev_get_drvdata(dev
);
988 if (fimc_capture_busy(fimc
))
989 ret
= fimc_capture_suspend(fimc
);
991 ret
= fimc_m2m_suspend(fimc
);
993 clk_disable(fimc
->clock
[CLK_GATE
]);
995 dbg("fimc%d: state: 0x%lx", fimc
->id
, fimc
->state
);
999 #ifdef CONFIG_PM_SLEEP
1000 static int fimc_resume(struct device
*dev
)
1002 struct fimc_dev
*fimc
= dev_get_drvdata(dev
);
1003 unsigned long flags
;
1005 dbg("fimc%d: state: 0x%lx", fimc
->id
, fimc
->state
);
1007 /* Do not resume if the device was idle before system suspend */
1008 spin_lock_irqsave(&fimc
->slock
, flags
);
1009 if (!test_and_clear_bit(ST_LPM
, &fimc
->state
) ||
1010 (!fimc_m2m_active(fimc
) && !fimc_capture_busy(fimc
))) {
1011 spin_unlock_irqrestore(&fimc
->slock
, flags
);
1014 fimc_hw_reset(fimc
);
1015 spin_unlock_irqrestore(&fimc
->slock
, flags
);
1017 if (fimc_capture_busy(fimc
))
1018 return fimc_capture_resume(fimc
);
1020 return fimc_m2m_resume(fimc
);
1023 static int fimc_suspend(struct device
*dev
)
1025 struct fimc_dev
*fimc
= dev_get_drvdata(dev
);
1027 dbg("fimc%d: state: 0x%lx", fimc
->id
, fimc
->state
);
1029 if (test_and_set_bit(ST_LPM
, &fimc
->state
))
1031 if (fimc_capture_busy(fimc
))
1032 return fimc_capture_suspend(fimc
);
1034 return fimc_m2m_suspend(fimc
);
1036 #endif /* CONFIG_PM_SLEEP */
1038 static int __devexit
fimc_remove(struct platform_device
*pdev
)
1040 struct fimc_dev
*fimc
= platform_get_drvdata(pdev
);
1042 pm_runtime_disable(&pdev
->dev
);
1043 pm_runtime_set_suspended(&pdev
->dev
);
1045 fimc_unregister_capture_subdev(fimc
);
1046 vb2_dma_contig_cleanup_ctx(fimc
->alloc_ctx
);
1048 clk_disable(fimc
->clock
[CLK_BUS
]);
1051 dev_info(&pdev
->dev
, "driver unloaded\n");
1055 /* Image pixel limits, similar across several FIMC HW revisions. */
1056 static struct fimc_pix_limit s5p_pix_limit
[4] = {
1058 .scaler_en_w
= 3264,
1059 .scaler_dis_w
= 8192,
1060 .in_rot_en_h
= 1920,
1061 .in_rot_dis_w
= 8192,
1062 .out_rot_en_w
= 1920,
1063 .out_rot_dis_w
= 4224,
1066 .scaler_en_w
= 4224,
1067 .scaler_dis_w
= 8192,
1068 .in_rot_en_h
= 1920,
1069 .in_rot_dis_w
= 8192,
1070 .out_rot_en_w
= 1920,
1071 .out_rot_dis_w
= 4224,
1074 .scaler_en_w
= 1920,
1075 .scaler_dis_w
= 8192,
1076 .in_rot_en_h
= 1280,
1077 .in_rot_dis_w
= 8192,
1078 .out_rot_en_w
= 1280,
1079 .out_rot_dis_w
= 1920,
1082 .scaler_en_w
= 1920,
1083 .scaler_dis_w
= 8192,
1084 .in_rot_en_h
= 1366,
1085 .in_rot_dis_w
= 8192,
1086 .out_rot_en_w
= 1366,
1087 .out_rot_dis_w
= 1920,
1091 static struct fimc_variant fimc0_variant_s5p
= {
1095 .min_inp_pixsize
= 16,
1096 .min_out_pixsize
= 16,
1097 .hor_offs_align
= 8,
1098 .min_vsize_align
= 16,
1100 .pix_limit
= &s5p_pix_limit
[0],
1103 static struct fimc_variant fimc2_variant_s5p
= {
1105 .min_inp_pixsize
= 16,
1106 .min_out_pixsize
= 16,
1107 .hor_offs_align
= 8,
1108 .min_vsize_align
= 16,
1110 .pix_limit
= &s5p_pix_limit
[1],
1113 static struct fimc_variant fimc0_variant_s5pv210
= {
1118 .min_inp_pixsize
= 16,
1119 .min_out_pixsize
= 16,
1120 .hor_offs_align
= 8,
1121 .min_vsize_align
= 16,
1123 .pix_limit
= &s5p_pix_limit
[1],
1126 static struct fimc_variant fimc1_variant_s5pv210
= {
1131 .has_mainscaler_ext
= 1,
1132 .min_inp_pixsize
= 16,
1133 .min_out_pixsize
= 16,
1134 .hor_offs_align
= 1,
1135 .min_vsize_align
= 1,
1137 .pix_limit
= &s5p_pix_limit
[2],
1140 static struct fimc_variant fimc2_variant_s5pv210
= {
1143 .min_inp_pixsize
= 16,
1144 .min_out_pixsize
= 16,
1145 .hor_offs_align
= 8,
1146 .min_vsize_align
= 16,
1148 .pix_limit
= &s5p_pix_limit
[2],
1151 static struct fimc_variant fimc0_variant_exynos4
= {
1157 .has_mainscaler_ext
= 1,
1159 .min_inp_pixsize
= 16,
1160 .min_out_pixsize
= 16,
1161 .hor_offs_align
= 2,
1162 .min_vsize_align
= 1,
1163 .out_buf_count
= 32,
1164 .pix_limit
= &s5p_pix_limit
[1],
1167 static struct fimc_variant fimc3_variant_exynos4
= {
1171 .has_mainscaler_ext
= 1,
1173 .min_inp_pixsize
= 16,
1174 .min_out_pixsize
= 16,
1175 .hor_offs_align
= 2,
1176 .min_vsize_align
= 1,
1177 .out_buf_count
= 32,
1178 .pix_limit
= &s5p_pix_limit
[3],
1182 static struct fimc_drvdata fimc_drvdata_s5p
= {
1184 [0] = &fimc0_variant_s5p
,
1185 [1] = &fimc0_variant_s5p
,
1186 [2] = &fimc2_variant_s5p
,
1189 .lclk_frequency
= 133000000UL,
1192 /* S5PV210, S5PC110 */
1193 static struct fimc_drvdata fimc_drvdata_s5pv210
= {
1195 [0] = &fimc0_variant_s5pv210
,
1196 [1] = &fimc1_variant_s5pv210
,
1197 [2] = &fimc2_variant_s5pv210
,
1200 .lclk_frequency
= 166000000UL,
1203 /* EXYNOS4210, S5PV310, S5PC210 */
1204 static struct fimc_drvdata fimc_drvdata_exynos4
= {
1206 [0] = &fimc0_variant_exynos4
,
1207 [1] = &fimc0_variant_exynos4
,
1208 [2] = &fimc0_variant_exynos4
,
1209 [3] = &fimc3_variant_exynos4
,
1212 .lclk_frequency
= 166000000UL,
1215 static struct platform_device_id fimc_driver_ids
[] = {
1218 .driver_data
= (unsigned long)&fimc_drvdata_s5p
,
1220 .name
= "s5pv210-fimc",
1221 .driver_data
= (unsigned long)&fimc_drvdata_s5pv210
,
1223 .name
= "exynos4-fimc",
1224 .driver_data
= (unsigned long)&fimc_drvdata_exynos4
,
1228 MODULE_DEVICE_TABLE(platform
, fimc_driver_ids
);
1230 static const struct dev_pm_ops fimc_pm_ops
= {
1231 SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend
, fimc_resume
)
1232 SET_RUNTIME_PM_OPS(fimc_runtime_suspend
, fimc_runtime_resume
, NULL
)
1235 static struct platform_driver fimc_driver
= {
1236 .probe
= fimc_probe
,
1237 .remove
= __devexit_p(fimc_remove
),
1238 .id_table
= fimc_driver_ids
,
1240 .name
= FIMC_MODULE_NAME
,
1241 .owner
= THIS_MODULE
,
1246 int __init
fimc_register_driver(void)
1248 return platform_driver_register(&fimc_driver
);
1251 void __exit
fimc_unregister_driver(void)
1253 platform_driver_unregister(&fimc_driver
);