2 * Register interface file for Samsung Camera Interface (FIMC) driver
4 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
5 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <media/s5p_fimc.h>
17 #include "fimc-core.h"
20 void fimc_hw_reset(struct fimc_dev
*dev
)
24 cfg
= readl(dev
->regs
+ FIMC_REG_CISRCFMT
);
25 cfg
|= FIMC_REG_CISRCFMT_ITU601_8BIT
;
26 writel(cfg
, dev
->regs
+ FIMC_REG_CISRCFMT
);
29 cfg
= readl(dev
->regs
+ FIMC_REG_CIGCTRL
);
30 cfg
|= (FIMC_REG_CIGCTRL_SWRST
| FIMC_REG_CIGCTRL_IRQ_LEVEL
);
31 writel(cfg
, dev
->regs
+ FIMC_REG_CIGCTRL
);
34 cfg
= readl(dev
->regs
+ FIMC_REG_CIGCTRL
);
35 cfg
&= ~FIMC_REG_CIGCTRL_SWRST
;
36 writel(cfg
, dev
->regs
+ FIMC_REG_CIGCTRL
);
38 if (dev
->variant
->out_buf_count
> 4)
39 fimc_hw_set_dma_seq(dev
, 0xF);
42 static u32
fimc_hw_get_in_flip(struct fimc_ctx
*ctx
)
44 u32 flip
= FIMC_REG_MSCTRL_FLIP_NORMAL
;
47 flip
= FIMC_REG_MSCTRL_FLIP_X_MIRROR
;
49 flip
= FIMC_REG_MSCTRL_FLIP_Y_MIRROR
;
51 if (ctx
->rotation
<= 90)
54 return (flip
^ FIMC_REG_MSCTRL_FLIP_180
) & FIMC_REG_MSCTRL_FLIP_180
;
57 static u32
fimc_hw_get_target_flip(struct fimc_ctx
*ctx
)
59 u32 flip
= FIMC_REG_CITRGFMT_FLIP_NORMAL
;
62 flip
|= FIMC_REG_CITRGFMT_FLIP_X_MIRROR
;
64 flip
|= FIMC_REG_CITRGFMT_FLIP_Y_MIRROR
;
66 if (ctx
->rotation
<= 90)
69 return (flip
^ FIMC_REG_CITRGFMT_FLIP_180
) & FIMC_REG_CITRGFMT_FLIP_180
;
72 void fimc_hw_set_rotation(struct fimc_ctx
*ctx
)
75 struct fimc_dev
*dev
= ctx
->fimc_dev
;
77 cfg
= readl(dev
->regs
+ FIMC_REG_CITRGFMT
);
78 cfg
&= ~(FIMC_REG_CITRGFMT_INROT90
| FIMC_REG_CITRGFMT_OUTROT90
|
79 FIMC_REG_CITRGFMT_FLIP_180
);
82 * The input and output rotator cannot work simultaneously.
83 * Use the output rotator in output DMA mode or the input rotator
84 * in direct fifo output mode.
86 if (ctx
->rotation
== 90 || ctx
->rotation
== 270) {
87 if (ctx
->out_path
== FIMC_IO_LCDFIFO
)
88 cfg
|= FIMC_REG_CITRGFMT_INROT90
;
90 cfg
|= FIMC_REG_CITRGFMT_OUTROT90
;
93 if (ctx
->out_path
== FIMC_IO_DMA
) {
94 cfg
|= fimc_hw_get_target_flip(ctx
);
95 writel(cfg
, dev
->regs
+ FIMC_REG_CITRGFMT
);
98 flip
= readl(dev
->regs
+ FIMC_REG_MSCTRL
);
99 flip
&= ~FIMC_REG_MSCTRL_FLIP_MASK
;
100 flip
|= fimc_hw_get_in_flip(ctx
);
101 writel(flip
, dev
->regs
+ FIMC_REG_MSCTRL
);
105 void fimc_hw_set_target_format(struct fimc_ctx
*ctx
)
108 struct fimc_dev
*dev
= ctx
->fimc_dev
;
109 struct fimc_frame
*frame
= &ctx
->d_frame
;
111 dbg("w= %d, h= %d color: %d", frame
->width
,
112 frame
->height
, frame
->fmt
->color
);
114 cfg
= readl(dev
->regs
+ FIMC_REG_CITRGFMT
);
115 cfg
&= ~(FIMC_REG_CITRGFMT_FMT_MASK
| FIMC_REG_CITRGFMT_HSIZE_MASK
|
116 FIMC_REG_CITRGFMT_VSIZE_MASK
);
118 switch (frame
->fmt
->color
) {
119 case FIMC_FMT_RGB444
...FIMC_FMT_RGB888
:
120 cfg
|= FIMC_REG_CITRGFMT_RGB
;
122 case FIMC_FMT_YCBCR420
:
123 cfg
|= FIMC_REG_CITRGFMT_YCBCR420
;
125 case FIMC_FMT_YCBYCR422
...FIMC_FMT_CRYCBY422
:
126 if (frame
->fmt
->colplanes
== 1)
127 cfg
|= FIMC_REG_CITRGFMT_YCBCR422_1P
;
129 cfg
|= FIMC_REG_CITRGFMT_YCBCR422
;
135 if (ctx
->rotation
== 90 || ctx
->rotation
== 270)
136 cfg
|= (frame
->height
<< 16) | frame
->width
;
138 cfg
|= (frame
->width
<< 16) | frame
->height
;
140 writel(cfg
, dev
->regs
+ FIMC_REG_CITRGFMT
);
142 cfg
= readl(dev
->regs
+ FIMC_REG_CITAREA
);
143 cfg
&= ~FIMC_REG_CITAREA_MASK
;
144 cfg
|= (frame
->width
* frame
->height
);
145 writel(cfg
, dev
->regs
+ FIMC_REG_CITAREA
);
148 static void fimc_hw_set_out_dma_size(struct fimc_ctx
*ctx
)
150 struct fimc_dev
*dev
= ctx
->fimc_dev
;
151 struct fimc_frame
*frame
= &ctx
->d_frame
;
154 cfg
= (frame
->f_height
<< 16) | frame
->f_width
;
155 writel(cfg
, dev
->regs
+ FIMC_REG_ORGOSIZE
);
157 /* Select color space conversion equation (HD/SD size).*/
158 cfg
= readl(dev
->regs
+ FIMC_REG_CIGCTRL
);
159 if (frame
->f_width
>= 1280) /* HD */
160 cfg
|= FIMC_REG_CIGCTRL_CSC_ITU601_709
;
162 cfg
&= ~FIMC_REG_CIGCTRL_CSC_ITU601_709
;
163 writel(cfg
, dev
->regs
+ FIMC_REG_CIGCTRL
);
167 void fimc_hw_set_out_dma(struct fimc_ctx
*ctx
)
169 struct fimc_dev
*dev
= ctx
->fimc_dev
;
170 struct fimc_frame
*frame
= &ctx
->d_frame
;
171 struct fimc_dma_offset
*offset
= &frame
->dma_offset
;
172 struct fimc_fmt
*fmt
= frame
->fmt
;
175 /* Set the input dma offsets. */
176 cfg
= (offset
->y_v
<< 16) | offset
->y_h
;
177 writel(cfg
, dev
->regs
+ FIMC_REG_CIOYOFF
);
179 cfg
= (offset
->cb_v
<< 16) | offset
->cb_h
;
180 writel(cfg
, dev
->regs
+ FIMC_REG_CIOCBOFF
);
182 cfg
= (offset
->cr_v
<< 16) | offset
->cr_h
;
183 writel(cfg
, dev
->regs
+ FIMC_REG_CIOCROFF
);
185 fimc_hw_set_out_dma_size(ctx
);
187 /* Configure chroma components order. */
188 cfg
= readl(dev
->regs
+ FIMC_REG_CIOCTRL
);
190 cfg
&= ~(FIMC_REG_CIOCTRL_ORDER2P_MASK
|
191 FIMC_REG_CIOCTRL_ORDER422_MASK
|
192 FIMC_REG_CIOCTRL_YCBCR_PLANE_MASK
|
193 FIMC_REG_CIOCTRL_RGB16FMT_MASK
);
195 if (fmt
->colplanes
== 1)
196 cfg
|= ctx
->out_order_1p
;
197 else if (fmt
->colplanes
== 2)
198 cfg
|= ctx
->out_order_2p
| FIMC_REG_CIOCTRL_YCBCR_2PLANE
;
199 else if (fmt
->colplanes
== 3)
200 cfg
|= FIMC_REG_CIOCTRL_YCBCR_3PLANE
;
202 if (fmt
->color
== FIMC_FMT_RGB565
)
203 cfg
|= FIMC_REG_CIOCTRL_RGB565
;
204 else if (fmt
->color
== FIMC_FMT_RGB555
)
205 cfg
|= FIMC_REG_CIOCTRL_ARGB1555
;
206 else if (fmt
->color
== FIMC_FMT_RGB444
)
207 cfg
|= FIMC_REG_CIOCTRL_ARGB4444
;
209 writel(cfg
, dev
->regs
+ FIMC_REG_CIOCTRL
);
212 static void fimc_hw_en_autoload(struct fimc_dev
*dev
, int enable
)
214 u32 cfg
= readl(dev
->regs
+ FIMC_REG_ORGISIZE
);
216 cfg
|= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN
;
218 cfg
&= ~FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN
;
219 writel(cfg
, dev
->regs
+ FIMC_REG_ORGISIZE
);
222 void fimc_hw_en_lastirq(struct fimc_dev
*dev
, int enable
)
224 u32 cfg
= readl(dev
->regs
+ FIMC_REG_CIOCTRL
);
226 cfg
|= FIMC_REG_CIOCTRL_LASTIRQ_ENABLE
;
228 cfg
&= ~FIMC_REG_CIOCTRL_LASTIRQ_ENABLE
;
229 writel(cfg
, dev
->regs
+ FIMC_REG_CIOCTRL
);
232 void fimc_hw_set_prescaler(struct fimc_ctx
*ctx
)
234 struct fimc_dev
*dev
= ctx
->fimc_dev
;
235 struct fimc_scaler
*sc
= &ctx
->scaler
;
238 shfactor
= 10 - (sc
->hfactor
+ sc
->vfactor
);
239 cfg
= shfactor
<< 28;
241 cfg
|= (sc
->pre_hratio
<< 16) | sc
->pre_vratio
;
242 writel(cfg
, dev
->regs
+ FIMC_REG_CISCPRERATIO
);
244 cfg
= (sc
->pre_dst_width
<< 16) | sc
->pre_dst_height
;
245 writel(cfg
, dev
->regs
+ FIMC_REG_CISCPREDST
);
248 static void fimc_hw_set_scaler(struct fimc_ctx
*ctx
)
250 struct fimc_dev
*dev
= ctx
->fimc_dev
;
251 struct fimc_scaler
*sc
= &ctx
->scaler
;
252 struct fimc_frame
*src_frame
= &ctx
->s_frame
;
253 struct fimc_frame
*dst_frame
= &ctx
->d_frame
;
255 u32 cfg
= readl(dev
->regs
+ FIMC_REG_CISCCTRL
);
257 cfg
&= ~(FIMC_REG_CISCCTRL_CSCR2Y_WIDE
| FIMC_REG_CISCCTRL_CSCY2R_WIDE
|
258 FIMC_REG_CISCCTRL_SCALEUP_H
| FIMC_REG_CISCCTRL_SCALEUP_V
|
259 FIMC_REG_CISCCTRL_SCALERBYPASS
| FIMC_REG_CISCCTRL_ONE2ONE
|
260 FIMC_REG_CISCCTRL_INRGB_FMT_MASK
| FIMC_REG_CISCCTRL_OUTRGB_FMT_MASK
|
261 FIMC_REG_CISCCTRL_INTERLACE
| FIMC_REG_CISCCTRL_RGB_EXT
);
263 if (!(ctx
->flags
& FIMC_COLOR_RANGE_NARROW
))
264 cfg
|= (FIMC_REG_CISCCTRL_CSCR2Y_WIDE
|
265 FIMC_REG_CISCCTRL_CSCY2R_WIDE
);
268 cfg
|= FIMC_REG_CISCCTRL_SCALERBYPASS
;
271 cfg
|= FIMC_REG_CISCCTRL_SCALEUP_H
;
274 cfg
|= FIMC_REG_CISCCTRL_SCALEUP_V
;
277 cfg
|= FIMC_REG_CISCCTRL_ONE2ONE
;
279 if (ctx
->in_path
== FIMC_IO_DMA
) {
280 switch (src_frame
->fmt
->color
) {
281 case FIMC_FMT_RGB565
:
282 cfg
|= FIMC_REG_CISCCTRL_INRGB_FMT_RGB565
;
284 case FIMC_FMT_RGB666
:
285 cfg
|= FIMC_REG_CISCCTRL_INRGB_FMT_RGB666
;
287 case FIMC_FMT_RGB888
:
288 cfg
|= FIMC_REG_CISCCTRL_INRGB_FMT_RGB888
;
293 if (ctx
->out_path
== FIMC_IO_DMA
) {
294 u32 color
= dst_frame
->fmt
->color
;
296 if (color
>= FIMC_FMT_RGB444
&& color
<= FIMC_FMT_RGB565
)
297 cfg
|= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565
;
298 else if (color
== FIMC_FMT_RGB666
)
299 cfg
|= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666
;
300 else if (color
== FIMC_FMT_RGB888
)
301 cfg
|= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888
;
303 cfg
|= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888
;
305 if (ctx
->flags
& FIMC_SCAN_MODE_INTERLACED
)
306 cfg
|= FIMC_REG_CISCCTRL_INTERLACE
;
309 writel(cfg
, dev
->regs
+ FIMC_REG_CISCCTRL
);
312 void fimc_hw_set_mainscaler(struct fimc_ctx
*ctx
)
314 struct fimc_dev
*dev
= ctx
->fimc_dev
;
315 struct fimc_variant
*variant
= dev
->variant
;
316 struct fimc_scaler
*sc
= &ctx
->scaler
;
319 dbg("main_hratio= 0x%X main_vratio= 0x%X",
320 sc
->main_hratio
, sc
->main_vratio
);
322 fimc_hw_set_scaler(ctx
);
324 cfg
= readl(dev
->regs
+ FIMC_REG_CISCCTRL
);
325 cfg
&= ~(FIMC_REG_CISCCTRL_MHRATIO_MASK
|
326 FIMC_REG_CISCCTRL_MVRATIO_MASK
);
328 if (variant
->has_mainscaler_ext
) {
329 cfg
|= FIMC_REG_CISCCTRL_MHRATIO_EXT(sc
->main_hratio
);
330 cfg
|= FIMC_REG_CISCCTRL_MVRATIO_EXT(sc
->main_vratio
);
331 writel(cfg
, dev
->regs
+ FIMC_REG_CISCCTRL
);
333 cfg
= readl(dev
->regs
+ FIMC_REG_CIEXTEN
);
335 cfg
&= ~(FIMC_REG_CIEXTEN_MVRATIO_EXT_MASK
|
336 FIMC_REG_CIEXTEN_MHRATIO_EXT_MASK
);
337 cfg
|= FIMC_REG_CIEXTEN_MHRATIO_EXT(sc
->main_hratio
);
338 cfg
|= FIMC_REG_CIEXTEN_MVRATIO_EXT(sc
->main_vratio
);
339 writel(cfg
, dev
->regs
+ FIMC_REG_CIEXTEN
);
341 cfg
|= FIMC_REG_CISCCTRL_MHRATIO(sc
->main_hratio
);
342 cfg
|= FIMC_REG_CISCCTRL_MVRATIO(sc
->main_vratio
);
343 writel(cfg
, dev
->regs
+ FIMC_REG_CISCCTRL
);
347 void fimc_hw_en_capture(struct fimc_ctx
*ctx
)
349 struct fimc_dev
*dev
= ctx
->fimc_dev
;
351 u32 cfg
= readl(dev
->regs
+ FIMC_REG_CIIMGCPT
);
353 if (ctx
->out_path
== FIMC_IO_DMA
) {
355 cfg
|= FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE
|
356 FIMC_REG_CIIMGCPT_IMGCPTEN
;
358 /* Continuous frame capture mode (freerun). */
359 cfg
&= ~(FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE
|
360 FIMC_REG_CIIMGCPT_CPT_FRMOD_CNT
);
361 cfg
|= FIMC_REG_CIIMGCPT_IMGCPTEN
;
364 if (ctx
->scaler
.enabled
)
365 cfg
|= FIMC_REG_CIIMGCPT_IMGCPTEN_SC
;
367 cfg
|= FIMC_REG_CIIMGCPT_IMGCPTEN
;
368 writel(cfg
, dev
->regs
+ FIMC_REG_CIIMGCPT
);
371 void fimc_hw_set_effect(struct fimc_ctx
*ctx
)
373 struct fimc_dev
*dev
= ctx
->fimc_dev
;
374 struct fimc_effect
*effect
= &ctx
->effect
;
377 if (effect
->type
!= FIMC_REG_CIIMGEFF_FIN_BYPASS
) {
378 cfg
|= FIMC_REG_CIIMGEFF_IE_SC_AFTER
|
379 FIMC_REG_CIIMGEFF_IE_ENABLE
;
381 if (effect
->type
== FIMC_REG_CIIMGEFF_FIN_ARBITRARY
)
382 cfg
|= (effect
->pat_cb
<< 13) | effect
->pat_cr
;
385 writel(cfg
, dev
->regs
+ FIMC_REG_CIIMGEFF
);
388 void fimc_hw_set_rgb_alpha(struct fimc_ctx
*ctx
)
390 struct fimc_dev
*dev
= ctx
->fimc_dev
;
391 struct fimc_frame
*frame
= &ctx
->d_frame
;
394 if (!(frame
->fmt
->flags
& FMT_HAS_ALPHA
))
397 cfg
= readl(dev
->regs
+ FIMC_REG_CIOCTRL
);
398 cfg
&= ~FIMC_REG_CIOCTRL_ALPHA_OUT_MASK
;
399 cfg
|= (frame
->alpha
<< 4);
400 writel(cfg
, dev
->regs
+ FIMC_REG_CIOCTRL
);
403 static void fimc_hw_set_in_dma_size(struct fimc_ctx
*ctx
)
405 struct fimc_dev
*dev
= ctx
->fimc_dev
;
406 struct fimc_frame
*frame
= &ctx
->s_frame
;
410 if (FIMC_IO_LCDFIFO
== ctx
->out_path
)
411 cfg_r
|= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN
;
413 cfg_o
|= (frame
->f_height
<< 16) | frame
->f_width
;
414 cfg_r
|= (frame
->height
<< 16) | frame
->width
;
416 writel(cfg_o
, dev
->regs
+ FIMC_REG_ORGISIZE
);
417 writel(cfg_r
, dev
->regs
+ FIMC_REG_CIREAL_ISIZE
);
420 void fimc_hw_set_in_dma(struct fimc_ctx
*ctx
)
422 struct fimc_dev
*dev
= ctx
->fimc_dev
;
423 struct fimc_frame
*frame
= &ctx
->s_frame
;
424 struct fimc_dma_offset
*offset
= &frame
->dma_offset
;
427 /* Set the pixel offsets. */
428 cfg
= (offset
->y_v
<< 16) | offset
->y_h
;
429 writel(cfg
, dev
->regs
+ FIMC_REG_CIIYOFF
);
431 cfg
= (offset
->cb_v
<< 16) | offset
->cb_h
;
432 writel(cfg
, dev
->regs
+ FIMC_REG_CIICBOFF
);
434 cfg
= (offset
->cr_v
<< 16) | offset
->cr_h
;
435 writel(cfg
, dev
->regs
+ FIMC_REG_CIICROFF
);
437 /* Input original and real size. */
438 fimc_hw_set_in_dma_size(ctx
);
440 /* Use DMA autoload only in FIFO mode. */
441 fimc_hw_en_autoload(dev
, ctx
->out_path
== FIMC_IO_LCDFIFO
);
443 /* Set the input DMA to process single frame only. */
444 cfg
= readl(dev
->regs
+ FIMC_REG_MSCTRL
);
445 cfg
&= ~(FIMC_REG_MSCTRL_INFORMAT_MASK
446 | FIMC_REG_MSCTRL_IN_BURST_COUNT_MASK
447 | FIMC_REG_MSCTRL_INPUT_MASK
448 | FIMC_REG_MSCTRL_C_INT_IN_MASK
449 | FIMC_REG_MSCTRL_2P_IN_ORDER_MASK
);
451 cfg
|= (FIMC_REG_MSCTRL_IN_BURST_COUNT(4)
452 | FIMC_REG_MSCTRL_INPUT_MEMORY
453 | FIMC_REG_MSCTRL_FIFO_CTRL_FULL
);
455 switch (frame
->fmt
->color
) {
456 case FIMC_FMT_RGB565
...FIMC_FMT_RGB888
:
457 cfg
|= FIMC_REG_MSCTRL_INFORMAT_RGB
;
459 case FIMC_FMT_YCBCR420
:
460 cfg
|= FIMC_REG_MSCTRL_INFORMAT_YCBCR420
;
462 if (frame
->fmt
->colplanes
== 2)
463 cfg
|= ctx
->in_order_2p
| FIMC_REG_MSCTRL_C_INT_IN_2PLANE
;
465 cfg
|= FIMC_REG_MSCTRL_C_INT_IN_3PLANE
;
468 case FIMC_FMT_YCBYCR422
...FIMC_FMT_CRYCBY422
:
469 if (frame
->fmt
->colplanes
== 1) {
470 cfg
|= ctx
->in_order_1p
471 | FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P
;
473 cfg
|= FIMC_REG_MSCTRL_INFORMAT_YCBCR422
;
475 if (frame
->fmt
->colplanes
== 2)
476 cfg
|= ctx
->in_order_2p
477 | FIMC_REG_MSCTRL_C_INT_IN_2PLANE
;
479 cfg
|= FIMC_REG_MSCTRL_C_INT_IN_3PLANE
;
486 writel(cfg
, dev
->regs
+ FIMC_REG_MSCTRL
);
488 /* Input/output DMA linear/tiled mode. */
489 cfg
= readl(dev
->regs
+ FIMC_REG_CIDMAPARAM
);
490 cfg
&= ~FIMC_REG_CIDMAPARAM_TILE_MASK
;
492 if (tiled_fmt(ctx
->s_frame
.fmt
))
493 cfg
|= FIMC_REG_CIDMAPARAM_R_64X32
;
495 if (tiled_fmt(ctx
->d_frame
.fmt
))
496 cfg
|= FIMC_REG_CIDMAPARAM_W_64X32
;
498 writel(cfg
, dev
->regs
+ FIMC_REG_CIDMAPARAM
);
502 void fimc_hw_set_input_path(struct fimc_ctx
*ctx
)
504 struct fimc_dev
*dev
= ctx
->fimc_dev
;
506 u32 cfg
= readl(dev
->regs
+ FIMC_REG_MSCTRL
);
507 cfg
&= ~FIMC_REG_MSCTRL_INPUT_MASK
;
509 if (ctx
->in_path
== FIMC_IO_DMA
)
510 cfg
|= FIMC_REG_MSCTRL_INPUT_MEMORY
;
512 cfg
|= FIMC_REG_MSCTRL_INPUT_EXTCAM
;
514 writel(cfg
, dev
->regs
+ FIMC_REG_MSCTRL
);
517 void fimc_hw_set_output_path(struct fimc_ctx
*ctx
)
519 struct fimc_dev
*dev
= ctx
->fimc_dev
;
521 u32 cfg
= readl(dev
->regs
+ FIMC_REG_CISCCTRL
);
522 cfg
&= ~FIMC_REG_CISCCTRL_LCDPATHEN_FIFO
;
523 if (ctx
->out_path
== FIMC_IO_LCDFIFO
)
524 cfg
|= FIMC_REG_CISCCTRL_LCDPATHEN_FIFO
;
525 writel(cfg
, dev
->regs
+ FIMC_REG_CISCCTRL
);
528 void fimc_hw_set_input_addr(struct fimc_dev
*dev
, struct fimc_addr
*paddr
)
530 u32 cfg
= readl(dev
->regs
+ FIMC_REG_CIREAL_ISIZE
);
531 cfg
|= FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS
;
532 writel(cfg
, dev
->regs
+ FIMC_REG_CIREAL_ISIZE
);
534 writel(paddr
->y
, dev
->regs
+ FIMC_REG_CIIYSA(0));
535 writel(paddr
->cb
, dev
->regs
+ FIMC_REG_CIICBSA(0));
536 writel(paddr
->cr
, dev
->regs
+ FIMC_REG_CIICRSA(0));
538 cfg
&= ~FIMC_REG_CIREAL_ISIZE_ADDR_CH_DIS
;
539 writel(cfg
, dev
->regs
+ FIMC_REG_CIREAL_ISIZE
);
542 void fimc_hw_set_output_addr(struct fimc_dev
*dev
,
543 struct fimc_addr
*paddr
, int index
)
545 int i
= (index
== -1) ? 0 : index
;
547 writel(paddr
->y
, dev
->regs
+ FIMC_REG_CIOYSA(i
));
548 writel(paddr
->cb
, dev
->regs
+ FIMC_REG_CIOCBSA(i
));
549 writel(paddr
->cr
, dev
->regs
+ FIMC_REG_CIOCRSA(i
));
550 dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
551 i
, paddr
->y
, paddr
->cb
, paddr
->cr
);
552 } while (index
== -1 && ++i
< FIMC_MAX_OUT_BUFS
);
555 int fimc_hw_set_camera_polarity(struct fimc_dev
*fimc
,
556 struct s5p_fimc_isp_info
*cam
)
558 u32 cfg
= readl(fimc
->regs
+ FIMC_REG_CIGCTRL
);
560 cfg
&= ~(FIMC_REG_CIGCTRL_INVPOLPCLK
| FIMC_REG_CIGCTRL_INVPOLVSYNC
|
561 FIMC_REG_CIGCTRL_INVPOLHREF
| FIMC_REG_CIGCTRL_INVPOLHSYNC
|
562 FIMC_REG_CIGCTRL_INVPOLFIELD
);
564 if (cam
->flags
& V4L2_MBUS_PCLK_SAMPLE_FALLING
)
565 cfg
|= FIMC_REG_CIGCTRL_INVPOLPCLK
;
567 if (cam
->flags
& V4L2_MBUS_VSYNC_ACTIVE_LOW
)
568 cfg
|= FIMC_REG_CIGCTRL_INVPOLVSYNC
;
570 if (cam
->flags
& V4L2_MBUS_HSYNC_ACTIVE_LOW
)
571 cfg
|= FIMC_REG_CIGCTRL_INVPOLHREF
;
573 if (cam
->flags
& V4L2_MBUS_HSYNC_ACTIVE_LOW
)
574 cfg
|= FIMC_REG_CIGCTRL_INVPOLHSYNC
;
576 if (cam
->flags
& V4L2_MBUS_FIELD_EVEN_LOW
)
577 cfg
|= FIMC_REG_CIGCTRL_INVPOLFIELD
;
579 writel(cfg
, fimc
->regs
+ FIMC_REG_CIGCTRL
);
584 struct mbus_pixfmt_desc
{
590 static const struct mbus_pixfmt_desc pix_desc
[] = {
591 { V4L2_MBUS_FMT_YUYV8_2X8
, FIMC_REG_CISRCFMT_ORDER422_YCBYCR
, 8 },
592 { V4L2_MBUS_FMT_YVYU8_2X8
, FIMC_REG_CISRCFMT_ORDER422_YCRYCB
, 8 },
593 { V4L2_MBUS_FMT_VYUY8_2X8
, FIMC_REG_CISRCFMT_ORDER422_CRYCBY
, 8 },
594 { V4L2_MBUS_FMT_UYVY8_2X8
, FIMC_REG_CISRCFMT_ORDER422_CBYCRY
, 8 },
597 int fimc_hw_set_camera_source(struct fimc_dev
*fimc
,
598 struct s5p_fimc_isp_info
*cam
)
600 struct fimc_frame
*f
= &fimc
->vid_cap
.ctx
->s_frame
;
605 if (cam
->bus_type
== FIMC_ITU_601
|| cam
->bus_type
== FIMC_ITU_656
) {
606 for (i
= 0; i
< ARRAY_SIZE(pix_desc
); i
++) {
607 if (fimc
->vid_cap
.mf
.code
== pix_desc
[i
].pixelcode
) {
608 cfg
= pix_desc
[i
].cisrcfmt
;
609 bus_width
= pix_desc
[i
].bus_width
;
614 if (i
== ARRAY_SIZE(pix_desc
)) {
615 v4l2_err(&fimc
->vid_cap
.vfd
,
616 "Camera color format not supported: %d\n",
617 fimc
->vid_cap
.mf
.code
);
621 if (cam
->bus_type
== FIMC_ITU_601
) {
623 cfg
|= FIMC_REG_CISRCFMT_ITU601_8BIT
;
624 else if (bus_width
== 16)
625 cfg
|= FIMC_REG_CISRCFMT_ITU601_16BIT
;
626 } /* else defaults to ITU-R BT.656 8-bit */
627 } else if (cam
->bus_type
== FIMC_MIPI_CSI2
) {
628 if (fimc_fmt_is_user_defined(f
->fmt
->color
))
629 cfg
|= FIMC_REG_CISRCFMT_ITU601_8BIT
;
632 cfg
|= (f
->o_width
<< 16) | f
->o_height
;
633 writel(cfg
, fimc
->regs
+ FIMC_REG_CISRCFMT
);
637 void fimc_hw_set_camera_offset(struct fimc_dev
*fimc
, struct fimc_frame
*f
)
641 u32 cfg
= readl(fimc
->regs
+ FIMC_REG_CIWDOFST
);
643 cfg
&= ~(FIMC_REG_CIWDOFST_HOROFF_MASK
| FIMC_REG_CIWDOFST_VEROFF_MASK
);
644 cfg
|= FIMC_REG_CIWDOFST_OFF_EN
|
645 (f
->offs_h
<< 16) | f
->offs_v
;
647 writel(cfg
, fimc
->regs
+ FIMC_REG_CIWDOFST
);
649 /* See CIWDOFSTn register description in the datasheet for details. */
650 hoff2
= f
->o_width
- f
->width
- f
->offs_h
;
651 voff2
= f
->o_height
- f
->height
- f
->offs_v
;
652 cfg
= (hoff2
<< 16) | voff2
;
653 writel(cfg
, fimc
->regs
+ FIMC_REG_CIWDOFST2
);
656 int fimc_hw_set_camera_type(struct fimc_dev
*fimc
,
657 struct s5p_fimc_isp_info
*cam
)
660 struct fimc_vid_cap
*vid_cap
= &fimc
->vid_cap
;
661 u32 csis_data_alignment
= 32;
663 cfg
= readl(fimc
->regs
+ FIMC_REG_CIGCTRL
);
665 /* Select ITU B interface, disable Writeback path and test pattern. */
666 cfg
&= ~(FIMC_REG_CIGCTRL_TESTPAT_MASK
| FIMC_REG_CIGCTRL_SELCAM_ITU_A
|
667 FIMC_REG_CIGCTRL_SELCAM_MIPI
| FIMC_REG_CIGCTRL_CAMIF_SELWB
|
668 FIMC_REG_CIGCTRL_SELCAM_MIPI_A
| FIMC_REG_CIGCTRL_CAM_JPEG
);
670 switch (cam
->bus_type
) {
672 cfg
|= FIMC_REG_CIGCTRL_SELCAM_MIPI
;
674 if (cam
->mux_id
== 0)
675 cfg
|= FIMC_REG_CIGCTRL_SELCAM_MIPI_A
;
677 /* TODO: add remaining supported formats. */
678 switch (vid_cap
->mf
.code
) {
679 case V4L2_MBUS_FMT_VYUY8_2X8
:
680 tmp
= FIMC_REG_CSIIMGFMT_YCBCR422_8BIT
;
682 case V4L2_MBUS_FMT_JPEG_1X8
:
683 case V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8
:
684 tmp
= FIMC_REG_CSIIMGFMT_USER(1);
685 cfg
|= FIMC_REG_CIGCTRL_CAM_JPEG
;
688 v4l2_err(&vid_cap
->vfd
,
689 "Not supported camera pixel format: %#x\n",
693 tmp
|= (csis_data_alignment
== 32) << 8;
695 writel(tmp
, fimc
->regs
+ FIMC_REG_CSIIMGFMT
);
697 case FIMC_ITU_601
...FIMC_ITU_656
:
698 if (cam
->mux_id
== 0) /* ITU-A, ITU-B: 0, 1 */
699 cfg
|= FIMC_REG_CIGCTRL_SELCAM_ITU_A
;
702 cfg
|= FIMC_REG_CIGCTRL_CAMIF_SELWB
;
705 v4l2_err(&vid_cap
->vfd
, "Invalid camera bus type selected\n");
708 writel(cfg
, fimc
->regs
+ FIMC_REG_CIGCTRL
);
713 void fimc_hw_clear_irq(struct fimc_dev
*dev
)
715 u32 cfg
= readl(dev
->regs
+ FIMC_REG_CIGCTRL
);
716 cfg
|= FIMC_REG_CIGCTRL_IRQ_CLR
;
717 writel(cfg
, dev
->regs
+ FIMC_REG_CIGCTRL
);
720 void fimc_hw_enable_scaler(struct fimc_dev
*dev
, bool on
)
722 u32 cfg
= readl(dev
->regs
+ FIMC_REG_CISCCTRL
);
724 cfg
|= FIMC_REG_CISCCTRL_SCALERSTART
;
726 cfg
&= ~FIMC_REG_CISCCTRL_SCALERSTART
;
727 writel(cfg
, dev
->regs
+ FIMC_REG_CISCCTRL
);
730 void fimc_hw_activate_input_dma(struct fimc_dev
*dev
, bool on
)
732 u32 cfg
= readl(dev
->regs
+ FIMC_REG_MSCTRL
);
734 cfg
|= FIMC_REG_MSCTRL_ENVID
;
736 cfg
&= ~FIMC_REG_MSCTRL_ENVID
;
737 writel(cfg
, dev
->regs
+ FIMC_REG_MSCTRL
);
740 void fimc_hw_dis_capture(struct fimc_dev
*dev
)
742 u32 cfg
= readl(dev
->regs
+ FIMC_REG_CIIMGCPT
);
743 cfg
&= ~(FIMC_REG_CIIMGCPT_IMGCPTEN
| FIMC_REG_CIIMGCPT_IMGCPTEN_SC
);
744 writel(cfg
, dev
->regs
+ FIMC_REG_CIIMGCPT
);
747 /* Return an index to the buffer actually being written. */
748 s32
fimc_hw_get_frame_index(struct fimc_dev
*dev
)
752 if (dev
->variant
->has_cistatus2
) {
753 reg
= readl(dev
->regs
+ FIMC_REG_CISTATUS2
) & 0x3f;
757 reg
= readl(dev
->regs
+ FIMC_REG_CISTATUS
);
759 return (reg
& FIMC_REG_CISTATUS_FRAMECNT_MASK
) >>
760 FIMC_REG_CISTATUS_FRAMECNT_SHIFT
;
763 /* Return an index to the buffer being written previously. */
764 s32
fimc_hw_get_prev_frame_index(struct fimc_dev
*dev
)
768 if (!dev
->variant
->has_cistatus2
)
771 reg
= readl(dev
->regs
+ FIMC_REG_CISTATUS2
);
772 return ((reg
>> 7) & 0x3f) - 1;
775 /* Locking: the caller holds fimc->slock */
776 void fimc_activate_capture(struct fimc_ctx
*ctx
)
778 fimc_hw_enable_scaler(ctx
->fimc_dev
, ctx
->scaler
.enabled
);
779 fimc_hw_en_capture(ctx
);
782 void fimc_deactivate_capture(struct fimc_dev
*fimc
)
784 fimc_hw_en_lastirq(fimc
, true);
785 fimc_hw_dis_capture(fimc
);
786 fimc_hw_enable_scaler(fimc
, false);
787 fimc_hw_en_lastirq(fimc
, false);