2 * Samsung S5P Multi Format Codec v 5.1
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
24 #include <media/videobuf2-core.h>
25 #include "s5p_mfc_common.h"
26 #include "s5p_mfc_ctrl.h"
27 #include "s5p_mfc_debug.h"
28 #include "s5p_mfc_dec.h"
29 #include "s5p_mfc_enc.h"
30 #include "s5p_mfc_intr.h"
31 #include "s5p_mfc_opr.h"
32 #include "s5p_mfc_cmd.h"
33 #include "s5p_mfc_pm.h"
35 #define S5P_MFC_NAME "s5p-mfc"
36 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
37 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
40 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
41 MODULE_PARM_DESC(debug
, "Debug level - higher value produces more verbose messages");
43 /* Helper functions for interrupt processing */
45 /* Remove from hw execution round robin */
46 void clear_work_bit(struct s5p_mfc_ctx
*ctx
)
48 struct s5p_mfc_dev
*dev
= ctx
->dev
;
50 spin_lock(&dev
->condlock
);
51 __clear_bit(ctx
->num
, &dev
->ctx_work_bits
);
52 spin_unlock(&dev
->condlock
);
55 /* Add to hw execution round robin */
56 void set_work_bit(struct s5p_mfc_ctx
*ctx
)
58 struct s5p_mfc_dev
*dev
= ctx
->dev
;
60 spin_lock(&dev
->condlock
);
61 __set_bit(ctx
->num
, &dev
->ctx_work_bits
);
62 spin_unlock(&dev
->condlock
);
65 /* Remove from hw execution round robin */
66 void clear_work_bit_irqsave(struct s5p_mfc_ctx
*ctx
)
68 struct s5p_mfc_dev
*dev
= ctx
->dev
;
71 spin_lock_irqsave(&dev
->condlock
, flags
);
72 __clear_bit(ctx
->num
, &dev
->ctx_work_bits
);
73 spin_unlock_irqrestore(&dev
->condlock
, flags
);
76 /* Add to hw execution round robin */
77 void set_work_bit_irqsave(struct s5p_mfc_ctx
*ctx
)
79 struct s5p_mfc_dev
*dev
= ctx
->dev
;
82 spin_lock_irqsave(&dev
->condlock
, flags
);
83 __set_bit(ctx
->num
, &dev
->ctx_work_bits
);
84 spin_unlock_irqrestore(&dev
->condlock
, flags
);
87 /* Wake up context wait_queue */
88 static void wake_up_ctx(struct s5p_mfc_ctx
*ctx
, unsigned int reason
,
92 ctx
->int_type
= reason
;
97 /* Wake up device wait_queue */
98 static void wake_up_dev(struct s5p_mfc_dev
*dev
, unsigned int reason
,
102 dev
->int_type
= reason
;
104 wake_up(&dev
->queue
);
107 static void s5p_mfc_watchdog(unsigned long arg
)
109 struct s5p_mfc_dev
*dev
= (struct s5p_mfc_dev
*)arg
;
111 if (test_bit(0, &dev
->hw_lock
))
112 atomic_inc(&dev
->watchdog_cnt
);
113 if (atomic_read(&dev
->watchdog_cnt
) >= MFC_WATCHDOG_CNT
) {
114 /* This means that hw is busy and no interrupts were
115 * generated by hw for the Nth time of running this
116 * watchdog timer. This usually means a serious hw
117 * error. Now it is time to kill all instances and
119 mfc_err("Time out during waiting for HW\n");
120 queue_work(dev
->watchdog_workqueue
, &dev
->watchdog_work
);
122 dev
->watchdog_timer
.expires
= jiffies
+
123 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL
);
124 add_timer(&dev
->watchdog_timer
);
127 static void s5p_mfc_watchdog_worker(struct work_struct
*work
)
129 struct s5p_mfc_dev
*dev
;
130 struct s5p_mfc_ctx
*ctx
;
135 dev
= container_of(work
, struct s5p_mfc_dev
, watchdog_work
);
137 mfc_err("Driver timeout error handling\n");
138 /* Lock the mutex that protects open and release.
139 * This is necessary as they may load and unload firmware. */
140 mutex_locked
= mutex_trylock(&dev
->mfc_mutex
);
142 mfc_err("Error: some instance may be closing/opening\n");
143 spin_lock_irqsave(&dev
->irqlock
, flags
);
147 for (i
= 0; i
< MFC_NUM_CONTEXTS
; i
++) {
151 ctx
->state
= MFCINST_ERROR
;
152 s5p_mfc_hw_call(dev
->mfc_ops
, cleanup_queue
, &ctx
->dst_queue
,
154 s5p_mfc_hw_call(dev
->mfc_ops
, cleanup_queue
, &ctx
->src_queue
,
157 wake_up_ctx(ctx
, S5P_MFC_R2H_CMD_ERR_RET
, 0);
159 clear_bit(0, &dev
->hw_lock
);
160 spin_unlock_irqrestore(&dev
->irqlock
, flags
);
161 /* Double check if there is at least one instance running.
162 * If no instance is in memory than no firmware should be present */
163 if (dev
->num_inst
> 0) {
164 ret
= s5p_mfc_reload_firmware(dev
);
166 mfc_err("Failed to reload FW\n");
170 ret
= s5p_mfc_init_hw(dev
);
172 mfc_err("Failed to reinit FW\n");
176 mutex_unlock(&dev
->mfc_mutex
);
179 static enum s5p_mfc_node_type
s5p_mfc_get_node_type(struct file
*file
)
181 struct video_device
*vdev
= video_devdata(file
);
184 mfc_err("failed to get video_device");
185 return MFCNODE_INVALID
;
187 if (vdev
->index
== 0)
188 return MFCNODE_DECODER
;
189 else if (vdev
->index
== 1)
190 return MFCNODE_ENCODER
;
191 return MFCNODE_INVALID
;
194 static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev
*dev
)
196 mfc_write(dev
, 0, S5P_FIMV_RISC_HOST_INT
);
197 mfc_write(dev
, 0, S5P_FIMV_RISC2HOST_CMD
);
198 mfc_write(dev
, 0xffff, S5P_FIMV_SI_RTN_CHID
);
201 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx
*ctx
)
203 struct s5p_mfc_buf
*dst_buf
;
204 struct s5p_mfc_dev
*dev
= ctx
->dev
;
206 ctx
->state
= MFCINST_FINISHED
;
208 while (!list_empty(&ctx
->dst_queue
)) {
209 dst_buf
= list_entry(ctx
->dst_queue
.next
,
210 struct s5p_mfc_buf
, list
);
211 mfc_debug(2, "Cleaning up buffer: %d\n",
212 dst_buf
->b
->v4l2_buf
.index
);
213 vb2_set_plane_payload(dst_buf
->b
, 0, 0);
214 vb2_set_plane_payload(dst_buf
->b
, 1, 0);
215 list_del(&dst_buf
->list
);
216 ctx
->dst_queue_cnt
--;
217 dst_buf
->b
->v4l2_buf
.sequence
= (ctx
->sequence
++);
219 if (s5p_mfc_hw_call(dev
->mfc_ops
, get_pic_type_top
, ctx
) ==
220 s5p_mfc_hw_call(dev
->mfc_ops
, get_pic_type_bot
, ctx
))
221 dst_buf
->b
->v4l2_buf
.field
= V4L2_FIELD_NONE
;
223 dst_buf
->b
->v4l2_buf
.field
= V4L2_FIELD_INTERLACED
;
225 ctx
->dec_dst_flag
&= ~(1 << dst_buf
->b
->v4l2_buf
.index
);
226 vb2_buffer_done(dst_buf
->b
, VB2_BUF_STATE_DONE
);
230 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx
*ctx
)
232 struct s5p_mfc_dev
*dev
= ctx
->dev
;
233 struct s5p_mfc_buf
*dst_buf
, *src_buf
;
235 unsigned int frame_type
;
237 dec_y_addr
= s5p_mfc_hw_call(dev
->mfc_ops
, get_dec_y_adr
, dev
);
238 frame_type
= s5p_mfc_hw_call(dev
->mfc_ops
, get_dec_frame_type
, dev
);
240 /* Copy timestamp / timecode from decoded src to dst and set
242 src_buf
= list_entry(ctx
->src_queue
.next
, struct s5p_mfc_buf
, list
);
243 list_for_each_entry(dst_buf
, &ctx
->dst_queue
, list
) {
244 if (vb2_dma_contig_plane_dma_addr(dst_buf
->b
, 0) == dec_y_addr
) {
245 memcpy(&dst_buf
->b
->v4l2_buf
.timecode
,
246 &src_buf
->b
->v4l2_buf
.timecode
,
247 sizeof(struct v4l2_timecode
));
248 memcpy(&dst_buf
->b
->v4l2_buf
.timestamp
,
249 &src_buf
->b
->v4l2_buf
.timestamp
,
250 sizeof(struct timeval
));
251 switch (frame_type
) {
252 case S5P_FIMV_DECODE_FRAME_I_FRAME
:
253 dst_buf
->b
->v4l2_buf
.flags
|=
254 V4L2_BUF_FLAG_KEYFRAME
;
256 case S5P_FIMV_DECODE_FRAME_P_FRAME
:
257 dst_buf
->b
->v4l2_buf
.flags
|=
258 V4L2_BUF_FLAG_PFRAME
;
260 case S5P_FIMV_DECODE_FRAME_B_FRAME
:
261 dst_buf
->b
->v4l2_buf
.flags
|=
262 V4L2_BUF_FLAG_BFRAME
;
270 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx
*ctx
, unsigned int err
)
272 struct s5p_mfc_dev
*dev
= ctx
->dev
;
273 struct s5p_mfc_buf
*dst_buf
;
275 unsigned int frame_type
;
278 dspl_y_addr
= s5p_mfc_hw_call(dev
->mfc_ops
, get_dspl_y_adr
, dev
);
279 frame_type
= s5p_mfc_hw_call(dev
->mfc_ops
, get_dec_frame_type
, dev
);
281 /* If frame is same as previous then skip and do not dequeue */
282 if (frame_type
== S5P_FIMV_DECODE_FRAME_SKIPPED
) {
283 if (!ctx
->after_packed_pb
)
285 ctx
->after_packed_pb
= 0;
289 /* The MFC returns address of the buffer, now we have to
290 * check which videobuf does it correspond to */
291 list_for_each_entry(dst_buf
, &ctx
->dst_queue
, list
) {
292 /* Check if this is the buffer we're looking for */
293 if (vb2_dma_contig_plane_dma_addr(dst_buf
->b
, 0) == dspl_y_addr
) {
294 list_del(&dst_buf
->list
);
295 ctx
->dst_queue_cnt
--;
296 dst_buf
->b
->v4l2_buf
.sequence
= ctx
->sequence
;
297 if (s5p_mfc_hw_call(dev
->mfc_ops
,
298 get_pic_type_top
, ctx
) ==
299 s5p_mfc_hw_call(dev
->mfc_ops
,
300 get_pic_type_bot
, ctx
))
301 dst_buf
->b
->v4l2_buf
.field
= V4L2_FIELD_NONE
;
303 dst_buf
->b
->v4l2_buf
.field
=
304 V4L2_FIELD_INTERLACED
;
305 vb2_set_plane_payload(dst_buf
->b
, 0, ctx
->luma_size
);
306 vb2_set_plane_payload(dst_buf
->b
, 1, ctx
->chroma_size
);
307 clear_bit(dst_buf
->b
->v4l2_buf
.index
,
310 vb2_buffer_done(dst_buf
->b
,
311 err
? VB2_BUF_STATE_ERROR
: VB2_BUF_STATE_DONE
);
313 index
= dst_buf
->b
->v4l2_buf
.index
;
319 /* Handle frame decoding interrupt */
320 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx
*ctx
,
321 unsigned int reason
, unsigned int err
)
323 struct s5p_mfc_dev
*dev
= ctx
->dev
;
324 unsigned int dst_frame_status
;
325 struct s5p_mfc_buf
*src_buf
;
327 unsigned int res_change
;
331 dst_frame_status
= s5p_mfc_hw_call(dev
->mfc_ops
, get_dspl_status
, dev
)
332 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK
;
333 res_change
= (s5p_mfc_hw_call(dev
->mfc_ops
, get_dspl_status
, dev
)
334 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK
)
335 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT
;
336 mfc_debug(2, "Frame Status: %x\n", dst_frame_status
);
337 if (ctx
->state
== MFCINST_RES_CHANGE_INIT
)
338 ctx
->state
= MFCINST_RES_CHANGE_FLUSH
;
339 if (res_change
== S5P_FIMV_RES_INCREASE
||
340 res_change
== S5P_FIMV_RES_DECREASE
) {
341 ctx
->state
= MFCINST_RES_CHANGE_INIT
;
342 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
343 wake_up_ctx(ctx
, reason
, err
);
344 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
347 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
350 if (ctx
->dpb_flush_flag
)
351 ctx
->dpb_flush_flag
= 0;
353 spin_lock_irqsave(&dev
->irqlock
, flags
);
354 /* All frames remaining in the buffer have been extracted */
355 if (dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_EMPTY
) {
356 if (ctx
->state
== MFCINST_RES_CHANGE_FLUSH
) {
357 s5p_mfc_handle_frame_all_extracted(ctx
);
358 ctx
->state
= MFCINST_RES_CHANGE_END
;
359 goto leave_handle_frame
;
361 s5p_mfc_handle_frame_all_extracted(ctx
);
365 if (dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_DISPLAY
||
366 dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_ONLY
)
367 s5p_mfc_handle_frame_copy_time(ctx
);
369 /* A frame has been decoded and is in the buffer */
370 if (dst_frame_status
== S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
||
371 dst_frame_status
== S5P_FIMV_DEC_STATUS_DECODING_DISPLAY
) {
372 s5p_mfc_handle_frame_new(ctx
, err
);
374 mfc_debug(2, "No frame decode\n");
376 /* Mark source buffer as complete */
377 if (dst_frame_status
!= S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
378 && !list_empty(&ctx
->src_queue
)) {
379 src_buf
= list_entry(ctx
->src_queue
.next
, struct s5p_mfc_buf
,
381 ctx
->consumed_stream
+= s5p_mfc_hw_call(dev
->mfc_ops
,
382 get_consumed_stream
, dev
);
383 if (ctx
->codec_mode
!= S5P_MFC_CODEC_H264_DEC
&&
384 s5p_mfc_hw_call(dev
->mfc_ops
,
385 get_dec_frame_type
, dev
) ==
386 S5P_FIMV_DECODE_FRAME_P_FRAME
387 && ctx
->consumed_stream
+ STUFF_BYTE
<
388 src_buf
->b
->v4l2_planes
[0].bytesused
) {
389 /* Run MFC again on the same buffer */
390 mfc_debug(2, "Running again the same buffer\n");
391 ctx
->after_packed_pb
= 1;
393 index
= src_buf
->b
->v4l2_buf
.index
;
394 mfc_debug(2, "MFC needs next buffer\n");
395 ctx
->consumed_stream
= 0;
396 list_del(&src_buf
->list
);
397 ctx
->src_queue_cnt
--;
398 if (s5p_mfc_hw_call(dev
->mfc_ops
, err_dec
, err
) > 0)
399 vb2_buffer_done(src_buf
->b
, VB2_BUF_STATE_ERROR
);
401 vb2_buffer_done(src_buf
->b
, VB2_BUF_STATE_DONE
);
405 spin_unlock_irqrestore(&dev
->irqlock
, flags
);
406 if ((ctx
->src_queue_cnt
== 0 && ctx
->state
!= MFCINST_FINISHING
)
407 || ctx
->dst_queue_cnt
< ctx
->dpb_count
)
409 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
410 wake_up_ctx(ctx
, reason
, err
);
411 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
414 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
417 /* Error handling for interrupt */
418 static void s5p_mfc_handle_error(struct s5p_mfc_ctx
*ctx
,
419 unsigned int reason
, unsigned int err
)
421 struct s5p_mfc_dev
*dev
;
424 /* If no context is available then all necessary
425 * processing has been done. */
430 mfc_err("Interrupt Error: %08x\n", err
);
431 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
432 wake_up_dev(dev
, reason
, err
);
434 /* Error recovery is dependent on the state of context */
435 switch (ctx
->state
) {
437 /* This error had to happen while acquireing instance */
438 case MFCINST_GOT_INST
:
439 /* This error had to happen while parsing the header */
440 case MFCINST_HEAD_PARSED
:
441 /* This error had to happen while setting dst buffers */
442 case MFCINST_RETURN_INST
:
443 /* This error had to happen while releasing instance */
445 wake_up_ctx(ctx
, reason
, err
);
446 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
449 ctx
->state
= MFCINST_ERROR
;
451 case MFCINST_FINISHING
:
452 case MFCINST_FINISHED
:
453 case MFCINST_RUNNING
:
454 /* It is higly probable that an error occured
455 * while decoding a frame */
457 ctx
->state
= MFCINST_ERROR
;
458 /* Mark all dst buffers as having an error */
459 spin_lock_irqsave(&dev
->irqlock
, flags
);
460 s5p_mfc_hw_call(dev
->mfc_ops
, cleanup_queue
, &ctx
->dst_queue
,
462 /* Mark all src buffers as having an error */
463 s5p_mfc_hw_call(dev
->mfc_ops
, cleanup_queue
, &ctx
->src_queue
,
465 spin_unlock_irqrestore(&dev
->irqlock
, flags
);
466 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
471 mfc_err("Encountered an error interrupt which had not been handled\n");
477 /* Header parsing interrupt handling */
478 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx
*ctx
,
479 unsigned int reason
, unsigned int err
)
481 struct s5p_mfc_dev
*dev
;
486 if (ctx
->c_ops
->post_seq_start
) {
487 if (ctx
->c_ops
->post_seq_start(ctx
))
488 mfc_err("post_seq_start() failed\n");
490 ctx
->img_width
= s5p_mfc_hw_call(dev
->mfc_ops
, get_img_width
,
492 ctx
->img_height
= s5p_mfc_hw_call(dev
->mfc_ops
, get_img_height
,
495 s5p_mfc_hw_call(dev
->mfc_ops
, dec_calc_dpb_size
, ctx
);
497 ctx
->dpb_count
= s5p_mfc_hw_call(dev
->mfc_ops
, get_dpb_count
,
499 ctx
->mv_count
= s5p_mfc_hw_call(dev
->mfc_ops
, get_mv_count
,
501 if (ctx
->img_width
== 0 || ctx
->img_height
== 0)
502 ctx
->state
= MFCINST_ERROR
;
504 ctx
->state
= MFCINST_HEAD_PARSED
;
506 if ((ctx
->codec_mode
== S5P_MFC_CODEC_H264_DEC
||
507 ctx
->codec_mode
== S5P_MFC_CODEC_H264_MVC_DEC
) &&
508 !list_empty(&ctx
->src_queue
)) {
509 struct s5p_mfc_buf
*src_buf
;
510 src_buf
= list_entry(ctx
->src_queue
.next
,
511 struct s5p_mfc_buf
, list
);
512 if (s5p_mfc_hw_call(dev
->mfc_ops
, get_consumed_stream
,
514 src_buf
->b
->v4l2_planes
[0].bytesused
)
515 ctx
->head_processed
= 0;
517 ctx
->head_processed
= 1;
519 ctx
->head_processed
= 1;
522 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
524 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
527 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
528 wake_up_ctx(ctx
, reason
, err
);
531 /* Header parsing interrupt handling */
532 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx
*ctx
,
533 unsigned int reason
, unsigned int err
)
535 struct s5p_mfc_buf
*src_buf
;
536 struct s5p_mfc_dev
*dev
;
542 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
543 ctx
->int_type
= reason
;
548 ctx
->state
= MFCINST_RUNNING
;
549 if (!ctx
->dpb_flush_flag
&& ctx
->head_processed
) {
550 spin_lock_irqsave(&dev
->irqlock
, flags
);
551 if (!list_empty(&ctx
->src_queue
)) {
552 src_buf
= list_entry(ctx
->src_queue
.next
,
553 struct s5p_mfc_buf
, list
);
554 list_del(&src_buf
->list
);
555 ctx
->src_queue_cnt
--;
556 vb2_buffer_done(src_buf
->b
,
559 spin_unlock_irqrestore(&dev
->irqlock
, flags
);
561 ctx
->dpb_flush_flag
= 0;
563 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
568 wake_up(&ctx
->queue
);
569 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
571 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
576 wake_up(&ctx
->queue
);
580 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx
*ctx
,
581 unsigned int reason
, unsigned int err
)
583 struct s5p_mfc_dev
*dev
= ctx
->dev
;
584 struct s5p_mfc_buf
*mb_entry
;
586 mfc_debug(2, "Stream completed");
588 s5p_mfc_clear_int_flags(dev
);
589 ctx
->int_type
= reason
;
591 ctx
->state
= MFCINST_FINISHED
;
593 spin_lock(&dev
->irqlock
);
594 if (!list_empty(&ctx
->dst_queue
)) {
595 mb_entry
= list_entry(ctx
->dst_queue
.next
, struct s5p_mfc_buf
,
597 list_del(&mb_entry
->list
);
598 ctx
->dst_queue_cnt
--;
599 vb2_set_plane_payload(mb_entry
->b
, 0, 0);
600 vb2_buffer_done(mb_entry
->b
, VB2_BUF_STATE_DONE
);
602 spin_unlock(&dev
->irqlock
);
606 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
610 wake_up(&ctx
->queue
);
611 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
614 /* Interrupt processing */
615 static irqreturn_t
s5p_mfc_irq(int irq
, void *priv
)
617 struct s5p_mfc_dev
*dev
= priv
;
618 struct s5p_mfc_ctx
*ctx
;
623 /* Reset the timeout watchdog */
624 atomic_set(&dev
->watchdog_cnt
, 0);
625 ctx
= dev
->ctx
[dev
->curr_ctx
];
626 /* Get the reason of interrupt and the error code */
627 reason
= s5p_mfc_hw_call(dev
->mfc_ops
, get_int_reason
, dev
);
628 err
= s5p_mfc_hw_call(dev
->mfc_ops
, get_int_err
, dev
);
629 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason
, err
);
631 case S5P_MFC_R2H_CMD_ERR_RET
:
632 /* An error has occured */
633 if (ctx
->state
== MFCINST_RUNNING
&&
634 s5p_mfc_hw_call(dev
->mfc_ops
, err_dec
, err
) >=
636 s5p_mfc_handle_frame(ctx
, reason
, err
);
638 s5p_mfc_handle_error(ctx
, reason
, err
);
639 clear_bit(0, &dev
->enter_suspend
);
642 case S5P_MFC_R2H_CMD_SLICE_DONE_RET
:
643 case S5P_MFC_R2H_CMD_FIELD_DONE_RET
:
644 case S5P_MFC_R2H_CMD_FRAME_DONE_RET
:
645 if (ctx
->c_ops
->post_frame_start
) {
646 if (ctx
->c_ops
->post_frame_start(ctx
))
647 mfc_err("post_frame_start() failed\n");
648 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
649 wake_up_ctx(ctx
, reason
, err
);
650 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
653 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
655 s5p_mfc_handle_frame(ctx
, reason
, err
);
659 case S5P_MFC_R2H_CMD_SEQ_DONE_RET
:
660 s5p_mfc_handle_seq_done(ctx
, reason
, err
);
663 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET
:
664 ctx
->inst_no
= s5p_mfc_hw_call(dev
->mfc_ops
, get_inst_no
, dev
);
665 ctx
->state
= MFCINST_GOT_INST
;
667 wake_up(&ctx
->queue
);
670 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET
:
672 ctx
->state
= MFCINST_FREE
;
673 wake_up(&ctx
->queue
);
676 case S5P_MFC_R2H_CMD_SYS_INIT_RET
:
677 case S5P_MFC_R2H_CMD_FW_STATUS_RET
:
678 case S5P_MFC_R2H_CMD_SLEEP_RET
:
679 case S5P_MFC_R2H_CMD_WAKEUP_RET
:
682 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
683 wake_up_dev(dev
, reason
, err
);
684 clear_bit(0, &dev
->hw_lock
);
685 clear_bit(0, &dev
->enter_suspend
);
688 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET
:
689 s5p_mfc_handle_init_buffers(ctx
, reason
, err
);
692 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET
:
693 s5p_mfc_handle_stream_complete(ctx
, reason
, err
);
697 mfc_debug(2, "Unknown int reason\n");
698 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
703 s5p_mfc_hw_call(dev
->mfc_ops
, clear_int_flags
, dev
);
704 ctx
->int_type
= reason
;
707 if (test_and_clear_bit(0, &dev
->hw_lock
) == 0)
708 mfc_err("Failed to unlock hw\n");
712 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
713 mfc_debug(2, "Exit via irq_cleanup_hw\n");
717 /* Open an MFC node */
718 static int s5p_mfc_open(struct file
*file
)
720 struct s5p_mfc_dev
*dev
= video_drvdata(file
);
721 struct s5p_mfc_ctx
*ctx
= NULL
;
726 if (mutex_lock_interruptible(&dev
->mfc_mutex
))
728 dev
->num_inst
++; /* It is guarded by mfc_mutex in vfd */
729 /* Allocate memory for context */
730 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
732 mfc_err("Not enough memory\n");
736 v4l2_fh_init(&ctx
->fh
, video_devdata(file
));
737 file
->private_data
= &ctx
->fh
;
738 v4l2_fh_add(&ctx
->fh
);
740 INIT_LIST_HEAD(&ctx
->src_queue
);
741 INIT_LIST_HEAD(&ctx
->dst_queue
);
742 ctx
->src_queue_cnt
= 0;
743 ctx
->dst_queue_cnt
= 0;
744 /* Get context number */
746 while (dev
->ctx
[ctx
->num
]) {
748 if (ctx
->num
>= MFC_NUM_CONTEXTS
) {
749 mfc_err("Too many open contexts\n");
754 /* Mark context as idle */
755 clear_work_bit_irqsave(ctx
);
756 dev
->ctx
[ctx
->num
] = ctx
;
757 if (s5p_mfc_get_node_type(file
) == MFCNODE_DECODER
) {
758 ctx
->type
= MFCINST_DECODER
;
759 ctx
->c_ops
= get_dec_codec_ops();
760 s5p_mfc_dec_init(ctx
);
761 /* Setup ctrl handler */
762 ret
= s5p_mfc_dec_ctrls_setup(ctx
);
764 mfc_err("Failed to setup mfc controls\n");
765 goto err_ctrls_setup
;
767 } else if (s5p_mfc_get_node_type(file
) == MFCNODE_ENCODER
) {
768 ctx
->type
= MFCINST_ENCODER
;
769 ctx
->c_ops
= get_enc_codec_ops();
770 /* only for encoder */
771 INIT_LIST_HEAD(&ctx
->ref_queue
);
772 ctx
->ref_queue_cnt
= 0;
773 s5p_mfc_enc_init(ctx
);
774 /* Setup ctrl handler */
775 ret
= s5p_mfc_enc_ctrls_setup(ctx
);
777 mfc_err("Failed to setup mfc controls\n");
778 goto err_ctrls_setup
;
784 ctx
->fh
.ctrl_handler
= &ctx
->ctrl_handler
;
786 /* Load firmware if this is the first instance */
787 if (dev
->num_inst
== 1) {
788 dev
->watchdog_timer
.expires
= jiffies
+
789 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL
);
790 add_timer(&dev
->watchdog_timer
);
791 ret
= s5p_mfc_power_on();
793 mfc_err("power on failed\n");
797 ret
= s5p_mfc_alloc_and_load_firmware(dev
);
801 ret
= s5p_mfc_init_hw(dev
);
806 /* Init videobuf2 queue for CAPTURE */
808 q
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
;
809 q
->drv_priv
= &ctx
->fh
;
810 if (s5p_mfc_get_node_type(file
) == MFCNODE_DECODER
) {
811 q
->io_modes
= VB2_MMAP
;
812 q
->ops
= get_dec_queue_ops();
813 } else if (s5p_mfc_get_node_type(file
) == MFCNODE_ENCODER
) {
814 q
->io_modes
= VB2_MMAP
| VB2_USERPTR
;
815 q
->ops
= get_enc_queue_ops();
820 q
->mem_ops
= (struct vb2_mem_ops
*)&vb2_dma_contig_memops
;
821 ret
= vb2_queue_init(q
);
823 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
826 /* Init videobuf2 queue for OUTPUT */
828 q
->type
= V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
;
829 q
->io_modes
= VB2_MMAP
;
830 q
->drv_priv
= &ctx
->fh
;
831 if (s5p_mfc_get_node_type(file
) == MFCNODE_DECODER
) {
832 q
->io_modes
= VB2_MMAP
;
833 q
->ops
= get_dec_queue_ops();
834 } else if (s5p_mfc_get_node_type(file
) == MFCNODE_ENCODER
) {
835 q
->io_modes
= VB2_MMAP
| VB2_USERPTR
;
836 q
->ops
= get_enc_queue_ops();
841 q
->mem_ops
= (struct vb2_mem_ops
*)&vb2_dma_contig_memops
;
842 ret
= vb2_queue_init(q
);
844 mfc_err("Failed to initialize videobuf2 queue(output)\n");
847 init_waitqueue_head(&ctx
->queue
);
848 mutex_unlock(&dev
->mfc_mutex
);
851 /* Deinit when failure occured */
854 s5p_mfc_release_firmware(dev
);
856 dev
->ctx
[ctx
->num
] = NULL
;
857 del_timer_sync(&dev
->watchdog_timer
);
860 if (dev
->num_inst
== 1) {
861 if (s5p_mfc_power_off() < 0)
862 mfc_err("power off failed\n");
863 s5p_mfc_release_firmware(dev
);
866 s5p_mfc_dec_ctrls_delete(ctx
);
869 v4l2_fh_del(&ctx
->fh
);
870 v4l2_fh_exit(&ctx
->fh
);
874 mutex_unlock(&dev
->mfc_mutex
);
879 /* Release MFC context */
880 static int s5p_mfc_release(struct file
*file
)
882 struct s5p_mfc_ctx
*ctx
= fh_to_ctx(file
->private_data
);
883 struct s5p_mfc_dev
*dev
= ctx
->dev
;
886 mutex_lock(&dev
->mfc_mutex
);
888 vb2_queue_release(&ctx
->vq_src
);
889 vb2_queue_release(&ctx
->vq_dst
);
890 /* Mark context as idle */
891 clear_work_bit_irqsave(ctx
);
892 /* If instance was initialised then
893 * return instance and free reosurces */
894 if (ctx
->inst_no
!= MFC_NO_INSTANCE_SET
) {
895 mfc_debug(2, "Has to free instance\n");
896 ctx
->state
= MFCINST_RETURN_INST
;
897 set_work_bit_irqsave(ctx
);
898 s5p_mfc_clean_ctx_int_flags(ctx
);
899 s5p_mfc_hw_call(dev
->mfc_ops
, try_run
, dev
);
900 /* Wait until instance is returned or timeout occured */
901 if (s5p_mfc_wait_for_done_ctx
902 (ctx
, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET
, 0)) {
904 mfc_err("Err returning instance\n");
906 mfc_debug(2, "After free instance\n");
908 s5p_mfc_hw_call(dev
->mfc_ops
, release_codec_buffers
, ctx
);
909 s5p_mfc_hw_call(dev
->mfc_ops
, release_instance_buffer
, ctx
);
910 if (ctx
->type
== MFCINST_DECODER
)
911 s5p_mfc_hw_call(dev
->mfc_ops
, release_dec_desc_buffer
,
914 ctx
->inst_no
= MFC_NO_INSTANCE_SET
;
916 /* hardware locking scheme */
917 if (dev
->curr_ctx
== ctx
->num
)
918 clear_bit(0, &dev
->hw_lock
);
920 if (dev
->num_inst
== 0) {
921 mfc_debug(2, "Last instance - release firmware\n");
922 /* reset <-> F/W release */
924 s5p_mfc_deinit_hw(dev
);
925 s5p_mfc_release_firmware(dev
);
926 del_timer_sync(&dev
->watchdog_timer
);
927 if (s5p_mfc_power_off() < 0)
928 mfc_err("Power off failed\n");
930 mfc_debug(2, "Shutting down clock\n");
932 dev
->ctx
[ctx
->num
] = NULL
;
933 s5p_mfc_dec_ctrls_delete(ctx
);
934 v4l2_fh_del(&ctx
->fh
);
935 v4l2_fh_exit(&ctx
->fh
);
938 mutex_unlock(&dev
->mfc_mutex
);
943 static unsigned int s5p_mfc_poll(struct file
*file
,
944 struct poll_table_struct
*wait
)
946 struct s5p_mfc_ctx
*ctx
= fh_to_ctx(file
->private_data
);
947 struct s5p_mfc_dev
*dev
= ctx
->dev
;
948 struct vb2_queue
*src_q
, *dst_q
;
949 struct vb2_buffer
*src_vb
= NULL
, *dst_vb
= NULL
;
953 mutex_lock(&dev
->mfc_mutex
);
954 src_q
= &ctx
->vq_src
;
955 dst_q
= &ctx
->vq_dst
;
957 * There has to be at least one buffer queued on each queued_list, which
958 * means either in driver already or waiting for driver to claim it
959 * and start processing.
961 if ((!src_q
->streaming
|| list_empty(&src_q
->queued_list
))
962 && (!dst_q
->streaming
|| list_empty(&dst_q
->queued_list
))) {
966 mutex_unlock(&dev
->mfc_mutex
);
967 poll_wait(file
, &ctx
->fh
.wait
, wait
);
968 poll_wait(file
, &src_q
->done_wq
, wait
);
969 poll_wait(file
, &dst_q
->done_wq
, wait
);
970 mutex_lock(&dev
->mfc_mutex
);
971 if (v4l2_event_pending(&ctx
->fh
))
973 spin_lock_irqsave(&src_q
->done_lock
, flags
);
974 if (!list_empty(&src_q
->done_list
))
975 src_vb
= list_first_entry(&src_q
->done_list
, struct vb2_buffer
,
977 if (src_vb
&& (src_vb
->state
== VB2_BUF_STATE_DONE
978 || src_vb
->state
== VB2_BUF_STATE_ERROR
))
979 rc
|= POLLOUT
| POLLWRNORM
;
980 spin_unlock_irqrestore(&src_q
->done_lock
, flags
);
981 spin_lock_irqsave(&dst_q
->done_lock
, flags
);
982 if (!list_empty(&dst_q
->done_list
))
983 dst_vb
= list_first_entry(&dst_q
->done_list
, struct vb2_buffer
,
985 if (dst_vb
&& (dst_vb
->state
== VB2_BUF_STATE_DONE
986 || dst_vb
->state
== VB2_BUF_STATE_ERROR
))
987 rc
|= POLLIN
| POLLRDNORM
;
988 spin_unlock_irqrestore(&dst_q
->done_lock
, flags
);
990 mutex_unlock(&dev
->mfc_mutex
);
995 static int s5p_mfc_mmap(struct file
*file
, struct vm_area_struct
*vma
)
997 struct s5p_mfc_ctx
*ctx
= fh_to_ctx(file
->private_data
);
998 struct s5p_mfc_dev
*dev
= ctx
->dev
;
999 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
1002 if (mutex_lock_interruptible(&dev
->mfc_mutex
))
1003 return -ERESTARTSYS
;
1004 if (offset
< DST_QUEUE_OFF_BASE
) {
1005 mfc_debug(2, "mmaping source\n");
1006 ret
= vb2_mmap(&ctx
->vq_src
, vma
);
1007 } else { /* capture */
1008 mfc_debug(2, "mmaping destination\n");
1009 vma
->vm_pgoff
-= (DST_QUEUE_OFF_BASE
>> PAGE_SHIFT
);
1010 ret
= vb2_mmap(&ctx
->vq_dst
, vma
);
1012 mutex_unlock(&dev
->mfc_mutex
);
1017 static const struct v4l2_file_operations s5p_mfc_fops
= {
1018 .owner
= THIS_MODULE
,
1019 .open
= s5p_mfc_open
,
1020 .release
= s5p_mfc_release
,
1021 .poll
= s5p_mfc_poll
,
1022 .unlocked_ioctl
= video_ioctl2
,
1023 .mmap
= s5p_mfc_mmap
,
1026 static int match_child(struct device
*dev
, void *data
)
1030 return !strcmp(dev_name(dev
), (char *)data
);
1033 /* MFC probe function */
1034 static int s5p_mfc_probe(struct platform_device
*pdev
)
1036 struct s5p_mfc_dev
*dev
;
1037 struct video_device
*vfd
;
1038 struct resource
*res
;
1041 pr_debug("%s++\n", __func__
);
1042 dev
= devm_kzalloc(&pdev
->dev
, sizeof(*dev
), GFP_KERNEL
);
1044 dev_err(&pdev
->dev
, "Not enough memory for MFC device\n");
1048 spin_lock_init(&dev
->irqlock
);
1049 spin_lock_init(&dev
->condlock
);
1050 dev
->plat_dev
= pdev
;
1051 if (!dev
->plat_dev
) {
1052 dev_err(&pdev
->dev
, "No platform data specified\n");
1056 dev
->variant
= (struct s5p_mfc_variant
*)
1057 platform_get_device_id(pdev
)->driver_data
;
1059 ret
= s5p_mfc_init_pm(dev
);
1061 dev_err(&pdev
->dev
, "failed to get mfc clock source\n");
1065 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1067 dev
->regs_base
= devm_request_and_ioremap(&pdev
->dev
, res
);
1068 if (dev
->regs_base
== NULL
) {
1069 dev_err(&pdev
->dev
, "Failed to obtain io memory\n");
1073 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1075 dev_err(&pdev
->dev
, "failed to get irq resource\n");
1079 dev
->irq
= res
->start
;
1080 ret
= devm_request_irq(&pdev
->dev
, dev
->irq
, s5p_mfc_irq
,
1081 IRQF_DISABLED
, pdev
->name
, dev
);
1083 dev_err(&pdev
->dev
, "Failed to install irq (%d)\n", ret
);
1087 dev
->mem_dev_l
= device_find_child(&dev
->plat_dev
->dev
, "s5p-mfc-l",
1089 if (!dev
->mem_dev_l
) {
1090 mfc_err("Mem child (L) device get failed\n");
1095 dev
->mem_dev_r
= device_find_child(&dev
->plat_dev
->dev
, "s5p-mfc-r",
1097 if (!dev
->mem_dev_r
) {
1098 mfc_err("Mem child (R) device get failed\n");
1103 dev
->alloc_ctx
[0] = vb2_dma_contig_init_ctx(dev
->mem_dev_l
);
1104 if (IS_ERR_OR_NULL(dev
->alloc_ctx
[0])) {
1105 ret
= PTR_ERR(dev
->alloc_ctx
[0]);
1108 dev
->alloc_ctx
[1] = vb2_dma_contig_init_ctx(dev
->mem_dev_r
);
1109 if (IS_ERR_OR_NULL(dev
->alloc_ctx
[1])) {
1110 ret
= PTR_ERR(dev
->alloc_ctx
[1]);
1111 goto err_mem_init_ctx_1
;
1114 mutex_init(&dev
->mfc_mutex
);
1116 ret
= v4l2_device_register(&pdev
->dev
, &dev
->v4l2_dev
);
1118 goto err_v4l2_dev_reg
;
1119 init_waitqueue_head(&dev
->queue
);
1122 vfd
= video_device_alloc();
1124 v4l2_err(&dev
->v4l2_dev
, "Failed to allocate video device\n");
1128 vfd
->fops
= &s5p_mfc_fops
,
1129 vfd
->ioctl_ops
= get_dec_v4l2_ioctl_ops();
1130 vfd
->release
= video_device_release
,
1131 vfd
->lock
= &dev
->mfc_mutex
;
1132 vfd
->v4l2_dev
= &dev
->v4l2_dev
;
1133 vfd
->vfl_dir
= VFL_DIR_M2M
;
1134 snprintf(vfd
->name
, sizeof(vfd
->name
), "%s", S5P_MFC_DEC_NAME
);
1136 ret
= video_register_device(vfd
, VFL_TYPE_GRABBER
, 0);
1138 v4l2_err(&dev
->v4l2_dev
, "Failed to register video device\n");
1139 video_device_release(vfd
);
1142 v4l2_info(&dev
->v4l2_dev
,
1143 "decoder registered as /dev/video%d\n", vfd
->num
);
1144 video_set_drvdata(vfd
, dev
);
1147 vfd
= video_device_alloc();
1149 v4l2_err(&dev
->v4l2_dev
, "Failed to allocate video device\n");
1153 vfd
->fops
= &s5p_mfc_fops
,
1154 vfd
->ioctl_ops
= get_enc_v4l2_ioctl_ops();
1155 vfd
->release
= video_device_release
,
1156 vfd
->lock
= &dev
->mfc_mutex
;
1157 vfd
->v4l2_dev
= &dev
->v4l2_dev
;
1158 vfd
->vfl_dir
= VFL_DIR_M2M
;
1159 snprintf(vfd
->name
, sizeof(vfd
->name
), "%s", S5P_MFC_ENC_NAME
);
1161 ret
= video_register_device(vfd
, VFL_TYPE_GRABBER
, 0);
1163 v4l2_err(&dev
->v4l2_dev
, "Failed to register video device\n");
1164 video_device_release(vfd
);
1167 v4l2_info(&dev
->v4l2_dev
,
1168 "encoder registered as /dev/video%d\n", vfd
->num
);
1169 video_set_drvdata(vfd
, dev
);
1170 platform_set_drvdata(pdev
, dev
);
1173 dev
->watchdog_workqueue
= create_singlethread_workqueue(S5P_MFC_NAME
);
1174 INIT_WORK(&dev
->watchdog_work
, s5p_mfc_watchdog_worker
);
1175 atomic_set(&dev
->watchdog_cnt
, 0);
1176 init_timer(&dev
->watchdog_timer
);
1177 dev
->watchdog_timer
.data
= (unsigned long)dev
;
1178 dev
->watchdog_timer
.function
= s5p_mfc_watchdog
;
1180 /* Initialize HW ops and commands based on MFC version */
1181 s5p_mfc_init_hw_ops(dev
);
1182 s5p_mfc_init_hw_cmds(dev
);
1184 pr_debug("%s--\n", __func__
);
1187 /* Deinit MFC if probe had failed */
1189 video_device_release(dev
->vfd_enc
);
1191 video_unregister_device(dev
->vfd_dec
);
1193 video_device_release(dev
->vfd_dec
);
1195 v4l2_device_unregister(&dev
->v4l2_dev
);
1197 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
[1]);
1199 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
[0]);
1201 s5p_mfc_final_pm(dev
);
1203 pr_debug("%s-- with error\n", __func__
);
1208 /* Remove the driver */
1209 static int __devexit
s5p_mfc_remove(struct platform_device
*pdev
)
1211 struct s5p_mfc_dev
*dev
= platform_get_drvdata(pdev
);
1213 v4l2_info(&dev
->v4l2_dev
, "Removing %s\n", pdev
->name
);
1215 del_timer_sync(&dev
->watchdog_timer
);
1216 flush_workqueue(dev
->watchdog_workqueue
);
1217 destroy_workqueue(dev
->watchdog_workqueue
);
1219 video_unregister_device(dev
->vfd_enc
);
1220 video_unregister_device(dev
->vfd_dec
);
1221 v4l2_device_unregister(&dev
->v4l2_dev
);
1222 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
[0]);
1223 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
[1]);
1225 s5p_mfc_final_pm(dev
);
1229 #ifdef CONFIG_PM_SLEEP
1231 static int s5p_mfc_suspend(struct device
*dev
)
1233 struct platform_device
*pdev
= to_platform_device(dev
);
1234 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1237 if (m_dev
->num_inst
== 0)
1240 if (test_and_set_bit(0, &m_dev
->enter_suspend
) != 0) {
1241 mfc_err("Error: going to suspend for a second time\n");
1245 /* Check if we're processing then wait if it necessary. */
1246 while (test_and_set_bit(0, &m_dev
->hw_lock
) != 0) {
1247 /* Try and lock the HW */
1248 /* Wait on the interrupt waitqueue */
1249 ret
= wait_event_interruptible_timeout(m_dev
->queue
,
1250 m_dev
->int_cond
|| m_dev
->ctx
[m_dev
->curr_ctx
]->int_cond
,
1251 msecs_to_jiffies(MFC_INT_TIMEOUT
));
1254 mfc_err("Waiting for hardware to finish timed out\n");
1259 return s5p_mfc_sleep(m_dev
);
1262 static int s5p_mfc_resume(struct device
*dev
)
1264 struct platform_device
*pdev
= to_platform_device(dev
);
1265 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1267 if (m_dev
->num_inst
== 0)
1269 return s5p_mfc_wakeup(m_dev
);
1273 #ifdef CONFIG_PM_RUNTIME
1274 static int s5p_mfc_runtime_suspend(struct device
*dev
)
1276 struct platform_device
*pdev
= to_platform_device(dev
);
1277 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1279 atomic_set(&m_dev
->pm
.power
, 0);
1283 static int s5p_mfc_runtime_resume(struct device
*dev
)
1285 struct platform_device
*pdev
= to_platform_device(dev
);
1286 struct s5p_mfc_dev
*m_dev
= platform_get_drvdata(pdev
);
1289 if (!m_dev
->alloc_ctx
)
1291 pre_power
= atomic_read(&m_dev
->pm
.power
);
1292 atomic_set(&m_dev
->pm
.power
, 1);
1297 /* Power management */
1298 static const struct dev_pm_ops s5p_mfc_pm_ops
= {
1299 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend
, s5p_mfc_resume
)
1300 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend
, s5p_mfc_runtime_resume
,
1304 struct s5p_mfc_buf_size_v5 mfc_buf_size_v5
= {
1305 .h264_ctx
= MFC_H264_CTX_BUF_SIZE
,
1306 .non_h264_ctx
= MFC_CTX_BUF_SIZE
,
1307 .dsc
= DESC_BUF_SIZE
,
1308 .shm
= SHARED_BUF_SIZE
,
1311 struct s5p_mfc_buf_size buf_size_v5
= {
1313 .cpb
= MAX_CPB_SIZE
,
1314 .priv
= &mfc_buf_size_v5
,
1317 struct s5p_mfc_buf_align mfc_buf_align_v5
= {
1318 .base
= MFC_BASE_ALIGN_ORDER
,
1321 static struct s5p_mfc_variant mfc_drvdata_v5
= {
1322 .version
= MFC_VERSION
,
1323 .port_num
= MFC_NUM_PORTS
,
1324 .buf_size
= &buf_size_v5
,
1325 .buf_align
= &mfc_buf_align_v5
,
1326 .mclk_name
= "sclk_mfc",
1327 .fw_name
= "s5p-mfc.fw",
1330 struct s5p_mfc_buf_size_v6 mfc_buf_size_v6
= {
1331 .dev_ctx
= MFC_CTX_BUF_SIZE_V6
,
1332 .h264_dec_ctx
= MFC_H264_DEC_CTX_BUF_SIZE_V6
,
1333 .other_dec_ctx
= MFC_OTHER_DEC_CTX_BUF_SIZE_V6
,
1334 .h264_enc_ctx
= MFC_H264_ENC_CTX_BUF_SIZE_V6
,
1335 .other_enc_ctx
= MFC_OTHER_ENC_CTX_BUF_SIZE_V6
,
1338 struct s5p_mfc_buf_size buf_size_v6
= {
1339 .fw
= MAX_FW_SIZE_V6
,
1340 .cpb
= MAX_CPB_SIZE_V6
,
1341 .priv
= &mfc_buf_size_v6
,
1344 struct s5p_mfc_buf_align mfc_buf_align_v6
= {
1348 static struct s5p_mfc_variant mfc_drvdata_v6
= {
1349 .version
= MFC_VERSION_V6
,
1350 .port_num
= MFC_NUM_PORTS_V6
,
1351 .buf_size
= &buf_size_v6
,
1352 .buf_align
= &mfc_buf_align_v6
,
1353 .mclk_name
= "aclk_333",
1354 .fw_name
= "s5p-mfc-v6.fw",
1357 static struct platform_device_id mfc_driver_ids
[] = {
1360 .driver_data
= (unsigned long)&mfc_drvdata_v5
,
1362 .name
= "s5p-mfc-v5",
1363 .driver_data
= (unsigned long)&mfc_drvdata_v5
,
1365 .name
= "s5p-mfc-v6",
1366 .driver_data
= (unsigned long)&mfc_drvdata_v6
,
1370 MODULE_DEVICE_TABLE(platform
, mfc_driver_ids
);
1372 static struct platform_driver s5p_mfc_driver
= {
1373 .probe
= s5p_mfc_probe
,
1374 .remove
= __devexit_p(s5p_mfc_remove
),
1375 .id_table
= mfc_driver_ids
,
1377 .name
= S5P_MFC_NAME
,
1378 .owner
= THIS_MODULE
,
1379 .pm
= &s5p_mfc_pm_ops
1383 module_platform_driver(s5p_mfc_driver
);
1385 MODULE_LICENSE("GPL");
1386 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1387 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");