drivers/media/platform/s5p-mfc/s5p_mfc_common.h

   1 /*
   2  * Samsung S5P Multi Format Codec v 5.0
   3  *
   4  * This file contains definitions of enums and structs used by the codec
   5  * driver.
   6  *
   7  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
   8  * Kamil Debski, <k.debski@samsung.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the
  13  * License, or (at your option) any later version
  14  */
  15
  16 #ifndef S5P_MFC_COMMON_H_
  17 #define S5P_MFC_COMMON_H_
  18
  19 #include "regs-mfc.h"
  20 #include <linux/platform_device.h>
  21 #include <linux/videodev2.h>
  22 #include <media/v4l2-ctrls.h>
  23 #include <media/v4l2-device.h>
  24 #include <media/v4l2-ioctl.h>
  25 #include <media/videobuf2-core.h>
  26
  27 /* Definitions related to MFC memory */
  28
  29 /* Offset base used to differentiate between CAPTURE and OUTPUT
  30 *  while mmaping */
  31 #define DST_QUEUE_OFF_BASE      (TASK_SIZE / 2)
  32
  33 /* Offset used by the hardware to store addresses */
  34 #define MFC_OFFSET_SHIFT        11
  35
  36 #define FIRMWARE_ALIGN          0x20000         /* 128KB */
  37 #define MFC_H264_CTX_BUF_SIZE   0x96000         /* 600KB per H264 instance */
  38 #define MFC_CTX_BUF_SIZE        0x2800          /* 10KB per instance */
  39 #define DESC_BUF_SIZE           0x20000         /* 128KB for DESC buffer */
  40 #define SHARED_BUF_SIZE         0x2000          /* 8KB for shared buffer */
  41
  42 #define DEF_CPB_SIZE            0x40000         /* 512KB */
  43
  44 #define MFC_BANK1_ALLOC_CTX     0
  45 #define MFC_BANK2_ALLOC_CTX     1
  46
  47 #define MFC_BANK1_ALIGN_ORDER   13
  48 #define MFC_BANK2_ALIGN_ORDER   13
  49 #define MFC_BASE_ALIGN_ORDER    17
  50
  51 #include <media/videobuf2-dma-contig.h>
  52
  53 static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
  54 {
  55         /* Same functionality as the vb2_dma_contig_plane_paddr */
  56         dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b);
  57
  58         return *paddr;
  59 }
  60
  61 /* MFC definitions */
  62 #define MFC_MAX_EXTRA_DPB       5
  63 #define MFC_MAX_BUFFERS         32
  64 #define MFC_NUM_CONTEXTS        4
  65 /* Interrupt timeout */
  66 #define MFC_INT_TIMEOUT         2000
  67 /* Busy wait timeout */
  68 #define MFC_BW_TIMEOUT          500
  69 /* Watchdog interval */
  70 #define MFC_WATCHDOG_INTERVAL   1000
  71 /* After how many executions watchdog should assume lock up */
  72 #define MFC_WATCHDOG_CNT        10
  73 #define MFC_NO_INSTANCE_SET     -1
  74 #define MFC_ENC_CAP_PLANE_COUNT 1
  75 #define MFC_ENC_OUT_PLANE_COUNT 2
  76 #define STUFF_BYTE              4
  77 #define MFC_MAX_CTRLS           64
  78
  79 #define mfc_read(dev, offset)           readl(dev->regs_base + (offset))
  80 #define mfc_write(dev, data, offset)    writel((data), dev->regs_base + \
  81                                                                 (offset))
  82
  83 /**
  84  * enum s5p_mfc_fmt_type - type of the pixelformat
  85  */
  86 enum s5p_mfc_fmt_type {
  87         MFC_FMT_DEC,
  88         MFC_FMT_ENC,
  89         MFC_FMT_RAW,
  90 };
  91
  92 /**
  93  * enum s5p_mfc_node_type - The type of an MFC device node.
  94  */
  95 enum s5p_mfc_node_type {
  96         MFCNODE_INVALID = -1,
  97         MFCNODE_DECODER = 0,
  98         MFCNODE_ENCODER = 1,
  99 };
 100
 101 /**
 102  * enum s5p_mfc_inst_type - The type of an MFC instance.
 103  */
 104 enum s5p_mfc_inst_type {
 105         MFCINST_INVALID,
 106         MFCINST_DECODER,
 107         MFCINST_ENCODER,
 108 };
 109
 110 /**
 111  * enum s5p_mfc_inst_state - The state of an MFC instance.
 112  */
 113 enum s5p_mfc_inst_state {
 114         MFCINST_FREE = 0,
 115         MFCINST_INIT = 100,
 116         MFCINST_GOT_INST,
 117         MFCINST_HEAD_PARSED,
 118         MFCINST_BUFS_SET,
 119         MFCINST_RUNNING,
 120         MFCINST_FINISHING,
 121         MFCINST_FINISHED,
 122         MFCINST_RETURN_INST,
 123         MFCINST_ERROR,
 124         MFCINST_ABORT,
 125         MFCINST_RES_CHANGE_INIT,
 126         MFCINST_RES_CHANGE_FLUSH,
 127         MFCINST_RES_CHANGE_END,
 128 };
 129
 130 /**
 131  * enum s5p_mfc_queue_state - The state of buffer queue.
 132  */
 133 enum s5p_mfc_queue_state {
 134         QUEUE_FREE,
 135         QUEUE_BUFS_REQUESTED,
 136         QUEUE_BUFS_QUERIED,
 137         QUEUE_BUFS_MMAPED,
 138 };
 139
 140 /**
 141  * enum s5p_mfc_decode_arg - type of frame decoding
 142  */
 143 enum s5p_mfc_decode_arg {
 144         MFC_DEC_FRAME,
 145         MFC_DEC_LAST_FRAME,
 146         MFC_DEC_RES_CHANGE,
 147 };
 148
 149 struct s5p_mfc_ctx;
 150
 151 /**
 152  * struct s5p_mfc_buf - MFC buffer
 153  */
 154 struct s5p_mfc_buf {
 155         struct list_head list;
 156         struct vb2_buffer *b;
 157         union {
 158                 struct {
 159                         size_t luma;
 160                         size_t chroma;
 161                 } raw;
 162                 size_t stream;
 163         } cookie;
 164         int used;
 165 };
 166
 167 /**
 168  * struct s5p_mfc_pm - power management data structure
 169  */
 170 struct s5p_mfc_pm {
 171         struct clk      *clock;
 172         struct clk      *clock_gate;
 173         atomic_t        power;
 174         struct device   *device;
 175 };
 176
 177 /**
 178  * struct s5p_mfc_dev - The struct containing driver internal parameters.
 179  *
 180  * @v4l2_dev:           v4l2_device
 181  * @vfd_dec:            video device for decoding
 182  * @vfd_enc:            video device for encoding
 183  * @plat_dev:           platform device
 184  * @mem_dev_l:          child device of the left memory bank (0)
 185  * @mem_dev_r:          child device of the right memory bank (1)
 186  * @regs_base:          base address of the MFC hw registers
 187  * @irq:                irq resource
 188  * @dec_ctrl_handler:   control framework handler for decoding
 189  * @enc_ctrl_handler:   control framework handler for encoding
 190  * @pm:                 power management control
 191  * @num_inst:           couter of active MFC instances
 192  * @irqlock:            lock for operations on videobuf2 queues
 193  * @condlock:           lock for changing/checking if a context is ready to be
 194  *                      processed
 195  * @mfc_mutex:          lock for video_device
 196  * @int_cond:           variable used by the waitqueue
 197  * @int_type:           type of last interrupt
 198  * @int_err:            error number for last interrupt
 199  * @queue:              waitqueue for waiting for completion of device commands
 200  * @fw_size:            size of firmware
 201  * @bank1:              address of the beggining of bank 1 memory
 202  * @bank2:              address of the beggining of bank 2 memory
 203  * @hw_lock:            used for hardware locking
 204  * @ctx:                array of driver contexts
 205  * @curr_ctx:           number of the currently running context
 206  * @ctx_work_bits:      used to mark which contexts are waiting for hardware
 207  * @watchdog_cnt:       counter for the watchdog
 208  * @watchdog_workqueue: workqueue for the watchdog
 209  * @watchdog_work:      worker for the watchdog
 210  * @alloc_ctx:          videobuf2 allocator contexts for two memory banks
 211  * @enter_suspend:      flag set when entering suspend
 212  *
 213  */
 214 struct s5p_mfc_dev {
 215         struct v4l2_device      v4l2_dev;
 216         struct video_device     *vfd_dec;
 217         struct video_device     *vfd_enc;
 218         struct platform_device  *plat_dev;
 219         struct device           *mem_dev_l;
 220         struct device           *mem_dev_r;
 221         void __iomem            *regs_base;
 222         int                     irq;
 223         struct v4l2_ctrl_handler dec_ctrl_handler;
 224         struct v4l2_ctrl_handler enc_ctrl_handler;
 225         struct s5p_mfc_pm       pm;
 226         int num_inst;
 227         spinlock_t irqlock;     /* lock when operating on videobuf2 queues */
 228         spinlock_t condlock;    /* lock when changing/checking if a context is
 229                                         ready to be processed */
 230         struct mutex mfc_mutex; /* video_device lock */
 231         int int_cond;
 232         int int_type;
 233         unsigned int int_err;
 234         wait_queue_head_t queue;
 235         size_t fw_size;
 236         size_t bank1;
 237         size_t bank2;
 238         unsigned long hw_lock;
 239         struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
 240         int curr_ctx;
 241         unsigned long ctx_work_bits;
 242         atomic_t watchdog_cnt;
 243         struct timer_list watchdog_timer;
 244         struct workqueue_struct *watchdog_workqueue;
 245         struct work_struct watchdog_work;
 246         void *alloc_ctx[2];
 247         unsigned long enter_suspend;
 248 };
 249
 250 /**
 251  * struct s5p_mfc_h264_enc_params - encoding parameters for h264
 252  */
 253 struct s5p_mfc_h264_enc_params {
 254         enum v4l2_mpeg_video_h264_profile profile;
 255         enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
 256         s8 loop_filter_alpha;
 257         s8 loop_filter_beta;
 258         enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
 259         u8 max_ref_pic;
 260         u8 num_ref_pic_4p;
 261         int _8x8_transform;
 262         int rc_mb;
 263         int rc_mb_dark;
 264         int rc_mb_smooth;
 265         int rc_mb_static;
 266         int rc_mb_activity;
 267         int vui_sar;
 268         u8 vui_sar_idc;
 269         u16 vui_ext_sar_width;
 270         u16 vui_ext_sar_height;
 271         int open_gop;
 272         u16 open_gop_size;
 273         u8 rc_frame_qp;
 274         u8 rc_min_qp;
 275         u8 rc_max_qp;
 276         u8 rc_p_frame_qp;
 277         u8 rc_b_frame_qp;
 278         enum v4l2_mpeg_video_h264_level level_v4l2;
 279         int level;
 280         u16 cpb_size;
 281 };
 282
 283 /**
 284  * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
 285  */
 286 struct s5p_mfc_mpeg4_enc_params {
 287         /* MPEG4 Only */
 288         enum v4l2_mpeg_video_mpeg4_profile profile;
 289         int quarter_pixel;
 290         /* Common for MPEG4, H263 */
 291         u16 vop_time_res;
 292         u16 vop_frm_delta;
 293         u8 rc_frame_qp;
 294         u8 rc_min_qp;
 295         u8 rc_max_qp;
 296         u8 rc_p_frame_qp;
 297         u8 rc_b_frame_qp;
 298         enum v4l2_mpeg_video_mpeg4_level level_v4l2;
 299         int level;
 300 };
 301
 302 /**
 303  * struct s5p_mfc_enc_params - general encoding parameters
 304  */
 305 struct s5p_mfc_enc_params {
 306         u16 width;
 307         u16 height;
 308
 309         u16 gop_size;
 310         enum v4l2_mpeg_video_multi_slice_mode slice_mode;
 311         u16 slice_mb;
 312         u32 slice_bit;
 313         u16 intra_refresh_mb;
 314         int pad;
 315         u8 pad_luma;
 316         u8 pad_cb;
 317         u8 pad_cr;
 318         int rc_frame;
 319         u32 rc_bitrate;
 320         u16 rc_reaction_coeff;
 321         u16 vbv_size;
 322
 323         enum v4l2_mpeg_video_header_mode seq_hdr_mode;
 324         enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
 325         int fixed_target_bit;
 326
 327         u8 num_b_frame;
 328         u32 rc_framerate_num;
 329         u32 rc_framerate_denom;
 330         int interlace;
 331
 332         union {
 333                 struct s5p_mfc_h264_enc_params h264;
 334                 struct s5p_mfc_mpeg4_enc_params mpeg4;
 335         } codec;
 336
 337 };
 338
 339 /**
 340  * struct s5p_mfc_codec_ops - codec ops, used by encoding
 341  */
 342 struct s5p_mfc_codec_ops {
 343         /* initialization routines */
 344         int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
 345         int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
 346         /* execution routines */
 347         int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
 348         int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
 349 };
 350
 351 #define call_cop(c, op, args...)                                \
 352         (((c)->c_ops->op) ?                                     \
 353                 ((c)->c_ops->op(args)) : 0)
 354
 355 /**
 356  * struct s5p_mfc_ctx - This struct contains the instance context
 357  *
 358  * @dev:                pointer to the s5p_mfc_dev of the device
 359  * @fh:                 struct v4l2_fh
 360  * @num:                number of the context that this structure describes
 361  * @int_cond:           variable used by the waitqueue
 362  * @int_type:           type of the last interrupt
 363  * @int_err:            error number received from MFC hw in the interrupt
 364  * @queue:              waitqueue that can be used to wait for this context to
 365  *                      finish
 366  * @src_fmt:            source pixelformat information
 367  * @dst_fmt:            destination pixelformat information
 368  * @vq_src:             vb2 queue for source buffers
 369  * @vq_dst:             vb2 queue for destination buffers
 370  * @src_queue:          driver internal queue for source buffers
 371  * @dst_queue:          driver internal queue for destination buffers
 372  * @src_queue_cnt:      number of buffers queued on the source internal queue
 373  * @dst_queue_cnt:      number of buffers queued on the dest internal queue
 374  * @type:               type of the instance - decoder or encoder
 375  * @state:              state of the context
 376  * @inst_no:            number of hw instance associated with the context
 377  * @img_width:          width of the image that is decoded or encoded
 378  * @img_height:         height of the image that is decoded or encoded
 379  * @buf_width:          width of the buffer for processed image
 380  * @buf_height:         height of the buffer for processed image
 381  * @luma_size:          size of a luma plane
 382  * @chroma_size:        size of a chroma plane
 383  * @mv_size:            size of a motion vectors buffer
 384  * @consumed_stream:    number of bytes that have been used so far from the
 385  *                      decoding buffer
 386  * @dpb_flush_flag:     flag used to indicate that a DPB buffers are being
 387  *                      flushed
 388  * @bank1_buf:          handle to memory allocated for temporary buffers from
 389  *                      memory bank 1
 390  * @bank1_phys:         address of the temporary buffers from memory bank 1
 391  * @bank1_size:         size of the memory allocated for temporary buffers from
 392  *                      memory bank 1
 393  * @bank2_buf:          handle to memory allocated for temporary buffers from
 394  *                      memory bank 2
 395  * @bank2_phys:         address of the temporary buffers from memory bank 2
 396  * @bank2_size:         size of the memory allocated for temporary buffers from
 397  *                      memory bank 2
 398  * @capture_state:      state of the capture buffers queue
 399  * @output_state:       state of the output buffers queue
 400  * @src_bufs:           information on allocated source buffers
 401  * @dst_bufs:           information on allocated destination buffers
 402  * @sequence:           counter for the sequence number for v4l2
 403  * @dec_dst_flag:       flags for buffers queued in the hardware
 404  * @dec_src_buf_size:   size of the buffer for source buffers in decoding
 405  * @codec_mode:         number of codec mode used by MFC hw
 406  * @slice_interface:    slice interface flag
 407  * @loop_filter_mpeg4:  loop filter for MPEG4 flag
 408  * @display_delay:      value of the display delay for H264
 409  * @display_delay_enable:       display delay for H264 enable flag
 410  * @after_packed_pb:    flag used to track buffer when stream is in
 411  *                      Packed PB format
 412  * @dpb_count:          count of the DPB buffers required by MFC hw
 413  * @total_dpb_count:    count of DPB buffers with additional buffers
 414  *                      requested by the application
 415  * @ctx_buf:            handle to the memory associated with this context
 416  * @ctx_phys:           address of the memory associated with this context
 417  * @ctx_size:           size of the memory associated with this context
 418  * @desc_buf:           description buffer for decoding handle
 419  * @desc_phys:          description buffer for decoding address
 420  * @shm_alloc:          handle for the shared memory buffer
 421  * @shm:                virtual address for the shared memory buffer
 422  * @shm_ofs:            address offset for shared memory
 423  * @enc_params:         encoding parameters for MFC
 424  * @enc_dst_buf_size:   size of the buffers for encoder output
 425  * @frame_type:         used to force the type of the next encoded frame
 426  * @ref_queue:          list of the reference buffers for encoding
 427  * @ref_queue_cnt:      number of the buffers in the reference list
 428  * @c_ops:              ops for encoding
 429  * @ctrls:              array of controls, used when adding controls to the
 430  *                      v4l2 control framework
 431  * @ctrl_handler:       handler for v4l2 framework
 432  */
 433 struct s5p_mfc_ctx {
 434         struct s5p_mfc_dev *dev;
 435         struct v4l2_fh fh;
 436
 437         int num;
 438
 439         int int_cond;
 440         int int_type;
 441         unsigned int int_err;
 442         wait_queue_head_t queue;
 443
 444         struct s5p_mfc_fmt *src_fmt;
 445         struct s5p_mfc_fmt *dst_fmt;
 446
 447         struct vb2_queue vq_src;
 448         struct vb2_queue vq_dst;
 449
 450         struct list_head src_queue;
 451         struct list_head dst_queue;
 452
 453         unsigned int src_queue_cnt;
 454         unsigned int dst_queue_cnt;
 455
 456         enum s5p_mfc_inst_type type;
 457         enum s5p_mfc_inst_state state;
 458         int inst_no;
 459
 460         /* Image parameters */
 461         int img_width;
 462         int img_height;
 463         int buf_width;
 464         int buf_height;
 465
 466         int luma_size;
 467         int chroma_size;
 468         int mv_size;
 469
 470         unsigned long consumed_stream;
 471
 472         unsigned int dpb_flush_flag;
 473
 474         /* Buffers */
 475         void *bank1_buf;
 476         size_t bank1_phys;
 477         size_t bank1_size;
 478
 479         void *bank2_buf;
 480         size_t bank2_phys;
 481         size_t bank2_size;
 482
 483         enum s5p_mfc_queue_state capture_state;
 484         enum s5p_mfc_queue_state output_state;
 485
 486         struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
 487         int src_bufs_cnt;
 488         struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
 489         int dst_bufs_cnt;
 490
 491         unsigned int sequence;
 492         unsigned long dec_dst_flag;
 493         size_t dec_src_buf_size;
 494
 495         /* Control values */
 496         int codec_mode;
 497         int slice_interface;
 498         int loop_filter_mpeg4;
 499         int display_delay;
 500         int display_delay_enable;
 501         int after_packed_pb;
 502
 503         int dpb_count;
 504         int total_dpb_count;
 505
 506         /* Buffers */
 507         void *ctx_buf;
 508         size_t ctx_phys;
 509         size_t ctx_ofs;
 510         size_t ctx_size;
 511
 512         void *desc_buf;
 513         size_t desc_phys;
 514
 515
 516         void *shm_alloc;
 517         void *shm;
 518         size_t shm_ofs;
 519
 520         struct s5p_mfc_enc_params enc_params;
 521
 522         size_t enc_dst_buf_size;
 523
 524         enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
 525
 526         struct list_head ref_queue;
 527         unsigned int ref_queue_cnt;
 528
 529         struct s5p_mfc_codec_ops *c_ops;
 530
 531         struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
 532         struct v4l2_ctrl_handler ctrl_handler;
 533 };
 534
 535 /*
 536  * struct s5p_mfc_fmt - structure used to store information about pixelformats
 537  *                      used by the MFC
 538  */
 539 struct s5p_mfc_fmt {
 540         char *name;
 541         u32 fourcc;
 542         u32 codec_mode;
 543         enum s5p_mfc_fmt_type type;
 544         u32 num_planes;
 545 };
 546
 547 /**
 548  * struct mfc_control - structure used to store information about MFC controls
 549  *                      it is used to initialize the control framework.
 550  */
 551 struct mfc_control {
 552         __u32                   id;
 553         enum v4l2_ctrl_type     type;
 554         __u8                    name[32];  /* Whatever */
 555         __s32                   minimum;   /* Note signedness */
 556         __s32                   maximum;
 557         __s32                   step;
 558         __u32                   menu_skip_mask;
 559         __s32                   default_value;
 560         __u32                   flags;
 561         __u32                   reserved[2];
 562         __u8                    is_volatile;
 563 };
 564
 565
 566 #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
 567 #define ctrl_to_ctx(__ctrl) \
 568         container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
 569
 570 #endif /* S5P_MFC_COMMON_H_ */