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mx2_camera: Fix regression caused by clock conversion
[deliverable/linux.git] / drivers / media / platform / soc_camera / mx2_camera.c
1 /*
2 * V4L2 Driver for i.MX27/i.MX25 camera host
3 *
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/errno.h>
21 #include <linux/fs.h>
22 #include <linux/gcd.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/math64.h>
26 #include <linux/mm.h>
27 #include <linux/moduleparam.h>
28 #include <linux/time.h>
29 #include <linux/device.h>
30 #include <linux/platform_device.h>
31 #include <linux/mutex.h>
32 #include <linux/clk.h>
33
34 #include <media/v4l2-common.h>
35 #include <media/v4l2-dev.h>
36 #include <media/videobuf2-core.h>
37 #include <media/videobuf2-dma-contig.h>
38 #include <media/soc_camera.h>
39 #include <media/soc_mediabus.h>
40
41 #include <linux/videodev2.h>
42
43 #include <linux/platform_data/camera-mx2.h>
44
45 #include <asm/dma.h>
46
47 #define MX2_CAM_DRV_NAME "mx2-camera"
48 #define MX2_CAM_VERSION "0.0.6"
49 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
50
51 /* reset values */
52 #define CSICR1_RESET_VAL 0x40000800
53 #define CSICR2_RESET_VAL 0x0
54 #define CSICR3_RESET_VAL 0x0
55
56 /* csi control reg 1 */
57 #define CSICR1_SWAP16_EN (1 << 31)
58 #define CSICR1_EXT_VSYNC (1 << 30)
59 #define CSICR1_EOF_INTEN (1 << 29)
60 #define CSICR1_PRP_IF_EN (1 << 28)
61 #define CSICR1_CCIR_MODE (1 << 27)
62 #define CSICR1_COF_INTEN (1 << 26)
63 #define CSICR1_SF_OR_INTEN (1 << 25)
64 #define CSICR1_RF_OR_INTEN (1 << 24)
65 #define CSICR1_STATFF_LEVEL (3 << 22)
66 #define CSICR1_STATFF_INTEN (1 << 21)
67 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
68 #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
69 #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
70 #define CSICR1_RXFF_INTEN (1 << 18)
71 #define CSICR1_SOF_POL (1 << 17)
72 #define CSICR1_SOF_INTEN (1 << 16)
73 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
74 #define CSICR1_HSYNC_POL (1 << 11)
75 #define CSICR1_CCIR_EN (1 << 10)
76 #define CSICR1_MCLKEN (1 << 9)
77 #define CSICR1_FCC (1 << 8)
78 #define CSICR1_PACK_DIR (1 << 7)
79 #define CSICR1_CLR_STATFIFO (1 << 6)
80 #define CSICR1_CLR_RXFIFO (1 << 5)
81 #define CSICR1_GCLK_MODE (1 << 4)
82 #define CSICR1_INV_DATA (1 << 3)
83 #define CSICR1_INV_PCLK (1 << 2)
84 #define CSICR1_REDGE (1 << 1)
85 #define CSICR1_FMT_MASK (CSICR1_PACK_DIR | CSICR1_SWAP16_EN)
86
87 #define SHIFT_STATFF_LEVEL 22
88 #define SHIFT_RXFF_LEVEL 19
89 #define SHIFT_MCLKDIV 12
90
91 /* control reg 3 */
92 #define CSICR3_FRMCNT (0xFFFF << 16)
93 #define CSICR3_FRMCNT_RST (1 << 15)
94 #define CSICR3_DMA_REFLASH_RFF (1 << 14)
95 #define CSICR3_DMA_REFLASH_SFF (1 << 13)
96 #define CSICR3_DMA_REQ_EN_RFF (1 << 12)
97 #define CSICR3_DMA_REQ_EN_SFF (1 << 11)
98 #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
99 #define CSICR3_CSI_SUP (1 << 3)
100 #define CSICR3_ZERO_PACK_EN (1 << 2)
101 #define CSICR3_ECC_INT_EN (1 << 1)
102 #define CSICR3_ECC_AUTO_EN (1 << 0)
103
104 #define SHIFT_FRMCNT 16
105
106 /* csi status reg */
107 #define CSISR_SFF_OR_INT (1 << 25)
108 #define CSISR_RFF_OR_INT (1 << 24)
109 #define CSISR_STATFF_INT (1 << 21)
110 #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
111 #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
112 #define CSISR_RXFF_INT (1 << 18)
113 #define CSISR_EOF_INT (1 << 17)
114 #define CSISR_SOF_INT (1 << 16)
115 #define CSISR_F2_INT (1 << 15)
116 #define CSISR_F1_INT (1 << 14)
117 #define CSISR_COF_INT (1 << 13)
118 #define CSISR_ECC_INT (1 << 1)
119 #define CSISR_DRDY (1 << 0)
120
121 #define CSICR1 0x00
122 #define CSICR2 0x04
123 #define CSISR_IMX25 0x18
124 #define CSISR_IMX27 0x08
125 #define CSISTATFIFO 0x0c
126 #define CSIRFIFO 0x10
127 #define CSIRXCNT 0x14
128 #define CSICR3_IMX25 0x08
129 #define CSICR3_IMX27 0x1c
130 #define CSIDMASA_STATFIFO 0x20
131 #define CSIDMATA_STATFIFO 0x24
132 #define CSIDMASA_FB1 0x28
133 #define CSIDMASA_FB2 0x2c
134 #define CSIFBUF_PARA 0x30
135 #define CSIIMAG_PARA 0x34
136
137 /* EMMA PrP */
138 #define PRP_CNTL 0x00
139 #define PRP_INTR_CNTL 0x04
140 #define PRP_INTRSTATUS 0x08
141 #define PRP_SOURCE_Y_PTR 0x0c
142 #define PRP_SOURCE_CB_PTR 0x10
143 #define PRP_SOURCE_CR_PTR 0x14
144 #define PRP_DEST_RGB1_PTR 0x18
145 #define PRP_DEST_RGB2_PTR 0x1c
146 #define PRP_DEST_Y_PTR 0x20
147 #define PRP_DEST_CB_PTR 0x24
148 #define PRP_DEST_CR_PTR 0x28
149 #define PRP_SRC_FRAME_SIZE 0x2c
150 #define PRP_DEST_CH1_LINE_STRIDE 0x30
151 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
152 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
153 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
154 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
155 #define PRP_SRC_LINE_STRIDE 0x44
156 #define PRP_CSC_COEF_012 0x48
157 #define PRP_CSC_COEF_345 0x4c
158 #define PRP_CSC_COEF_678 0x50
159 #define PRP_CH1_RZ_HORI_COEF1 0x54
160 #define PRP_CH1_RZ_HORI_COEF2 0x58
161 #define PRP_CH1_RZ_HORI_VALID 0x5c
162 #define PRP_CH1_RZ_VERT_COEF1 0x60
163 #define PRP_CH1_RZ_VERT_COEF2 0x64
164 #define PRP_CH1_RZ_VERT_VALID 0x68
165 #define PRP_CH2_RZ_HORI_COEF1 0x6c
166 #define PRP_CH2_RZ_HORI_COEF2 0x70
167 #define PRP_CH2_RZ_HORI_VALID 0x74
168 #define PRP_CH2_RZ_VERT_COEF1 0x78
169 #define PRP_CH2_RZ_VERT_COEF2 0x7c
170 #define PRP_CH2_RZ_VERT_VALID 0x80
171
172 #define PRP_CNTL_CH1EN (1 << 0)
173 #define PRP_CNTL_CH2EN (1 << 1)
174 #define PRP_CNTL_CSIEN (1 << 2)
175 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
176 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
177 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
178 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
179 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
180 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
181 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
182 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
183 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
184 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
185 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
186 #define PRP_CNTL_CH1_LEN (1 << 9)
187 #define PRP_CNTL_CH2_LEN (1 << 10)
188 #define PRP_CNTL_SKIP_FRAME (1 << 11)
189 #define PRP_CNTL_SWRST (1 << 12)
190 #define PRP_CNTL_CLKEN (1 << 13)
191 #define PRP_CNTL_WEN (1 << 14)
192 #define PRP_CNTL_CH1BYP (1 << 15)
193 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
194 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
195 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
196 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
197 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
198 #define PRP_CNTL_CH2B1EN (1 << 29)
199 #define PRP_CNTL_CH2B2EN (1 << 30)
200 #define PRP_CNTL_CH2FEN (1 << 31)
201
202 /* IRQ Enable and status register */
203 #define PRP_INTR_RDERR (1 << 0)
204 #define PRP_INTR_CH1WERR (1 << 1)
205 #define PRP_INTR_CH2WERR (1 << 2)
206 #define PRP_INTR_CH1FC (1 << 3)
207 #define PRP_INTR_CH2FC (1 << 5)
208 #define PRP_INTR_LBOVF (1 << 7)
209 #define PRP_INTR_CH2OVF (1 << 8)
210
211 /* Resizing registers */
212 #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
213 #define PRP_RZ_VALID_BILINEAR (1 << 31)
214
215 #define MAX_VIDEO_MEM 16
216
217 #define RESIZE_NUM_MIN 1
218 #define RESIZE_NUM_MAX 20
219 #define BC_COEF 3
220 #define SZ_COEF (1 << BC_COEF)
221
222 #define RESIZE_DIR_H 0
223 #define RESIZE_DIR_V 1
224
225 #define RESIZE_ALGO_BILINEAR 0
226 #define RESIZE_ALGO_AVERAGING 1
227
228 struct mx2_prp_cfg {
229 int channel;
230 u32 in_fmt;
231 u32 out_fmt;
232 u32 src_pixel;
233 u32 ch1_pixel;
234 u32 irq_flags;
235 u32 csicr1;
236 };
237
238 /* prp resizing parameters */
239 struct emma_prp_resize {
240 int algo; /* type of algorithm used */
241 int len; /* number of coefficients */
242 unsigned char s[RESIZE_NUM_MAX]; /* table of coefficients */
243 };
244
245 /* prp configuration for a client-host fmt pair */
246 struct mx2_fmt_cfg {
247 enum v4l2_mbus_pixelcode in_fmt;
248 u32 out_fmt;
249 struct mx2_prp_cfg cfg;
250 };
251
252 enum mx2_buffer_state {
253 MX2_STATE_QUEUED,
254 MX2_STATE_ACTIVE,
255 MX2_STATE_DONE,
256 };
257
258 struct mx2_buf_internal {
259 struct list_head queue;
260 int bufnum;
261 bool discard;
262 };
263
264 /* buffer for one video frame */
265 struct mx2_buffer {
266 /* common v4l buffer stuff -- must be first */
267 struct vb2_buffer vb;
268 enum mx2_buffer_state state;
269 struct mx2_buf_internal internal;
270 };
271
272 enum mx2_camera_type {
273 IMX25_CAMERA,
274 IMX27_CAMERA,
275 };
276
277 struct mx2_camera_dev {
278 struct device *dev;
279 struct soc_camera_host soc_host;
280 struct soc_camera_device *icd;
281 struct clk *clk_emma_ahb, *clk_emma_ipg;
282 struct clk *clk_csi_ahb, *clk_csi_per;
283
284 void __iomem *base_csi, *base_emma;
285
286 struct mx2_camera_platform_data *pdata;
287 unsigned long platform_flags;
288
289 struct list_head capture;
290 struct list_head active_bufs;
291 struct list_head discard;
292
293 spinlock_t lock;
294
295 int dma;
296 struct mx2_buffer *active;
297 struct mx2_buffer *fb1_active;
298 struct mx2_buffer *fb2_active;
299
300 u32 csicr1;
301 u32 reg_csisr;
302 u32 reg_csicr3;
303 enum mx2_camera_type devtype;
304
305 struct mx2_buf_internal buf_discard[2];
306 void *discard_buffer;
307 dma_addr_t discard_buffer_dma;
308 size_t discard_size;
309 struct mx2_fmt_cfg *emma_prp;
310 struct emma_prp_resize resizing[2];
311 unsigned int s_width, s_height;
312 u32 frame_count;
313 struct vb2_alloc_ctx *alloc_ctx;
314 };
315
316 static struct platform_device_id mx2_camera_devtype[] = {
317 {
318 .name = "imx25-camera",
319 .driver_data = IMX25_CAMERA,
320 }, {
321 .name = "imx27-camera",
322 .driver_data = IMX27_CAMERA,
323 }, {
324 /* sentinel */
325 }
326 };
327 MODULE_DEVICE_TABLE(platform, mx2_camera_devtype);
328
329 static inline int is_imx25_camera(struct mx2_camera_dev *pcdev)
330 {
331 return pcdev->devtype == IMX25_CAMERA;
332 }
333
334 static inline int is_imx27_camera(struct mx2_camera_dev *pcdev)
335 {
336 return pcdev->devtype == IMX27_CAMERA;
337 }
338
339 static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
340 {
341 return container_of(int_buf, struct mx2_buffer, internal);
342 }
343
344 static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
345 /*
346 * This is a generic configuration which is valid for most
347 * prp input-output format combinations.
348 * We set the incomming and outgoing pixelformat to a
349 * 16 Bit wide format and adjust the bytesperline
350 * accordingly. With this configuration the inputdata
351 * will not be changed by the emma and could be any type
352 * of 16 Bit Pixelformat.
353 */
354 {
355 .in_fmt = 0,
356 .out_fmt = 0,
357 .cfg = {
358 .channel = 1,
359 .in_fmt = PRP_CNTL_DATA_IN_RGB16,
360 .out_fmt = PRP_CNTL_CH1_OUT_RGB16,
361 .src_pixel = 0x2ca00565, /* RGB565 */
362 .ch1_pixel = 0x2ca00565, /* RGB565 */
363 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
364 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
365 .csicr1 = 0,
366 }
367 },
368 {
369 .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8,
370 .out_fmt = V4L2_PIX_FMT_YUYV,
371 .cfg = {
372 .channel = 1,
373 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
374 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
375 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
376 .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */
377 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
378 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
379 .csicr1 = CSICR1_SWAP16_EN,
380 }
381 },
382 {
383 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
384 .out_fmt = V4L2_PIX_FMT_YUYV,
385 .cfg = {
386 .channel = 1,
387 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
388 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
389 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
390 .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */
391 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
392 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
393 .csicr1 = CSICR1_PACK_DIR,
394 }
395 },
396 {
397 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
398 .out_fmt = V4L2_PIX_FMT_YUV420,
399 .cfg = {
400 .channel = 2,
401 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
402 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
403 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
404 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
405 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
406 PRP_INTR_CH2OVF,
407 .csicr1 = CSICR1_PACK_DIR,
408 }
409 },
410 {
411 .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8,
412 .out_fmt = V4L2_PIX_FMT_YUV420,
413 .cfg = {
414 .channel = 2,
415 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
416 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
417 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
418 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
419 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
420 PRP_INTR_CH2OVF,
421 .csicr1 = CSICR1_SWAP16_EN,
422 }
423 },
424 };
425
426 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
427 enum v4l2_mbus_pixelcode in_fmt,
428 u32 out_fmt)
429 {
430 int i;
431
432 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
433 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
434 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
435 return &mx27_emma_prp_table[i];
436 }
437 /* If no match return the most generic configuration */
438 return &mx27_emma_prp_table[0];
439 };
440
441 static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
442 unsigned long phys, int bufnum)
443 {
444 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
445
446 if (prp->cfg.channel == 1) {
447 writel(phys, pcdev->base_emma +
448 PRP_DEST_RGB1_PTR + 4 * bufnum);
449 } else {
450 writel(phys, pcdev->base_emma +
451 PRP_DEST_Y_PTR - 0x14 * bufnum);
452 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
453 u32 imgsize = pcdev->icd->user_height *
454 pcdev->icd->user_width;
455
456 writel(phys + imgsize, pcdev->base_emma +
457 PRP_DEST_CB_PTR - 0x14 * bufnum);
458 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
459 PRP_DEST_CR_PTR - 0x14 * bufnum);
460 }
461 }
462 }
463
464 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
465 {
466 unsigned long flags;
467
468 clk_disable_unprepare(pcdev->clk_csi_ahb);
469 clk_disable_unprepare(pcdev->clk_csi_per);
470 writel(0, pcdev->base_csi + CSICR1);
471 if (is_imx27_camera(pcdev)) {
472 writel(0, pcdev->base_emma + PRP_CNTL);
473 } else if (is_imx25_camera(pcdev)) {
474 spin_lock_irqsave(&pcdev->lock, flags);
475 pcdev->fb1_active = NULL;
476 pcdev->fb2_active = NULL;
477 writel(0, pcdev->base_csi + CSIDMASA_FB1);
478 writel(0, pcdev->base_csi + CSIDMASA_FB2);
479 spin_unlock_irqrestore(&pcdev->lock, flags);
480 }
481 }
482
483 /*
484 * The following two functions absolutely depend on the fact, that
485 * there can be only one camera on mx2 camera sensor interface
486 */
487 static int mx2_camera_add_device(struct soc_camera_device *icd)
488 {
489 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
490 struct mx2_camera_dev *pcdev = ici->priv;
491 int ret;
492 u32 csicr1;
493
494 if (pcdev->icd)
495 return -EBUSY;
496
497 ret = clk_prepare_enable(pcdev->clk_csi_ahb);
498 if (ret < 0)
499 return ret;
500
501 ret = clk_prepare_enable(pcdev->clk_csi_per);
502 if (ret < 0)
503 goto exit_csi_ahb;
504
505 csicr1 = CSICR1_MCLKEN;
506
507 if (is_imx27_camera(pcdev))
508 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
509 CSICR1_RXFF_LEVEL(0);
510
511 pcdev->csicr1 = csicr1;
512 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
513
514 pcdev->icd = icd;
515 pcdev->frame_count = 0;
516
517 dev_info(icd->parent, "Camera driver attached to camera %d\n",
518 icd->devnum);
519
520 return 0;
521
522 exit_csi_ahb:
523 clk_disable_unprepare(pcdev->clk_csi_ahb);
524
525 return ret;
526 }
527
528 static void mx2_camera_remove_device(struct soc_camera_device *icd)
529 {
530 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
531 struct mx2_camera_dev *pcdev = ici->priv;
532
533 BUG_ON(icd != pcdev->icd);
534
535 dev_info(icd->parent, "Camera driver detached from camera %d\n",
536 icd->devnum);
537
538 mx2_camera_deactivate(pcdev);
539
540 pcdev->icd = NULL;
541 }
542
543 static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
544 int state)
545 {
546 struct vb2_buffer *vb;
547 struct mx2_buffer *buf;
548 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
549 &pcdev->fb2_active;
550 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
551 unsigned long flags;
552
553 spin_lock_irqsave(&pcdev->lock, flags);
554
555 if (*fb_active == NULL)
556 goto out;
557
558 vb = &(*fb_active)->vb;
559 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
560 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
561
562 do_gettimeofday(&vb->v4l2_buf.timestamp);
563 vb->v4l2_buf.sequence++;
564 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
565
566 if (list_empty(&pcdev->capture)) {
567 buf = NULL;
568 writel(0, pcdev->base_csi + fb_reg);
569 } else {
570 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
571 internal.queue);
572 vb = &buf->vb;
573 list_del(&buf->internal.queue);
574 buf->state = MX2_STATE_ACTIVE;
575 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
576 pcdev->base_csi + fb_reg);
577 }
578
579 *fb_active = buf;
580
581 out:
582 spin_unlock_irqrestore(&pcdev->lock, flags);
583 }
584
585 static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
586 {
587 struct mx2_camera_dev *pcdev = data;
588 u32 status = readl(pcdev->base_csi + pcdev->reg_csisr);
589
590 if (status & CSISR_DMA_TSF_FB1_INT)
591 mx25_camera_frame_done(pcdev, 1, MX2_STATE_DONE);
592 else if (status & CSISR_DMA_TSF_FB2_INT)
593 mx25_camera_frame_done(pcdev, 2, MX2_STATE_DONE);
594
595 /* FIXME: handle CSISR_RFF_OR_INT */
596
597 writel(status, pcdev->base_csi + pcdev->reg_csisr);
598
599 return IRQ_HANDLED;
600 }
601
602 /*
603 * Videobuf operations
604 */
605 static int mx2_videobuf_setup(struct vb2_queue *vq,
606 const struct v4l2_format *fmt,
607 unsigned int *count, unsigned int *num_planes,
608 unsigned int sizes[], void *alloc_ctxs[])
609 {
610 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
611 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
612 struct mx2_camera_dev *pcdev = ici->priv;
613
614 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
615
616 /* TODO: support for VIDIOC_CREATE_BUFS not ready */
617 if (fmt != NULL)
618 return -ENOTTY;
619
620 alloc_ctxs[0] = pcdev->alloc_ctx;
621
622 sizes[0] = icd->sizeimage;
623
624 if (0 == *count)
625 *count = 32;
626 if (!*num_planes &&
627 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
628 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
629
630 *num_planes = 1;
631
632 return 0;
633 }
634
635 static int mx2_videobuf_prepare(struct vb2_buffer *vb)
636 {
637 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
638 int ret = 0;
639
640 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
641 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
642
643 #ifdef DEBUG
644 /*
645 * This can be useful if you want to see if we actually fill
646 * the buffer with something
647 */
648 memset((void *)vb2_plane_vaddr(vb, 0),
649 0xaa, vb2_get_plane_payload(vb, 0));
650 #endif
651
652 vb2_set_plane_payload(vb, 0, icd->sizeimage);
653 if (vb2_plane_vaddr(vb, 0) &&
654 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
655 ret = -EINVAL;
656 goto out;
657 }
658
659 return 0;
660
661 out:
662 return ret;
663 }
664
665 static void mx2_videobuf_queue(struct vb2_buffer *vb)
666 {
667 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
668 struct soc_camera_host *ici =
669 to_soc_camera_host(icd->parent);
670 struct mx2_camera_dev *pcdev = ici->priv;
671 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
672 unsigned long flags;
673
674 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
675 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
676
677 spin_lock_irqsave(&pcdev->lock, flags);
678
679 buf->state = MX2_STATE_QUEUED;
680 list_add_tail(&buf->internal.queue, &pcdev->capture);
681
682 if (is_imx25_camera(pcdev)) {
683 u32 csicr3, dma_inten = 0;
684
685 if (pcdev->fb1_active == NULL) {
686 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
687 pcdev->base_csi + CSIDMASA_FB1);
688 pcdev->fb1_active = buf;
689 dma_inten = CSICR1_FB1_DMA_INTEN;
690 } else if (pcdev->fb2_active == NULL) {
691 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
692 pcdev->base_csi + CSIDMASA_FB2);
693 pcdev->fb2_active = buf;
694 dma_inten = CSICR1_FB2_DMA_INTEN;
695 }
696
697 if (dma_inten) {
698 list_del(&buf->internal.queue);
699 buf->state = MX2_STATE_ACTIVE;
700
701 csicr3 = readl(pcdev->base_csi + pcdev->reg_csicr3);
702
703 /* Reflash DMA */
704 writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
705 pcdev->base_csi + pcdev->reg_csicr3);
706
707 /* clear & enable interrupts */
708 writel(dma_inten, pcdev->base_csi + pcdev->reg_csisr);
709 pcdev->csicr1 |= dma_inten;
710 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
711
712 /* enable DMA */
713 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
714 writel(csicr3, pcdev->base_csi + pcdev->reg_csicr3);
715 }
716 }
717
718 spin_unlock_irqrestore(&pcdev->lock, flags);
719 }
720
721 static void mx2_videobuf_release(struct vb2_buffer *vb)
722 {
723 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
724 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
725 struct mx2_camera_dev *pcdev = ici->priv;
726 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
727 unsigned long flags;
728
729 #ifdef DEBUG
730 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
731 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
732
733 switch (buf->state) {
734 case MX2_STATE_ACTIVE:
735 dev_info(icd->parent, "%s (active)\n", __func__);
736 break;
737 case MX2_STATE_QUEUED:
738 dev_info(icd->parent, "%s (queued)\n", __func__);
739 break;
740 default:
741 dev_info(icd->parent, "%s (unknown) %d\n", __func__,
742 buf->state);
743 break;
744 }
745 #endif
746
747 /*
748 * Terminate only queued but inactive buffers. Active buffers are
749 * released when they become inactive after videobuf_waiton().
750 *
751 * FIXME: implement forced termination of active buffers for mx27 and
752 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
753 * state. This requires a specific handling for each of the these DMA
754 * types.
755 */
756
757 spin_lock_irqsave(&pcdev->lock, flags);
758 if (is_imx25_camera(pcdev) && buf->state == MX2_STATE_ACTIVE) {
759 if (pcdev->fb1_active == buf) {
760 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN;
761 writel(0, pcdev->base_csi + CSIDMASA_FB1);
762 pcdev->fb1_active = NULL;
763 } else if (pcdev->fb2_active == buf) {
764 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN;
765 writel(0, pcdev->base_csi + CSIDMASA_FB2);
766 pcdev->fb2_active = NULL;
767 }
768 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
769 }
770 spin_unlock_irqrestore(&pcdev->lock, flags);
771 }
772
773 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
774 int bytesperline)
775 {
776 struct soc_camera_host *ici =
777 to_soc_camera_host(icd->parent);
778 struct mx2_camera_dev *pcdev = ici->priv;
779 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
780
781 writel((pcdev->s_width << 16) | pcdev->s_height,
782 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
783 writel(prp->cfg.src_pixel,
784 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
785 if (prp->cfg.channel == 1) {
786 writel((icd->user_width << 16) | icd->user_height,
787 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
788 writel(bytesperline,
789 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
790 writel(prp->cfg.ch1_pixel,
791 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
792 } else { /* channel 2 */
793 writel((icd->user_width << 16) | icd->user_height,
794 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
795 }
796
797 /* Enable interrupts */
798 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
799 }
800
801 static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev)
802 {
803 int dir;
804
805 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
806 unsigned char *s = pcdev->resizing[dir].s;
807 int len = pcdev->resizing[dir].len;
808 unsigned int coeff[2] = {0, 0};
809 unsigned int valid = 0;
810 int i;
811
812 if (len == 0)
813 continue;
814
815 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) {
816 int j;
817
818 j = i > 9 ? 1 : 0;
819 coeff[j] = (coeff[j] << BC_COEF) |
820 (s[i] & (SZ_COEF - 1));
821
822 if (i == 5 || i == 15)
823 coeff[j] <<= 1;
824
825 valid = (valid << 1) | (s[i] >> BC_COEF);
826 }
827
828 valid |= PRP_RZ_VALID_TBL_LEN(len);
829
830 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR)
831 valid |= PRP_RZ_VALID_BILINEAR;
832
833 if (pcdev->emma_prp->cfg.channel == 1) {
834 if (dir == RESIZE_DIR_H) {
835 writel(coeff[0], pcdev->base_emma +
836 PRP_CH1_RZ_HORI_COEF1);
837 writel(coeff[1], pcdev->base_emma +
838 PRP_CH1_RZ_HORI_COEF2);
839 writel(valid, pcdev->base_emma +
840 PRP_CH1_RZ_HORI_VALID);
841 } else {
842 writel(coeff[0], pcdev->base_emma +
843 PRP_CH1_RZ_VERT_COEF1);
844 writel(coeff[1], pcdev->base_emma +
845 PRP_CH1_RZ_VERT_COEF2);
846 writel(valid, pcdev->base_emma +
847 PRP_CH1_RZ_VERT_VALID);
848 }
849 } else {
850 if (dir == RESIZE_DIR_H) {
851 writel(coeff[0], pcdev->base_emma +
852 PRP_CH2_RZ_HORI_COEF1);
853 writel(coeff[1], pcdev->base_emma +
854 PRP_CH2_RZ_HORI_COEF2);
855 writel(valid, pcdev->base_emma +
856 PRP_CH2_RZ_HORI_VALID);
857 } else {
858 writel(coeff[0], pcdev->base_emma +
859 PRP_CH2_RZ_VERT_COEF1);
860 writel(coeff[1], pcdev->base_emma +
861 PRP_CH2_RZ_VERT_COEF2);
862 writel(valid, pcdev->base_emma +
863 PRP_CH2_RZ_VERT_VALID);
864 }
865 }
866 }
867 }
868
869 static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
870 {
871 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
872 struct soc_camera_host *ici =
873 to_soc_camera_host(icd->parent);
874 struct mx2_camera_dev *pcdev = ici->priv;
875 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
876 struct vb2_buffer *vb;
877 struct mx2_buffer *buf;
878 unsigned long phys;
879 int bytesperline;
880
881 if (is_imx27_camera(pcdev)) {
882 unsigned long flags;
883 if (count < 2)
884 return -EINVAL;
885
886 spin_lock_irqsave(&pcdev->lock, flags);
887
888 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
889 internal.queue);
890 buf->internal.bufnum = 0;
891 vb = &buf->vb;
892 buf->state = MX2_STATE_ACTIVE;
893
894 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
895 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
896 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
897
898 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
899 internal.queue);
900 buf->internal.bufnum = 1;
901 vb = &buf->vb;
902 buf->state = MX2_STATE_ACTIVE;
903
904 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
905 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
906 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
907
908 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
909 icd->current_fmt->host_fmt);
910 if (bytesperline < 0)
911 return bytesperline;
912
913 /*
914 * I didn't manage to properly enable/disable the prp
915 * on a per frame basis during running transfers,
916 * thus we allocate a buffer here and use it to
917 * discard frames when no buffer is available.
918 * Feel free to work on this ;)
919 */
920 pcdev->discard_size = icd->user_height * bytesperline;
921 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
922 pcdev->discard_size, &pcdev->discard_buffer_dma,
923 GFP_KERNEL);
924 if (!pcdev->discard_buffer)
925 return -ENOMEM;
926
927 pcdev->buf_discard[0].discard = true;
928 list_add_tail(&pcdev->buf_discard[0].queue,
929 &pcdev->discard);
930
931 pcdev->buf_discard[1].discard = true;
932 list_add_tail(&pcdev->buf_discard[1].queue,
933 &pcdev->discard);
934
935 mx2_prp_resize_commit(pcdev);
936
937 mx27_camera_emma_buf_init(icd, bytesperline);
938
939 if (prp->cfg.channel == 1) {
940 writel(PRP_CNTL_CH1EN |
941 PRP_CNTL_CSIEN |
942 prp->cfg.in_fmt |
943 prp->cfg.out_fmt |
944 PRP_CNTL_CH1_LEN |
945 PRP_CNTL_CH1BYP |
946 PRP_CNTL_CH1_TSKIP(0) |
947 PRP_CNTL_IN_TSKIP(0),
948 pcdev->base_emma + PRP_CNTL);
949 } else {
950 writel(PRP_CNTL_CH2EN |
951 PRP_CNTL_CSIEN |
952 prp->cfg.in_fmt |
953 prp->cfg.out_fmt |
954 PRP_CNTL_CH2_LEN |
955 PRP_CNTL_CH2_TSKIP(0) |
956 PRP_CNTL_IN_TSKIP(0),
957 pcdev->base_emma + PRP_CNTL);
958 }
959 spin_unlock_irqrestore(&pcdev->lock, flags);
960 }
961
962 return 0;
963 }
964
965 static int mx2_stop_streaming(struct vb2_queue *q)
966 {
967 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
968 struct soc_camera_host *ici =
969 to_soc_camera_host(icd->parent);
970 struct mx2_camera_dev *pcdev = ici->priv;
971 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
972 unsigned long flags;
973 void *b;
974 u32 cntl;
975
976 if (is_imx27_camera(pcdev)) {
977 spin_lock_irqsave(&pcdev->lock, flags);
978
979 cntl = readl(pcdev->base_emma + PRP_CNTL);
980 if (prp->cfg.channel == 1) {
981 writel(cntl & ~PRP_CNTL_CH1EN,
982 pcdev->base_emma + PRP_CNTL);
983 } else {
984 writel(cntl & ~PRP_CNTL_CH2EN,
985 pcdev->base_emma + PRP_CNTL);
986 }
987 INIT_LIST_HEAD(&pcdev->capture);
988 INIT_LIST_HEAD(&pcdev->active_bufs);
989 INIT_LIST_HEAD(&pcdev->discard);
990
991 b = pcdev->discard_buffer;
992 pcdev->discard_buffer = NULL;
993
994 spin_unlock_irqrestore(&pcdev->lock, flags);
995
996 dma_free_coherent(ici->v4l2_dev.dev,
997 pcdev->discard_size, b, pcdev->discard_buffer_dma);
998 }
999
1000 return 0;
1001 }
1002
1003 static struct vb2_ops mx2_videobuf_ops = {
1004 .queue_setup = mx2_videobuf_setup,
1005 .buf_prepare = mx2_videobuf_prepare,
1006 .buf_queue = mx2_videobuf_queue,
1007 .buf_cleanup = mx2_videobuf_release,
1008 .start_streaming = mx2_start_streaming,
1009 .stop_streaming = mx2_stop_streaming,
1010 };
1011
1012 static int mx2_camera_init_videobuf(struct vb2_queue *q,
1013 struct soc_camera_device *icd)
1014 {
1015 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1016 q->io_modes = VB2_MMAP | VB2_USERPTR;
1017 q->drv_priv = icd;
1018 q->ops = &mx2_videobuf_ops;
1019 q->mem_ops = &vb2_dma_contig_memops;
1020 q->buf_struct_size = sizeof(struct mx2_buffer);
1021
1022 return vb2_queue_init(q);
1023 }
1024
1025 #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
1026 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
1027 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
1028 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
1029 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
1030 V4L2_MBUS_PCLK_SAMPLE_RISING | \
1031 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
1032 V4L2_MBUS_DATA_ACTIVE_HIGH | \
1033 V4L2_MBUS_DATA_ACTIVE_LOW)
1034
1035 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
1036 {
1037 u32 cntl;
1038 int count = 0;
1039
1040 cntl = readl(pcdev->base_emma + PRP_CNTL);
1041 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
1042 while (count++ < 100) {
1043 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
1044 return 0;
1045 barrier();
1046 udelay(1);
1047 }
1048
1049 return -ETIMEDOUT;
1050 }
1051
1052 static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
1053 {
1054 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1055 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1056 struct mx2_camera_dev *pcdev = ici->priv;
1057 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1058 unsigned long common_flags;
1059 int ret;
1060 int bytesperline;
1061 u32 csicr1 = pcdev->csicr1;
1062
1063 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1064 if (!ret) {
1065 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
1066 if (!common_flags) {
1067 dev_warn(icd->parent,
1068 "Flags incompatible: camera 0x%x, host 0x%x\n",
1069 cfg.flags, MX2_BUS_FLAGS);
1070 return -EINVAL;
1071 }
1072 } else if (ret != -ENOIOCTLCMD) {
1073 return ret;
1074 } else {
1075 common_flags = MX2_BUS_FLAGS;
1076 }
1077
1078 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1079 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1080 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
1081 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1082 else
1083 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1084 }
1085
1086 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1087 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1088 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
1089 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1090 else
1091 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1092 }
1093
1094 cfg.flags = common_flags;
1095 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1096 if (ret < 0 && ret != -ENOIOCTLCMD) {
1097 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
1098 common_flags, ret);
1099 return ret;
1100 }
1101
1102 csicr1 = (csicr1 & ~CSICR1_FMT_MASK) | pcdev->emma_prp->cfg.csicr1;
1103
1104 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1105 csicr1 |= CSICR1_REDGE;
1106 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1107 csicr1 |= CSICR1_SOF_POL;
1108 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1109 csicr1 |= CSICR1_HSYNC_POL;
1110 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
1111 csicr1 |= CSICR1_EXT_VSYNC;
1112 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
1113 csicr1 |= CSICR1_CCIR_EN;
1114 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
1115 csicr1 |= CSICR1_CCIR_MODE;
1116 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
1117 csicr1 |= CSICR1_GCLK_MODE;
1118 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
1119 csicr1 |= CSICR1_INV_DATA;
1120
1121 pcdev->csicr1 = csicr1;
1122
1123 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
1124 icd->current_fmt->host_fmt);
1125 if (bytesperline < 0)
1126 return bytesperline;
1127
1128 if (is_imx27_camera(pcdev)) {
1129 ret = mx27_camera_emma_prp_reset(pcdev);
1130 if (ret)
1131 return ret;
1132 } else if (is_imx25_camera(pcdev)) {
1133 writel((bytesperline * icd->user_height) >> 2,
1134 pcdev->base_csi + CSIRXCNT);
1135 writel((bytesperline << 16) | icd->user_height,
1136 pcdev->base_csi + CSIIMAG_PARA);
1137 }
1138
1139 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
1140
1141 return 0;
1142 }
1143
1144 static int mx2_camera_set_crop(struct soc_camera_device *icd,
1145 struct v4l2_crop *a)
1146 {
1147 struct v4l2_rect *rect = &a->c;
1148 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1149 struct v4l2_mbus_framefmt mf;
1150 int ret;
1151
1152 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
1153 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
1154
1155 ret = v4l2_subdev_call(sd, video, s_crop, a);
1156 if (ret < 0)
1157 return ret;
1158
1159 /* The capture device might have changed its output */
1160 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
1161 if (ret < 0)
1162 return ret;
1163
1164 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
1165 mf.width, mf.height);
1166
1167 icd->user_width = mf.width;
1168 icd->user_height = mf.height;
1169
1170 return ret;
1171 }
1172
1173 static int mx2_camera_get_formats(struct soc_camera_device *icd,
1174 unsigned int idx,
1175 struct soc_camera_format_xlate *xlate)
1176 {
1177 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1178 const struct soc_mbus_pixelfmt *fmt;
1179 struct device *dev = icd->parent;
1180 enum v4l2_mbus_pixelcode code;
1181 int ret, formats = 0;
1182
1183 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1184 if (ret < 0)
1185 /* no more formats */
1186 return 0;
1187
1188 fmt = soc_mbus_get_fmtdesc(code);
1189 if (!fmt) {
1190 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
1191 return 0;
1192 }
1193
1194 if (code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1195 code == V4L2_MBUS_FMT_UYVY8_2X8) {
1196 formats++;
1197 if (xlate) {
1198 /*
1199 * CH2 can output YUV420 which is a standard format in
1200 * soc_mediabus.c
1201 */
1202 xlate->host_fmt =
1203 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8);
1204 xlate->code = code;
1205 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1206 xlate->host_fmt->name, code);
1207 xlate++;
1208 }
1209 }
1210
1211 if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
1212 formats++;
1213 if (xlate) {
1214 xlate->host_fmt =
1215 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_2X8);
1216 xlate->code = code;
1217 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1218 xlate->host_fmt->name, code);
1219 xlate++;
1220 }
1221 }
1222
1223 /* Generic pass-trough */
1224 formats++;
1225 if (xlate) {
1226 xlate->host_fmt = fmt;
1227 xlate->code = code;
1228 xlate++;
1229 }
1230 return formats;
1231 }
1232
1233 static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev,
1234 struct v4l2_mbus_framefmt *mf_in,
1235 struct v4l2_pix_format *pix_out, bool apply)
1236 {
1237 int num, den;
1238 unsigned long m;
1239 int i, dir;
1240
1241 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
1242 struct emma_prp_resize tmprsz;
1243 unsigned char *s = tmprsz.s;
1244 int len = 0;
1245 int in, out;
1246
1247 if (dir == RESIZE_DIR_H) {
1248 in = mf_in->width;
1249 out = pix_out->width;
1250 } else {
1251 in = mf_in->height;
1252 out = pix_out->height;
1253 }
1254
1255 if (in < out)
1256 return -EINVAL;
1257 else if (in == out)
1258 continue;
1259
1260 /* Calculate ratio */
1261 m = gcd(in, out);
1262 num = in / m;
1263 den = out / m;
1264 if (num > RESIZE_NUM_MAX)
1265 return -EINVAL;
1266
1267 if ((num >= 2 * den) && (den == 1) &&
1268 (num < 9) && (!(num & 0x01))) {
1269 int sum = 0;
1270 int j;
1271
1272 /* Average scaling for >= 2:1 ratios */
1273 /* Support can be added for num >=9 and odd values */
1274
1275 tmprsz.algo = RESIZE_ALGO_AVERAGING;
1276 len = num;
1277
1278 for (i = 0; i < (len / 2); i++)
1279 s[i] = 8;
1280
1281 do {
1282 for (i = 0; i < (len / 2); i++) {
1283 s[i] = s[i] >> 1;
1284 sum = 0;
1285 for (j = 0; j < (len / 2); j++)
1286 sum += s[j];
1287 if (sum == 4)
1288 break;
1289 }
1290 } while (sum != 4);
1291
1292 for (i = (len / 2); i < len; i++)
1293 s[i] = s[len - i - 1];
1294
1295 s[len - 1] |= SZ_COEF;
1296 } else {
1297 /* bilinear scaling for < 2:1 ratios */
1298 int v; /* overflow counter */
1299 int coeff, nxt; /* table output */
1300 int in_pos_inc = 2 * den;
1301 int out_pos = num;
1302 int out_pos_inc = 2 * num;
1303 int init_carry = num - den;
1304 int carry = init_carry;
1305
1306 tmprsz.algo = RESIZE_ALGO_BILINEAR;
1307 v = den + in_pos_inc;
1308 do {
1309 coeff = v - out_pos;
1310 out_pos += out_pos_inc;
1311 carry += out_pos_inc;
1312 for (nxt = 0; v < out_pos; nxt++) {
1313 v += in_pos_inc;
1314 carry -= in_pos_inc;
1315 }
1316
1317 if (len > RESIZE_NUM_MAX)
1318 return -EINVAL;
1319
1320 coeff = ((coeff << BC_COEF) +
1321 (in_pos_inc >> 1)) / in_pos_inc;
1322
1323 if (coeff >= (SZ_COEF - 1))
1324 coeff--;
1325
1326 coeff |= SZ_COEF;
1327 s[len] = (unsigned char)coeff;
1328 len++;
1329
1330 for (i = 1; i < nxt; i++) {
1331 if (len >= RESIZE_NUM_MAX)
1332 return -EINVAL;
1333 s[len] = 0;
1334 len++;
1335 }
1336 } while (carry != init_carry);
1337 }
1338 tmprsz.len = len;
1339 if (dir == RESIZE_DIR_H)
1340 mf_in->width = pix_out->width;
1341 else
1342 mf_in->height = pix_out->height;
1343
1344 if (apply)
1345 memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz));
1346 }
1347 return 0;
1348 }
1349
1350 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1351 struct v4l2_format *f)
1352 {
1353 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1354 struct mx2_camera_dev *pcdev = ici->priv;
1355 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1356 const struct soc_camera_format_xlate *xlate;
1357 struct v4l2_pix_format *pix = &f->fmt.pix;
1358 struct v4l2_mbus_framefmt mf;
1359 int ret;
1360
1361 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1362 __func__, pix->width, pix->height);
1363
1364 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1365 if (!xlate) {
1366 dev_warn(icd->parent, "Format %x not found\n",
1367 pix->pixelformat);
1368 return -EINVAL;
1369 }
1370
1371 mf.width = pix->width;
1372 mf.height = pix->height;
1373 mf.field = pix->field;
1374 mf.colorspace = pix->colorspace;
1375 mf.code = xlate->code;
1376
1377 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1378 if (ret < 0 && ret != -ENOIOCTLCMD)
1379 return ret;
1380
1381 /* Store width and height returned by the sensor for resizing */
1382 pcdev->s_width = mf.width;
1383 pcdev->s_height = mf.height;
1384 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1385 __func__, pcdev->s_width, pcdev->s_height);
1386
1387 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1388 xlate->host_fmt->fourcc);
1389
1390 memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1391 if ((mf.width != pix->width || mf.height != pix->height) &&
1392 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1393 if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0)
1394 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1395 }
1396
1397 if (mf.code != xlate->code)
1398 return -EINVAL;
1399
1400 pix->width = mf.width;
1401 pix->height = mf.height;
1402 pix->field = mf.field;
1403 pix->colorspace = mf.colorspace;
1404 icd->current_fmt = xlate;
1405
1406 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1407 __func__, pix->width, pix->height);
1408
1409 return 0;
1410 }
1411
1412 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1413 struct v4l2_format *f)
1414 {
1415 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1416 const struct soc_camera_format_xlate *xlate;
1417 struct v4l2_pix_format *pix = &f->fmt.pix;
1418 struct v4l2_mbus_framefmt mf;
1419 __u32 pixfmt = pix->pixelformat;
1420 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1421 struct mx2_camera_dev *pcdev = ici->priv;
1422 struct mx2_fmt_cfg *emma_prp;
1423 unsigned int width_limit;
1424 int ret;
1425
1426 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1427 __func__, pix->width, pix->height);
1428
1429 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1430 if (pixfmt && !xlate) {
1431 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1432 return -EINVAL;
1433 }
1434
1435 /* FIXME: implement MX27 limits */
1436
1437 /* limit to MX25 hardware capabilities */
1438 if (is_imx25_camera(pcdev)) {
1439 if (xlate->host_fmt->bits_per_sample <= 8)
1440 width_limit = 0xffff * 4;
1441 else
1442 width_limit = 0xffff * 2;
1443 /* CSIIMAG_PARA limit */
1444 if (pix->width > width_limit)
1445 pix->width = width_limit;
1446 if (pix->height > 0xffff)
1447 pix->height = 0xffff;
1448
1449 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1450 xlate->host_fmt);
1451 if (pix->bytesperline < 0)
1452 return pix->bytesperline;
1453 pix->sizeimage = soc_mbus_image_size(xlate->host_fmt,
1454 pix->bytesperline, pix->height);
1455 /* Check against the CSIRXCNT limit */
1456 if (pix->sizeimage > 4 * 0x3ffff) {
1457 /* Adjust geometry, preserve aspect ratio */
1458 unsigned int new_height = int_sqrt(div_u64(0x3ffffULL *
1459 4 * pix->height, pix->bytesperline));
1460 pix->width = new_height * pix->width / pix->height;
1461 pix->height = new_height;
1462 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1463 xlate->host_fmt);
1464 BUG_ON(pix->bytesperline < 0);
1465 pix->sizeimage = soc_mbus_image_size(xlate->host_fmt,
1466 pix->bytesperline, pix->height);
1467 }
1468 }
1469
1470 /* limit to sensor capabilities */
1471 mf.width = pix->width;
1472 mf.height = pix->height;
1473 mf.field = pix->field;
1474 mf.colorspace = pix->colorspace;
1475 mf.code = xlate->code;
1476
1477 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1478 if (ret < 0)
1479 return ret;
1480
1481 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1482 __func__, pcdev->s_width, pcdev->s_height);
1483
1484 /* If the sensor does not support image size try PrP resizing */
1485 emma_prp = mx27_emma_prp_get_format(xlate->code,
1486 xlate->host_fmt->fourcc);
1487
1488 if ((mf.width != pix->width || mf.height != pix->height) &&
1489 emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1490 if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0)
1491 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1492 }
1493
1494 if (mf.field == V4L2_FIELD_ANY)
1495 mf.field = V4L2_FIELD_NONE;
1496 /*
1497 * Driver supports interlaced images provided they have
1498 * both fields so that they can be processed as if they
1499 * were progressive.
1500 */
1501 if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) {
1502 dev_err(icd->parent, "Field type %d unsupported.\n",
1503 mf.field);
1504 return -EINVAL;
1505 }
1506
1507 pix->width = mf.width;
1508 pix->height = mf.height;
1509 pix->field = mf.field;
1510 pix->colorspace = mf.colorspace;
1511
1512 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1513 __func__, pix->width, pix->height);
1514
1515 return 0;
1516 }
1517
1518 static int mx2_camera_querycap(struct soc_camera_host *ici,
1519 struct v4l2_capability *cap)
1520 {
1521 /* cap->name is set by the friendly caller:-> */
1522 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1523 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1524
1525 return 0;
1526 }
1527
1528 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1529 {
1530 struct soc_camera_device *icd = file->private_data;
1531
1532 return vb2_poll(&icd->vb2_vidq, file, pt);
1533 }
1534
1535 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1536 .owner = THIS_MODULE,
1537 .add = mx2_camera_add_device,
1538 .remove = mx2_camera_remove_device,
1539 .set_fmt = mx2_camera_set_fmt,
1540 .set_crop = mx2_camera_set_crop,
1541 .get_formats = mx2_camera_get_formats,
1542 .try_fmt = mx2_camera_try_fmt,
1543 .init_videobuf2 = mx2_camera_init_videobuf,
1544 .poll = mx2_camera_poll,
1545 .querycap = mx2_camera_querycap,
1546 .set_bus_param = mx2_camera_set_bus_param,
1547 };
1548
1549 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1550 int bufnum, bool err)
1551 {
1552 #ifdef DEBUG
1553 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1554 #endif
1555 struct mx2_buf_internal *ibuf;
1556 struct mx2_buffer *buf;
1557 struct vb2_buffer *vb;
1558 unsigned long phys;
1559
1560 ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1561 queue);
1562
1563 BUG_ON(ibuf->bufnum != bufnum);
1564
1565 if (ibuf->discard) {
1566 /*
1567 * Discard buffer must not be returned to user space.
1568 * Just return it to the discard queue.
1569 */
1570 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1571 } else {
1572 buf = mx2_ibuf_to_buf(ibuf);
1573
1574 vb = &buf->vb;
1575 #ifdef DEBUG
1576 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1577 if (prp->cfg.channel == 1) {
1578 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1579 4 * bufnum) != phys) {
1580 dev_err(pcdev->dev, "%lx != %x\n", phys,
1581 readl(pcdev->base_emma +
1582 PRP_DEST_RGB1_PTR + 4 * bufnum));
1583 }
1584 } else {
1585 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1586 0x14 * bufnum) != phys) {
1587 dev_err(pcdev->dev, "%lx != %x\n", phys,
1588 readl(pcdev->base_emma +
1589 PRP_DEST_Y_PTR - 0x14 * bufnum));
1590 }
1591 }
1592 #endif
1593 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1594 vb2_plane_vaddr(vb, 0),
1595 vb2_get_plane_payload(vb, 0));
1596
1597 list_del_init(&buf->internal.queue);
1598 do_gettimeofday(&vb->v4l2_buf.timestamp);
1599 vb->v4l2_buf.sequence = pcdev->frame_count;
1600 if (err)
1601 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1602 else
1603 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1604 }
1605
1606 pcdev->frame_count++;
1607
1608 if (list_empty(&pcdev->capture)) {
1609 if (list_empty(&pcdev->discard)) {
1610 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1611 __func__);
1612 return;
1613 }
1614
1615 ibuf = list_first_entry(&pcdev->discard,
1616 struct mx2_buf_internal, queue);
1617 ibuf->bufnum = bufnum;
1618
1619 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1620 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1621 return;
1622 }
1623
1624 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1625 internal.queue);
1626
1627 buf->internal.bufnum = bufnum;
1628
1629 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1630
1631 vb = &buf->vb;
1632 buf->state = MX2_STATE_ACTIVE;
1633
1634 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1635 mx27_update_emma_buf(pcdev, phys, bufnum);
1636 }
1637
1638 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1639 {
1640 struct mx2_camera_dev *pcdev = data;
1641 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1642 struct mx2_buf_internal *ibuf;
1643
1644 spin_lock(&pcdev->lock);
1645
1646 if (list_empty(&pcdev->active_bufs)) {
1647 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1648 __func__);
1649
1650 if (!status) {
1651 spin_unlock(&pcdev->lock);
1652 return IRQ_NONE;
1653 }
1654 }
1655
1656 if (status & (1 << 7)) { /* overflow */
1657 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1658 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1659 pcdev->base_emma + PRP_CNTL);
1660 writel(cntl, pcdev->base_emma + PRP_CNTL);
1661
1662 ibuf = list_first_entry(&pcdev->active_bufs,
1663 struct mx2_buf_internal, queue);
1664 mx27_camera_frame_done_emma(pcdev,
1665 ibuf->bufnum, true);
1666
1667 status &= ~(1 << 7);
1668 } else if (((status & (3 << 5)) == (3 << 5)) ||
1669 ((status & (3 << 3)) == (3 << 3))) {
1670 /*
1671 * Both buffers have triggered, process the one we're expecting
1672 * to first
1673 */
1674 ibuf = list_first_entry(&pcdev->active_bufs,
1675 struct mx2_buf_internal, queue);
1676 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1677 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */
1678 } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1679 mx27_camera_frame_done_emma(pcdev, 0, false);
1680 } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1681 mx27_camera_frame_done_emma(pcdev, 1, false);
1682 }
1683
1684 spin_unlock(&pcdev->lock);
1685 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1686
1687 return IRQ_HANDLED;
1688 }
1689
1690 static int __devinit mx27_camera_emma_init(struct platform_device *pdev)
1691 {
1692 struct mx2_camera_dev *pcdev = platform_get_drvdata(pdev);
1693 struct resource *res_emma;
1694 int irq_emma;
1695 int err = 0;
1696
1697 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1698 irq_emma = platform_get_irq(pdev, 1);
1699 if (!res_emma || !irq_emma) {
1700 dev_err(pcdev->dev, "no EMMA resources\n");
1701 err = -ENODEV;
1702 goto out;
1703 }
1704
1705 pcdev->base_emma = devm_request_and_ioremap(pcdev->dev, res_emma);
1706 if (!pcdev->base_emma) {
1707 err = -EADDRNOTAVAIL;
1708 goto out;
1709 }
1710
1711 err = devm_request_irq(pcdev->dev, irq_emma, mx27_camera_emma_irq, 0,
1712 MX2_CAM_DRV_NAME, pcdev);
1713 if (err) {
1714 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
1715 goto out;
1716 }
1717
1718 pcdev->clk_emma_ipg = devm_clk_get(pcdev->dev, "emma-ipg");
1719 if (IS_ERR(pcdev->clk_emma_ipg)) {
1720 err = PTR_ERR(pcdev->clk_emma_ipg);
1721 goto out;
1722 }
1723
1724 clk_prepare_enable(pcdev->clk_emma_ipg);
1725
1726 pcdev->clk_emma_ahb = devm_clk_get(pcdev->dev, "emma-ahb");
1727 if (IS_ERR(pcdev->clk_emma_ahb)) {
1728 err = PTR_ERR(pcdev->clk_emma_ahb);
1729 goto exit_clk_emma_ipg;
1730 }
1731
1732 clk_prepare_enable(pcdev->clk_emma_ahb);
1733
1734 err = mx27_camera_emma_prp_reset(pcdev);
1735 if (err)
1736 goto exit_clk_emma_ahb;
1737
1738 return err;
1739
1740 exit_clk_emma_ahb:
1741 clk_disable_unprepare(pcdev->clk_emma_ahb);
1742 exit_clk_emma_ipg:
1743 clk_disable_unprepare(pcdev->clk_emma_ipg);
1744 out:
1745 return err;
1746 }
1747
1748 static int __devinit mx2_camera_probe(struct platform_device *pdev)
1749 {
1750 struct mx2_camera_dev *pcdev;
1751 struct resource *res_csi;
1752 int irq_csi;
1753 int err = 0;
1754
1755 dev_dbg(&pdev->dev, "initialising\n");
1756
1757 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1758 irq_csi = platform_get_irq(pdev, 0);
1759 if (res_csi == NULL || irq_csi < 0) {
1760 dev_err(&pdev->dev, "Missing platform resources data\n");
1761 err = -ENODEV;
1762 goto exit;
1763 }
1764
1765 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
1766 if (!pcdev) {
1767 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1768 err = -ENOMEM;
1769 goto exit;
1770 }
1771
1772 pcdev->devtype = pdev->id_entry->driver_data;
1773 switch (pcdev->devtype) {
1774 case IMX25_CAMERA:
1775 pcdev->reg_csisr = CSISR_IMX25;
1776 pcdev->reg_csicr3 = CSICR3_IMX25;
1777 break;
1778 case IMX27_CAMERA:
1779 pcdev->reg_csisr = CSISR_IMX27;
1780 pcdev->reg_csicr3 = CSICR3_IMX27;
1781 break;
1782 default:
1783 break;
1784 }
1785
1786 pcdev->clk_csi_ahb = devm_clk_get(&pdev->dev, "ahb");
1787 if (IS_ERR(pcdev->clk_csi_ahb)) {
1788 dev_err(&pdev->dev, "Could not get csi ahb clock\n");
1789 err = PTR_ERR(pcdev->clk_csi_ahb);
1790 goto exit;
1791 }
1792
1793 pcdev->clk_csi_per = devm_clk_get(&pdev->dev, "per");
1794 if (IS_ERR(pcdev->clk_csi_per)) {
1795 dev_err(&pdev->dev, "Could not get csi per clock\n");
1796 err = PTR_ERR(pcdev->clk_csi_per);
1797 goto exit;
1798 }
1799
1800 pcdev->pdata = pdev->dev.platform_data;
1801 if (pcdev->pdata) {
1802 long rate;
1803
1804 pcdev->platform_flags = pcdev->pdata->flags;
1805
1806 rate = clk_round_rate(pcdev->clk_csi_per,
1807 pcdev->pdata->clk * 2);
1808 if (rate <= 0) {
1809 err = -ENODEV;
1810 goto exit;
1811 }
1812 err = clk_set_rate(pcdev->clk_csi_per, rate);
1813 if (err < 0)
1814 goto exit;
1815 }
1816
1817 INIT_LIST_HEAD(&pcdev->capture);
1818 INIT_LIST_HEAD(&pcdev->active_bufs);
1819 INIT_LIST_HEAD(&pcdev->discard);
1820 spin_lock_init(&pcdev->lock);
1821
1822 pcdev->base_csi = devm_request_and_ioremap(&pdev->dev, res_csi);
1823 if (!pcdev->base_csi) {
1824 err = -EADDRNOTAVAIL;
1825 goto exit;
1826 }
1827
1828 pcdev->dev = &pdev->dev;
1829 platform_set_drvdata(pdev, pcdev);
1830
1831 if (is_imx25_camera(pcdev)) {
1832 err = devm_request_irq(&pdev->dev, irq_csi, mx25_camera_irq, 0,
1833 MX2_CAM_DRV_NAME, pcdev);
1834 if (err) {
1835 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1836 goto exit;
1837 }
1838 }
1839
1840 if (is_imx27_camera(pcdev)) {
1841 err = mx27_camera_emma_init(pdev);
1842 if (err)
1843 goto exit;
1844 }
1845
1846 /*
1847 * We're done with drvdata here. Clear the pointer so that
1848 * v4l2 core can start using drvdata on its purpose.
1849 */
1850 platform_set_drvdata(pdev, NULL);
1851
1852 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1853 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1854 pcdev->soc_host.priv = pcdev;
1855 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1856 pcdev->soc_host.nr = pdev->id;
1857 if (is_imx25_camera(pcdev))
1858 pcdev->soc_host.capabilities = SOCAM_HOST_CAP_STRIDE;
1859
1860 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1861 if (IS_ERR(pcdev->alloc_ctx)) {
1862 err = PTR_ERR(pcdev->alloc_ctx);
1863 goto eallocctx;
1864 }
1865 err = soc_camera_host_register(&pcdev->soc_host);
1866 if (err)
1867 goto exit_free_emma;
1868
1869 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1870 clk_get_rate(pcdev->clk_csi_per));
1871
1872 return 0;
1873
1874 exit_free_emma:
1875 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1876 eallocctx:
1877 if (is_imx27_camera(pcdev)) {
1878 clk_disable_unprepare(pcdev->clk_emma_ipg);
1879 clk_disable_unprepare(pcdev->clk_emma_ahb);
1880 }
1881 exit:
1882 return err;
1883 }
1884
1885 static int __devexit mx2_camera_remove(struct platform_device *pdev)
1886 {
1887 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1888 struct mx2_camera_dev *pcdev = container_of(soc_host,
1889 struct mx2_camera_dev, soc_host);
1890
1891 soc_camera_host_unregister(&pcdev->soc_host);
1892
1893 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1894
1895 if (is_imx27_camera(pcdev)) {
1896 clk_disable_unprepare(pcdev->clk_emma_ipg);
1897 clk_disable_unprepare(pcdev->clk_emma_ahb);
1898 }
1899
1900 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1901
1902 return 0;
1903 }
1904
1905 static struct platform_driver mx2_camera_driver = {
1906 .driver = {
1907 .name = MX2_CAM_DRV_NAME,
1908 },
1909 .id_table = mx2_camera_devtype,
1910 .remove = __devexit_p(mx2_camera_remove),
1911 };
1912
1913
1914 static int __init mx2_camera_init(void)
1915 {
1916 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
1917 }
1918
1919 static void __exit mx2_camera_exit(void)
1920 {
1921 return platform_driver_unregister(&mx2_camera_driver);
1922 }
1923
1924 module_init(mx2_camera_init);
1925 module_exit(mx2_camera_exit);
1926
1927 MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1928 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1929 MODULE_LICENSE("GPL");
1930 MODULE_VERSION(MX2_CAM_VERSION);
Linux kernel - Deliverables
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