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Merge branch 'slab/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/penberg...
[deliverable/linux.git] / drivers / media / platform / soc_camera / mx3_camera.c
1 /*
2 * V4L2 Driver for i.MX3x camera host
3 *
4 * Copyright (C) 2008
5 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/videodev2.h>
15 #include <linux/platform_device.h>
16 #include <linux/clk.h>
17 #include <linux/vmalloc.h>
18 #include <linux/interrupt.h>
19 #include <linux/sched.h>
20 #include <linux/dma/ipu-dma.h>
21
22 #include <media/v4l2-common.h>
23 #include <media/v4l2-dev.h>
24 #include <media/videobuf2-dma-contig.h>
25 #include <media/soc_camera.h>
26 #include <media/soc_mediabus.h>
27
28 #include <linux/platform_data/camera-mx3.h>
29 #include <linux/platform_data/dma-imx.h>
30
31 #define MX3_CAM_DRV_NAME "mx3-camera"
32
33 /* CMOS Sensor Interface Registers */
34 #define CSI_REG_START 0x60
35
36 #define CSI_SENS_CONF (0x60 - CSI_REG_START)
37 #define CSI_SENS_FRM_SIZE (0x64 - CSI_REG_START)
38 #define CSI_ACT_FRM_SIZE (0x68 - CSI_REG_START)
39 #define CSI_OUT_FRM_CTRL (0x6C - CSI_REG_START)
40 #define CSI_TST_CTRL (0x70 - CSI_REG_START)
41 #define CSI_CCIR_CODE_1 (0x74 - CSI_REG_START)
42 #define CSI_CCIR_CODE_2 (0x78 - CSI_REG_START)
43 #define CSI_CCIR_CODE_3 (0x7C - CSI_REG_START)
44 #define CSI_FLASH_STROBE_1 (0x80 - CSI_REG_START)
45 #define CSI_FLASH_STROBE_2 (0x84 - CSI_REG_START)
46
47 #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
48 #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
49 #define CSI_SENS_CONF_DATA_POL_SHIFT 2
50 #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
51 #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
52 #define CSI_SENS_CONF_SENS_CLKSRC_SHIFT 7
53 #define CSI_SENS_CONF_DATA_FMT_SHIFT 8
54 #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 10
55 #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
56 #define CSI_SENS_CONF_DIVRATIO_SHIFT 16
57
58 #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 (0UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
59 #define CSI_SENS_CONF_DATA_FMT_YUV422 (2UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
60 #define CSI_SENS_CONF_DATA_FMT_BAYER (3UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
61
62 #define MAX_VIDEO_MEM 16
63
64 struct mx3_camera_buffer {
65 /* common v4l buffer stuff -- must be first */
66 struct vb2_buffer vb;
67 struct list_head queue;
68
69 /* One descriptot per scatterlist (per frame) */
70 struct dma_async_tx_descriptor *txd;
71
72 /* We have to "build" a scatterlist ourselves - one element per frame */
73 struct scatterlist sg;
74 };
75
76 /**
77 * struct mx3_camera_dev - i.MX3x camera (CSI) object
78 * @dev: camera device, to which the coherent buffer is attached
79 * @icd: currently attached camera sensor
80 * @clk: pointer to clock
81 * @base: remapped register base address
82 * @pdata: platform data
83 * @platform_flags: platform flags
84 * @mclk: master clock frequency in Hz
85 * @capture: list of capture videobuffers
86 * @lock: protects video buffer lists
87 * @active: active video buffer
88 * @idmac_channel: array of pointers to IPU DMAC DMA channels
89 * @soc_host: embedded soc_host object
90 */
91 struct mx3_camera_dev {
92 /*
93 * i.MX3x is only supposed to handle one camera on its Camera Sensor
94 * Interface. If anyone ever builds hardware to enable more than one
95 * camera _simultaneously_, they will have to modify this driver too
96 */
97 struct clk *clk;
98
99 void __iomem *base;
100
101 struct mx3_camera_pdata *pdata;
102
103 unsigned long platform_flags;
104 unsigned long mclk;
105 u16 width_flags; /* max 15 bits */
106
107 struct list_head capture;
108 spinlock_t lock; /* Protects video buffer lists */
109 struct mx3_camera_buffer *active;
110 size_t buf_total;
111 struct vb2_alloc_ctx *alloc_ctx;
112 enum v4l2_field field;
113 int sequence;
114
115 /* IDMAC / dmaengine interface */
116 struct idmac_channel *idmac_channel[1]; /* We need one channel */
117
118 struct soc_camera_host soc_host;
119 };
120
121 struct dma_chan_request {
122 struct mx3_camera_dev *mx3_cam;
123 enum ipu_channel id;
124 };
125
126 static u32 csi_reg_read(struct mx3_camera_dev *mx3, off_t reg)
127 {
128 return __raw_readl(mx3->base + reg);
129 }
130
131 static void csi_reg_write(struct mx3_camera_dev *mx3, u32 value, off_t reg)
132 {
133 __raw_writel(value, mx3->base + reg);
134 }
135
136 static struct mx3_camera_buffer *to_mx3_vb(struct vb2_buffer *vb)
137 {
138 return container_of(vb, struct mx3_camera_buffer, vb);
139 }
140
141 /* Called from the IPU IDMAC ISR */
142 static void mx3_cam_dma_done(void *arg)
143 {
144 struct idmac_tx_desc *desc = to_tx_desc(arg);
145 struct dma_chan *chan = desc->txd.chan;
146 struct idmac_channel *ichannel = to_idmac_chan(chan);
147 struct mx3_camera_dev *mx3_cam = ichannel->client;
148
149 dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n",
150 desc->txd.cookie, mx3_cam->active ? sg_dma_address(&mx3_cam->active->sg) : 0);
151
152 spin_lock(&mx3_cam->lock);
153 if (mx3_cam->active) {
154 struct vb2_buffer *vb = &mx3_cam->active->vb;
155 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
156
157 list_del_init(&buf->queue);
158 v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
159 vb->v4l2_buf.field = mx3_cam->field;
160 vb->v4l2_buf.sequence = mx3_cam->sequence++;
161 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
162 }
163
164 if (list_empty(&mx3_cam->capture)) {
165 mx3_cam->active = NULL;
166 spin_unlock(&mx3_cam->lock);
167
168 /*
169 * stop capture - without further buffers IPU_CHA_BUF0_RDY will
170 * not get updated
171 */
172 return;
173 }
174
175 mx3_cam->active = list_entry(mx3_cam->capture.next,
176 struct mx3_camera_buffer, queue);
177 spin_unlock(&mx3_cam->lock);
178 }
179
180 /*
181 * Videobuf operations
182 */
183
184 /*
185 * Calculate the __buffer__ (not data) size and number of buffers.
186 */
187 static int mx3_videobuf_setup(struct vb2_queue *vq,
188 const struct v4l2_format *fmt,
189 unsigned int *count, unsigned int *num_planes,
190 unsigned int sizes[], void *alloc_ctxs[])
191 {
192 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
193 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
194 struct mx3_camera_dev *mx3_cam = ici->priv;
195
196 if (!mx3_cam->idmac_channel[0])
197 return -EINVAL;
198
199 if (fmt) {
200 const struct soc_camera_format_xlate *xlate = soc_camera_xlate_by_fourcc(icd,
201 fmt->fmt.pix.pixelformat);
202 unsigned int bytes_per_line;
203 int ret;
204
205 if (!xlate)
206 return -EINVAL;
207
208 ret = soc_mbus_bytes_per_line(fmt->fmt.pix.width,
209 xlate->host_fmt);
210 if (ret < 0)
211 return ret;
212
213 bytes_per_line = max_t(u32, fmt->fmt.pix.bytesperline, ret);
214
215 ret = soc_mbus_image_size(xlate->host_fmt, bytes_per_line,
216 fmt->fmt.pix.height);
217 if (ret < 0)
218 return ret;
219
220 sizes[0] = max_t(u32, fmt->fmt.pix.sizeimage, ret);
221 } else {
222 /* Called from VIDIOC_REQBUFS or in compatibility mode */
223 sizes[0] = icd->sizeimage;
224 }
225
226 alloc_ctxs[0] = mx3_cam->alloc_ctx;
227
228 if (!vq->num_buffers)
229 mx3_cam->sequence = 0;
230
231 if (!*count)
232 *count = 2;
233
234 /* If *num_planes != 0, we have already verified *count. */
235 if (!*num_planes &&
236 sizes[0] * *count + mx3_cam->buf_total > MAX_VIDEO_MEM * 1024 * 1024)
237 *count = (MAX_VIDEO_MEM * 1024 * 1024 - mx3_cam->buf_total) /
238 sizes[0];
239
240 *num_planes = 1;
241
242 return 0;
243 }
244
245 static enum pixel_fmt fourcc_to_ipu_pix(__u32 fourcc)
246 {
247 /* Add more formats as need arises and test possibilities appear... */
248 switch (fourcc) {
249 case V4L2_PIX_FMT_RGB24:
250 return IPU_PIX_FMT_RGB24;
251 case V4L2_PIX_FMT_UYVY:
252 case V4L2_PIX_FMT_RGB565:
253 default:
254 return IPU_PIX_FMT_GENERIC;
255 }
256 }
257
258 static void mx3_videobuf_queue(struct vb2_buffer *vb)
259 {
260 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
261 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
262 struct mx3_camera_dev *mx3_cam = ici->priv;
263 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
264 struct scatterlist *sg = &buf->sg;
265 struct dma_async_tx_descriptor *txd;
266 struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
267 struct idmac_video_param *video = &ichan->params.video;
268 const struct soc_mbus_pixelfmt *host_fmt = icd->current_fmt->host_fmt;
269 dma_cookie_t cookie;
270 size_t new_size;
271
272 new_size = icd->sizeimage;
273
274 if (vb2_plane_size(vb, 0) < new_size) {
275 dev_err(icd->parent, "Buffer #%d too small (%lu < %zu)\n",
276 vb->v4l2_buf.index, vb2_plane_size(vb, 0), new_size);
277 goto error;
278 }
279
280 if (!buf->txd) {
281 sg_dma_address(sg) = vb2_dma_contig_plane_dma_addr(vb, 0);
282 sg_dma_len(sg) = new_size;
283
284 txd = dmaengine_prep_slave_sg(
285 &ichan->dma_chan, sg, 1, DMA_DEV_TO_MEM,
286 DMA_PREP_INTERRUPT);
287 if (!txd)
288 goto error;
289
290 txd->callback_param = txd;
291 txd->callback = mx3_cam_dma_done;
292
293 buf->txd = txd;
294 } else {
295 txd = buf->txd;
296 }
297
298 vb2_set_plane_payload(vb, 0, new_size);
299
300 /* This is the configuration of one sg-element */
301 video->out_pixel_fmt = fourcc_to_ipu_pix(host_fmt->fourcc);
302
303 if (video->out_pixel_fmt == IPU_PIX_FMT_GENERIC) {
304 /*
305 * If the IPU DMA channel is configured to transfer generic
306 * 8-bit data, we have to set up the geometry parameters
307 * correctly, according to the current pixel format. The DMA
308 * horizontal parameters in this case are expressed in bytes,
309 * not in pixels.
310 */
311 video->out_width = icd->bytesperline;
312 video->out_height = icd->user_height;
313 video->out_stride = icd->bytesperline;
314 } else {
315 /*
316 * For IPU known formats the pixel unit will be managed
317 * successfully by the IPU code
318 */
319 video->out_width = icd->user_width;
320 video->out_height = icd->user_height;
321 video->out_stride = icd->user_width;
322 }
323
324 #ifdef DEBUG
325 /* helps to see what DMA actually has written */
326 if (vb2_plane_vaddr(vb, 0))
327 memset(vb2_plane_vaddr(vb, 0), 0xaa, vb2_get_plane_payload(vb, 0));
328 #endif
329
330 spin_lock_irq(&mx3_cam->lock);
331 list_add_tail(&buf->queue, &mx3_cam->capture);
332
333 if (!mx3_cam->active)
334 mx3_cam->active = buf;
335
336 spin_unlock_irq(&mx3_cam->lock);
337
338 cookie = txd->tx_submit(txd);
339 dev_dbg(icd->parent, "Submitted cookie %d DMA 0x%08x\n",
340 cookie, sg_dma_address(&buf->sg));
341
342 if (cookie >= 0)
343 return;
344
345 spin_lock_irq(&mx3_cam->lock);
346
347 /* Submit error */
348 list_del_init(&buf->queue);
349
350 if (mx3_cam->active == buf)
351 mx3_cam->active = NULL;
352
353 spin_unlock_irq(&mx3_cam->lock);
354 error:
355 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
356 }
357
358 static void mx3_videobuf_release(struct vb2_buffer *vb)
359 {
360 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
361 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
362 struct mx3_camera_dev *mx3_cam = ici->priv;
363 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
364 struct dma_async_tx_descriptor *txd = buf->txd;
365 unsigned long flags;
366
367 dev_dbg(icd->parent,
368 "Release%s DMA 0x%08x, queue %sempty\n",
369 mx3_cam->active == buf ? " active" : "", sg_dma_address(&buf->sg),
370 list_empty(&buf->queue) ? "" : "not ");
371
372 spin_lock_irqsave(&mx3_cam->lock, flags);
373
374 if (mx3_cam->active == buf)
375 mx3_cam->active = NULL;
376
377 /* Doesn't hurt also if the list is empty */
378 list_del_init(&buf->queue);
379
380 if (txd) {
381 buf->txd = NULL;
382 if (mx3_cam->idmac_channel[0])
383 async_tx_ack(txd);
384 }
385
386 spin_unlock_irqrestore(&mx3_cam->lock, flags);
387
388 mx3_cam->buf_total -= vb2_plane_size(vb, 0);
389 }
390
391 static int mx3_videobuf_init(struct vb2_buffer *vb)
392 {
393 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
394 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
395 struct mx3_camera_dev *mx3_cam = ici->priv;
396 struct mx3_camera_buffer *buf = to_mx3_vb(vb);
397
398 if (!buf->txd) {
399 /* This is for locking debugging only */
400 INIT_LIST_HEAD(&buf->queue);
401 sg_init_table(&buf->sg, 1);
402
403 mx3_cam->buf_total += vb2_plane_size(vb, 0);
404 }
405
406 return 0;
407 }
408
409 static void mx3_stop_streaming(struct vb2_queue *q)
410 {
411 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
412 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
413 struct mx3_camera_dev *mx3_cam = ici->priv;
414 struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
415 struct mx3_camera_buffer *buf, *tmp;
416 unsigned long flags;
417
418 if (ichan) {
419 struct dma_chan *chan = &ichan->dma_chan;
420 chan->device->device_control(chan, DMA_PAUSE, 0);
421 }
422
423 spin_lock_irqsave(&mx3_cam->lock, flags);
424
425 mx3_cam->active = NULL;
426
427 list_for_each_entry_safe(buf, tmp, &mx3_cam->capture, queue) {
428 list_del_init(&buf->queue);
429 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
430 }
431
432 spin_unlock_irqrestore(&mx3_cam->lock, flags);
433 }
434
435 static struct vb2_ops mx3_videobuf_ops = {
436 .queue_setup = mx3_videobuf_setup,
437 .buf_queue = mx3_videobuf_queue,
438 .buf_cleanup = mx3_videobuf_release,
439 .buf_init = mx3_videobuf_init,
440 .wait_prepare = soc_camera_unlock,
441 .wait_finish = soc_camera_lock,
442 .stop_streaming = mx3_stop_streaming,
443 };
444
445 static int mx3_camera_init_videobuf(struct vb2_queue *q,
446 struct soc_camera_device *icd)
447 {
448 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
449 q->io_modes = VB2_MMAP | VB2_USERPTR;
450 q->drv_priv = icd;
451 q->ops = &mx3_videobuf_ops;
452 q->mem_ops = &vb2_dma_contig_memops;
453 q->buf_struct_size = sizeof(struct mx3_camera_buffer);
454 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
455
456 return vb2_queue_init(q);
457 }
458
459 /* First part of ipu_csi_init_interface() */
460 static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam)
461 {
462 u32 conf;
463 long rate;
464
465 /* Set default size: ipu_csi_set_window_size() */
466 csi_reg_write(mx3_cam, (640 - 1) | ((480 - 1) << 16), CSI_ACT_FRM_SIZE);
467 /* ...and position to 0:0: ipu_csi_set_window_pos() */
468 conf = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
469 csi_reg_write(mx3_cam, conf, CSI_OUT_FRM_CTRL);
470
471 /* We use only gated clock synchronisation mode so far */
472 conf = 0 << CSI_SENS_CONF_SENS_PRTCL_SHIFT;
473
474 /* Set generic data, platform-biggest bus-width */
475 conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
476
477 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)
478 conf |= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
479 else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)
480 conf |= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
481 else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)
482 conf |= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
483 else/* if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)*/
484 conf |= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
485
486 if (mx3_cam->platform_flags & MX3_CAMERA_CLK_SRC)
487 conf |= 1 << CSI_SENS_CONF_SENS_CLKSRC_SHIFT;
488 if (mx3_cam->platform_flags & MX3_CAMERA_EXT_VSYNC)
489 conf |= 1 << CSI_SENS_CONF_EXT_VSYNC_SHIFT;
490 if (mx3_cam->platform_flags & MX3_CAMERA_DP)
491 conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
492 if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
493 conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
494 if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
495 conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
496 if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
497 conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
498
499 /* ipu_csi_init_interface() */
500 csi_reg_write(mx3_cam, conf, CSI_SENS_CONF);
501
502 clk_prepare_enable(mx3_cam->clk);
503 rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk);
504 dev_dbg(mx3_cam->soc_host.v4l2_dev.dev, "Set SENS_CONF to %x, rate %ld\n", conf, rate);
505 if (rate)
506 clk_set_rate(mx3_cam->clk, rate);
507 }
508
509 static int mx3_camera_add_device(struct soc_camera_device *icd)
510 {
511 dev_info(icd->parent, "MX3 Camera driver attached to camera %d\n",
512 icd->devnum);
513
514 return 0;
515 }
516
517 static void mx3_camera_remove_device(struct soc_camera_device *icd)
518 {
519 dev_info(icd->parent, "MX3 Camera driver detached from camera %d\n",
520 icd->devnum);
521 }
522
523 /* Called with .host_lock held */
524 static int mx3_camera_clock_start(struct soc_camera_host *ici)
525 {
526 struct mx3_camera_dev *mx3_cam = ici->priv;
527
528 mx3_camera_activate(mx3_cam);
529
530 mx3_cam->buf_total = 0;
531
532 return 0;
533 }
534
535 /* Called with .host_lock held */
536 static void mx3_camera_clock_stop(struct soc_camera_host *ici)
537 {
538 struct mx3_camera_dev *mx3_cam = ici->priv;
539 struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
540
541 if (*ichan) {
542 dma_release_channel(&(*ichan)->dma_chan);
543 *ichan = NULL;
544 }
545
546 clk_disable_unprepare(mx3_cam->clk);
547 }
548
549 static int test_platform_param(struct mx3_camera_dev *mx3_cam,
550 unsigned char buswidth, unsigned long *flags)
551 {
552 /*
553 * If requested data width is supported by the platform, use it or any
554 * possible lower value - i.MX31 is smart enough to shift bits
555 */
556 if (buswidth > fls(mx3_cam->width_flags))
557 return -EINVAL;
558
559 /*
560 * Platform specified synchronization and pixel clock polarities are
561 * only a recommendation and are only used during probing. MX3x
562 * camera interface only works in master mode, i.e., uses HSYNC and
563 * VSYNC signals from the sensor
564 */
565 *flags = V4L2_MBUS_MASTER |
566 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
567 V4L2_MBUS_HSYNC_ACTIVE_LOW |
568 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
569 V4L2_MBUS_VSYNC_ACTIVE_LOW |
570 V4L2_MBUS_PCLK_SAMPLE_RISING |
571 V4L2_MBUS_PCLK_SAMPLE_FALLING |
572 V4L2_MBUS_DATA_ACTIVE_HIGH |
573 V4L2_MBUS_DATA_ACTIVE_LOW;
574
575 return 0;
576 }
577
578 static int mx3_camera_try_bus_param(struct soc_camera_device *icd,
579 const unsigned int depth)
580 {
581 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
582 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
583 struct mx3_camera_dev *mx3_cam = ici->priv;
584 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
585 unsigned long bus_flags, common_flags;
586 int ret = test_platform_param(mx3_cam, depth, &bus_flags);
587
588 dev_dbg(icd->parent, "request bus width %d bit: %d\n", depth, ret);
589
590 if (ret < 0)
591 return ret;
592
593 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
594 if (!ret) {
595 common_flags = soc_mbus_config_compatible(&cfg,
596 bus_flags);
597 if (!common_flags) {
598 dev_warn(icd->parent,
599 "Flags incompatible: camera 0x%x, host 0x%lx\n",
600 cfg.flags, bus_flags);
601 return -EINVAL;
602 }
603 } else if (ret != -ENOIOCTLCMD) {
604 return ret;
605 }
606
607 return 0;
608 }
609
610 static bool chan_filter(struct dma_chan *chan, void *arg)
611 {
612 struct dma_chan_request *rq = arg;
613 struct mx3_camera_pdata *pdata;
614
615 if (!imx_dma_is_ipu(chan))
616 return false;
617
618 if (!rq)
619 return false;
620
621 pdata = rq->mx3_cam->soc_host.v4l2_dev.dev->platform_data;
622
623 return rq->id == chan->chan_id &&
624 pdata->dma_dev == chan->device->dev;
625 }
626
627 static const struct soc_mbus_pixelfmt mx3_camera_formats[] = {
628 {
629 .fourcc = V4L2_PIX_FMT_SBGGR8,
630 .name = "Bayer BGGR (sRGB) 8 bit",
631 .bits_per_sample = 8,
632 .packing = SOC_MBUS_PACKING_NONE,
633 .order = SOC_MBUS_ORDER_LE,
634 .layout = SOC_MBUS_LAYOUT_PACKED,
635 }, {
636 .fourcc = V4L2_PIX_FMT_GREY,
637 .name = "Monochrome 8 bit",
638 .bits_per_sample = 8,
639 .packing = SOC_MBUS_PACKING_NONE,
640 .order = SOC_MBUS_ORDER_LE,
641 .layout = SOC_MBUS_LAYOUT_PACKED,
642 },
643 };
644
645 /* This will be corrected as we get more formats */
646 static bool mx3_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
647 {
648 return fmt->packing == SOC_MBUS_PACKING_NONE ||
649 (fmt->bits_per_sample == 8 &&
650 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
651 (fmt->bits_per_sample > 8 &&
652 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
653 }
654
655 static int mx3_camera_get_formats(struct soc_camera_device *icd, unsigned int idx,
656 struct soc_camera_format_xlate *xlate)
657 {
658 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
659 struct device *dev = icd->parent;
660 int formats = 0, ret;
661 enum v4l2_mbus_pixelcode code;
662 const struct soc_mbus_pixelfmt *fmt;
663
664 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
665 if (ret < 0)
666 /* No more formats */
667 return 0;
668
669 fmt = soc_mbus_get_fmtdesc(code);
670 if (!fmt) {
671 dev_warn(icd->parent,
672 "Unsupported format code #%u: 0x%x\n", idx, code);
673 return 0;
674 }
675
676 /* This also checks support for the requested bits-per-sample */
677 ret = mx3_camera_try_bus_param(icd, fmt->bits_per_sample);
678 if (ret < 0)
679 return 0;
680
681 switch (code) {
682 case V4L2_MBUS_FMT_SBGGR10_1X10:
683 formats++;
684 if (xlate) {
685 xlate->host_fmt = &mx3_camera_formats[0];
686 xlate->code = code;
687 xlate++;
688 dev_dbg(dev, "Providing format %s using code 0x%x\n",
689 mx3_camera_formats[0].name, code);
690 }
691 break;
692 case V4L2_MBUS_FMT_Y10_1X10:
693 formats++;
694 if (xlate) {
695 xlate->host_fmt = &mx3_camera_formats[1];
696 xlate->code = code;
697 xlate++;
698 dev_dbg(dev, "Providing format %s using code 0x%x\n",
699 mx3_camera_formats[1].name, code);
700 }
701 break;
702 default:
703 if (!mx3_camera_packing_supported(fmt))
704 return 0;
705 }
706
707 /* Generic pass-through */
708 formats++;
709 if (xlate) {
710 xlate->host_fmt = fmt;
711 xlate->code = code;
712 dev_dbg(dev, "Providing format %c%c%c%c in pass-through mode\n",
713 (fmt->fourcc >> (0*8)) & 0xFF,
714 (fmt->fourcc >> (1*8)) & 0xFF,
715 (fmt->fourcc >> (2*8)) & 0xFF,
716 (fmt->fourcc >> (3*8)) & 0xFF);
717 xlate++;
718 }
719
720 return formats;
721 }
722
723 static void configure_geometry(struct mx3_camera_dev *mx3_cam,
724 unsigned int width, unsigned int height,
725 const struct soc_mbus_pixelfmt *fmt)
726 {
727 u32 ctrl, width_field, height_field;
728
729 if (fourcc_to_ipu_pix(fmt->fourcc) == IPU_PIX_FMT_GENERIC) {
730 /*
731 * As the CSI will be configured to output BAYER, here
732 * the width parameter count the number of samples to
733 * capture to complete the whole image width.
734 */
735 unsigned int num, den;
736 int ret = soc_mbus_samples_per_pixel(fmt, &num, &den);
737 BUG_ON(ret < 0);
738 width = width * num / den;
739 }
740
741 /* Setup frame size - this cannot be changed on-the-fly... */
742 width_field = width - 1;
743 height_field = height - 1;
744 csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_SENS_FRM_SIZE);
745
746 csi_reg_write(mx3_cam, width_field << 16, CSI_FLASH_STROBE_1);
747 csi_reg_write(mx3_cam, (height_field << 16) | 0x22, CSI_FLASH_STROBE_2);
748
749 csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_ACT_FRM_SIZE);
750
751 /* ...and position */
752 ctrl = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
753 /* Sensor does the cropping */
754 csi_reg_write(mx3_cam, ctrl | 0 | (0 << 8), CSI_OUT_FRM_CTRL);
755 }
756
757 static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam)
758 {
759 dma_cap_mask_t mask;
760 struct dma_chan *chan;
761 struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
762 /* We have to use IDMAC_IC_7 for Bayer / generic data */
763 struct dma_chan_request rq = {.mx3_cam = mx3_cam,
764 .id = IDMAC_IC_7};
765
766 dma_cap_zero(mask);
767 dma_cap_set(DMA_SLAVE, mask);
768 dma_cap_set(DMA_PRIVATE, mask);
769 chan = dma_request_channel(mask, chan_filter, &rq);
770 if (!chan)
771 return -EBUSY;
772
773 *ichan = to_idmac_chan(chan);
774 (*ichan)->client = mx3_cam;
775
776 return 0;
777 }
778
779 /*
780 * FIXME: learn to use stride != width, then we can keep stride properly aligned
781 * and support arbitrary (even) widths.
782 */
783 static inline void stride_align(__u32 *width)
784 {
785 if (ALIGN(*width, 8) < 4096)
786 *width = ALIGN(*width, 8);
787 else
788 *width = *width & ~7;
789 }
790
791 /*
792 * As long as we don't implement host-side cropping and scaling, we can use
793 * default g_crop and cropcap from soc_camera.c
794 */
795 static int mx3_camera_set_crop(struct soc_camera_device *icd,
796 const struct v4l2_crop *a)
797 {
798 struct v4l2_crop a_writable = *a;
799 struct v4l2_rect *rect = &a_writable.c;
800 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
801 struct mx3_camera_dev *mx3_cam = ici->priv;
802 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
803 struct v4l2_mbus_framefmt mf;
804 int ret;
805
806 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
807 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
808
809 ret = v4l2_subdev_call(sd, video, s_crop, a);
810 if (ret < 0)
811 return ret;
812
813 /* The capture device might have changed its output sizes */
814 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
815 if (ret < 0)
816 return ret;
817
818 if (mf.code != icd->current_fmt->code)
819 return -EINVAL;
820
821 if (mf.width & 7) {
822 /* Ouch! We can only handle 8-byte aligned width... */
823 stride_align(&mf.width);
824 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
825 if (ret < 0)
826 return ret;
827 }
828
829 if (mf.width != icd->user_width || mf.height != icd->user_height)
830 configure_geometry(mx3_cam, mf.width, mf.height,
831 icd->current_fmt->host_fmt);
832
833 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
834 mf.width, mf.height);
835
836 icd->user_width = mf.width;
837 icd->user_height = mf.height;
838
839 return ret;
840 }
841
842 static int mx3_camera_set_fmt(struct soc_camera_device *icd,
843 struct v4l2_format *f)
844 {
845 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
846 struct mx3_camera_dev *mx3_cam = ici->priv;
847 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
848 const struct soc_camera_format_xlate *xlate;
849 struct v4l2_pix_format *pix = &f->fmt.pix;
850 struct v4l2_mbus_framefmt mf;
851 int ret;
852
853 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
854 if (!xlate) {
855 dev_warn(icd->parent, "Format %x not found\n",
856 pix->pixelformat);
857 return -EINVAL;
858 }
859
860 stride_align(&pix->width);
861 dev_dbg(icd->parent, "Set format %dx%d\n", pix->width, pix->height);
862
863 /*
864 * Might have to perform a complete interface initialisation like in
865 * ipu_csi_init_interface() in mxc_v4l2_s_param(). Also consider
866 * mxc_v4l2_s_fmt()
867 */
868
869 configure_geometry(mx3_cam, pix->width, pix->height, xlate->host_fmt);
870
871 mf.width = pix->width;
872 mf.height = pix->height;
873 mf.field = pix->field;
874 mf.colorspace = pix->colorspace;
875 mf.code = xlate->code;
876
877 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
878 if (ret < 0)
879 return ret;
880
881 if (mf.code != xlate->code)
882 return -EINVAL;
883
884 if (!mx3_cam->idmac_channel[0]) {
885 ret = acquire_dma_channel(mx3_cam);
886 if (ret < 0)
887 return ret;
888 }
889
890 pix->width = mf.width;
891 pix->height = mf.height;
892 pix->field = mf.field;
893 mx3_cam->field = mf.field;
894 pix->colorspace = mf.colorspace;
895 icd->current_fmt = xlate;
896
897 dev_dbg(icd->parent, "Sensor set %dx%d\n", pix->width, pix->height);
898
899 return ret;
900 }
901
902 static int mx3_camera_try_fmt(struct soc_camera_device *icd,
903 struct v4l2_format *f)
904 {
905 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
906 const struct soc_camera_format_xlate *xlate;
907 struct v4l2_pix_format *pix = &f->fmt.pix;
908 struct v4l2_mbus_framefmt mf;
909 __u32 pixfmt = pix->pixelformat;
910 int ret;
911
912 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
913 if (pixfmt && !xlate) {
914 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
915 return -EINVAL;
916 }
917
918 /* limit to MX3 hardware capabilities */
919 if (pix->height > 4096)
920 pix->height = 4096;
921 if (pix->width > 4096)
922 pix->width = 4096;
923
924 /* limit to sensor capabilities */
925 mf.width = pix->width;
926 mf.height = pix->height;
927 mf.field = pix->field;
928 mf.colorspace = pix->colorspace;
929 mf.code = xlate->code;
930
931 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
932 if (ret < 0)
933 return ret;
934
935 pix->width = mf.width;
936 pix->height = mf.height;
937 pix->colorspace = mf.colorspace;
938
939 switch (mf.field) {
940 case V4L2_FIELD_ANY:
941 pix->field = V4L2_FIELD_NONE;
942 break;
943 case V4L2_FIELD_NONE:
944 break;
945 default:
946 dev_err(icd->parent, "Field type %d unsupported.\n",
947 mf.field);
948 ret = -EINVAL;
949 }
950
951 return ret;
952 }
953
954 static int mx3_camera_reqbufs(struct soc_camera_device *icd,
955 struct v4l2_requestbuffers *p)
956 {
957 return 0;
958 }
959
960 static unsigned int mx3_camera_poll(struct file *file, poll_table *pt)
961 {
962 struct soc_camera_device *icd = file->private_data;
963
964 return vb2_poll(&icd->vb2_vidq, file, pt);
965 }
966
967 static int mx3_camera_querycap(struct soc_camera_host *ici,
968 struct v4l2_capability *cap)
969 {
970 /* cap->name is set by the firendly caller:-> */
971 strlcpy(cap->card, "i.MX3x Camera", sizeof(cap->card));
972 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
973
974 return 0;
975 }
976
977 static int mx3_camera_set_bus_param(struct soc_camera_device *icd)
978 {
979 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
980 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
981 struct mx3_camera_dev *mx3_cam = ici->priv;
982 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
983 u32 pixfmt = icd->current_fmt->host_fmt->fourcc;
984 unsigned long bus_flags, common_flags;
985 u32 dw, sens_conf;
986 const struct soc_mbus_pixelfmt *fmt;
987 int buswidth;
988 int ret;
989 const struct soc_camera_format_xlate *xlate;
990 struct device *dev = icd->parent;
991
992 fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code);
993 if (!fmt)
994 return -EINVAL;
995
996 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
997 if (!xlate) {
998 dev_warn(dev, "Format %x not found\n", pixfmt);
999 return -EINVAL;
1000 }
1001
1002 buswidth = fmt->bits_per_sample;
1003 ret = test_platform_param(mx3_cam, buswidth, &bus_flags);
1004
1005 dev_dbg(dev, "requested bus width %d bit: %d\n", buswidth, ret);
1006
1007 if (ret < 0)
1008 return ret;
1009
1010 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1011 if (!ret) {
1012 common_flags = soc_mbus_config_compatible(&cfg,
1013 bus_flags);
1014 if (!common_flags) {
1015 dev_warn(icd->parent,
1016 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1017 cfg.flags, bus_flags);
1018 return -EINVAL;
1019 }
1020 } else if (ret != -ENOIOCTLCMD) {
1021 return ret;
1022 } else {
1023 common_flags = bus_flags;
1024 }
1025
1026 dev_dbg(dev, "Flags cam: 0x%x host: 0x%lx common: 0x%lx\n",
1027 cfg.flags, bus_flags, common_flags);
1028
1029 /* Make choices, based on platform preferences */
1030 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1031 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1032 if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
1033 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1034 else
1035 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1036 }
1037
1038 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1039 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1040 if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
1041 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1042 else
1043 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1044 }
1045
1046 if ((common_flags & V4L2_MBUS_DATA_ACTIVE_HIGH) &&
1047 (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW)) {
1048 if (mx3_cam->platform_flags & MX3_CAMERA_DP)
1049 common_flags &= ~V4L2_MBUS_DATA_ACTIVE_HIGH;
1050 else
1051 common_flags &= ~V4L2_MBUS_DATA_ACTIVE_LOW;
1052 }
1053
1054 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1055 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1056 if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
1057 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1058 else
1059 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1060 }
1061
1062 cfg.flags = common_flags;
1063 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1064 if (ret < 0 && ret != -ENOIOCTLCMD) {
1065 dev_dbg(dev, "camera s_mbus_config(0x%lx) returned %d\n",
1066 common_flags, ret);
1067 return ret;
1068 }
1069
1070 /*
1071 * So far only gated clock mode is supported. Add a line
1072 * (3 << CSI_SENS_CONF_SENS_PRTCL_SHIFT) |
1073 * below and select the required mode when supporting other
1074 * synchronisation protocols.
1075 */
1076 sens_conf = csi_reg_read(mx3_cam, CSI_SENS_CONF) &
1077 ~((1 << CSI_SENS_CONF_VSYNC_POL_SHIFT) |
1078 (1 << CSI_SENS_CONF_HSYNC_POL_SHIFT) |
1079 (1 << CSI_SENS_CONF_DATA_POL_SHIFT) |
1080 (1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT) |
1081 (3 << CSI_SENS_CONF_DATA_FMT_SHIFT) |
1082 (3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT));
1083
1084 /* TODO: Support RGB and YUV formats */
1085
1086 /* This has been set in mx3_camera_activate(), but we clear it above */
1087 sens_conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
1088
1089 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1090 sens_conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
1091 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1092 sens_conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
1093 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1094 sens_conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
1095 if (common_flags & V4L2_MBUS_DATA_ACTIVE_LOW)
1096 sens_conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
1097
1098 /* Just do what we're asked to do */
1099 switch (xlate->host_fmt->bits_per_sample) {
1100 case 4:
1101 dw = 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1102 break;
1103 case 8:
1104 dw = 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1105 break;
1106 case 10:
1107 dw = 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1108 break;
1109 default:
1110 /*
1111 * Actually it can only be 15 now, default is just to silence
1112 * compiler warnings
1113 */
1114 case 15:
1115 dw = 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
1116 }
1117
1118 csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF);
1119
1120 dev_dbg(dev, "Set SENS_CONF to %x\n", sens_conf | dw);
1121
1122 return 0;
1123 }
1124
1125 static struct soc_camera_host_ops mx3_soc_camera_host_ops = {
1126 .owner = THIS_MODULE,
1127 .add = mx3_camera_add_device,
1128 .remove = mx3_camera_remove_device,
1129 .clock_start = mx3_camera_clock_start,
1130 .clock_stop = mx3_camera_clock_stop,
1131 .set_crop = mx3_camera_set_crop,
1132 .set_fmt = mx3_camera_set_fmt,
1133 .try_fmt = mx3_camera_try_fmt,
1134 .get_formats = mx3_camera_get_formats,
1135 .init_videobuf2 = mx3_camera_init_videobuf,
1136 .reqbufs = mx3_camera_reqbufs,
1137 .poll = mx3_camera_poll,
1138 .querycap = mx3_camera_querycap,
1139 .set_bus_param = mx3_camera_set_bus_param,
1140 };
1141
1142 static int mx3_camera_probe(struct platform_device *pdev)
1143 {
1144 struct mx3_camera_pdata *pdata = pdev->dev.platform_data;
1145 struct mx3_camera_dev *mx3_cam;
1146 struct resource *res;
1147 void __iomem *base;
1148 int err = 0;
1149 struct soc_camera_host *soc_host;
1150
1151 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1152 base = devm_ioremap_resource(&pdev->dev, res);
1153 if (IS_ERR(base))
1154 return PTR_ERR(base);
1155
1156 if (!pdata)
1157 return -EINVAL;
1158
1159 mx3_cam = devm_kzalloc(&pdev->dev, sizeof(*mx3_cam), GFP_KERNEL);
1160 if (!mx3_cam) {
1161 dev_err(&pdev->dev, "Could not allocate mx3 camera object\n");
1162 return -ENOMEM;
1163 }
1164
1165 mx3_cam->clk = devm_clk_get(&pdev->dev, NULL);
1166 if (IS_ERR(mx3_cam->clk))
1167 return PTR_ERR(mx3_cam->clk);
1168
1169 mx3_cam->pdata = pdata;
1170 mx3_cam->platform_flags = pdata->flags;
1171 if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_MASK)) {
1172 /*
1173 * Platform hasn't set available data widths. This is bad.
1174 * Warn and use a default.
1175 */
1176 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1177 "data widths, using default 8 bit\n");
1178 mx3_cam->platform_flags |= MX3_CAMERA_DATAWIDTH_8;
1179 }
1180 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)
1181 mx3_cam->width_flags = 1 << 3;
1182 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)
1183 mx3_cam->width_flags |= 1 << 7;
1184 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)
1185 mx3_cam->width_flags |= 1 << 9;
1186 if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)
1187 mx3_cam->width_flags |= 1 << 14;
1188
1189 mx3_cam->mclk = pdata->mclk_10khz * 10000;
1190 if (!mx3_cam->mclk) {
1191 dev_warn(&pdev->dev,
1192 "mclk_10khz == 0! Please, fix your platform data. "
1193 "Using default 20MHz\n");
1194 mx3_cam->mclk = 20000000;
1195 }
1196
1197 /* list of video-buffers */
1198 INIT_LIST_HEAD(&mx3_cam->capture);
1199 spin_lock_init(&mx3_cam->lock);
1200
1201 mx3_cam->base = base;
1202
1203 soc_host = &mx3_cam->soc_host;
1204 soc_host->drv_name = MX3_CAM_DRV_NAME;
1205 soc_host->ops = &mx3_soc_camera_host_ops;
1206 soc_host->priv = mx3_cam;
1207 soc_host->v4l2_dev.dev = &pdev->dev;
1208 soc_host->nr = pdev->id;
1209
1210 mx3_cam->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1211 if (IS_ERR(mx3_cam->alloc_ctx))
1212 return PTR_ERR(mx3_cam->alloc_ctx);
1213
1214 if (pdata->asd_sizes) {
1215 soc_host->asd = pdata->asd;
1216 soc_host->asd_sizes = pdata->asd_sizes;
1217 }
1218
1219 err = soc_camera_host_register(soc_host);
1220 if (err)
1221 goto ecamhostreg;
1222
1223 /* IDMAC interface */
1224 dmaengine_get();
1225
1226 return 0;
1227
1228 ecamhostreg:
1229 vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx);
1230 return err;
1231 }
1232
1233 static int mx3_camera_remove(struct platform_device *pdev)
1234 {
1235 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1236 struct mx3_camera_dev *mx3_cam = container_of(soc_host,
1237 struct mx3_camera_dev, soc_host);
1238
1239 soc_camera_host_unregister(soc_host);
1240
1241 /*
1242 * The channel has either not been allocated,
1243 * or should have been released
1244 */
1245 if (WARN_ON(mx3_cam->idmac_channel[0]))
1246 dma_release_channel(&mx3_cam->idmac_channel[0]->dma_chan);
1247
1248 vb2_dma_contig_cleanup_ctx(mx3_cam->alloc_ctx);
1249
1250 dmaengine_put();
1251
1252 return 0;
1253 }
1254
1255 static struct platform_driver mx3_camera_driver = {
1256 .driver = {
1257 .name = MX3_CAM_DRV_NAME,
1258 .owner = THIS_MODULE,
1259 },
1260 .probe = mx3_camera_probe,
1261 .remove = mx3_camera_remove,
1262 };
1263
1264 module_platform_driver(mx3_camera_driver);
1265
1266 MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver");
1267 MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1268 MODULE_LICENSE("GPL v2");
1269 MODULE_VERSION("0.2.3");
1270 MODULE_ALIAS("platform:" MX3_CAM_DRV_NAME);
Linux kernel - Deliverables
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