2 * V4L2 Driver for i.MX3x camera host
5 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/videodev2.h>
15 #include <linux/platform_device.h>
16 #include <linux/clk.h>
17 #include <linux/vmalloc.h>
18 #include <linux/interrupt.h>
19 #include <linux/sched.h>
20 #include <linux/dma/ipu-dma.h>
22 #include <media/v4l2-common.h>
23 #include <media/v4l2-dev.h>
24 #include <media/videobuf2-dma-contig.h>
25 #include <media/soc_camera.h>
26 #include <media/soc_mediabus.h>
28 #include <linux/platform_data/camera-mx3.h>
29 #include <linux/platform_data/dma-imx.h>
31 #define MX3_CAM_DRV_NAME "mx3-camera"
33 /* CMOS Sensor Interface Registers */
34 #define CSI_REG_START 0x60
36 #define CSI_SENS_CONF (0x60 - CSI_REG_START)
37 #define CSI_SENS_FRM_SIZE (0x64 - CSI_REG_START)
38 #define CSI_ACT_FRM_SIZE (0x68 - CSI_REG_START)
39 #define CSI_OUT_FRM_CTRL (0x6C - CSI_REG_START)
40 #define CSI_TST_CTRL (0x70 - CSI_REG_START)
41 #define CSI_CCIR_CODE_1 (0x74 - CSI_REG_START)
42 #define CSI_CCIR_CODE_2 (0x78 - CSI_REG_START)
43 #define CSI_CCIR_CODE_3 (0x7C - CSI_REG_START)
44 #define CSI_FLASH_STROBE_1 (0x80 - CSI_REG_START)
45 #define CSI_FLASH_STROBE_2 (0x84 - CSI_REG_START)
47 #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
48 #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
49 #define CSI_SENS_CONF_DATA_POL_SHIFT 2
50 #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
51 #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
52 #define CSI_SENS_CONF_SENS_CLKSRC_SHIFT 7
53 #define CSI_SENS_CONF_DATA_FMT_SHIFT 8
54 #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 10
55 #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
56 #define CSI_SENS_CONF_DIVRATIO_SHIFT 16
58 #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 (0UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
59 #define CSI_SENS_CONF_DATA_FMT_YUV422 (2UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
60 #define CSI_SENS_CONF_DATA_FMT_BAYER (3UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
62 #define MAX_VIDEO_MEM 16
64 struct mx3_camera_buffer
{
65 /* common v4l buffer stuff -- must be first */
67 struct list_head queue
;
69 /* One descriptot per scatterlist (per frame) */
70 struct dma_async_tx_descriptor
*txd
;
72 /* We have to "build" a scatterlist ourselves - one element per frame */
73 struct scatterlist sg
;
77 * struct mx3_camera_dev - i.MX3x camera (CSI) object
78 * @dev: camera device, to which the coherent buffer is attached
79 * @icd: currently attached camera sensor
80 * @clk: pointer to clock
81 * @base: remapped register base address
82 * @pdata: platform data
83 * @platform_flags: platform flags
84 * @mclk: master clock frequency in Hz
85 * @capture: list of capture videobuffers
86 * @lock: protects video buffer lists
87 * @active: active video buffer
88 * @idmac_channel: array of pointers to IPU DMAC DMA channels
89 * @soc_host: embedded soc_host object
91 struct mx3_camera_dev
{
93 * i.MX3x is only supposed to handle one camera on its Camera Sensor
94 * Interface. If anyone ever builds hardware to enable more than one
95 * camera _simultaneously_, they will have to modify this driver too
101 struct mx3_camera_pdata
*pdata
;
103 unsigned long platform_flags
;
105 u16 width_flags
; /* max 15 bits */
107 struct list_head capture
;
108 spinlock_t lock
; /* Protects video buffer lists */
109 struct mx3_camera_buffer
*active
;
111 struct vb2_alloc_ctx
*alloc_ctx
;
112 enum v4l2_field field
;
115 /* IDMAC / dmaengine interface */
116 struct idmac_channel
*idmac_channel
[1]; /* We need one channel */
118 struct soc_camera_host soc_host
;
121 struct dma_chan_request
{
122 struct mx3_camera_dev
*mx3_cam
;
126 static u32
csi_reg_read(struct mx3_camera_dev
*mx3
, off_t reg
)
128 return __raw_readl(mx3
->base
+ reg
);
131 static void csi_reg_write(struct mx3_camera_dev
*mx3
, u32 value
, off_t reg
)
133 __raw_writel(value
, mx3
->base
+ reg
);
136 static struct mx3_camera_buffer
*to_mx3_vb(struct vb2_buffer
*vb
)
138 return container_of(vb
, struct mx3_camera_buffer
, vb
);
141 /* Called from the IPU IDMAC ISR */
142 static void mx3_cam_dma_done(void *arg
)
144 struct idmac_tx_desc
*desc
= to_tx_desc(arg
);
145 struct dma_chan
*chan
= desc
->txd
.chan
;
146 struct idmac_channel
*ichannel
= to_idmac_chan(chan
);
147 struct mx3_camera_dev
*mx3_cam
= ichannel
->client
;
149 dev_dbg(chan
->device
->dev
, "callback cookie %d, active DMA 0x%08x\n",
150 desc
->txd
.cookie
, mx3_cam
->active
? sg_dma_address(&mx3_cam
->active
->sg
) : 0);
152 spin_lock(&mx3_cam
->lock
);
153 if (mx3_cam
->active
) {
154 struct vb2_buffer
*vb
= &mx3_cam
->active
->vb
;
155 struct mx3_camera_buffer
*buf
= to_mx3_vb(vb
);
157 list_del_init(&buf
->queue
);
158 v4l2_get_timestamp(&vb
->v4l2_buf
.timestamp
);
159 vb
->v4l2_buf
.field
= mx3_cam
->field
;
160 vb
->v4l2_buf
.sequence
= mx3_cam
->sequence
++;
161 vb2_buffer_done(vb
, VB2_BUF_STATE_DONE
);
164 if (list_empty(&mx3_cam
->capture
)) {
165 mx3_cam
->active
= NULL
;
166 spin_unlock(&mx3_cam
->lock
);
169 * stop capture - without further buffers IPU_CHA_BUF0_RDY will
175 mx3_cam
->active
= list_entry(mx3_cam
->capture
.next
,
176 struct mx3_camera_buffer
, queue
);
177 spin_unlock(&mx3_cam
->lock
);
181 * Videobuf operations
185 * Calculate the __buffer__ (not data) size and number of buffers.
187 static int mx3_videobuf_setup(struct vb2_queue
*vq
,
188 const struct v4l2_format
*fmt
,
189 unsigned int *count
, unsigned int *num_planes
,
190 unsigned int sizes
[], void *alloc_ctxs
[])
192 struct soc_camera_device
*icd
= soc_camera_from_vb2q(vq
);
193 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
194 struct mx3_camera_dev
*mx3_cam
= ici
->priv
;
196 if (!mx3_cam
->idmac_channel
[0])
200 const struct soc_camera_format_xlate
*xlate
= soc_camera_xlate_by_fourcc(icd
,
201 fmt
->fmt
.pix
.pixelformat
);
202 unsigned int bytes_per_line
;
208 ret
= soc_mbus_bytes_per_line(fmt
->fmt
.pix
.width
,
213 bytes_per_line
= max_t(u32
, fmt
->fmt
.pix
.bytesperline
, ret
);
215 ret
= soc_mbus_image_size(xlate
->host_fmt
, bytes_per_line
,
216 fmt
->fmt
.pix
.height
);
220 sizes
[0] = max_t(u32
, fmt
->fmt
.pix
.sizeimage
, ret
);
222 /* Called from VIDIOC_REQBUFS or in compatibility mode */
223 sizes
[0] = icd
->sizeimage
;
226 alloc_ctxs
[0] = mx3_cam
->alloc_ctx
;
228 if (!vq
->num_buffers
)
229 mx3_cam
->sequence
= 0;
234 /* If *num_planes != 0, we have already verified *count. */
236 sizes
[0] * *count
+ mx3_cam
->buf_total
> MAX_VIDEO_MEM
* 1024 * 1024)
237 *count
= (MAX_VIDEO_MEM
* 1024 * 1024 - mx3_cam
->buf_total
) /
245 static enum pixel_fmt
fourcc_to_ipu_pix(__u32 fourcc
)
247 /* Add more formats as need arises and test possibilities appear... */
249 case V4L2_PIX_FMT_RGB24
:
250 return IPU_PIX_FMT_RGB24
;
251 case V4L2_PIX_FMT_UYVY
:
252 case V4L2_PIX_FMT_RGB565
:
254 return IPU_PIX_FMT_GENERIC
;
258 static void mx3_videobuf_queue(struct vb2_buffer
*vb
)
260 struct soc_camera_device
*icd
= soc_camera_from_vb2q(vb
->vb2_queue
);
261 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
262 struct mx3_camera_dev
*mx3_cam
= ici
->priv
;
263 struct mx3_camera_buffer
*buf
= to_mx3_vb(vb
);
264 struct scatterlist
*sg
= &buf
->sg
;
265 struct dma_async_tx_descriptor
*txd
;
266 struct idmac_channel
*ichan
= mx3_cam
->idmac_channel
[0];
267 struct idmac_video_param
*video
= &ichan
->params
.video
;
268 const struct soc_mbus_pixelfmt
*host_fmt
= icd
->current_fmt
->host_fmt
;
272 new_size
= icd
->sizeimage
;
274 if (vb2_plane_size(vb
, 0) < new_size
) {
275 dev_err(icd
->parent
, "Buffer #%d too small (%lu < %zu)\n",
276 vb
->v4l2_buf
.index
, vb2_plane_size(vb
, 0), new_size
);
281 sg_dma_address(sg
) = vb2_dma_contig_plane_dma_addr(vb
, 0);
282 sg_dma_len(sg
) = new_size
;
284 txd
= dmaengine_prep_slave_sg(
285 &ichan
->dma_chan
, sg
, 1, DMA_DEV_TO_MEM
,
290 txd
->callback_param
= txd
;
291 txd
->callback
= mx3_cam_dma_done
;
298 vb2_set_plane_payload(vb
, 0, new_size
);
300 /* This is the configuration of one sg-element */
301 video
->out_pixel_fmt
= fourcc_to_ipu_pix(host_fmt
->fourcc
);
303 if (video
->out_pixel_fmt
== IPU_PIX_FMT_GENERIC
) {
305 * If the IPU DMA channel is configured to transfer generic
306 * 8-bit data, we have to set up the geometry parameters
307 * correctly, according to the current pixel format. The DMA
308 * horizontal parameters in this case are expressed in bytes,
311 video
->out_width
= icd
->bytesperline
;
312 video
->out_height
= icd
->user_height
;
313 video
->out_stride
= icd
->bytesperline
;
316 * For IPU known formats the pixel unit will be managed
317 * successfully by the IPU code
319 video
->out_width
= icd
->user_width
;
320 video
->out_height
= icd
->user_height
;
321 video
->out_stride
= icd
->user_width
;
325 /* helps to see what DMA actually has written */
326 if (vb2_plane_vaddr(vb
, 0))
327 memset(vb2_plane_vaddr(vb
, 0), 0xaa, vb2_get_plane_payload(vb
, 0));
330 spin_lock_irq(&mx3_cam
->lock
);
331 list_add_tail(&buf
->queue
, &mx3_cam
->capture
);
333 if (!mx3_cam
->active
)
334 mx3_cam
->active
= buf
;
336 spin_unlock_irq(&mx3_cam
->lock
);
338 cookie
= txd
->tx_submit(txd
);
339 dev_dbg(icd
->parent
, "Submitted cookie %d DMA 0x%08x\n",
340 cookie
, sg_dma_address(&buf
->sg
));
345 spin_lock_irq(&mx3_cam
->lock
);
348 list_del_init(&buf
->queue
);
350 if (mx3_cam
->active
== buf
)
351 mx3_cam
->active
= NULL
;
353 spin_unlock_irq(&mx3_cam
->lock
);
355 vb2_buffer_done(vb
, VB2_BUF_STATE_ERROR
);
358 static void mx3_videobuf_release(struct vb2_buffer
*vb
)
360 struct soc_camera_device
*icd
= soc_camera_from_vb2q(vb
->vb2_queue
);
361 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
362 struct mx3_camera_dev
*mx3_cam
= ici
->priv
;
363 struct mx3_camera_buffer
*buf
= to_mx3_vb(vb
);
364 struct dma_async_tx_descriptor
*txd
= buf
->txd
;
368 "Release%s DMA 0x%08x, queue %sempty\n",
369 mx3_cam
->active
== buf
? " active" : "", sg_dma_address(&buf
->sg
),
370 list_empty(&buf
->queue
) ? "" : "not ");
372 spin_lock_irqsave(&mx3_cam
->lock
, flags
);
374 if (mx3_cam
->active
== buf
)
375 mx3_cam
->active
= NULL
;
377 /* Doesn't hurt also if the list is empty */
378 list_del_init(&buf
->queue
);
382 if (mx3_cam
->idmac_channel
[0])
386 spin_unlock_irqrestore(&mx3_cam
->lock
, flags
);
388 mx3_cam
->buf_total
-= vb2_plane_size(vb
, 0);
391 static int mx3_videobuf_init(struct vb2_buffer
*vb
)
393 struct soc_camera_device
*icd
= soc_camera_from_vb2q(vb
->vb2_queue
);
394 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
395 struct mx3_camera_dev
*mx3_cam
= ici
->priv
;
396 struct mx3_camera_buffer
*buf
= to_mx3_vb(vb
);
399 /* This is for locking debugging only */
400 INIT_LIST_HEAD(&buf
->queue
);
401 sg_init_table(&buf
->sg
, 1);
403 mx3_cam
->buf_total
+= vb2_plane_size(vb
, 0);
409 static void mx3_stop_streaming(struct vb2_queue
*q
)
411 struct soc_camera_device
*icd
= soc_camera_from_vb2q(q
);
412 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
413 struct mx3_camera_dev
*mx3_cam
= ici
->priv
;
414 struct idmac_channel
*ichan
= mx3_cam
->idmac_channel
[0];
415 struct mx3_camera_buffer
*buf
, *tmp
;
419 dmaengine_pause(&ichan
->dma_chan
);
421 spin_lock_irqsave(&mx3_cam
->lock
, flags
);
423 mx3_cam
->active
= NULL
;
425 list_for_each_entry_safe(buf
, tmp
, &mx3_cam
->capture
, queue
) {
426 list_del_init(&buf
->queue
);
427 vb2_buffer_done(&buf
->vb
, VB2_BUF_STATE_ERROR
);
430 spin_unlock_irqrestore(&mx3_cam
->lock
, flags
);
433 static struct vb2_ops mx3_videobuf_ops
= {
434 .queue_setup
= mx3_videobuf_setup
,
435 .buf_queue
= mx3_videobuf_queue
,
436 .buf_cleanup
= mx3_videobuf_release
,
437 .buf_init
= mx3_videobuf_init
,
438 .wait_prepare
= soc_camera_unlock
,
439 .wait_finish
= soc_camera_lock
,
440 .stop_streaming
= mx3_stop_streaming
,
443 static int mx3_camera_init_videobuf(struct vb2_queue
*q
,
444 struct soc_camera_device
*icd
)
446 q
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE
;
447 q
->io_modes
= VB2_MMAP
| VB2_USERPTR
;
449 q
->ops
= &mx3_videobuf_ops
;
450 q
->mem_ops
= &vb2_dma_contig_memops
;
451 q
->buf_struct_size
= sizeof(struct mx3_camera_buffer
);
452 q
->timestamp_flags
= V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC
;
454 return vb2_queue_init(q
);
457 /* First part of ipu_csi_init_interface() */
458 static void mx3_camera_activate(struct mx3_camera_dev
*mx3_cam
)
463 /* Set default size: ipu_csi_set_window_size() */
464 csi_reg_write(mx3_cam
, (640 - 1) | ((480 - 1) << 16), CSI_ACT_FRM_SIZE
);
465 /* ...and position to 0:0: ipu_csi_set_window_pos() */
466 conf
= csi_reg_read(mx3_cam
, CSI_OUT_FRM_CTRL
) & 0xffff0000;
467 csi_reg_write(mx3_cam
, conf
, CSI_OUT_FRM_CTRL
);
469 /* We use only gated clock synchronisation mode so far */
470 conf
= 0 << CSI_SENS_CONF_SENS_PRTCL_SHIFT
;
472 /* Set generic data, platform-biggest bus-width */
473 conf
|= CSI_SENS_CONF_DATA_FMT_BAYER
;
475 if (mx3_cam
->platform_flags
& MX3_CAMERA_DATAWIDTH_15
)
476 conf
|= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT
;
477 else if (mx3_cam
->platform_flags
& MX3_CAMERA_DATAWIDTH_10
)
478 conf
|= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT
;
479 else if (mx3_cam
->platform_flags
& MX3_CAMERA_DATAWIDTH_8
)
480 conf
|= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT
;
481 else/* if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)*/
482 conf
|= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT
;
484 if (mx3_cam
->platform_flags
& MX3_CAMERA_CLK_SRC
)
485 conf
|= 1 << CSI_SENS_CONF_SENS_CLKSRC_SHIFT
;
486 if (mx3_cam
->platform_flags
& MX3_CAMERA_EXT_VSYNC
)
487 conf
|= 1 << CSI_SENS_CONF_EXT_VSYNC_SHIFT
;
488 if (mx3_cam
->platform_flags
& MX3_CAMERA_DP
)
489 conf
|= 1 << CSI_SENS_CONF_DATA_POL_SHIFT
;
490 if (mx3_cam
->platform_flags
& MX3_CAMERA_PCP
)
491 conf
|= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT
;
492 if (mx3_cam
->platform_flags
& MX3_CAMERA_HSP
)
493 conf
|= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT
;
494 if (mx3_cam
->platform_flags
& MX3_CAMERA_VSP
)
495 conf
|= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT
;
497 /* ipu_csi_init_interface() */
498 csi_reg_write(mx3_cam
, conf
, CSI_SENS_CONF
);
500 clk_prepare_enable(mx3_cam
->clk
);
501 rate
= clk_round_rate(mx3_cam
->clk
, mx3_cam
->mclk
);
502 dev_dbg(mx3_cam
->soc_host
.v4l2_dev
.dev
, "Set SENS_CONF to %x, rate %ld\n", conf
, rate
);
504 clk_set_rate(mx3_cam
->clk
, rate
);
507 static int mx3_camera_add_device(struct soc_camera_device
*icd
)
509 dev_info(icd
->parent
, "MX3 Camera driver attached to camera %d\n",
515 static void mx3_camera_remove_device(struct soc_camera_device
*icd
)
517 dev_info(icd
->parent
, "MX3 Camera driver detached from camera %d\n",
521 /* Called with .host_lock held */
522 static int mx3_camera_clock_start(struct soc_camera_host
*ici
)
524 struct mx3_camera_dev
*mx3_cam
= ici
->priv
;
526 mx3_camera_activate(mx3_cam
);
528 mx3_cam
->buf_total
= 0;
533 /* Called with .host_lock held */
534 static void mx3_camera_clock_stop(struct soc_camera_host
*ici
)
536 struct mx3_camera_dev
*mx3_cam
= ici
->priv
;
537 struct idmac_channel
**ichan
= &mx3_cam
->idmac_channel
[0];
540 dma_release_channel(&(*ichan
)->dma_chan
);
544 clk_disable_unprepare(mx3_cam
->clk
);
547 static int test_platform_param(struct mx3_camera_dev
*mx3_cam
,
548 unsigned char buswidth
, unsigned long *flags
)
551 * If requested data width is supported by the platform, use it or any
552 * possible lower value - i.MX31 is smart enough to shift bits
554 if (buswidth
> fls(mx3_cam
->width_flags
))
558 * Platform specified synchronization and pixel clock polarities are
559 * only a recommendation and are only used during probing. MX3x
560 * camera interface only works in master mode, i.e., uses HSYNC and
561 * VSYNC signals from the sensor
563 *flags
= V4L2_MBUS_MASTER
|
564 V4L2_MBUS_HSYNC_ACTIVE_HIGH
|
565 V4L2_MBUS_HSYNC_ACTIVE_LOW
|
566 V4L2_MBUS_VSYNC_ACTIVE_HIGH
|
567 V4L2_MBUS_VSYNC_ACTIVE_LOW
|
568 V4L2_MBUS_PCLK_SAMPLE_RISING
|
569 V4L2_MBUS_PCLK_SAMPLE_FALLING
|
570 V4L2_MBUS_DATA_ACTIVE_HIGH
|
571 V4L2_MBUS_DATA_ACTIVE_LOW
;
576 static int mx3_camera_try_bus_param(struct soc_camera_device
*icd
,
577 const unsigned int depth
)
579 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
580 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
581 struct mx3_camera_dev
*mx3_cam
= ici
->priv
;
582 struct v4l2_mbus_config cfg
= {.type
= V4L2_MBUS_PARALLEL
,};
583 unsigned long bus_flags
, common_flags
;
584 int ret
= test_platform_param(mx3_cam
, depth
, &bus_flags
);
586 dev_dbg(icd
->parent
, "request bus width %d bit: %d\n", depth
, ret
);
591 ret
= v4l2_subdev_call(sd
, video
, g_mbus_config
, &cfg
);
593 common_flags
= soc_mbus_config_compatible(&cfg
,
596 dev_warn(icd
->parent
,
597 "Flags incompatible: camera 0x%x, host 0x%lx\n",
598 cfg
.flags
, bus_flags
);
601 } else if (ret
!= -ENOIOCTLCMD
) {
608 static bool chan_filter(struct dma_chan
*chan
, void *arg
)
610 struct dma_chan_request
*rq
= arg
;
611 struct mx3_camera_pdata
*pdata
;
613 if (!imx_dma_is_ipu(chan
))
619 pdata
= rq
->mx3_cam
->soc_host
.v4l2_dev
.dev
->platform_data
;
621 return rq
->id
== chan
->chan_id
&&
622 pdata
->dma_dev
== chan
->device
->dev
;
625 static const struct soc_mbus_pixelfmt mx3_camera_formats
[] = {
627 .fourcc
= V4L2_PIX_FMT_SBGGR8
,
628 .name
= "Bayer BGGR (sRGB) 8 bit",
629 .bits_per_sample
= 8,
630 .packing
= SOC_MBUS_PACKING_NONE
,
631 .order
= SOC_MBUS_ORDER_LE
,
632 .layout
= SOC_MBUS_LAYOUT_PACKED
,
634 .fourcc
= V4L2_PIX_FMT_GREY
,
635 .name
= "Monochrome 8 bit",
636 .bits_per_sample
= 8,
637 .packing
= SOC_MBUS_PACKING_NONE
,
638 .order
= SOC_MBUS_ORDER_LE
,
639 .layout
= SOC_MBUS_LAYOUT_PACKED
,
643 /* This will be corrected as we get more formats */
644 static bool mx3_camera_packing_supported(const struct soc_mbus_pixelfmt
*fmt
)
646 return fmt
->packing
== SOC_MBUS_PACKING_NONE
||
647 (fmt
->bits_per_sample
== 8 &&
648 fmt
->packing
== SOC_MBUS_PACKING_2X8_PADHI
) ||
649 (fmt
->bits_per_sample
> 8 &&
650 fmt
->packing
== SOC_MBUS_PACKING_EXTEND16
);
653 static int mx3_camera_get_formats(struct soc_camera_device
*icd
, unsigned int idx
,
654 struct soc_camera_format_xlate
*xlate
)
656 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
657 struct device
*dev
= icd
->parent
;
658 int formats
= 0, ret
;
659 enum v4l2_mbus_pixelcode code
;
660 const struct soc_mbus_pixelfmt
*fmt
;
662 ret
= v4l2_subdev_call(sd
, video
, enum_mbus_fmt
, idx
, &code
);
664 /* No more formats */
667 fmt
= soc_mbus_get_fmtdesc(code
);
669 dev_warn(icd
->parent
,
670 "Unsupported format code #%u: 0x%x\n", idx
, code
);
674 /* This also checks support for the requested bits-per-sample */
675 ret
= mx3_camera_try_bus_param(icd
, fmt
->bits_per_sample
);
680 case V4L2_MBUS_FMT_SBGGR10_1X10
:
683 xlate
->host_fmt
= &mx3_camera_formats
[0];
686 dev_dbg(dev
, "Providing format %s using code 0x%x\n",
687 mx3_camera_formats
[0].name
, code
);
690 case V4L2_MBUS_FMT_Y10_1X10
:
693 xlate
->host_fmt
= &mx3_camera_formats
[1];
696 dev_dbg(dev
, "Providing format %s using code 0x%x\n",
697 mx3_camera_formats
[1].name
, code
);
701 if (!mx3_camera_packing_supported(fmt
))
705 /* Generic pass-through */
708 xlate
->host_fmt
= fmt
;
710 dev_dbg(dev
, "Providing format %c%c%c%c in pass-through mode\n",
711 (fmt
->fourcc
>> (0*8)) & 0xFF,
712 (fmt
->fourcc
>> (1*8)) & 0xFF,
713 (fmt
->fourcc
>> (2*8)) & 0xFF,
714 (fmt
->fourcc
>> (3*8)) & 0xFF);
721 static void configure_geometry(struct mx3_camera_dev
*mx3_cam
,
722 unsigned int width
, unsigned int height
,
723 const struct soc_mbus_pixelfmt
*fmt
)
725 u32 ctrl
, width_field
, height_field
;
727 if (fourcc_to_ipu_pix(fmt
->fourcc
) == IPU_PIX_FMT_GENERIC
) {
729 * As the CSI will be configured to output BAYER, here
730 * the width parameter count the number of samples to
731 * capture to complete the whole image width.
733 unsigned int num
, den
;
734 int ret
= soc_mbus_samples_per_pixel(fmt
, &num
, &den
);
736 width
= width
* num
/ den
;
739 /* Setup frame size - this cannot be changed on-the-fly... */
740 width_field
= width
- 1;
741 height_field
= height
- 1;
742 csi_reg_write(mx3_cam
, width_field
| (height_field
<< 16), CSI_SENS_FRM_SIZE
);
744 csi_reg_write(mx3_cam
, width_field
<< 16, CSI_FLASH_STROBE_1
);
745 csi_reg_write(mx3_cam
, (height_field
<< 16) | 0x22, CSI_FLASH_STROBE_2
);
747 csi_reg_write(mx3_cam
, width_field
| (height_field
<< 16), CSI_ACT_FRM_SIZE
);
749 /* ...and position */
750 ctrl
= csi_reg_read(mx3_cam
, CSI_OUT_FRM_CTRL
) & 0xffff0000;
751 /* Sensor does the cropping */
752 csi_reg_write(mx3_cam
, ctrl
| 0 | (0 << 8), CSI_OUT_FRM_CTRL
);
755 static int acquire_dma_channel(struct mx3_camera_dev
*mx3_cam
)
758 struct dma_chan
*chan
;
759 struct idmac_channel
**ichan
= &mx3_cam
->idmac_channel
[0];
760 /* We have to use IDMAC_IC_7 for Bayer / generic data */
761 struct dma_chan_request rq
= {.mx3_cam
= mx3_cam
,
765 dma_cap_set(DMA_SLAVE
, mask
);
766 dma_cap_set(DMA_PRIVATE
, mask
);
767 chan
= dma_request_channel(mask
, chan_filter
, &rq
);
771 *ichan
= to_idmac_chan(chan
);
772 (*ichan
)->client
= mx3_cam
;
778 * FIXME: learn to use stride != width, then we can keep stride properly aligned
779 * and support arbitrary (even) widths.
781 static inline void stride_align(__u32
*width
)
783 if (ALIGN(*width
, 8) < 4096)
784 *width
= ALIGN(*width
, 8);
786 *width
= *width
& ~7;
790 * As long as we don't implement host-side cropping and scaling, we can use
791 * default g_crop and cropcap from soc_camera.c
793 static int mx3_camera_set_crop(struct soc_camera_device
*icd
,
794 const struct v4l2_crop
*a
)
796 struct v4l2_crop a_writable
= *a
;
797 struct v4l2_rect
*rect
= &a_writable
.c
;
798 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
799 struct mx3_camera_dev
*mx3_cam
= ici
->priv
;
800 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
801 struct v4l2_mbus_framefmt mf
;
804 soc_camera_limit_side(&rect
->left
, &rect
->width
, 0, 2, 4096);
805 soc_camera_limit_side(&rect
->top
, &rect
->height
, 0, 2, 4096);
807 ret
= v4l2_subdev_call(sd
, video
, s_crop
, a
);
811 /* The capture device might have changed its output sizes */
812 ret
= v4l2_subdev_call(sd
, video
, g_mbus_fmt
, &mf
);
816 if (mf
.code
!= icd
->current_fmt
->code
)
820 /* Ouch! We can only handle 8-byte aligned width... */
821 stride_align(&mf
.width
);
822 ret
= v4l2_subdev_call(sd
, video
, s_mbus_fmt
, &mf
);
827 if (mf
.width
!= icd
->user_width
|| mf
.height
!= icd
->user_height
)
828 configure_geometry(mx3_cam
, mf
.width
, mf
.height
,
829 icd
->current_fmt
->host_fmt
);
831 dev_dbg(icd
->parent
, "Sensor cropped %dx%d\n",
832 mf
.width
, mf
.height
);
834 icd
->user_width
= mf
.width
;
835 icd
->user_height
= mf
.height
;
840 static int mx3_camera_set_fmt(struct soc_camera_device
*icd
,
841 struct v4l2_format
*f
)
843 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
844 struct mx3_camera_dev
*mx3_cam
= ici
->priv
;
845 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
846 const struct soc_camera_format_xlate
*xlate
;
847 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
848 struct v4l2_mbus_framefmt mf
;
851 xlate
= soc_camera_xlate_by_fourcc(icd
, pix
->pixelformat
);
853 dev_warn(icd
->parent
, "Format %x not found\n",
858 stride_align(&pix
->width
);
859 dev_dbg(icd
->parent
, "Set format %dx%d\n", pix
->width
, pix
->height
);
862 * Might have to perform a complete interface initialisation like in
863 * ipu_csi_init_interface() in mxc_v4l2_s_param(). Also consider
867 configure_geometry(mx3_cam
, pix
->width
, pix
->height
, xlate
->host_fmt
);
869 mf
.width
= pix
->width
;
870 mf
.height
= pix
->height
;
871 mf
.field
= pix
->field
;
872 mf
.colorspace
= pix
->colorspace
;
873 mf
.code
= xlate
->code
;
875 ret
= v4l2_subdev_call(sd
, video
, s_mbus_fmt
, &mf
);
879 if (mf
.code
!= xlate
->code
)
882 if (!mx3_cam
->idmac_channel
[0]) {
883 ret
= acquire_dma_channel(mx3_cam
);
888 pix
->width
= mf
.width
;
889 pix
->height
= mf
.height
;
890 pix
->field
= mf
.field
;
891 mx3_cam
->field
= mf
.field
;
892 pix
->colorspace
= mf
.colorspace
;
893 icd
->current_fmt
= xlate
;
895 dev_dbg(icd
->parent
, "Sensor set %dx%d\n", pix
->width
, pix
->height
);
900 static int mx3_camera_try_fmt(struct soc_camera_device
*icd
,
901 struct v4l2_format
*f
)
903 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
904 const struct soc_camera_format_xlate
*xlate
;
905 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
906 struct v4l2_mbus_framefmt mf
;
907 __u32 pixfmt
= pix
->pixelformat
;
910 xlate
= soc_camera_xlate_by_fourcc(icd
, pixfmt
);
911 if (pixfmt
&& !xlate
) {
912 dev_warn(icd
->parent
, "Format %x not found\n", pixfmt
);
916 /* limit to MX3 hardware capabilities */
917 if (pix
->height
> 4096)
919 if (pix
->width
> 4096)
922 /* limit to sensor capabilities */
923 mf
.width
= pix
->width
;
924 mf
.height
= pix
->height
;
925 mf
.field
= pix
->field
;
926 mf
.colorspace
= pix
->colorspace
;
927 mf
.code
= xlate
->code
;
929 ret
= v4l2_subdev_call(sd
, video
, try_mbus_fmt
, &mf
);
933 pix
->width
= mf
.width
;
934 pix
->height
= mf
.height
;
935 pix
->colorspace
= mf
.colorspace
;
939 pix
->field
= V4L2_FIELD_NONE
;
941 case V4L2_FIELD_NONE
:
944 dev_err(icd
->parent
, "Field type %d unsupported.\n",
952 static int mx3_camera_reqbufs(struct soc_camera_device
*icd
,
953 struct v4l2_requestbuffers
*p
)
958 static unsigned int mx3_camera_poll(struct file
*file
, poll_table
*pt
)
960 struct soc_camera_device
*icd
= file
->private_data
;
962 return vb2_poll(&icd
->vb2_vidq
, file
, pt
);
965 static int mx3_camera_querycap(struct soc_camera_host
*ici
,
966 struct v4l2_capability
*cap
)
968 /* cap->name is set by the firendly caller:-> */
969 strlcpy(cap
->card
, "i.MX3x Camera", sizeof(cap
->card
));
970 cap
->capabilities
= V4L2_CAP_VIDEO_CAPTURE
| V4L2_CAP_STREAMING
;
975 static int mx3_camera_set_bus_param(struct soc_camera_device
*icd
)
977 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
978 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
979 struct mx3_camera_dev
*mx3_cam
= ici
->priv
;
980 struct v4l2_mbus_config cfg
= {.type
= V4L2_MBUS_PARALLEL
,};
981 u32 pixfmt
= icd
->current_fmt
->host_fmt
->fourcc
;
982 unsigned long bus_flags
, common_flags
;
984 const struct soc_mbus_pixelfmt
*fmt
;
987 const struct soc_camera_format_xlate
*xlate
;
988 struct device
*dev
= icd
->parent
;
990 fmt
= soc_mbus_get_fmtdesc(icd
->current_fmt
->code
);
994 xlate
= soc_camera_xlate_by_fourcc(icd
, pixfmt
);
996 dev_warn(dev
, "Format %x not found\n", pixfmt
);
1000 buswidth
= fmt
->bits_per_sample
;
1001 ret
= test_platform_param(mx3_cam
, buswidth
, &bus_flags
);
1003 dev_dbg(dev
, "requested bus width %d bit: %d\n", buswidth
, ret
);
1008 ret
= v4l2_subdev_call(sd
, video
, g_mbus_config
, &cfg
);
1010 common_flags
= soc_mbus_config_compatible(&cfg
,
1012 if (!common_flags
) {
1013 dev_warn(icd
->parent
,
1014 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1015 cfg
.flags
, bus_flags
);
1018 } else if (ret
!= -ENOIOCTLCMD
) {
1021 common_flags
= bus_flags
;
1024 dev_dbg(dev
, "Flags cam: 0x%x host: 0x%lx common: 0x%lx\n",
1025 cfg
.flags
, bus_flags
, common_flags
);
1027 /* Make choices, based on platform preferences */
1028 if ((common_flags
& V4L2_MBUS_HSYNC_ACTIVE_HIGH
) &&
1029 (common_flags
& V4L2_MBUS_HSYNC_ACTIVE_LOW
)) {
1030 if (mx3_cam
->platform_flags
& MX3_CAMERA_HSP
)
1031 common_flags
&= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH
;
1033 common_flags
&= ~V4L2_MBUS_HSYNC_ACTIVE_LOW
;
1036 if ((common_flags
& V4L2_MBUS_VSYNC_ACTIVE_HIGH
) &&
1037 (common_flags
& V4L2_MBUS_VSYNC_ACTIVE_LOW
)) {
1038 if (mx3_cam
->platform_flags
& MX3_CAMERA_VSP
)
1039 common_flags
&= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH
;
1041 common_flags
&= ~V4L2_MBUS_VSYNC_ACTIVE_LOW
;
1044 if ((common_flags
& V4L2_MBUS_DATA_ACTIVE_HIGH
) &&
1045 (common_flags
& V4L2_MBUS_DATA_ACTIVE_LOW
)) {
1046 if (mx3_cam
->platform_flags
& MX3_CAMERA_DP
)
1047 common_flags
&= ~V4L2_MBUS_DATA_ACTIVE_HIGH
;
1049 common_flags
&= ~V4L2_MBUS_DATA_ACTIVE_LOW
;
1052 if ((common_flags
& V4L2_MBUS_PCLK_SAMPLE_RISING
) &&
1053 (common_flags
& V4L2_MBUS_PCLK_SAMPLE_FALLING
)) {
1054 if (mx3_cam
->platform_flags
& MX3_CAMERA_PCP
)
1055 common_flags
&= ~V4L2_MBUS_PCLK_SAMPLE_RISING
;
1057 common_flags
&= ~V4L2_MBUS_PCLK_SAMPLE_FALLING
;
1060 cfg
.flags
= common_flags
;
1061 ret
= v4l2_subdev_call(sd
, video
, s_mbus_config
, &cfg
);
1062 if (ret
< 0 && ret
!= -ENOIOCTLCMD
) {
1063 dev_dbg(dev
, "camera s_mbus_config(0x%lx) returned %d\n",
1069 * So far only gated clock mode is supported. Add a line
1070 * (3 << CSI_SENS_CONF_SENS_PRTCL_SHIFT) |
1071 * below and select the required mode when supporting other
1072 * synchronisation protocols.
1074 sens_conf
= csi_reg_read(mx3_cam
, CSI_SENS_CONF
) &
1075 ~((1 << CSI_SENS_CONF_VSYNC_POL_SHIFT
) |
1076 (1 << CSI_SENS_CONF_HSYNC_POL_SHIFT
) |
1077 (1 << CSI_SENS_CONF_DATA_POL_SHIFT
) |
1078 (1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT
) |
1079 (3 << CSI_SENS_CONF_DATA_FMT_SHIFT
) |
1080 (3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT
));
1082 /* TODO: Support RGB and YUV formats */
1084 /* This has been set in mx3_camera_activate(), but we clear it above */
1085 sens_conf
|= CSI_SENS_CONF_DATA_FMT_BAYER
;
1087 if (common_flags
& V4L2_MBUS_PCLK_SAMPLE_FALLING
)
1088 sens_conf
|= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT
;
1089 if (common_flags
& V4L2_MBUS_HSYNC_ACTIVE_LOW
)
1090 sens_conf
|= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT
;
1091 if (common_flags
& V4L2_MBUS_VSYNC_ACTIVE_LOW
)
1092 sens_conf
|= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT
;
1093 if (common_flags
& V4L2_MBUS_DATA_ACTIVE_LOW
)
1094 sens_conf
|= 1 << CSI_SENS_CONF_DATA_POL_SHIFT
;
1096 /* Just do what we're asked to do */
1097 switch (xlate
->host_fmt
->bits_per_sample
) {
1099 dw
= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT
;
1102 dw
= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT
;
1105 dw
= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT
;
1109 * Actually it can only be 15 now, default is just to silence
1113 dw
= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT
;
1116 csi_reg_write(mx3_cam
, sens_conf
| dw
, CSI_SENS_CONF
);
1118 dev_dbg(dev
, "Set SENS_CONF to %x\n", sens_conf
| dw
);
1123 static struct soc_camera_host_ops mx3_soc_camera_host_ops
= {
1124 .owner
= THIS_MODULE
,
1125 .add
= mx3_camera_add_device
,
1126 .remove
= mx3_camera_remove_device
,
1127 .clock_start
= mx3_camera_clock_start
,
1128 .clock_stop
= mx3_camera_clock_stop
,
1129 .set_crop
= mx3_camera_set_crop
,
1130 .set_fmt
= mx3_camera_set_fmt
,
1131 .try_fmt
= mx3_camera_try_fmt
,
1132 .get_formats
= mx3_camera_get_formats
,
1133 .init_videobuf2
= mx3_camera_init_videobuf
,
1134 .reqbufs
= mx3_camera_reqbufs
,
1135 .poll
= mx3_camera_poll
,
1136 .querycap
= mx3_camera_querycap
,
1137 .set_bus_param
= mx3_camera_set_bus_param
,
1140 static int mx3_camera_probe(struct platform_device
*pdev
)
1142 struct mx3_camera_pdata
*pdata
= pdev
->dev
.platform_data
;
1143 struct mx3_camera_dev
*mx3_cam
;
1144 struct resource
*res
;
1147 struct soc_camera_host
*soc_host
;
1149 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1150 base
= devm_ioremap_resource(&pdev
->dev
, res
);
1152 return PTR_ERR(base
);
1157 mx3_cam
= devm_kzalloc(&pdev
->dev
, sizeof(*mx3_cam
), GFP_KERNEL
);
1159 dev_err(&pdev
->dev
, "Could not allocate mx3 camera object\n");
1163 mx3_cam
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1164 if (IS_ERR(mx3_cam
->clk
))
1165 return PTR_ERR(mx3_cam
->clk
);
1167 mx3_cam
->pdata
= pdata
;
1168 mx3_cam
->platform_flags
= pdata
->flags
;
1169 if (!(mx3_cam
->platform_flags
& MX3_CAMERA_DATAWIDTH_MASK
)) {
1171 * Platform hasn't set available data widths. This is bad.
1172 * Warn and use a default.
1174 dev_warn(&pdev
->dev
, "WARNING! Platform hasn't set available "
1175 "data widths, using default 8 bit\n");
1176 mx3_cam
->platform_flags
|= MX3_CAMERA_DATAWIDTH_8
;
1178 if (mx3_cam
->platform_flags
& MX3_CAMERA_DATAWIDTH_4
)
1179 mx3_cam
->width_flags
= 1 << 3;
1180 if (mx3_cam
->platform_flags
& MX3_CAMERA_DATAWIDTH_8
)
1181 mx3_cam
->width_flags
|= 1 << 7;
1182 if (mx3_cam
->platform_flags
& MX3_CAMERA_DATAWIDTH_10
)
1183 mx3_cam
->width_flags
|= 1 << 9;
1184 if (mx3_cam
->platform_flags
& MX3_CAMERA_DATAWIDTH_15
)
1185 mx3_cam
->width_flags
|= 1 << 14;
1187 mx3_cam
->mclk
= pdata
->mclk_10khz
* 10000;
1188 if (!mx3_cam
->mclk
) {
1189 dev_warn(&pdev
->dev
,
1190 "mclk_10khz == 0! Please, fix your platform data. "
1191 "Using default 20MHz\n");
1192 mx3_cam
->mclk
= 20000000;
1195 /* list of video-buffers */
1196 INIT_LIST_HEAD(&mx3_cam
->capture
);
1197 spin_lock_init(&mx3_cam
->lock
);
1199 mx3_cam
->base
= base
;
1201 soc_host
= &mx3_cam
->soc_host
;
1202 soc_host
->drv_name
= MX3_CAM_DRV_NAME
;
1203 soc_host
->ops
= &mx3_soc_camera_host_ops
;
1204 soc_host
->priv
= mx3_cam
;
1205 soc_host
->v4l2_dev
.dev
= &pdev
->dev
;
1206 soc_host
->nr
= pdev
->id
;
1208 mx3_cam
->alloc_ctx
= vb2_dma_contig_init_ctx(&pdev
->dev
);
1209 if (IS_ERR(mx3_cam
->alloc_ctx
))
1210 return PTR_ERR(mx3_cam
->alloc_ctx
);
1212 if (pdata
->asd_sizes
) {
1213 soc_host
->asd
= pdata
->asd
;
1214 soc_host
->asd_sizes
= pdata
->asd_sizes
;
1217 err
= soc_camera_host_register(soc_host
);
1221 /* IDMAC interface */
1227 vb2_dma_contig_cleanup_ctx(mx3_cam
->alloc_ctx
);
1231 static int mx3_camera_remove(struct platform_device
*pdev
)
1233 struct soc_camera_host
*soc_host
= to_soc_camera_host(&pdev
->dev
);
1234 struct mx3_camera_dev
*mx3_cam
= container_of(soc_host
,
1235 struct mx3_camera_dev
, soc_host
);
1237 soc_camera_host_unregister(soc_host
);
1240 * The channel has either not been allocated,
1241 * or should have been released
1243 if (WARN_ON(mx3_cam
->idmac_channel
[0]))
1244 dma_release_channel(&mx3_cam
->idmac_channel
[0]->dma_chan
);
1246 vb2_dma_contig_cleanup_ctx(mx3_cam
->alloc_ctx
);
1253 static struct platform_driver mx3_camera_driver
= {
1255 .name
= MX3_CAM_DRV_NAME
,
1256 .owner
= THIS_MODULE
,
1258 .probe
= mx3_camera_probe
,
1259 .remove
= mx3_camera_remove
,
1262 module_platform_driver(mx3_camera_driver
);
1264 MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver");
1265 MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1266 MODULE_LICENSE("GPL v2");
1267 MODULE_VERSION("0.2.3");
1268 MODULE_ALIAS("platform:" MX3_CAM_DRV_NAME
);