2 * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver
4 * Copyright (c) 2013 Texas Instruments Inc.
5 * David Griego, <dagriego@biglakesoftware.com>
6 * Dale Farnsworth, <dale@farnsworth.org>
7 * Archit Taneja, <archit@ti.com>
9 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
10 * Pawel Osciak, <pawel@osciak.com>
11 * Marek Szyprowski, <m.szyprowski@samsung.com>
13 * Based on the virtual v4l2-mem2mem example device
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License version 2 as published by
17 * the Free Software Foundation
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/err.h>
24 #include <linux/interrupt.h>
26 #include <linux/ioctl.h>
27 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <linux/videodev2.h>
34 #include <linux/log2.h>
35 #include <linux/sizes.h>
37 #include <media/v4l2-common.h>
38 #include <media/v4l2-ctrls.h>
39 #include <media/v4l2-device.h>
40 #include <media/v4l2-event.h>
41 #include <media/v4l2-ioctl.h>
42 #include <media/v4l2-mem2mem.h>
43 #include <media/videobuf2-v4l2.h>
44 #include <media/videobuf2-dma-contig.h>
51 #define VPE_MODULE_NAME "vpe"
53 /* minimum and maximum frame sizes */
59 /* required alignments */
60 #define S_ALIGN 0 /* multiple of 1 */
61 #define H_ALIGN 1 /* multiple of 2 */
63 /* flags that indicate a format can be used for capture/output */
64 #define VPE_FMT_TYPE_CAPTURE (1 << 0)
65 #define VPE_FMT_TYPE_OUTPUT (1 << 1)
67 /* used as plane indices */
68 #define VPE_MAX_PLANES 2
72 /* per m2m context info */
73 #define VPE_MAX_SRC_BUFS 3 /* need 3 src fields to de-interlace */
75 #define VPE_DEF_BUFS_PER_JOB 1 /* default one buffer per batch job */
78 * each VPE context can need up to 3 config descriptors, 7 input descriptors,
79 * 3 output descriptors, and 10 control descriptors
81 #define VPE_DESC_LIST_SIZE (10 * VPDMA_DTD_DESC_SIZE + \
82 13 * VPDMA_CFD_CTD_DESC_SIZE)
84 #define vpe_dbg(vpedev, fmt, arg...) \
85 dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg)
86 #define vpe_err(vpedev, fmt, arg...) \
87 dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg)
89 struct vpe_us_coeffs
{
90 unsigned short anchor_fid0_c0
;
91 unsigned short anchor_fid0_c1
;
92 unsigned short anchor_fid0_c2
;
93 unsigned short anchor_fid0_c3
;
94 unsigned short interp_fid0_c0
;
95 unsigned short interp_fid0_c1
;
96 unsigned short interp_fid0_c2
;
97 unsigned short interp_fid0_c3
;
98 unsigned short anchor_fid1_c0
;
99 unsigned short anchor_fid1_c1
;
100 unsigned short anchor_fid1_c2
;
101 unsigned short anchor_fid1_c3
;
102 unsigned short interp_fid1_c0
;
103 unsigned short interp_fid1_c1
;
104 unsigned short interp_fid1_c2
;
105 unsigned short interp_fid1_c3
;
109 * Default upsampler coefficients
111 static const struct vpe_us_coeffs us_coeffs
[] = {
113 /* Coefficients for progressive input */
114 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
115 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
118 /* Coefficients for Top Field Interlaced input */
119 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3,
120 /* Coefficients for Bottom Field Interlaced input */
121 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9,
126 * the following registers are for configuring some of the parameters of the
127 * motion and edge detection blocks inside DEI, these generally remain the same,
128 * these could be passed later via userspace if some one needs to tweak these.
130 struct vpe_dei_regs
{
131 unsigned long mdt_spacial_freq_thr_reg
; /* VPE_DEI_REG2 */
132 unsigned long edi_config_reg
; /* VPE_DEI_REG3 */
133 unsigned long edi_lut_reg0
; /* VPE_DEI_REG4 */
134 unsigned long edi_lut_reg1
; /* VPE_DEI_REG5 */
135 unsigned long edi_lut_reg2
; /* VPE_DEI_REG6 */
136 unsigned long edi_lut_reg3
; /* VPE_DEI_REG7 */
140 * default expert DEI register values, unlikely to be modified.
142 static const struct vpe_dei_regs dei_regs
= {
143 .mdt_spacial_freq_thr_reg
= 0x020C0804u
,
144 .edi_config_reg
= 0x0118100Fu
,
145 .edi_lut_reg0
= 0x08040200u
,
146 .edi_lut_reg1
= 0x1010100Cu
,
147 .edi_lut_reg2
= 0x10101010u
,
148 .edi_lut_reg3
= 0x10101010u
,
152 * The port_data structure contains per-port data.
154 struct vpe_port_data
{
155 enum vpdma_channel channel
; /* VPDMA channel */
156 u8 vb_index
; /* input frame f, f-1, f-2 index */
157 u8 vb_part
; /* plane index for co-panar formats */
161 * Define indices into the port_data tables
163 #define VPE_PORT_LUMA1_IN 0
164 #define VPE_PORT_CHROMA1_IN 1
165 #define VPE_PORT_LUMA2_IN 2
166 #define VPE_PORT_CHROMA2_IN 3
167 #define VPE_PORT_LUMA3_IN 4
168 #define VPE_PORT_CHROMA3_IN 5
169 #define VPE_PORT_MV_IN 6
170 #define VPE_PORT_MV_OUT 7
171 #define VPE_PORT_LUMA_OUT 8
172 #define VPE_PORT_CHROMA_OUT 9
173 #define VPE_PORT_RGB_OUT 10
175 static const struct vpe_port_data port_data
[11] = {
176 [VPE_PORT_LUMA1_IN
] = {
177 .channel
= VPE_CHAN_LUMA1_IN
,
181 [VPE_PORT_CHROMA1_IN
] = {
182 .channel
= VPE_CHAN_CHROMA1_IN
,
184 .vb_part
= VPE_CHROMA
,
186 [VPE_PORT_LUMA2_IN
] = {
187 .channel
= VPE_CHAN_LUMA2_IN
,
191 [VPE_PORT_CHROMA2_IN
] = {
192 .channel
= VPE_CHAN_CHROMA2_IN
,
194 .vb_part
= VPE_CHROMA
,
196 [VPE_PORT_LUMA3_IN
] = {
197 .channel
= VPE_CHAN_LUMA3_IN
,
201 [VPE_PORT_CHROMA3_IN
] = {
202 .channel
= VPE_CHAN_CHROMA3_IN
,
204 .vb_part
= VPE_CHROMA
,
207 .channel
= VPE_CHAN_MV_IN
,
209 [VPE_PORT_MV_OUT
] = {
210 .channel
= VPE_CHAN_MV_OUT
,
212 [VPE_PORT_LUMA_OUT
] = {
213 .channel
= VPE_CHAN_LUMA_OUT
,
216 [VPE_PORT_CHROMA_OUT
] = {
217 .channel
= VPE_CHAN_CHROMA_OUT
,
218 .vb_part
= VPE_CHROMA
,
220 [VPE_PORT_RGB_OUT
] = {
221 .channel
= VPE_CHAN_RGB_OUT
,
227 /* driver info for each of the supported video formats */
229 char *name
; /* human-readable name */
230 u32 fourcc
; /* standard format identifier */
231 u8 types
; /* CAPTURE and/or OUTPUT */
232 u8 coplanar
; /* set for unpacked Luma and Chroma */
233 /* vpdma format info for each plane */
234 struct vpdma_data_format
const *vpdma_fmt
[VPE_MAX_PLANES
];
237 static struct vpe_fmt vpe_formats
[] = {
239 .name
= "YUV 422 co-planar",
240 .fourcc
= V4L2_PIX_FMT_NV16
,
241 .types
= VPE_FMT_TYPE_CAPTURE
| VPE_FMT_TYPE_OUTPUT
,
243 .vpdma_fmt
= { &vpdma_yuv_fmts
[VPDMA_DATA_FMT_Y444
],
244 &vpdma_yuv_fmts
[VPDMA_DATA_FMT_C444
],
248 .name
= "YUV 420 co-planar",
249 .fourcc
= V4L2_PIX_FMT_NV12
,
250 .types
= VPE_FMT_TYPE_CAPTURE
| VPE_FMT_TYPE_OUTPUT
,
252 .vpdma_fmt
= { &vpdma_yuv_fmts
[VPDMA_DATA_FMT_Y420
],
253 &vpdma_yuv_fmts
[VPDMA_DATA_FMT_C420
],
257 .name
= "YUYV 422 packed",
258 .fourcc
= V4L2_PIX_FMT_YUYV
,
259 .types
= VPE_FMT_TYPE_CAPTURE
| VPE_FMT_TYPE_OUTPUT
,
261 .vpdma_fmt
= { &vpdma_yuv_fmts
[VPDMA_DATA_FMT_YC422
],
265 .name
= "UYVY 422 packed",
266 .fourcc
= V4L2_PIX_FMT_UYVY
,
267 .types
= VPE_FMT_TYPE_CAPTURE
| VPE_FMT_TYPE_OUTPUT
,
269 .vpdma_fmt
= { &vpdma_yuv_fmts
[VPDMA_DATA_FMT_CY422
],
273 .name
= "RGB888 packed",
274 .fourcc
= V4L2_PIX_FMT_RGB24
,
275 .types
= VPE_FMT_TYPE_CAPTURE
,
277 .vpdma_fmt
= { &vpdma_rgb_fmts
[VPDMA_DATA_FMT_RGB24
],
282 .fourcc
= V4L2_PIX_FMT_RGB32
,
283 .types
= VPE_FMT_TYPE_CAPTURE
,
285 .vpdma_fmt
= { &vpdma_rgb_fmts
[VPDMA_DATA_FMT_ARGB32
],
289 .name
= "BGR888 packed",
290 .fourcc
= V4L2_PIX_FMT_BGR24
,
291 .types
= VPE_FMT_TYPE_CAPTURE
,
293 .vpdma_fmt
= { &vpdma_rgb_fmts
[VPDMA_DATA_FMT_BGR24
],
298 .fourcc
= V4L2_PIX_FMT_BGR32
,
299 .types
= VPE_FMT_TYPE_CAPTURE
,
301 .vpdma_fmt
= { &vpdma_rgb_fmts
[VPDMA_DATA_FMT_ABGR32
],
307 * per-queue, driver-specific private data.
308 * there is one source queue and one destination queue for each m2m context.
311 unsigned int width
; /* frame width */
312 unsigned int height
; /* frame height */
313 unsigned int bytesperline
[VPE_MAX_PLANES
]; /* bytes per line in memory */
314 enum v4l2_colorspace colorspace
;
315 enum v4l2_field field
; /* supported field value */
317 unsigned int sizeimage
[VPE_MAX_PLANES
]; /* image size in memory */
318 struct v4l2_rect c_rect
; /* crop/compose rectangle */
319 struct vpe_fmt
*fmt
; /* format info */
322 /* vpe_q_data flag bits */
323 #define Q_DATA_FRAME_1D (1 << 0)
324 #define Q_DATA_MODE_TILED (1 << 1)
325 #define Q_DATA_INTERLACED (1 << 2)
332 /* find our format description corresponding to the passed v4l2_format */
333 static struct vpe_fmt
*find_format(struct v4l2_format
*f
)
338 for (k
= 0; k
< ARRAY_SIZE(vpe_formats
); k
++) {
339 fmt
= &vpe_formats
[k
];
340 if (fmt
->fourcc
== f
->fmt
.pix
.pixelformat
)
348 * there is one vpe_dev structure in the driver, it is shared by
352 struct v4l2_device v4l2_dev
;
353 struct video_device vfd
;
354 struct v4l2_m2m_dev
*m2m_dev
;
356 atomic_t num_instances
; /* count of driver instances */
357 dma_addr_t loaded_mmrs
; /* shadow mmrs in device */
358 struct mutex dev_mutex
;
363 struct resource
*res
;
365 struct vb2_alloc_ctx
*alloc_ctx
;
366 struct vpdma_data
*vpdma
; /* vpdma data handle */
367 struct sc_data
*sc
; /* scaler data handle */
368 struct csc_data
*csc
; /* csc data handle */
372 * There is one vpe_ctx structure for each m2m context.
377 struct v4l2_ctrl_handler hdl
;
379 unsigned int field
; /* current field */
380 unsigned int sequence
; /* current frame/field seq */
381 unsigned int aborting
; /* abort after next irq */
383 unsigned int bufs_per_job
; /* input buffers per batch */
384 unsigned int bufs_completed
; /* bufs done in this batch */
386 struct vpe_q_data q_data
[2]; /* src & dst queue data */
387 struct vb2_buffer
*src_vbs
[VPE_MAX_SRC_BUFS
];
388 struct vb2_buffer
*dst_vb
;
390 dma_addr_t mv_buf_dma
[2]; /* dma addrs of motion vector in/out bufs */
391 void *mv_buf
[2]; /* virtual addrs of motion vector bufs */
392 size_t mv_buf_size
; /* current motion vector buffer size */
393 struct vpdma_buf mmr_adb
; /* shadow reg addr/data block */
394 struct vpdma_buf sc_coeff_h
; /* h coeff buffer */
395 struct vpdma_buf sc_coeff_v
; /* v coeff buffer */
396 struct vpdma_desc_list desc_list
; /* DMA descriptor list */
398 bool deinterlacing
; /* using de-interlacer */
399 bool load_mmrs
; /* have new shadow reg values */
401 unsigned int src_mv_buf_selector
;
406 * M2M devices get 2 queues.
407 * Return the queue given the type.
409 static struct vpe_q_data
*get_q_data(struct vpe_ctx
*ctx
,
410 enum v4l2_buf_type type
)
413 case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
:
414 case V4L2_BUF_TYPE_VIDEO_OUTPUT
:
415 return &ctx
->q_data
[Q_DATA_SRC
];
416 case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
:
417 case V4L2_BUF_TYPE_VIDEO_CAPTURE
:
418 return &ctx
->q_data
[Q_DATA_DST
];
425 static u32
read_reg(struct vpe_dev
*dev
, int offset
)
427 return ioread32(dev
->base
+ offset
);
430 static void write_reg(struct vpe_dev
*dev
, int offset
, u32 value
)
432 iowrite32(value
, dev
->base
+ offset
);
435 /* register field read/write helpers */
436 static int get_field(u32 value
, u32 mask
, int shift
)
438 return (value
& (mask
<< shift
)) >> shift
;
441 static int read_field_reg(struct vpe_dev
*dev
, int offset
, u32 mask
, int shift
)
443 return get_field(read_reg(dev
, offset
), mask
, shift
);
446 static void write_field(u32
*valp
, u32 field
, u32 mask
, int shift
)
450 val
&= ~(mask
<< shift
);
451 val
|= (field
& mask
) << shift
;
455 static void write_field_reg(struct vpe_dev
*dev
, int offset
, u32 field
,
458 u32 val
= read_reg(dev
, offset
);
460 write_field(&val
, field
, mask
, shift
);
462 write_reg(dev
, offset
, val
);
466 * DMA address/data block for the shadow registers
469 struct vpdma_adb_hdr out_fmt_hdr
;
472 struct vpdma_adb_hdr us1_hdr
;
474 struct vpdma_adb_hdr us2_hdr
;
476 struct vpdma_adb_hdr us3_hdr
;
478 struct vpdma_adb_hdr dei_hdr
;
480 struct vpdma_adb_hdr sc_hdr0
;
483 struct vpdma_adb_hdr sc_hdr8
;
486 struct vpdma_adb_hdr sc_hdr17
;
489 struct vpdma_adb_hdr csc_hdr
;
494 #define GET_OFFSET_TOP(ctx, obj, reg) \
495 ((obj)->res->start - ctx->dev->res->start + reg)
497 #define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \
498 VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
500 * Set the headers for all of the address/data block structures.
502 static void init_adb_hdrs(struct vpe_ctx
*ctx
)
504 VPE_SET_MMR_ADB_HDR(ctx
, out_fmt_hdr
, out_fmt_reg
, VPE_CLK_FORMAT_SELECT
);
505 VPE_SET_MMR_ADB_HDR(ctx
, us1_hdr
, us1_regs
, VPE_US1_R0
);
506 VPE_SET_MMR_ADB_HDR(ctx
, us2_hdr
, us2_regs
, VPE_US2_R0
);
507 VPE_SET_MMR_ADB_HDR(ctx
, us3_hdr
, us3_regs
, VPE_US3_R0
);
508 VPE_SET_MMR_ADB_HDR(ctx
, dei_hdr
, dei_regs
, VPE_DEI_FRAME_SIZE
);
509 VPE_SET_MMR_ADB_HDR(ctx
, sc_hdr0
, sc_regs0
,
510 GET_OFFSET_TOP(ctx
, ctx
->dev
->sc
, CFG_SC0
));
511 VPE_SET_MMR_ADB_HDR(ctx
, sc_hdr8
, sc_regs8
,
512 GET_OFFSET_TOP(ctx
, ctx
->dev
->sc
, CFG_SC8
));
513 VPE_SET_MMR_ADB_HDR(ctx
, sc_hdr17
, sc_regs17
,
514 GET_OFFSET_TOP(ctx
, ctx
->dev
->sc
, CFG_SC17
));
515 VPE_SET_MMR_ADB_HDR(ctx
, csc_hdr
, csc_regs
,
516 GET_OFFSET_TOP(ctx
, ctx
->dev
->csc
, CSC_CSC00
));
520 * Allocate or re-allocate the motion vector DMA buffers
521 * There are two buffers, one for input and one for output.
522 * However, the roles are reversed after each field is processed.
523 * In other words, after each field is processed, the previous
524 * output (dst) MV buffer becomes the new input (src) MV buffer.
526 static int realloc_mv_buffers(struct vpe_ctx
*ctx
, size_t size
)
528 struct device
*dev
= ctx
->dev
->v4l2_dev
.dev
;
530 if (ctx
->mv_buf_size
== size
)
534 dma_free_coherent(dev
, ctx
->mv_buf_size
, ctx
->mv_buf
[0],
538 dma_free_coherent(dev
, ctx
->mv_buf_size
, ctx
->mv_buf
[1],
544 ctx
->mv_buf
[0] = dma_alloc_coherent(dev
, size
, &ctx
->mv_buf_dma
[0],
546 if (!ctx
->mv_buf
[0]) {
547 vpe_err(ctx
->dev
, "failed to allocate motion vector buffer\n");
551 ctx
->mv_buf
[1] = dma_alloc_coherent(dev
, size
, &ctx
->mv_buf_dma
[1],
553 if (!ctx
->mv_buf
[1]) {
554 vpe_err(ctx
->dev
, "failed to allocate motion vector buffer\n");
555 dma_free_coherent(dev
, size
, ctx
->mv_buf
[0],
561 ctx
->mv_buf_size
= size
;
562 ctx
->src_mv_buf_selector
= 0;
567 static void free_mv_buffers(struct vpe_ctx
*ctx
)
569 realloc_mv_buffers(ctx
, 0);
573 * While de-interlacing, we keep the two most recent input buffers
574 * around. This function frees those two buffers when we have
575 * finished processing the current stream.
577 static void free_vbs(struct vpe_ctx
*ctx
)
579 struct vpe_dev
*dev
= ctx
->dev
;
582 if (ctx
->src_vbs
[2] == NULL
)
585 spin_lock_irqsave(&dev
->lock
, flags
);
586 if (ctx
->src_vbs
[2]) {
587 v4l2_m2m_buf_done(ctx
->src_vbs
[2], VB2_BUF_STATE_DONE
);
588 v4l2_m2m_buf_done(ctx
->src_vbs
[1], VB2_BUF_STATE_DONE
);
590 spin_unlock_irqrestore(&dev
->lock
, flags
);
594 * Enable or disable the VPE clocks
596 static void vpe_set_clock_enable(struct vpe_dev
*dev
, bool on
)
601 val
= VPE_DATA_PATH_CLK_ENABLE
| VPE_VPEDMA_CLK_ENABLE
;
602 write_reg(dev
, VPE_CLK_ENABLE
, val
);
605 static void vpe_top_reset(struct vpe_dev
*dev
)
608 write_field_reg(dev
, VPE_CLK_RESET
, 1, VPE_DATA_PATH_CLK_RESET_MASK
,
609 VPE_DATA_PATH_CLK_RESET_SHIFT
);
611 usleep_range(100, 150);
613 write_field_reg(dev
, VPE_CLK_RESET
, 0, VPE_DATA_PATH_CLK_RESET_MASK
,
614 VPE_DATA_PATH_CLK_RESET_SHIFT
);
617 static void vpe_top_vpdma_reset(struct vpe_dev
*dev
)
619 write_field_reg(dev
, VPE_CLK_RESET
, 1, VPE_VPDMA_CLK_RESET_MASK
,
620 VPE_VPDMA_CLK_RESET_SHIFT
);
622 usleep_range(100, 150);
624 write_field_reg(dev
, VPE_CLK_RESET
, 0, VPE_VPDMA_CLK_RESET_MASK
,
625 VPE_VPDMA_CLK_RESET_SHIFT
);
629 * Load the correct of upsampler coefficients into the shadow MMRs
631 static void set_us_coefficients(struct vpe_ctx
*ctx
)
633 struct vpe_mmr_adb
*mmr_adb
= ctx
->mmr_adb
.addr
;
634 struct vpe_q_data
*s_q_data
= &ctx
->q_data
[Q_DATA_SRC
];
635 u32
*us1_reg
= &mmr_adb
->us1_regs
[0];
636 u32
*us2_reg
= &mmr_adb
->us2_regs
[0];
637 u32
*us3_reg
= &mmr_adb
->us3_regs
[0];
638 const unsigned short *cp
, *end_cp
;
640 cp
= &us_coeffs
[0].anchor_fid0_c0
;
642 if (s_q_data
->flags
& Q_DATA_INTERLACED
) /* interlaced */
643 cp
+= sizeof(us_coeffs
[0]) / sizeof(*cp
);
645 end_cp
= cp
+ sizeof(us_coeffs
[0]) / sizeof(*cp
);
647 while (cp
< end_cp
) {
648 write_field(us1_reg
, *cp
++, VPE_US_C0_MASK
, VPE_US_C0_SHIFT
);
649 write_field(us1_reg
, *cp
++, VPE_US_C1_MASK
, VPE_US_C1_SHIFT
);
650 *us2_reg
++ = *us1_reg
;
651 *us3_reg
++ = *us1_reg
++;
653 ctx
->load_mmrs
= true;
657 * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs.
659 static void set_cfg_and_line_modes(struct vpe_ctx
*ctx
)
661 struct vpe_fmt
*fmt
= ctx
->q_data
[Q_DATA_SRC
].fmt
;
662 struct vpe_mmr_adb
*mmr_adb
= ctx
->mmr_adb
.addr
;
663 u32
*us1_reg0
= &mmr_adb
->us1_regs
[0];
664 u32
*us2_reg0
= &mmr_adb
->us2_regs
[0];
665 u32
*us3_reg0
= &mmr_adb
->us3_regs
[0];
670 * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing.
671 * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing.
674 if (fmt
->fourcc
== V4L2_PIX_FMT_NV12
) {
676 line_mode
= 0; /* double lines to line buffer */
679 write_field(us1_reg0
, cfg_mode
, VPE_US_MODE_MASK
, VPE_US_MODE_SHIFT
);
680 write_field(us2_reg0
, cfg_mode
, VPE_US_MODE_MASK
, VPE_US_MODE_SHIFT
);
681 write_field(us3_reg0
, cfg_mode
, VPE_US_MODE_MASK
, VPE_US_MODE_SHIFT
);
684 vpdma_set_line_mode(ctx
->dev
->vpdma
, line_mode
, VPE_CHAN_CHROMA1_IN
);
685 vpdma_set_line_mode(ctx
->dev
->vpdma
, line_mode
, VPE_CHAN_CHROMA2_IN
);
686 vpdma_set_line_mode(ctx
->dev
->vpdma
, line_mode
, VPE_CHAN_CHROMA3_IN
);
688 /* frame start for input luma */
689 vpdma_set_frame_start_event(ctx
->dev
->vpdma
, VPDMA_FSEVENT_CHANNEL_ACTIVE
,
691 vpdma_set_frame_start_event(ctx
->dev
->vpdma
, VPDMA_FSEVENT_CHANNEL_ACTIVE
,
693 vpdma_set_frame_start_event(ctx
->dev
->vpdma
, VPDMA_FSEVENT_CHANNEL_ACTIVE
,
696 /* frame start for input chroma */
697 vpdma_set_frame_start_event(ctx
->dev
->vpdma
, VPDMA_FSEVENT_CHANNEL_ACTIVE
,
698 VPE_CHAN_CHROMA1_IN
);
699 vpdma_set_frame_start_event(ctx
->dev
->vpdma
, VPDMA_FSEVENT_CHANNEL_ACTIVE
,
700 VPE_CHAN_CHROMA2_IN
);
701 vpdma_set_frame_start_event(ctx
->dev
->vpdma
, VPDMA_FSEVENT_CHANNEL_ACTIVE
,
702 VPE_CHAN_CHROMA3_IN
);
704 /* frame start for MV in client */
705 vpdma_set_frame_start_event(ctx
->dev
->vpdma
, VPDMA_FSEVENT_CHANNEL_ACTIVE
,
708 ctx
->load_mmrs
= true;
712 * Set the shadow registers that are modified when the source
715 static void set_src_registers(struct vpe_ctx
*ctx
)
717 set_us_coefficients(ctx
);
721 * Set the shadow registers that are modified when the destination
724 static void set_dst_registers(struct vpe_ctx
*ctx
)
726 struct vpe_mmr_adb
*mmr_adb
= ctx
->mmr_adb
.addr
;
727 enum v4l2_colorspace clrspc
= ctx
->q_data
[Q_DATA_DST
].colorspace
;
728 struct vpe_fmt
*fmt
= ctx
->q_data
[Q_DATA_DST
].fmt
;
731 if (clrspc
== V4L2_COLORSPACE_SRGB
)
732 val
|= VPE_RGB_OUT_SELECT
;
733 else if (fmt
->fourcc
== V4L2_PIX_FMT_NV16
)
734 val
|= VPE_COLOR_SEPARATE_422
;
737 * the source of CHR_DS and CSC is always the scaler, irrespective of
738 * whether it's used or not
740 val
|= VPE_DS_SRC_DEI_SCALER
| VPE_CSC_SRC_DEI_SCALER
;
742 if (fmt
->fourcc
!= V4L2_PIX_FMT_NV12
)
743 val
|= VPE_DS_BYPASS
;
745 mmr_adb
->out_fmt_reg
[0] = val
;
747 ctx
->load_mmrs
= true;
751 * Set the de-interlacer shadow register values
753 static void set_dei_regs(struct vpe_ctx
*ctx
)
755 struct vpe_mmr_adb
*mmr_adb
= ctx
->mmr_adb
.addr
;
756 struct vpe_q_data
*s_q_data
= &ctx
->q_data
[Q_DATA_SRC
];
757 unsigned int src_h
= s_q_data
->c_rect
.height
;
758 unsigned int src_w
= s_q_data
->c_rect
.width
;
759 u32
*dei_mmr0
= &mmr_adb
->dei_regs
[0];
760 bool deinterlace
= true;
764 * according to TRM, we should set DEI in progressive bypass mode when
765 * the input content is progressive, however, DEI is bypassed correctly
766 * for both progressive and interlace content in interlace bypass mode.
767 * It has been recommended not to use progressive bypass mode.
769 if ((!ctx
->deinterlacing
&& (s_q_data
->flags
& Q_DATA_INTERLACED
)) ||
770 !(s_q_data
->flags
& Q_DATA_INTERLACED
)) {
772 val
= VPE_DEI_INTERLACE_BYPASS
;
775 src_h
= deinterlace
? src_h
* 2 : src_h
;
777 val
|= (src_h
<< VPE_DEI_HEIGHT_SHIFT
) |
778 (src_w
<< VPE_DEI_WIDTH_SHIFT
) |
783 ctx
->load_mmrs
= true;
786 static void set_dei_shadow_registers(struct vpe_ctx
*ctx
)
788 struct vpe_mmr_adb
*mmr_adb
= ctx
->mmr_adb
.addr
;
789 u32
*dei_mmr
= &mmr_adb
->dei_regs
[0];
790 const struct vpe_dei_regs
*cur
= &dei_regs
;
792 dei_mmr
[2] = cur
->mdt_spacial_freq_thr_reg
;
793 dei_mmr
[3] = cur
->edi_config_reg
;
794 dei_mmr
[4] = cur
->edi_lut_reg0
;
795 dei_mmr
[5] = cur
->edi_lut_reg1
;
796 dei_mmr
[6] = cur
->edi_lut_reg2
;
797 dei_mmr
[7] = cur
->edi_lut_reg3
;
799 ctx
->load_mmrs
= true;
803 * Set the shadow registers whose values are modified when either the
804 * source or destination format is changed.
806 static int set_srcdst_params(struct vpe_ctx
*ctx
)
808 struct vpe_q_data
*s_q_data
= &ctx
->q_data
[Q_DATA_SRC
];
809 struct vpe_q_data
*d_q_data
= &ctx
->q_data
[Q_DATA_DST
];
810 struct vpe_mmr_adb
*mmr_adb
= ctx
->mmr_adb
.addr
;
811 unsigned int src_w
= s_q_data
->c_rect
.width
;
812 unsigned int src_h
= s_q_data
->c_rect
.height
;
813 unsigned int dst_w
= d_q_data
->c_rect
.width
;
814 unsigned int dst_h
= d_q_data
->c_rect
.height
;
819 ctx
->field
= V4L2_FIELD_TOP
;
821 if ((s_q_data
->flags
& Q_DATA_INTERLACED
) &&
822 !(d_q_data
->flags
& Q_DATA_INTERLACED
)) {
824 const struct vpdma_data_format
*mv
=
825 &vpdma_misc_fmts
[VPDMA_DATA_FMT_MV
];
828 * we make sure that the source image has a 16 byte aligned
829 * stride, we need to do the same for the motion vector buffer
830 * by aligning it's stride to the next 16 byte boundry. this
831 * extra space will not be used by the de-interlacer, but will
832 * ensure that vpdma operates correctly
834 bytes_per_line
= ALIGN((s_q_data
->width
* mv
->depth
) >> 3,
836 mv_buf_size
= bytes_per_line
* s_q_data
->height
;
838 ctx
->deinterlacing
= true;
841 ctx
->deinterlacing
= false;
847 ret
= realloc_mv_buffers(ctx
, mv_buf_size
);
851 set_cfg_and_line_modes(ctx
);
854 csc_set_coeff(ctx
->dev
->csc
, &mmr_adb
->csc_regs
[0],
855 s_q_data
->colorspace
, d_q_data
->colorspace
);
857 sc_set_hs_coeffs(ctx
->dev
->sc
, ctx
->sc_coeff_h
.addr
, src_w
, dst_w
);
858 sc_set_vs_coeffs(ctx
->dev
->sc
, ctx
->sc_coeff_v
.addr
, src_h
, dst_h
);
860 sc_config_scaler(ctx
->dev
->sc
, &mmr_adb
->sc_regs0
[0],
861 &mmr_adb
->sc_regs8
[0], &mmr_adb
->sc_regs17
[0],
862 src_w
, src_h
, dst_w
, dst_h
);
868 * Return the vpe_ctx structure for a given struct file
870 static struct vpe_ctx
*file2ctx(struct file
*file
)
872 return container_of(file
->private_data
, struct vpe_ctx
, fh
);
880 * job_ready() - check whether an instance is ready to be scheduled to run
882 static int job_ready(void *priv
)
884 struct vpe_ctx
*ctx
= priv
;
885 int needed
= ctx
->bufs_per_job
;
887 if (ctx
->deinterlacing
&& ctx
->src_vbs
[2] == NULL
)
888 needed
+= 2; /* need additional two most recent fields */
890 if (v4l2_m2m_num_src_bufs_ready(ctx
->fh
.m2m_ctx
) < needed
)
893 if (v4l2_m2m_num_dst_bufs_ready(ctx
->fh
.m2m_ctx
) < needed
)
899 static void job_abort(void *priv
)
901 struct vpe_ctx
*ctx
= priv
;
903 /* Will cancel the transaction in the next interrupt handler */
908 * Lock access to the device
910 static void vpe_lock(void *priv
)
912 struct vpe_ctx
*ctx
= priv
;
913 struct vpe_dev
*dev
= ctx
->dev
;
914 mutex_lock(&dev
->dev_mutex
);
917 static void vpe_unlock(void *priv
)
919 struct vpe_ctx
*ctx
= priv
;
920 struct vpe_dev
*dev
= ctx
->dev
;
921 mutex_unlock(&dev
->dev_mutex
);
924 static void vpe_dump_regs(struct vpe_dev
*dev
)
926 #define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r))
928 vpe_dbg(dev
, "VPE Registers:\n");
932 DUMPREG(INT0_STATUS0_RAW
);
933 DUMPREG(INT0_STATUS0
);
934 DUMPREG(INT0_ENABLE0
);
935 DUMPREG(INT0_STATUS1_RAW
);
936 DUMPREG(INT0_STATUS1
);
937 DUMPREG(INT0_ENABLE1
);
940 DUMPREG(CLK_FORMAT_SELECT
);
941 DUMPREG(CLK_RANGE_MAP
);
966 DUMPREG(DEI_FRAME_SIZE
);
968 DUMPREG(MDT_SF_THRESHOLD
);
970 DUMPREG(DEI_EDI_LUT_R0
);
971 DUMPREG(DEI_EDI_LUT_R1
);
972 DUMPREG(DEI_EDI_LUT_R2
);
973 DUMPREG(DEI_EDI_LUT_R3
);
974 DUMPREG(DEI_FMD_WINDOW_R0
);
975 DUMPREG(DEI_FMD_WINDOW_R1
);
976 DUMPREG(DEI_FMD_CONTROL_R0
);
977 DUMPREG(DEI_FMD_CONTROL_R1
);
978 DUMPREG(DEI_FMD_STATUS_R0
);
979 DUMPREG(DEI_FMD_STATUS_R1
);
980 DUMPREG(DEI_FMD_STATUS_R2
);
983 sc_dump_regs(dev
->sc
);
984 csc_dump_regs(dev
->csc
);
987 static void add_out_dtd(struct vpe_ctx
*ctx
, int port
)
989 struct vpe_q_data
*q_data
= &ctx
->q_data
[Q_DATA_DST
];
990 const struct vpe_port_data
*p_data
= &port_data
[port
];
991 struct vb2_buffer
*vb
= ctx
->dst_vb
;
992 struct vpe_fmt
*fmt
= q_data
->fmt
;
993 const struct vpdma_data_format
*vpdma_fmt
;
994 int mv_buf_selector
= !ctx
->src_mv_buf_selector
;
998 if (port
== VPE_PORT_MV_OUT
) {
999 vpdma_fmt
= &vpdma_misc_fmts
[VPDMA_DATA_FMT_MV
];
1000 dma_addr
= ctx
->mv_buf_dma
[mv_buf_selector
];
1002 /* to incorporate interleaved formats */
1003 int plane
= fmt
->coplanar
? p_data
->vb_part
: 0;
1005 vpdma_fmt
= fmt
->vpdma_fmt
[plane
];
1006 dma_addr
= vb2_dma_contig_plane_dma_addr(vb
, plane
);
1009 "acquiring output buffer(%d) dma_addr failed\n",
1015 if (q_data
->flags
& Q_DATA_FRAME_1D
)
1016 flags
|= VPDMA_DATA_FRAME_1D
;
1017 if (q_data
->flags
& Q_DATA_MODE_TILED
)
1018 flags
|= VPDMA_DATA_MODE_TILED
;
1020 vpdma_add_out_dtd(&ctx
->desc_list
, q_data
->width
, &q_data
->c_rect
,
1021 vpdma_fmt
, dma_addr
, p_data
->channel
, flags
);
1024 static void add_in_dtd(struct vpe_ctx
*ctx
, int port
)
1026 struct vpe_q_data
*q_data
= &ctx
->q_data
[Q_DATA_SRC
];
1027 const struct vpe_port_data
*p_data
= &port_data
[port
];
1028 struct vb2_buffer
*vb
= ctx
->src_vbs
[p_data
->vb_index
];
1029 struct vpe_fmt
*fmt
= q_data
->fmt
;
1030 const struct vpdma_data_format
*vpdma_fmt
;
1031 int mv_buf_selector
= ctx
->src_mv_buf_selector
;
1032 int field
= vb
->v4l2_buf
.field
== V4L2_FIELD_BOTTOM
;
1033 int frame_width
, frame_height
;
1034 dma_addr_t dma_addr
;
1037 if (port
== VPE_PORT_MV_IN
) {
1038 vpdma_fmt
= &vpdma_misc_fmts
[VPDMA_DATA_FMT_MV
];
1039 dma_addr
= ctx
->mv_buf_dma
[mv_buf_selector
];
1041 /* to incorporate interleaved formats */
1042 int plane
= fmt
->coplanar
? p_data
->vb_part
: 0;
1044 vpdma_fmt
= fmt
->vpdma_fmt
[plane
];
1046 dma_addr
= vb2_dma_contig_plane_dma_addr(vb
, plane
);
1049 "acquiring input buffer(%d) dma_addr failed\n",
1055 if (q_data
->flags
& Q_DATA_FRAME_1D
)
1056 flags
|= VPDMA_DATA_FRAME_1D
;
1057 if (q_data
->flags
& Q_DATA_MODE_TILED
)
1058 flags
|= VPDMA_DATA_MODE_TILED
;
1060 frame_width
= q_data
->c_rect
.width
;
1061 frame_height
= q_data
->c_rect
.height
;
1063 if (p_data
->vb_part
&& fmt
->fourcc
== V4L2_PIX_FMT_NV12
)
1066 vpdma_add_in_dtd(&ctx
->desc_list
, q_data
->width
, &q_data
->c_rect
,
1067 vpdma_fmt
, dma_addr
, p_data
->channel
, field
, flags
, frame_width
,
1068 frame_height
, 0, 0);
1072 * Enable the expected IRQ sources
1074 static void enable_irqs(struct vpe_ctx
*ctx
)
1076 write_reg(ctx
->dev
, VPE_INT0_ENABLE0_SET
, VPE_INT0_LIST0_COMPLETE
);
1077 write_reg(ctx
->dev
, VPE_INT0_ENABLE1_SET
, VPE_DEI_ERROR_INT
|
1078 VPE_DS1_UV_ERROR_INT
);
1080 vpdma_enable_list_complete_irq(ctx
->dev
->vpdma
, 0, true);
1083 static void disable_irqs(struct vpe_ctx
*ctx
)
1085 write_reg(ctx
->dev
, VPE_INT0_ENABLE0_CLR
, 0xffffffff);
1086 write_reg(ctx
->dev
, VPE_INT0_ENABLE1_CLR
, 0xffffffff);
1088 vpdma_enable_list_complete_irq(ctx
->dev
->vpdma
, 0, false);
1091 /* device_run() - prepares and starts the device
1093 * This function is only called when both the source and destination
1094 * buffers are in place.
1096 static void device_run(void *priv
)
1098 struct vpe_ctx
*ctx
= priv
;
1099 struct sc_data
*sc
= ctx
->dev
->sc
;
1100 struct vpe_q_data
*d_q_data
= &ctx
->q_data
[Q_DATA_DST
];
1102 if (ctx
->deinterlacing
&& ctx
->src_vbs
[2] == NULL
) {
1103 ctx
->src_vbs
[2] = v4l2_m2m_src_buf_remove(ctx
->fh
.m2m_ctx
);
1104 WARN_ON(ctx
->src_vbs
[2] == NULL
);
1105 ctx
->src_vbs
[1] = v4l2_m2m_src_buf_remove(ctx
->fh
.m2m_ctx
);
1106 WARN_ON(ctx
->src_vbs
[1] == NULL
);
1109 ctx
->src_vbs
[0] = v4l2_m2m_src_buf_remove(ctx
->fh
.m2m_ctx
);
1110 WARN_ON(ctx
->src_vbs
[0] == NULL
);
1111 ctx
->dst_vb
= v4l2_m2m_dst_buf_remove(ctx
->fh
.m2m_ctx
);
1112 WARN_ON(ctx
->dst_vb
== NULL
);
1114 /* config descriptors */
1115 if (ctx
->dev
->loaded_mmrs
!= ctx
->mmr_adb
.dma_addr
|| ctx
->load_mmrs
) {
1116 vpdma_map_desc_buf(ctx
->dev
->vpdma
, &ctx
->mmr_adb
);
1117 vpdma_add_cfd_adb(&ctx
->desc_list
, CFD_MMR_CLIENT
, &ctx
->mmr_adb
);
1118 ctx
->dev
->loaded_mmrs
= ctx
->mmr_adb
.dma_addr
;
1119 ctx
->load_mmrs
= false;
1122 if (sc
->loaded_coeff_h
!= ctx
->sc_coeff_h
.dma_addr
||
1124 vpdma_map_desc_buf(ctx
->dev
->vpdma
, &ctx
->sc_coeff_h
);
1125 vpdma_add_cfd_block(&ctx
->desc_list
, CFD_SC_CLIENT
,
1126 &ctx
->sc_coeff_h
, 0);
1128 sc
->loaded_coeff_h
= ctx
->sc_coeff_h
.dma_addr
;
1129 sc
->load_coeff_h
= false;
1132 if (sc
->loaded_coeff_v
!= ctx
->sc_coeff_v
.dma_addr
||
1134 vpdma_map_desc_buf(ctx
->dev
->vpdma
, &ctx
->sc_coeff_v
);
1135 vpdma_add_cfd_block(&ctx
->desc_list
, CFD_SC_CLIENT
,
1136 &ctx
->sc_coeff_v
, SC_COEF_SRAM_SIZE
>> 4);
1138 sc
->loaded_coeff_v
= ctx
->sc_coeff_v
.dma_addr
;
1139 sc
->load_coeff_v
= false;
1142 /* output data descriptors */
1143 if (ctx
->deinterlacing
)
1144 add_out_dtd(ctx
, VPE_PORT_MV_OUT
);
1146 if (d_q_data
->colorspace
== V4L2_COLORSPACE_SRGB
) {
1147 add_out_dtd(ctx
, VPE_PORT_RGB_OUT
);
1149 add_out_dtd(ctx
, VPE_PORT_LUMA_OUT
);
1150 if (d_q_data
->fmt
->coplanar
)
1151 add_out_dtd(ctx
, VPE_PORT_CHROMA_OUT
);
1154 /* input data descriptors */
1155 if (ctx
->deinterlacing
) {
1156 add_in_dtd(ctx
, VPE_PORT_LUMA3_IN
);
1157 add_in_dtd(ctx
, VPE_PORT_CHROMA3_IN
);
1159 add_in_dtd(ctx
, VPE_PORT_LUMA2_IN
);
1160 add_in_dtd(ctx
, VPE_PORT_CHROMA2_IN
);
1163 add_in_dtd(ctx
, VPE_PORT_LUMA1_IN
);
1164 add_in_dtd(ctx
, VPE_PORT_CHROMA1_IN
);
1166 if (ctx
->deinterlacing
)
1167 add_in_dtd(ctx
, VPE_PORT_MV_IN
);
1169 /* sync on channel control descriptors for input ports */
1170 vpdma_add_sync_on_channel_ctd(&ctx
->desc_list
, VPE_CHAN_LUMA1_IN
);
1171 vpdma_add_sync_on_channel_ctd(&ctx
->desc_list
, VPE_CHAN_CHROMA1_IN
);
1173 if (ctx
->deinterlacing
) {
1174 vpdma_add_sync_on_channel_ctd(&ctx
->desc_list
,
1176 vpdma_add_sync_on_channel_ctd(&ctx
->desc_list
,
1177 VPE_CHAN_CHROMA2_IN
);
1179 vpdma_add_sync_on_channel_ctd(&ctx
->desc_list
,
1181 vpdma_add_sync_on_channel_ctd(&ctx
->desc_list
,
1182 VPE_CHAN_CHROMA3_IN
);
1184 vpdma_add_sync_on_channel_ctd(&ctx
->desc_list
, VPE_CHAN_MV_IN
);
1187 /* sync on channel control descriptors for output ports */
1188 if (d_q_data
->colorspace
== V4L2_COLORSPACE_SRGB
) {
1189 vpdma_add_sync_on_channel_ctd(&ctx
->desc_list
,
1192 vpdma_add_sync_on_channel_ctd(&ctx
->desc_list
,
1194 if (d_q_data
->fmt
->coplanar
)
1195 vpdma_add_sync_on_channel_ctd(&ctx
->desc_list
,
1196 VPE_CHAN_CHROMA_OUT
);
1199 if (ctx
->deinterlacing
)
1200 vpdma_add_sync_on_channel_ctd(&ctx
->desc_list
, VPE_CHAN_MV_OUT
);
1204 vpdma_map_desc_buf(ctx
->dev
->vpdma
, &ctx
->desc_list
.buf
);
1205 vpdma_submit_descs(ctx
->dev
->vpdma
, &ctx
->desc_list
);
1208 static void dei_error(struct vpe_ctx
*ctx
)
1210 dev_warn(ctx
->dev
->v4l2_dev
.dev
,
1211 "received DEI error interrupt\n");
1214 static void ds1_uv_error(struct vpe_ctx
*ctx
)
1216 dev_warn(ctx
->dev
->v4l2_dev
.dev
,
1217 "received downsampler error interrupt\n");
1220 static irqreturn_t
vpe_irq(int irq_vpe
, void *data
)
1222 struct vpe_dev
*dev
= (struct vpe_dev
*)data
;
1223 struct vpe_ctx
*ctx
;
1224 struct vpe_q_data
*d_q_data
;
1225 struct vb2_buffer
*s_vb
, *d_vb
;
1226 struct v4l2_buffer
*s_buf
, *d_buf
;
1227 unsigned long flags
;
1230 irqst0
= read_reg(dev
, VPE_INT0_STATUS0
);
1232 write_reg(dev
, VPE_INT0_STATUS0_CLR
, irqst0
);
1233 vpe_dbg(dev
, "INT0_STATUS0 = 0x%08x\n", irqst0
);
1236 irqst1
= read_reg(dev
, VPE_INT0_STATUS1
);
1238 write_reg(dev
, VPE_INT0_STATUS1_CLR
, irqst1
);
1239 vpe_dbg(dev
, "INT0_STATUS1 = 0x%08x\n", irqst1
);
1242 ctx
= v4l2_m2m_get_curr_priv(dev
->m2m_dev
);
1244 vpe_err(dev
, "instance released before end of transaction\n");
1249 if (irqst1
& VPE_DEI_ERROR_INT
) {
1250 irqst1
&= ~VPE_DEI_ERROR_INT
;
1253 if (irqst1
& VPE_DS1_UV_ERROR_INT
) {
1254 irqst1
&= ~VPE_DS1_UV_ERROR_INT
;
1260 if (irqst0
& VPE_INT0_LIST0_COMPLETE
)
1261 vpdma_clear_list_stat(ctx
->dev
->vpdma
);
1263 irqst0
&= ~(VPE_INT0_LIST0_COMPLETE
);
1266 if (irqst0
| irqst1
) {
1267 dev_warn(dev
->v4l2_dev
.dev
, "Unexpected interrupt: "
1268 "INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n",
1274 vpdma_unmap_desc_buf(dev
->vpdma
, &ctx
->desc_list
.buf
);
1275 vpdma_unmap_desc_buf(dev
->vpdma
, &ctx
->mmr_adb
);
1276 vpdma_unmap_desc_buf(dev
->vpdma
, &ctx
->sc_coeff_h
);
1277 vpdma_unmap_desc_buf(dev
->vpdma
, &ctx
->sc_coeff_v
);
1279 vpdma_reset_desc_list(&ctx
->desc_list
);
1281 /* the previous dst mv buffer becomes the next src mv buffer */
1282 ctx
->src_mv_buf_selector
= !ctx
->src_mv_buf_selector
;
1287 s_vb
= ctx
->src_vbs
[0];
1289 s_buf
= &s_vb
->v4l2_buf
;
1290 d_buf
= &d_vb
->v4l2_buf
;
1292 d_buf
->flags
= s_buf
->flags
;
1294 d_buf
->timestamp
= s_buf
->timestamp
;
1295 if (s_buf
->flags
& V4L2_BUF_FLAG_TIMECODE
)
1296 d_buf
->timecode
= s_buf
->timecode
;
1298 d_buf
->sequence
= ctx
->sequence
;
1300 d_q_data
= &ctx
->q_data
[Q_DATA_DST
];
1301 if (d_q_data
->flags
& Q_DATA_INTERLACED
) {
1302 d_buf
->field
= ctx
->field
;
1303 if (ctx
->field
== V4L2_FIELD_BOTTOM
) {
1305 ctx
->field
= V4L2_FIELD_TOP
;
1307 WARN_ON(ctx
->field
!= V4L2_FIELD_TOP
);
1308 ctx
->field
= V4L2_FIELD_BOTTOM
;
1311 d_buf
->field
= V4L2_FIELD_NONE
;
1315 if (ctx
->deinterlacing
)
1316 s_vb
= ctx
->src_vbs
[2];
1318 spin_lock_irqsave(&dev
->lock
, flags
);
1319 v4l2_m2m_buf_done(s_vb
, VB2_BUF_STATE_DONE
);
1320 v4l2_m2m_buf_done(d_vb
, VB2_BUF_STATE_DONE
);
1321 spin_unlock_irqrestore(&dev
->lock
, flags
);
1323 if (ctx
->deinterlacing
) {
1324 ctx
->src_vbs
[2] = ctx
->src_vbs
[1];
1325 ctx
->src_vbs
[1] = ctx
->src_vbs
[0];
1328 ctx
->bufs_completed
++;
1329 if (ctx
->bufs_completed
< ctx
->bufs_per_job
) {
1335 vpe_dbg(ctx
->dev
, "finishing transaction\n");
1336 ctx
->bufs_completed
= 0;
1337 v4l2_m2m_job_finish(dev
->m2m_dev
, ctx
->fh
.m2m_ctx
);
1345 static int vpe_querycap(struct file
*file
, void *priv
,
1346 struct v4l2_capability
*cap
)
1348 strncpy(cap
->driver
, VPE_MODULE_NAME
, sizeof(cap
->driver
) - 1);
1349 strncpy(cap
->card
, VPE_MODULE_NAME
, sizeof(cap
->card
) - 1);
1350 snprintf(cap
->bus_info
, sizeof(cap
->bus_info
), "platform:%s",
1352 cap
->device_caps
= V4L2_CAP_VIDEO_M2M_MPLANE
| V4L2_CAP_STREAMING
;
1353 cap
->capabilities
= cap
->device_caps
| V4L2_CAP_DEVICE_CAPS
;
1357 static int __enum_fmt(struct v4l2_fmtdesc
*f
, u32 type
)
1360 struct vpe_fmt
*fmt
= NULL
;
1363 for (i
= 0; i
< ARRAY_SIZE(vpe_formats
); ++i
) {
1364 if (vpe_formats
[i
].types
& type
) {
1365 if (index
== f
->index
) {
1366 fmt
= &vpe_formats
[i
];
1376 strncpy(f
->description
, fmt
->name
, sizeof(f
->description
) - 1);
1377 f
->pixelformat
= fmt
->fourcc
;
1381 static int vpe_enum_fmt(struct file
*file
, void *priv
,
1382 struct v4l2_fmtdesc
*f
)
1384 if (V4L2_TYPE_IS_OUTPUT(f
->type
))
1385 return __enum_fmt(f
, VPE_FMT_TYPE_OUTPUT
);
1387 return __enum_fmt(f
, VPE_FMT_TYPE_CAPTURE
);
1390 static int vpe_g_fmt(struct file
*file
, void *priv
, struct v4l2_format
*f
)
1392 struct v4l2_pix_format_mplane
*pix
= &f
->fmt
.pix_mp
;
1393 struct vpe_ctx
*ctx
= file2ctx(file
);
1394 struct vb2_queue
*vq
;
1395 struct vpe_q_data
*q_data
;
1398 vq
= v4l2_m2m_get_vq(ctx
->fh
.m2m_ctx
, f
->type
);
1402 q_data
= get_q_data(ctx
, f
->type
);
1404 pix
->width
= q_data
->width
;
1405 pix
->height
= q_data
->height
;
1406 pix
->pixelformat
= q_data
->fmt
->fourcc
;
1407 pix
->field
= q_data
->field
;
1409 if (V4L2_TYPE_IS_OUTPUT(f
->type
)) {
1410 pix
->colorspace
= q_data
->colorspace
;
1412 struct vpe_q_data
*s_q_data
;
1414 /* get colorspace from the source queue */
1415 s_q_data
= get_q_data(ctx
, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
);
1417 pix
->colorspace
= s_q_data
->colorspace
;
1420 pix
->num_planes
= q_data
->fmt
->coplanar
? 2 : 1;
1422 for (i
= 0; i
< pix
->num_planes
; i
++) {
1423 pix
->plane_fmt
[i
].bytesperline
= q_data
->bytesperline
[i
];
1424 pix
->plane_fmt
[i
].sizeimage
= q_data
->sizeimage
[i
];
1430 static int __vpe_try_fmt(struct vpe_ctx
*ctx
, struct v4l2_format
*f
,
1431 struct vpe_fmt
*fmt
, int type
)
1433 struct v4l2_pix_format_mplane
*pix
= &f
->fmt
.pix_mp
;
1434 struct v4l2_plane_pix_format
*plane_fmt
;
1435 unsigned int w_align
;
1436 int i
, depth
, depth_bytes
;
1438 if (!fmt
|| !(fmt
->types
& type
)) {
1439 vpe_err(ctx
->dev
, "Fourcc format (0x%08x) invalid.\n",
1444 if (pix
->field
!= V4L2_FIELD_NONE
&& pix
->field
!= V4L2_FIELD_ALTERNATE
)
1445 pix
->field
= V4L2_FIELD_NONE
;
1447 depth
= fmt
->vpdma_fmt
[VPE_LUMA
]->depth
;
1450 * the line stride should 16 byte aligned for VPDMA to work, based on
1451 * the bytes per pixel, figure out how much the width should be aligned
1452 * to make sure line stride is 16 byte aligned
1454 depth_bytes
= depth
>> 3;
1456 if (depth_bytes
== 3)
1458 * if bpp is 3(as in some RGB formats), the pixel width doesn't
1459 * really help in ensuring line stride is 16 byte aligned
1464 * for the remainder bpp(4, 2 and 1), the pixel width alignment
1465 * can ensure a line stride alignment of 16 bytes. For example,
1466 * if bpp is 2, then the line stride can be 16 byte aligned if
1467 * the width is 8 byte aligned
1469 w_align
= order_base_2(VPDMA_DESC_ALIGN
/ depth_bytes
);
1471 v4l_bound_align_image(&pix
->width
, MIN_W
, MAX_W
, w_align
,
1472 &pix
->height
, MIN_H
, MAX_H
, H_ALIGN
,
1475 pix
->num_planes
= fmt
->coplanar
? 2 : 1;
1476 pix
->pixelformat
= fmt
->fourcc
;
1478 if (!pix
->colorspace
) {
1479 if (fmt
->fourcc
== V4L2_PIX_FMT_RGB24
||
1480 fmt
->fourcc
== V4L2_PIX_FMT_BGR24
||
1481 fmt
->fourcc
== V4L2_PIX_FMT_RGB32
||
1482 fmt
->fourcc
== V4L2_PIX_FMT_BGR32
) {
1483 pix
->colorspace
= V4L2_COLORSPACE_SRGB
;
1485 if (pix
->height
> 1280) /* HD */
1486 pix
->colorspace
= V4L2_COLORSPACE_REC709
;
1488 pix
->colorspace
= V4L2_COLORSPACE_SMPTE170M
;
1492 memset(pix
->reserved
, 0, sizeof(pix
->reserved
));
1493 for (i
= 0; i
< pix
->num_planes
; i
++) {
1494 plane_fmt
= &pix
->plane_fmt
[i
];
1495 depth
= fmt
->vpdma_fmt
[i
]->depth
;
1498 plane_fmt
->bytesperline
= (pix
->width
* depth
) >> 3;
1500 plane_fmt
->bytesperline
= pix
->width
;
1502 plane_fmt
->sizeimage
=
1503 (pix
->height
* pix
->width
* depth
) >> 3;
1505 memset(plane_fmt
->reserved
, 0, sizeof(plane_fmt
->reserved
));
1511 static int vpe_try_fmt(struct file
*file
, void *priv
, struct v4l2_format
*f
)
1513 struct vpe_ctx
*ctx
= file2ctx(file
);
1514 struct vpe_fmt
*fmt
= find_format(f
);
1516 if (V4L2_TYPE_IS_OUTPUT(f
->type
))
1517 return __vpe_try_fmt(ctx
, f
, fmt
, VPE_FMT_TYPE_OUTPUT
);
1519 return __vpe_try_fmt(ctx
, f
, fmt
, VPE_FMT_TYPE_CAPTURE
);
1522 static int __vpe_s_fmt(struct vpe_ctx
*ctx
, struct v4l2_format
*f
)
1524 struct v4l2_pix_format_mplane
*pix
= &f
->fmt
.pix_mp
;
1525 struct v4l2_plane_pix_format
*plane_fmt
;
1526 struct vpe_q_data
*q_data
;
1527 struct vb2_queue
*vq
;
1530 vq
= v4l2_m2m_get_vq(ctx
->fh
.m2m_ctx
, f
->type
);
1534 if (vb2_is_busy(vq
)) {
1535 vpe_err(ctx
->dev
, "queue busy\n");
1539 q_data
= get_q_data(ctx
, f
->type
);
1543 q_data
->fmt
= find_format(f
);
1544 q_data
->width
= pix
->width
;
1545 q_data
->height
= pix
->height
;
1546 q_data
->colorspace
= pix
->colorspace
;
1547 q_data
->field
= pix
->field
;
1549 for (i
= 0; i
< pix
->num_planes
; i
++) {
1550 plane_fmt
= &pix
->plane_fmt
[i
];
1552 q_data
->bytesperline
[i
] = plane_fmt
->bytesperline
;
1553 q_data
->sizeimage
[i
] = plane_fmt
->sizeimage
;
1556 q_data
->c_rect
.left
= 0;
1557 q_data
->c_rect
.top
= 0;
1558 q_data
->c_rect
.width
= q_data
->width
;
1559 q_data
->c_rect
.height
= q_data
->height
;
1561 if (q_data
->field
== V4L2_FIELD_ALTERNATE
)
1562 q_data
->flags
|= Q_DATA_INTERLACED
;
1564 q_data
->flags
&= ~Q_DATA_INTERLACED
;
1566 vpe_dbg(ctx
->dev
, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d",
1567 f
->type
, q_data
->width
, q_data
->height
, q_data
->fmt
->fourcc
,
1568 q_data
->bytesperline
[VPE_LUMA
]);
1569 if (q_data
->fmt
->coplanar
)
1570 vpe_dbg(ctx
->dev
, " bpl_uv %d\n",
1571 q_data
->bytesperline
[VPE_CHROMA
]);
1576 static int vpe_s_fmt(struct file
*file
, void *priv
, struct v4l2_format
*f
)
1579 struct vpe_ctx
*ctx
= file2ctx(file
);
1581 ret
= vpe_try_fmt(file
, priv
, f
);
1585 ret
= __vpe_s_fmt(ctx
, f
);
1589 if (V4L2_TYPE_IS_OUTPUT(f
->type
))
1590 set_src_registers(ctx
);
1592 set_dst_registers(ctx
);
1594 return set_srcdst_params(ctx
);
1597 static int __vpe_try_selection(struct vpe_ctx
*ctx
, struct v4l2_selection
*s
)
1599 struct vpe_q_data
*q_data
;
1601 if ((s
->type
!= V4L2_BUF_TYPE_VIDEO_CAPTURE
) &&
1602 (s
->type
!= V4L2_BUF_TYPE_VIDEO_OUTPUT
))
1605 q_data
= get_q_data(ctx
, s
->type
);
1609 switch (s
->target
) {
1610 case V4L2_SEL_TGT_COMPOSE
:
1612 * COMPOSE target is only valid for capture buffer type, return
1613 * error for output buffer type
1615 if (s
->type
== V4L2_BUF_TYPE_VIDEO_OUTPUT
)
1618 case V4L2_SEL_TGT_CROP
:
1620 * CROP target is only valid for output buffer type, return
1621 * error for capture buffer type
1623 if (s
->type
== V4L2_BUF_TYPE_VIDEO_CAPTURE
)
1627 * bound and default crop/compose targets are invalid targets to
1634 if (s
->r
.top
< 0 || s
->r
.left
< 0) {
1635 vpe_err(ctx
->dev
, "negative values for top and left\n");
1636 s
->r
.top
= s
->r
.left
= 0;
1639 v4l_bound_align_image(&s
->r
.width
, MIN_W
, q_data
->width
, 1,
1640 &s
->r
.height
, MIN_H
, q_data
->height
, H_ALIGN
, S_ALIGN
);
1642 /* adjust left/top if cropping rectangle is out of bounds */
1643 if (s
->r
.left
+ s
->r
.width
> q_data
->width
)
1644 s
->r
.left
= q_data
->width
- s
->r
.width
;
1645 if (s
->r
.top
+ s
->r
.height
> q_data
->height
)
1646 s
->r
.top
= q_data
->height
- s
->r
.height
;
1651 static int vpe_g_selection(struct file
*file
, void *fh
,
1652 struct v4l2_selection
*s
)
1654 struct vpe_ctx
*ctx
= file2ctx(file
);
1655 struct vpe_q_data
*q_data
;
1656 bool use_c_rect
= false;
1658 if ((s
->type
!= V4L2_BUF_TYPE_VIDEO_CAPTURE
) &&
1659 (s
->type
!= V4L2_BUF_TYPE_VIDEO_OUTPUT
))
1662 q_data
= get_q_data(ctx
, s
->type
);
1666 switch (s
->target
) {
1667 case V4L2_SEL_TGT_COMPOSE_DEFAULT
:
1668 case V4L2_SEL_TGT_COMPOSE_BOUNDS
:
1669 if (s
->type
== V4L2_BUF_TYPE_VIDEO_OUTPUT
)
1672 case V4L2_SEL_TGT_CROP_BOUNDS
:
1673 case V4L2_SEL_TGT_CROP_DEFAULT
:
1674 if (s
->type
== V4L2_BUF_TYPE_VIDEO_CAPTURE
)
1677 case V4L2_SEL_TGT_COMPOSE
:
1678 if (s
->type
== V4L2_BUF_TYPE_VIDEO_OUTPUT
)
1682 case V4L2_SEL_TGT_CROP
:
1683 if (s
->type
== V4L2_BUF_TYPE_VIDEO_CAPTURE
)
1693 * for CROP/COMPOSE target type, return c_rect params from the
1694 * respective buffer type
1696 s
->r
= q_data
->c_rect
;
1699 * for DEFAULT/BOUNDS target type, return width and height from
1700 * S_FMT of the respective buffer type
1704 s
->r
.width
= q_data
->width
;
1705 s
->r
.height
= q_data
->height
;
1712 static int vpe_s_selection(struct file
*file
, void *fh
,
1713 struct v4l2_selection
*s
)
1715 struct vpe_ctx
*ctx
= file2ctx(file
);
1716 struct vpe_q_data
*q_data
;
1717 struct v4l2_selection sel
= *s
;
1720 ret
= __vpe_try_selection(ctx
, &sel
);
1724 q_data
= get_q_data(ctx
, sel
.type
);
1728 if ((q_data
->c_rect
.left
== sel
.r
.left
) &&
1729 (q_data
->c_rect
.top
== sel
.r
.top
) &&
1730 (q_data
->c_rect
.width
== sel
.r
.width
) &&
1731 (q_data
->c_rect
.height
== sel
.r
.height
)) {
1733 "requested crop/compose values are already set\n");
1737 q_data
->c_rect
= sel
.r
;
1739 return set_srcdst_params(ctx
);
1743 * defines number of buffers/frames a context can process with VPE before
1744 * switching to a different context. default value is 1 buffer per context
1746 #define V4L2_CID_VPE_BUFS_PER_JOB (V4L2_CID_USER_TI_VPE_BASE + 0)
1748 static int vpe_s_ctrl(struct v4l2_ctrl
*ctrl
)
1750 struct vpe_ctx
*ctx
=
1751 container_of(ctrl
->handler
, struct vpe_ctx
, hdl
);
1754 case V4L2_CID_VPE_BUFS_PER_JOB
:
1755 ctx
->bufs_per_job
= ctrl
->val
;
1759 vpe_err(ctx
->dev
, "Invalid control\n");
1766 static const struct v4l2_ctrl_ops vpe_ctrl_ops
= {
1767 .s_ctrl
= vpe_s_ctrl
,
1770 static const struct v4l2_ioctl_ops vpe_ioctl_ops
= {
1771 .vidioc_querycap
= vpe_querycap
,
1773 .vidioc_enum_fmt_vid_cap_mplane
= vpe_enum_fmt
,
1774 .vidioc_g_fmt_vid_cap_mplane
= vpe_g_fmt
,
1775 .vidioc_try_fmt_vid_cap_mplane
= vpe_try_fmt
,
1776 .vidioc_s_fmt_vid_cap_mplane
= vpe_s_fmt
,
1778 .vidioc_enum_fmt_vid_out_mplane
= vpe_enum_fmt
,
1779 .vidioc_g_fmt_vid_out_mplane
= vpe_g_fmt
,
1780 .vidioc_try_fmt_vid_out_mplane
= vpe_try_fmt
,
1781 .vidioc_s_fmt_vid_out_mplane
= vpe_s_fmt
,
1783 .vidioc_g_selection
= vpe_g_selection
,
1784 .vidioc_s_selection
= vpe_s_selection
,
1786 .vidioc_reqbufs
= v4l2_m2m_ioctl_reqbufs
,
1787 .vidioc_querybuf
= v4l2_m2m_ioctl_querybuf
,
1788 .vidioc_qbuf
= v4l2_m2m_ioctl_qbuf
,
1789 .vidioc_dqbuf
= v4l2_m2m_ioctl_dqbuf
,
1790 .vidioc_streamon
= v4l2_m2m_ioctl_streamon
,
1791 .vidioc_streamoff
= v4l2_m2m_ioctl_streamoff
,
1793 .vidioc_subscribe_event
= v4l2_ctrl_subscribe_event
,
1794 .vidioc_unsubscribe_event
= v4l2_event_unsubscribe
,
1800 static int vpe_queue_setup(struct vb2_queue
*vq
,
1801 const struct v4l2_format
*fmt
,
1802 unsigned int *nbuffers
, unsigned int *nplanes
,
1803 unsigned int sizes
[], void *alloc_ctxs
[])
1806 struct vpe_ctx
*ctx
= vb2_get_drv_priv(vq
);
1807 struct vpe_q_data
*q_data
;
1809 q_data
= get_q_data(ctx
, vq
->type
);
1811 *nplanes
= q_data
->fmt
->coplanar
? 2 : 1;
1813 for (i
= 0; i
< *nplanes
; i
++) {
1814 sizes
[i
] = q_data
->sizeimage
[i
];
1815 alloc_ctxs
[i
] = ctx
->dev
->alloc_ctx
;
1818 vpe_dbg(ctx
->dev
, "get %d buffer(s) of size %d", *nbuffers
,
1820 if (q_data
->fmt
->coplanar
)
1821 vpe_dbg(ctx
->dev
, " and %d\n", sizes
[VPE_CHROMA
]);
1826 static int vpe_buf_prepare(struct vb2_buffer
*vb
)
1828 struct vpe_ctx
*ctx
= vb2_get_drv_priv(vb
->vb2_queue
);
1829 struct vpe_q_data
*q_data
;
1832 vpe_dbg(ctx
->dev
, "type: %d\n", vb
->vb2_queue
->type
);
1834 q_data
= get_q_data(ctx
, vb
->vb2_queue
->type
);
1835 num_planes
= q_data
->fmt
->coplanar
? 2 : 1;
1837 if (vb
->vb2_queue
->type
== V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
) {
1838 if (!(q_data
->flags
& Q_DATA_INTERLACED
)) {
1839 vb
->v4l2_buf
.field
= V4L2_FIELD_NONE
;
1841 if (vb
->v4l2_buf
.field
!= V4L2_FIELD_TOP
&&
1842 vb
->v4l2_buf
.field
!= V4L2_FIELD_BOTTOM
)
1847 for (i
= 0; i
< num_planes
; i
++) {
1848 if (vb2_plane_size(vb
, i
) < q_data
->sizeimage
[i
]) {
1850 "data will not fit into plane (%lu < %lu)\n",
1851 vb2_plane_size(vb
, i
),
1852 (long) q_data
->sizeimage
[i
]);
1857 for (i
= 0; i
< num_planes
; i
++)
1858 vb2_set_plane_payload(vb
, i
, q_data
->sizeimage
[i
]);
1863 static void vpe_buf_queue(struct vb2_buffer
*vb
)
1865 struct vpe_ctx
*ctx
= vb2_get_drv_priv(vb
->vb2_queue
);
1867 v4l2_m2m_buf_queue(ctx
->fh
.m2m_ctx
, vb
);
1870 static int vpe_start_streaming(struct vb2_queue
*q
, unsigned int count
)
1872 /* currently we do nothing here */
1877 static void vpe_stop_streaming(struct vb2_queue
*q
)
1879 struct vpe_ctx
*ctx
= vb2_get_drv_priv(q
);
1881 vpe_dump_regs(ctx
->dev
);
1882 vpdma_dump_regs(ctx
->dev
->vpdma
);
1885 static struct vb2_ops vpe_qops
= {
1886 .queue_setup
= vpe_queue_setup
,
1887 .buf_prepare
= vpe_buf_prepare
,
1888 .buf_queue
= vpe_buf_queue
,
1889 .wait_prepare
= vb2_ops_wait_prepare
,
1890 .wait_finish
= vb2_ops_wait_finish
,
1891 .start_streaming
= vpe_start_streaming
,
1892 .stop_streaming
= vpe_stop_streaming
,
1895 static int queue_init(void *priv
, struct vb2_queue
*src_vq
,
1896 struct vb2_queue
*dst_vq
)
1898 struct vpe_ctx
*ctx
= priv
;
1899 struct vpe_dev
*dev
= ctx
->dev
;
1902 memset(src_vq
, 0, sizeof(*src_vq
));
1903 src_vq
->type
= V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
;
1904 src_vq
->io_modes
= VB2_MMAP
| VB2_DMABUF
;
1905 src_vq
->drv_priv
= ctx
;
1906 src_vq
->buf_struct_size
= sizeof(struct v4l2_m2m_buffer
);
1907 src_vq
->ops
= &vpe_qops
;
1908 src_vq
->mem_ops
= &vb2_dma_contig_memops
;
1909 src_vq
->timestamp_flags
= V4L2_BUF_FLAG_TIMESTAMP_COPY
;
1910 src_vq
->lock
= &dev
->dev_mutex
;
1912 ret
= vb2_queue_init(src_vq
);
1916 memset(dst_vq
, 0, sizeof(*dst_vq
));
1917 dst_vq
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
;
1918 dst_vq
->io_modes
= VB2_MMAP
| VB2_DMABUF
;
1919 dst_vq
->drv_priv
= ctx
;
1920 dst_vq
->buf_struct_size
= sizeof(struct v4l2_m2m_buffer
);
1921 dst_vq
->ops
= &vpe_qops
;
1922 dst_vq
->mem_ops
= &vb2_dma_contig_memops
;
1923 dst_vq
->timestamp_flags
= V4L2_BUF_FLAG_TIMESTAMP_COPY
;
1924 dst_vq
->lock
= &dev
->dev_mutex
;
1926 return vb2_queue_init(dst_vq
);
1929 static const struct v4l2_ctrl_config vpe_bufs_per_job
= {
1930 .ops
= &vpe_ctrl_ops
,
1931 .id
= V4L2_CID_VPE_BUFS_PER_JOB
,
1932 .name
= "Buffers Per Transaction",
1933 .type
= V4L2_CTRL_TYPE_INTEGER
,
1934 .def
= VPE_DEF_BUFS_PER_JOB
,
1936 .max
= VIDEO_MAX_FRAME
,
1943 static int vpe_open(struct file
*file
)
1945 struct vpe_dev
*dev
= video_drvdata(file
);
1946 struct vpe_q_data
*s_q_data
;
1947 struct v4l2_ctrl_handler
*hdl
;
1948 struct vpe_ctx
*ctx
;
1951 vpe_dbg(dev
, "vpe_open\n");
1953 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
1959 if (mutex_lock_interruptible(&dev
->dev_mutex
)) {
1964 ret
= vpdma_create_desc_list(&ctx
->desc_list
, VPE_DESC_LIST_SIZE
,
1965 VPDMA_LIST_TYPE_NORMAL
);
1969 ret
= vpdma_alloc_desc_buf(&ctx
->mmr_adb
, sizeof(struct vpe_mmr_adb
));
1971 goto free_desc_list
;
1973 ret
= vpdma_alloc_desc_buf(&ctx
->sc_coeff_h
, SC_COEF_SRAM_SIZE
);
1977 ret
= vpdma_alloc_desc_buf(&ctx
->sc_coeff_v
, SC_COEF_SRAM_SIZE
);
1983 v4l2_fh_init(&ctx
->fh
, video_devdata(file
));
1984 file
->private_data
= &ctx
->fh
;
1987 v4l2_ctrl_handler_init(hdl
, 1);
1988 v4l2_ctrl_new_custom(hdl
, &vpe_bufs_per_job
, NULL
);
1993 ctx
->fh
.ctrl_handler
= hdl
;
1994 v4l2_ctrl_handler_setup(hdl
);
1996 s_q_data
= &ctx
->q_data
[Q_DATA_SRC
];
1997 s_q_data
->fmt
= &vpe_formats
[2];
1998 s_q_data
->width
= 1920;
1999 s_q_data
->height
= 1080;
2000 s_q_data
->bytesperline
[VPE_LUMA
] = (s_q_data
->width
*
2001 s_q_data
->fmt
->vpdma_fmt
[VPE_LUMA
]->depth
) >> 3;
2002 s_q_data
->sizeimage
[VPE_LUMA
] = (s_q_data
->bytesperline
[VPE_LUMA
] *
2004 s_q_data
->colorspace
= V4L2_COLORSPACE_REC709
;
2005 s_q_data
->field
= V4L2_FIELD_NONE
;
2006 s_q_data
->c_rect
.left
= 0;
2007 s_q_data
->c_rect
.top
= 0;
2008 s_q_data
->c_rect
.width
= s_q_data
->width
;
2009 s_q_data
->c_rect
.height
= s_q_data
->height
;
2010 s_q_data
->flags
= 0;
2012 ctx
->q_data
[Q_DATA_DST
] = *s_q_data
;
2014 set_dei_shadow_registers(ctx
);
2015 set_src_registers(ctx
);
2016 set_dst_registers(ctx
);
2017 ret
= set_srcdst_params(ctx
);
2021 ctx
->fh
.m2m_ctx
= v4l2_m2m_ctx_init(dev
->m2m_dev
, ctx
, &queue_init
);
2023 if (IS_ERR(ctx
->fh
.m2m_ctx
)) {
2024 ret
= PTR_ERR(ctx
->fh
.m2m_ctx
);
2028 v4l2_fh_add(&ctx
->fh
);
2031 * for now, just report the creation of the first instance, we can later
2032 * optimize the driver to enable or disable clocks when the first
2033 * instance is created or the last instance released
2035 if (atomic_inc_return(&dev
->num_instances
) == 1)
2036 vpe_dbg(dev
, "first instance created\n");
2038 ctx
->bufs_per_job
= VPE_DEF_BUFS_PER_JOB
;
2040 ctx
->load_mmrs
= true;
2042 vpe_dbg(dev
, "created instance %p, m2m_ctx: %p\n",
2043 ctx
, ctx
->fh
.m2m_ctx
);
2045 mutex_unlock(&dev
->dev_mutex
);
2049 v4l2_ctrl_handler_free(hdl
);
2050 v4l2_fh_exit(&ctx
->fh
);
2051 vpdma_free_desc_buf(&ctx
->sc_coeff_v
);
2053 vpdma_free_desc_buf(&ctx
->sc_coeff_h
);
2055 vpdma_free_desc_buf(&ctx
->mmr_adb
);
2057 vpdma_free_desc_list(&ctx
->desc_list
);
2059 mutex_unlock(&dev
->dev_mutex
);
2065 static int vpe_release(struct file
*file
)
2067 struct vpe_dev
*dev
= video_drvdata(file
);
2068 struct vpe_ctx
*ctx
= file2ctx(file
);
2070 vpe_dbg(dev
, "releasing instance %p\n", ctx
);
2072 mutex_lock(&dev
->dev_mutex
);
2074 free_mv_buffers(ctx
);
2075 vpdma_free_desc_list(&ctx
->desc_list
);
2076 vpdma_free_desc_buf(&ctx
->mmr_adb
);
2078 v4l2_fh_del(&ctx
->fh
);
2079 v4l2_fh_exit(&ctx
->fh
);
2080 v4l2_ctrl_handler_free(&ctx
->hdl
);
2081 v4l2_m2m_ctx_release(ctx
->fh
.m2m_ctx
);
2086 * for now, just report the release of the last instance, we can later
2087 * optimize the driver to enable or disable clocks when the first
2088 * instance is created or the last instance released
2090 if (atomic_dec_return(&dev
->num_instances
) == 0)
2091 vpe_dbg(dev
, "last instance released\n");
2093 mutex_unlock(&dev
->dev_mutex
);
2098 static const struct v4l2_file_operations vpe_fops
= {
2099 .owner
= THIS_MODULE
,
2101 .release
= vpe_release
,
2102 .poll
= v4l2_m2m_fop_poll
,
2103 .unlocked_ioctl
= video_ioctl2
,
2104 .mmap
= v4l2_m2m_fop_mmap
,
2107 static struct video_device vpe_videodev
= {
2108 .name
= VPE_MODULE_NAME
,
2110 .ioctl_ops
= &vpe_ioctl_ops
,
2112 .release
= video_device_release_empty
,
2113 .vfl_dir
= VFL_DIR_M2M
,
2116 static struct v4l2_m2m_ops m2m_ops
= {
2117 .device_run
= device_run
,
2118 .job_ready
= job_ready
,
2119 .job_abort
= job_abort
,
2121 .unlock
= vpe_unlock
,
2124 static int vpe_runtime_get(struct platform_device
*pdev
)
2128 dev_dbg(&pdev
->dev
, "vpe_runtime_get\n");
2130 r
= pm_runtime_get_sync(&pdev
->dev
);
2132 return r
< 0 ? r
: 0;
2135 static void vpe_runtime_put(struct platform_device
*pdev
)
2140 dev_dbg(&pdev
->dev
, "vpe_runtime_put\n");
2142 r
= pm_runtime_put_sync(&pdev
->dev
);
2143 WARN_ON(r
< 0 && r
!= -ENOSYS
);
2146 static void vpe_fw_cb(struct platform_device
*pdev
)
2148 struct vpe_dev
*dev
= platform_get_drvdata(pdev
);
2149 struct video_device
*vfd
;
2153 *vfd
= vpe_videodev
;
2154 vfd
->lock
= &dev
->dev_mutex
;
2155 vfd
->v4l2_dev
= &dev
->v4l2_dev
;
2157 ret
= video_register_device(vfd
, VFL_TYPE_GRABBER
, 0);
2159 vpe_err(dev
, "Failed to register video device\n");
2161 vpe_set_clock_enable(dev
, 0);
2162 vpe_runtime_put(pdev
);
2163 pm_runtime_disable(&pdev
->dev
);
2164 v4l2_m2m_release(dev
->m2m_dev
);
2165 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
);
2166 v4l2_device_unregister(&dev
->v4l2_dev
);
2171 video_set_drvdata(vfd
, dev
);
2172 snprintf(vfd
->name
, sizeof(vfd
->name
), "%s", vpe_videodev
.name
);
2173 dev_info(dev
->v4l2_dev
.dev
, "Device registered as /dev/video%d\n",
2177 static int vpe_probe(struct platform_device
*pdev
)
2179 struct vpe_dev
*dev
;
2182 dev
= devm_kzalloc(&pdev
->dev
, sizeof(*dev
), GFP_KERNEL
);
2186 spin_lock_init(&dev
->lock
);
2188 ret
= v4l2_device_register(&pdev
->dev
, &dev
->v4l2_dev
);
2192 atomic_set(&dev
->num_instances
, 0);
2193 mutex_init(&dev
->dev_mutex
);
2195 dev
->res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
2198 * HACK: we get resource info from device tree in the form of a list of
2199 * VPE sub blocks, the driver currently uses only the base of vpe_top
2200 * for register access, the driver should be changed later to access
2201 * registers based on the sub block base addresses
2203 dev
->base
= devm_ioremap(&pdev
->dev
, dev
->res
->start
, SZ_32K
);
2206 goto v4l2_dev_unreg
;
2209 irq
= platform_get_irq(pdev
, 0);
2210 ret
= devm_request_irq(&pdev
->dev
, irq
, vpe_irq
, 0, VPE_MODULE_NAME
,
2213 goto v4l2_dev_unreg
;
2215 platform_set_drvdata(pdev
, dev
);
2217 dev
->alloc_ctx
= vb2_dma_contig_init_ctx(&pdev
->dev
);
2218 if (IS_ERR(dev
->alloc_ctx
)) {
2219 vpe_err(dev
, "Failed to alloc vb2 context\n");
2220 ret
= PTR_ERR(dev
->alloc_ctx
);
2221 goto v4l2_dev_unreg
;
2224 dev
->m2m_dev
= v4l2_m2m_init(&m2m_ops
);
2225 if (IS_ERR(dev
->m2m_dev
)) {
2226 vpe_err(dev
, "Failed to init mem2mem device\n");
2227 ret
= PTR_ERR(dev
->m2m_dev
);
2231 pm_runtime_enable(&pdev
->dev
);
2233 ret
= vpe_runtime_get(pdev
);
2237 /* Perform clk enable followed by reset */
2238 vpe_set_clock_enable(dev
, 1);
2242 func
= read_field_reg(dev
, VPE_PID
, VPE_PID_FUNC_MASK
,
2243 VPE_PID_FUNC_SHIFT
);
2244 vpe_dbg(dev
, "VPE PID function %x\n", func
);
2246 vpe_top_vpdma_reset(dev
);
2248 dev
->sc
= sc_create(pdev
);
2249 if (IS_ERR(dev
->sc
)) {
2250 ret
= PTR_ERR(dev
->sc
);
2254 dev
->csc
= csc_create(pdev
);
2255 if (IS_ERR(dev
->csc
)) {
2256 ret
= PTR_ERR(dev
->csc
);
2260 dev
->vpdma
= vpdma_create(pdev
, vpe_fw_cb
);
2261 if (IS_ERR(dev
->vpdma
)) {
2262 ret
= PTR_ERR(dev
->vpdma
);
2269 vpe_runtime_put(pdev
);
2271 pm_runtime_disable(&pdev
->dev
);
2272 v4l2_m2m_release(dev
->m2m_dev
);
2274 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
);
2276 v4l2_device_unregister(&dev
->v4l2_dev
);
2281 static int vpe_remove(struct platform_device
*pdev
)
2283 struct vpe_dev
*dev
= platform_get_drvdata(pdev
);
2285 v4l2_info(&dev
->v4l2_dev
, "Removing " VPE_MODULE_NAME
);
2287 v4l2_m2m_release(dev
->m2m_dev
);
2288 video_unregister_device(&dev
->vfd
);
2289 v4l2_device_unregister(&dev
->v4l2_dev
);
2290 vb2_dma_contig_cleanup_ctx(dev
->alloc_ctx
);
2292 vpe_set_clock_enable(dev
, 0);
2293 vpe_runtime_put(pdev
);
2294 pm_runtime_disable(&pdev
->dev
);
2299 #if defined(CONFIG_OF)
2300 static const struct of_device_id vpe_of_match
[] = {
2302 .compatible
= "ti,vpe",
2308 static struct platform_driver vpe_pdrv
= {
2310 .remove
= vpe_remove
,
2312 .name
= VPE_MODULE_NAME
,
2313 .of_match_table
= of_match_ptr(vpe_of_match
),
2317 module_platform_driver(vpe_pdrv
);
2319 MODULE_DESCRIPTION("TI VPE driver");
2320 MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>");
2321 MODULE_LICENSE("GPL");