Merge tag 'iwlwifi-next-for-kalle-2016-07-06' of git://git.kernel.org/pub/scm/linux...
[deliverable/linux.git] / drivers / media / platform / ti-vpe / vpe_regs.h
1 /*
2 * Copyright (c) 2013 Texas Instruments Inc.
3 *
4 * David Griego, <dagriego@biglakesoftware.com>
5 * Dale Farnsworth, <dale@farnsworth.org>
6 * Archit Taneja, <archit@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 */
12
13 #ifndef __TI_VPE_REGS_H
14 #define __TI_VPE_REGS_H
15
16 /* VPE register offsets and field selectors */
17
18 /* VPE top level regs */
19 #define VPE_PID 0x0000
20 #define VPE_PID_MINOR_MASK 0x3f
21 #define VPE_PID_MINOR_SHIFT 0
22 #define VPE_PID_CUSTOM_MASK 0x03
23 #define VPE_PID_CUSTOM_SHIFT 6
24 #define VPE_PID_MAJOR_MASK 0x07
25 #define VPE_PID_MAJOR_SHIFT 8
26 #define VPE_PID_RTL_MASK 0x1f
27 #define VPE_PID_RTL_SHIFT 11
28 #define VPE_PID_FUNC_MASK 0xfff
29 #define VPE_PID_FUNC_SHIFT 16
30 #define VPE_PID_SCHEME_MASK 0x03
31 #define VPE_PID_SCHEME_SHIFT 30
32
33 #define VPE_SYSCONFIG 0x0010
34 #define VPE_SYSCONFIG_IDLE_MASK 0x03
35 #define VPE_SYSCONFIG_IDLE_SHIFT 2
36 #define VPE_SYSCONFIG_STANDBY_MASK 0x03
37 #define VPE_SYSCONFIG_STANDBY_SHIFT 4
38 #define VPE_FORCE_IDLE_MODE 0
39 #define VPE_NO_IDLE_MODE 1
40 #define VPE_SMART_IDLE_MODE 2
41 #define VPE_SMART_IDLE_WAKEUP_MODE 3
42 #define VPE_FORCE_STANDBY_MODE 0
43 #define VPE_NO_STANDBY_MODE 1
44 #define VPE_SMART_STANDBY_MODE 2
45 #define VPE_SMART_STANDBY_WAKEUP_MODE 3
46
47 #define VPE_INT0_STATUS0_RAW_SET 0x0020
48 #define VPE_INT0_STATUS0_RAW VPE_INT0_STATUS0_RAW_SET
49 #define VPE_INT0_STATUS0_CLR 0x0028
50 #define VPE_INT0_STATUS0 VPE_INT0_STATUS0_CLR
51 #define VPE_INT0_ENABLE0_SET 0x0030
52 #define VPE_INT0_ENABLE0 VPE_INT0_ENABLE0_SET
53 #define VPE_INT0_ENABLE0_CLR 0x0038
54 #define VPE_INT0_LIST0_COMPLETE (1 << 0)
55 #define VPE_INT0_LIST0_NOTIFY (1 << 1)
56 #define VPE_INT0_LIST1_COMPLETE (1 << 2)
57 #define VPE_INT0_LIST1_NOTIFY (1 << 3)
58 #define VPE_INT0_LIST2_COMPLETE (1 << 4)
59 #define VPE_INT0_LIST2_NOTIFY (1 << 5)
60 #define VPE_INT0_LIST3_COMPLETE (1 << 6)
61 #define VPE_INT0_LIST3_NOTIFY (1 << 7)
62 #define VPE_INT0_LIST4_COMPLETE (1 << 8)
63 #define VPE_INT0_LIST4_NOTIFY (1 << 9)
64 #define VPE_INT0_LIST5_COMPLETE (1 << 10)
65 #define VPE_INT0_LIST5_NOTIFY (1 << 11)
66 #define VPE_INT0_LIST6_COMPLETE (1 << 12)
67 #define VPE_INT0_LIST6_NOTIFY (1 << 13)
68 #define VPE_INT0_LIST7_COMPLETE (1 << 14)
69 #define VPE_INT0_LIST7_NOTIFY (1 << 15)
70 #define VPE_INT0_DESCRIPTOR (1 << 16)
71 #define VPE_DEI_FMD_INT (1 << 18)
72
73 #define VPE_INT0_STATUS1_RAW_SET 0x0024
74 #define VPE_INT0_STATUS1_RAW VPE_INT0_STATUS1_RAW_SET
75 #define VPE_INT0_STATUS1_CLR 0x002c
76 #define VPE_INT0_STATUS1 VPE_INT0_STATUS1_CLR
77 #define VPE_INT0_ENABLE1_SET 0x0034
78 #define VPE_INT0_ENABLE1 VPE_INT0_ENABLE1_SET
79 #define VPE_INT0_ENABLE1_CLR 0x003c
80 #define VPE_INT0_CHANNEL_GROUP0 (1 << 0)
81 #define VPE_INT0_CHANNEL_GROUP1 (1 << 1)
82 #define VPE_INT0_CHANNEL_GROUP2 (1 << 2)
83 #define VPE_INT0_CHANNEL_GROUP3 (1 << 3)
84 #define VPE_INT0_CHANNEL_GROUP4 (1 << 4)
85 #define VPE_INT0_CHANNEL_GROUP5 (1 << 5)
86 #define VPE_INT0_CLIENT (1 << 7)
87 #define VPE_DEI_ERROR_INT (1 << 16)
88 #define VPE_DS1_UV_ERROR_INT (1 << 22)
89
90 #define VPE_INTC_EOI 0x00a0
91
92 #define VPE_CLK_ENABLE 0x0100
93 #define VPE_VPEDMA_CLK_ENABLE (1 << 0)
94 #define VPE_DATA_PATH_CLK_ENABLE (1 << 1)
95
96 #define VPE_CLK_RESET 0x0104
97 #define VPE_VPDMA_CLK_RESET_MASK 0x1
98 #define VPE_VPDMA_CLK_RESET_SHIFT 0
99 #define VPE_DATA_PATH_CLK_RESET_MASK 0x1
100 #define VPE_DATA_PATH_CLK_RESET_SHIFT 1
101 #define VPE_MAIN_RESET_MASK 0x1
102 #define VPE_MAIN_RESET_SHIFT 31
103
104 #define VPE_CLK_FORMAT_SELECT 0x010c
105 #define VPE_CSC_SRC_SELECT_MASK 0x03
106 #define VPE_CSC_SRC_SELECT_SHIFT 0
107 #define VPE_RGB_OUT_SELECT (1 << 8)
108 #define VPE_DS_SRC_SELECT_MASK 0x07
109 #define VPE_DS_SRC_SELECT_SHIFT 9
110 #define VPE_DS_BYPASS (1 << 16)
111 #define VPE_COLOR_SEPARATE_422 (1 << 18)
112
113 #define VPE_DS_SRC_DEI_SCALER (5 << VPE_DS_SRC_SELECT_SHIFT)
114 #define VPE_CSC_SRC_DEI_SCALER (3 << VPE_CSC_SRC_SELECT_SHIFT)
115
116 #define VPE_CLK_RANGE_MAP 0x011c
117 #define VPE_RANGE_RANGE_MAP_Y_MASK 0x07
118 #define VPE_RANGE_RANGE_MAP_Y_SHIFT 0
119 #define VPE_RANGE_RANGE_MAP_UV_MASK 0x07
120 #define VPE_RANGE_RANGE_MAP_UV_SHIFT 3
121 #define VPE_RANGE_MAP_ON (1 << 6)
122 #define VPE_RANGE_REDUCTION_ON (1 << 28)
123
124 /* VPE chrominance upsampler regs */
125 #define VPE_US1_R0 0x0304
126 #define VPE_US2_R0 0x0404
127 #define VPE_US3_R0 0x0504
128 #define VPE_US_C1_MASK 0x3fff
129 #define VPE_US_C1_SHIFT 2
130 #define VPE_US_C0_MASK 0x3fff
131 #define VPE_US_C0_SHIFT 18
132 #define VPE_US_MODE_MASK 0x03
133 #define VPE_US_MODE_SHIFT 16
134 #define VPE_ANCHOR_FID0_C1_MASK 0x3fff
135 #define VPE_ANCHOR_FID0_C1_SHIFT 2
136 #define VPE_ANCHOR_FID0_C0_MASK 0x3fff
137 #define VPE_ANCHOR_FID0_C0_SHIFT 18
138
139 #define VPE_US1_R1 0x0308
140 #define VPE_US2_R1 0x0408
141 #define VPE_US3_R1 0x0508
142 #define VPE_ANCHOR_FID0_C3_MASK 0x3fff
143 #define VPE_ANCHOR_FID0_C3_SHIFT 2
144 #define VPE_ANCHOR_FID0_C2_MASK 0x3fff
145 #define VPE_ANCHOR_FID0_C2_SHIFT 18
146
147 #define VPE_US1_R2 0x030c
148 #define VPE_US2_R2 0x040c
149 #define VPE_US3_R2 0x050c
150 #define VPE_INTERP_FID0_C1_MASK 0x3fff
151 #define VPE_INTERP_FID0_C1_SHIFT 2
152 #define VPE_INTERP_FID0_C0_MASK 0x3fff
153 #define VPE_INTERP_FID0_C0_SHIFT 18
154
155 #define VPE_US1_R3 0x0310
156 #define VPE_US2_R3 0x0410
157 #define VPE_US3_R3 0x0510
158 #define VPE_INTERP_FID0_C3_MASK 0x3fff
159 #define VPE_INTERP_FID0_C3_SHIFT 2
160 #define VPE_INTERP_FID0_C2_MASK 0x3fff
161 #define VPE_INTERP_FID0_C2_SHIFT 18
162
163 #define VPE_US1_R4 0x0314
164 #define VPE_US2_R4 0x0414
165 #define VPE_US3_R4 0x0514
166 #define VPE_ANCHOR_FID1_C1_MASK 0x3fff
167 #define VPE_ANCHOR_FID1_C1_SHIFT 2
168 #define VPE_ANCHOR_FID1_C0_MASK 0x3fff
169 #define VPE_ANCHOR_FID1_C0_SHIFT 18
170
171 #define VPE_US1_R5 0x0318
172 #define VPE_US2_R5 0x0418
173 #define VPE_US3_R5 0x0518
174 #define VPE_ANCHOR_FID1_C3_MASK 0x3fff
175 #define VPE_ANCHOR_FID1_C3_SHIFT 2
176 #define VPE_ANCHOR_FID1_C2_MASK 0x3fff
177 #define VPE_ANCHOR_FID1_C2_SHIFT 18
178
179 #define VPE_US1_R6 0x031c
180 #define VPE_US2_R6 0x041c
181 #define VPE_US3_R6 0x051c
182 #define VPE_INTERP_FID1_C1_MASK 0x3fff
183 #define VPE_INTERP_FID1_C1_SHIFT 2
184 #define VPE_INTERP_FID1_C0_MASK 0x3fff
185 #define VPE_INTERP_FID1_C0_SHIFT 18
186
187 #define VPE_US1_R7 0x0320
188 #define VPE_US2_R7 0x0420
189 #define VPE_US3_R7 0x0520
190 #define VPE_INTERP_FID0_C3_MASK 0x3fff
191 #define VPE_INTERP_FID0_C3_SHIFT 2
192 #define VPE_INTERP_FID0_C2_MASK 0x3fff
193 #define VPE_INTERP_FID0_C2_SHIFT 18
194
195 /* VPE de-interlacer regs */
196 #define VPE_DEI_FRAME_SIZE 0x0600
197 #define VPE_DEI_WIDTH_MASK 0x07ff
198 #define VPE_DEI_WIDTH_SHIFT 0
199 #define VPE_DEI_HEIGHT_MASK 0x07ff
200 #define VPE_DEI_HEIGHT_SHIFT 16
201 #define VPE_DEI_INTERLACE_BYPASS (1 << 29)
202 #define VPE_DEI_FIELD_FLUSH (1 << 30)
203 #define VPE_DEI_PROGRESSIVE (1 << 31)
204
205 #define VPE_MDT_BYPASS 0x0604
206 #define VPE_MDT_TEMPMAX_BYPASS (1 << 0)
207 #define VPE_MDT_SPATMAX_BYPASS (1 << 1)
208
209 #define VPE_MDT_SF_THRESHOLD 0x0608
210 #define VPE_MDT_SF_SC_THR1_MASK 0xff
211 #define VPE_MDT_SF_SC_THR1_SHIFT 0
212 #define VPE_MDT_SF_SC_THR2_MASK 0xff
213 #define VPE_MDT_SF_SC_THR2_SHIFT 0
214 #define VPE_MDT_SF_SC_THR3_MASK 0xff
215 #define VPE_MDT_SF_SC_THR3_SHIFT 0
216
217 #define VPE_EDI_CONFIG 0x060c
218 #define VPE_EDI_INP_MODE_MASK 0x03
219 #define VPE_EDI_INP_MODE_SHIFT 0
220 #define VPE_EDI_ENABLE_3D (1 << 2)
221 #define VPE_EDI_ENABLE_CHROMA_3D (1 << 3)
222 #define VPE_EDI_CHROMA3D_COR_THR_MASK 0xff
223 #define VPE_EDI_CHROMA3D_COR_THR_SHIFT 8
224 #define VPE_EDI_DIR_COR_LOWER_THR_MASK 0xff
225 #define VPE_EDI_DIR_COR_LOWER_THR_SHIFT 16
226 #define VPE_EDI_COR_SCALE_FACTOR_MASK 0xff
227 #define VPE_EDI_COR_SCALE_FACTOR_SHIFT 23
228
229 #define VPE_DEI_EDI_LUT_R0 0x0610
230 #define VPE_EDI_LUT0_MASK 0x1f
231 #define VPE_EDI_LUT0_SHIFT 0
232 #define VPE_EDI_LUT1_MASK 0x1f
233 #define VPE_EDI_LUT1_SHIFT 8
234 #define VPE_EDI_LUT2_MASK 0x1f
235 #define VPE_EDI_LUT2_SHIFT 16
236 #define VPE_EDI_LUT3_MASK 0x1f
237 #define VPE_EDI_LUT3_SHIFT 24
238
239 #define VPE_DEI_EDI_LUT_R1 0x0614
240 #define VPE_EDI_LUT0_MASK 0x1f
241 #define VPE_EDI_LUT0_SHIFT 0
242 #define VPE_EDI_LUT1_MASK 0x1f
243 #define VPE_EDI_LUT1_SHIFT 8
244 #define VPE_EDI_LUT2_MASK 0x1f
245 #define VPE_EDI_LUT2_SHIFT 16
246 #define VPE_EDI_LUT3_MASK 0x1f
247 #define VPE_EDI_LUT3_SHIFT 24
248
249 #define VPE_DEI_EDI_LUT_R2 0x0618
250 #define VPE_EDI_LUT4_MASK 0x1f
251 #define VPE_EDI_LUT4_SHIFT 0
252 #define VPE_EDI_LUT5_MASK 0x1f
253 #define VPE_EDI_LUT5_SHIFT 8
254 #define VPE_EDI_LUT6_MASK 0x1f
255 #define VPE_EDI_LUT6_SHIFT 16
256 #define VPE_EDI_LUT7_MASK 0x1f
257 #define VPE_EDI_LUT7_SHIFT 24
258
259 #define VPE_DEI_EDI_LUT_R3 0x061c
260 #define VPE_EDI_LUT8_MASK 0x1f
261 #define VPE_EDI_LUT8_SHIFT 0
262 #define VPE_EDI_LUT9_MASK 0x1f
263 #define VPE_EDI_LUT9_SHIFT 8
264 #define VPE_EDI_LUT10_MASK 0x1f
265 #define VPE_EDI_LUT10_SHIFT 16
266 #define VPE_EDI_LUT11_MASK 0x1f
267 #define VPE_EDI_LUT11_SHIFT 24
268
269 #define VPE_DEI_FMD_WINDOW_R0 0x0620
270 #define VPE_FMD_WINDOW_MINX_MASK 0x07ff
271 #define VPE_FMD_WINDOW_MINX_SHIFT 0
272 #define VPE_FMD_WINDOW_MAXX_MASK 0x07ff
273 #define VPE_FMD_WINDOW_MAXX_SHIFT 16
274 #define VPE_FMD_WINDOW_ENABLE (1 << 31)
275
276 #define VPE_DEI_FMD_WINDOW_R1 0x0624
277 #define VPE_FMD_WINDOW_MINY_MASK 0x07ff
278 #define VPE_FMD_WINDOW_MINY_SHIFT 0
279 #define VPE_FMD_WINDOW_MAXY_MASK 0x07ff
280 #define VPE_FMD_WINDOW_MAXY_SHIFT 16
281
282 #define VPE_DEI_FMD_CONTROL_R0 0x0628
283 #define VPE_FMD_ENABLE (1 << 0)
284 #define VPE_FMD_LOCK (1 << 1)
285 #define VPE_FMD_JAM_DIR (1 << 2)
286 #define VPE_FMD_BED_ENABLE (1 << 3)
287 #define VPE_FMD_CAF_FIELD_THR_MASK 0xff
288 #define VPE_FMD_CAF_FIELD_THR_SHIFT 16
289 #define VPE_FMD_CAF_LINE_THR_MASK 0xff
290 #define VPE_FMD_CAF_LINE_THR_SHIFT 24
291
292 #define VPE_DEI_FMD_CONTROL_R1 0x062c
293 #define VPE_FMD_CAF_THR_MASK 0x000fffff
294 #define VPE_FMD_CAF_THR_SHIFT 0
295
296 #define VPE_DEI_FMD_STATUS_R0 0x0630
297 #define VPE_FMD_CAF_MASK 0x000fffff
298 #define VPE_FMD_CAF_SHIFT 0
299 #define VPE_FMD_RESET (1 << 24)
300
301 #define VPE_DEI_FMD_STATUS_R1 0x0634
302 #define VPE_FMD_FIELD_DIFF_MASK 0x0fffffff
303 #define VPE_FMD_FIELD_DIFF_SHIFT 0
304
305 #define VPE_DEI_FMD_STATUS_R2 0x0638
306 #define VPE_FMD_FRAME_DIFF_MASK 0x000fffff
307 #define VPE_FMD_FRAME_DIFF_SHIFT 0
308
309 #endif
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