drivers/media/platform/vsp1/vsp1_pipe.c

   1 /*
   2  * vsp1_pipe.c  --  R-Car VSP1 Pipeline
   3  *
   4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/list.h>
  16 #include <linux/sched.h>
  17 #include <linux/wait.h>
  18
  19 #include <media/media-entity.h>
  20 #include <media/v4l2-subdev.h>
  21
  22 #include "vsp1.h"
  23 #include "vsp1_bru.h"
  24 #include "vsp1_dl.h"
  25 #include "vsp1_entity.h"
  26 #include "vsp1_pipe.h"
  27 #include "vsp1_rwpf.h"
  28 #include "vsp1_uds.h"
  29
  30 /* -----------------------------------------------------------------------------
  31  * Helper Functions
  32  */
  33
  34 static const struct vsp1_format_info vsp1_video_formats[] = {
  35         { V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32,
  36           VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  37           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  38           1, { 8, 0, 0 }, false, false, 1, 1, false },
  39         { V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
  40           VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  41           VI6_RPF_DSWAP_P_WDS,
  42           1, { 16, 0, 0 }, false, false, 1, 1, true },
  43         { V4L2_PIX_FMT_XRGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
  44           VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  45           VI6_RPF_DSWAP_P_WDS,
  46           1, { 16, 0, 0 }, false, false, 1, 1, false },
  47         { V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
  48           VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  49           VI6_RPF_DSWAP_P_WDS,
  50           1, { 16, 0, 0 }, false, false, 1, 1, true },
  51         { V4L2_PIX_FMT_XRGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
  52           VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  53           VI6_RPF_DSWAP_P_WDS,
  54           1, { 16, 0, 0 }, false, false, 1, 1, false },
  55         { V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32,
  56           VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  57           VI6_RPF_DSWAP_P_WDS,
  58           1, { 16, 0, 0 }, false, false, 1, 1, false },
  59         { V4L2_PIX_FMT_BGR24, MEDIA_BUS_FMT_ARGB8888_1X32,
  60           VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  61           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  62           1, { 24, 0, 0 }, false, false, 1, 1, false },
  63         { V4L2_PIX_FMT_RGB24, MEDIA_BUS_FMT_ARGB8888_1X32,
  64           VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  65           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  66           1, { 24, 0, 0 }, false, false, 1, 1, false },
  67         { V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
  68           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
  69           1, { 32, 0, 0 }, false, false, 1, 1, true },
  70         { V4L2_PIX_FMT_XBGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
  71           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
  72           1, { 32, 0, 0 }, false, false, 1, 1, false },
  73         { V4L2_PIX_FMT_ARGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
  74           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  75           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  76           1, { 32, 0, 0 }, false, false, 1, 1, true },
  77         { V4L2_PIX_FMT_XRGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
  78           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  79           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  80           1, { 32, 0, 0 }, false, false, 1, 1, false },
  81         { V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32,
  82           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  83           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  84           1, { 16, 0, 0 }, false, false, 2, 1, false },
  85         { V4L2_PIX_FMT_VYUY, MEDIA_BUS_FMT_AYUV8_1X32,
  86           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  87           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  88           1, { 16, 0, 0 }, false, true, 2, 1, false },
  89         { V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_AYUV8_1X32,
  90           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  91           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  92           1, { 16, 0, 0 }, true, false, 2, 1, false },
  93         { V4L2_PIX_FMT_YVYU, MEDIA_BUS_FMT_AYUV8_1X32,
  94           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  95           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  96           1, { 16, 0, 0 }, true, true, 2, 1, false },
  97         { V4L2_PIX_FMT_NV12M, MEDIA_BUS_FMT_AYUV8_1X32,
  98           VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  99           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 100           2, { 8, 16, 0 }, false, false, 2, 2, false },
 101         { V4L2_PIX_FMT_NV21M, MEDIA_BUS_FMT_AYUV8_1X32,
 102           VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 103           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 104           2, { 8, 16, 0 }, false, true, 2, 2, false },
 105         { V4L2_PIX_FMT_NV16M, MEDIA_BUS_FMT_AYUV8_1X32,
 106           VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 107           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 108           2, { 8, 16, 0 }, false, false, 2, 1, false },
 109         { V4L2_PIX_FMT_NV61M, MEDIA_BUS_FMT_AYUV8_1X32,
 110           VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 111           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 112           2, { 8, 16, 0 }, false, true, 2, 1, false },
 113         { V4L2_PIX_FMT_YUV420M, MEDIA_BUS_FMT_AYUV8_1X32,
 114           VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 115           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 116           3, { 8, 8, 8 }, false, false, 2, 2, false },
 117         { V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32,
 118           VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 119           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 120           3, { 8, 8, 8 }, false, true, 2, 2, false },
 121         { V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32,
 122           VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 123           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 124           3, { 8, 8, 8 }, false, false, 2, 1, false },
 125         { V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32,
 126           VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 127           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 128           3, { 8, 8, 8 }, false, true, 2, 1, false },
 129         { V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32,
 130           VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 131           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 132           3, { 8, 8, 8 }, false, false, 1, 1, false },
 133         { V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32,
 134           VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 135           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 136           3, { 8, 8, 8 }, false, true, 1, 1, false },
 137 };
 138
 139 /*
 140  * vsp1_get_format_info - Retrieve format information for a 4CC
 141  * @fourcc: the format 4CC
 142  *
 143  * Return a pointer to the format information structure corresponding to the
 144  * given V4L2 format 4CC, or NULL if no corresponding format can be found.
 145  */
 146 const struct vsp1_format_info *vsp1_get_format_info(u32 fourcc)
 147 {
 148         unsigned int i;
 149
 150         for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) {
 151                 const struct vsp1_format_info *info = &vsp1_video_formats[i];
 152
 153                 if (info->fourcc == fourcc)
 154                         return info;
 155         }
 156
 157         return NULL;
 158 }
 159
 160 /* -----------------------------------------------------------------------------
 161  * Pipeline Management
 162  */
 163
 164 void vsp1_pipeline_reset(struct vsp1_pipeline *pipe)
 165 {
 166         unsigned int i;
 167
 168         if (pipe->bru) {
 169                 struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);
 170
 171                 for (i = 0; i < ARRAY_SIZE(bru->inputs); ++i)
 172                         bru->inputs[i].rpf = NULL;
 173         }
 174
 175         for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
 176                 if (pipe->inputs[i]) {
 177                         pipe->inputs[i]->pipe = NULL;
 178                         pipe->inputs[i] = NULL;
 179                 }
 180         }
 181
 182         if (pipe->output) {
 183                 pipe->output->pipe = NULL;
 184                 pipe->output = NULL;
 185         }
 186
 187         INIT_LIST_HEAD(&pipe->entities);
 188         pipe->state = VSP1_PIPELINE_STOPPED;
 189         pipe->buffers_ready = 0;
 190         pipe->num_inputs = 0;
 191         pipe->bru = NULL;
 192         pipe->lif = NULL;
 193         pipe->uds = NULL;
 194 }
 195
 196 void vsp1_pipeline_init(struct vsp1_pipeline *pipe)
 197 {
 198         mutex_init(&pipe->lock);
 199         spin_lock_init(&pipe->irqlock);
 200         init_waitqueue_head(&pipe->wq);
 201         kref_init(&pipe->kref);
 202
 203         INIT_LIST_HEAD(&pipe->entities);
 204         pipe->state = VSP1_PIPELINE_STOPPED;
 205 }
 206
 207 /* Must be called with the pipe irqlock held. */
 208 void vsp1_pipeline_run(struct vsp1_pipeline *pipe)
 209 {
 210         struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
 211
 212         if (pipe->state == VSP1_PIPELINE_STOPPED) {
 213                 vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index),
 214                            VI6_CMD_STRCMD);
 215                 pipe->state = VSP1_PIPELINE_RUNNING;
 216         }
 217
 218         pipe->buffers_ready = 0;
 219 }
 220
 221 bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe)
 222 {
 223         unsigned long flags;
 224         bool stopped;
 225
 226         spin_lock_irqsave(&pipe->irqlock, flags);
 227         stopped = pipe->state == VSP1_PIPELINE_STOPPED;
 228         spin_unlock_irqrestore(&pipe->irqlock, flags);
 229
 230         return stopped;
 231 }
 232
 233 int vsp1_pipeline_stop(struct vsp1_pipeline *pipe)
 234 {
 235         struct vsp1_entity *entity;
 236         unsigned long flags;
 237         int ret;
 238
 239         if (pipe->lif) {
 240                 /* When using display lists in continuous frame mode the only
 241                  * way to stop the pipeline is to reset the hardware.
 242                  */
 243                 ret = vsp1_reset_wpf(pipe->output->entity.vsp1,
 244                                      pipe->output->entity.index);
 245                 if (ret == 0) {
 246                         spin_lock_irqsave(&pipe->irqlock, flags);
 247                         pipe->state = VSP1_PIPELINE_STOPPED;
 248                         spin_unlock_irqrestore(&pipe->irqlock, flags);
 249                 }
 250         } else {
 251                 /* Otherwise just request a stop and wait. */
 252                 spin_lock_irqsave(&pipe->irqlock, flags);
 253                 if (pipe->state == VSP1_PIPELINE_RUNNING)
 254                         pipe->state = VSP1_PIPELINE_STOPPING;
 255                 spin_unlock_irqrestore(&pipe->irqlock, flags);
 256
 257                 ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
 258                                          msecs_to_jiffies(500));
 259                 ret = ret == 0 ? -ETIMEDOUT : 0;
 260         }
 261
 262         list_for_each_entry(entity, &pipe->entities, list_pipe) {
 263                 if (entity->route && entity->route->reg)
 264                         vsp1_write(entity->vsp1, entity->route->reg,
 265                                    VI6_DPR_NODE_UNUSED);
 266         }
 267
 268         v4l2_subdev_call(&pipe->output->entity.subdev, video, s_stream, 0);
 269
 270         return ret;
 271 }
 272
 273 bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe)
 274 {
 275         unsigned int mask;
 276
 277         mask = ((1 << pipe->num_inputs) - 1) << 1;
 278         if (!pipe->lif)
 279                 mask |= 1 << 0;
 280
 281         return pipe->buffers_ready == mask;
 282 }
 283
 284 void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
 285 {
 286         if (pipe == NULL)
 287                 return;
 288
 289         vsp1_dlm_irq_frame_end(pipe->output->dlm);
 290
 291         if (pipe->frame_end)
 292                 pipe->frame_end(pipe);
 293
 294         pipe->sequence++;
 295 }
 296
 297 /*
 298  * Propagate the alpha value through the pipeline.
 299  *
 300  * As the UDS has restricted scaling capabilities when the alpha component needs
 301  * to be scaled, we disable alpha scaling when the UDS input has a fixed alpha
 302  * value. The UDS then outputs a fixed alpha value which needs to be programmed
 303  * from the input RPF alpha.
 304  */
 305 void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
 306                                    struct vsp1_dl_list *dl, unsigned int alpha)
 307 {
 308         if (!pipe->uds)
 309                 return;
 310
 311         /* The BRU background color has a fixed alpha value set to 255, the
 312          * output alpha value is thus always equal to 255.
 313          */
 314         if (pipe->uds_input->type == VSP1_ENTITY_BRU)
 315                 alpha = 255;
 316
 317         vsp1_uds_set_alpha(pipe->uds, dl, alpha);
 318 }
 319
 320 void vsp1_pipelines_suspend(struct vsp1_device *vsp1)
 321 {
 322         unsigned long flags;
 323         unsigned int i;
 324         int ret;
 325
 326         /* To avoid increasing the system suspend time needlessly, loop over the
 327          * pipelines twice, first to set them all to the stopping state, and
 328          * then to wait for the stop to complete.
 329          */
 330         for (i = 0; i < vsp1->info->wpf_count; ++i) {
 331                 struct vsp1_rwpf *wpf = vsp1->wpf[i];
 332                 struct vsp1_pipeline *pipe;
 333
 334                 if (wpf == NULL)
 335                         continue;
 336
 337                 pipe = wpf->pipe;
 338                 if (pipe == NULL)
 339                         continue;
 340
 341                 spin_lock_irqsave(&pipe->irqlock, flags);
 342                 if (pipe->state == VSP1_PIPELINE_RUNNING)
 343                         pipe->state = VSP1_PIPELINE_STOPPING;
 344                 spin_unlock_irqrestore(&pipe->irqlock, flags);
 345         }
 346
 347         for (i = 0; i < vsp1->info->wpf_count; ++i) {
 348                 struct vsp1_rwpf *wpf = vsp1->wpf[i];
 349                 struct vsp1_pipeline *pipe;
 350
 351                 if (wpf == NULL)
 352                         continue;
 353
 354                 pipe = wpf->pipe;
 355                 if (pipe == NULL)
 356                         continue;
 357
 358                 ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
 359                                          msecs_to_jiffies(500));
 360                 if (ret == 0)
 361                         dev_warn(vsp1->dev, "pipeline %u stop timeout\n",
 362                                  wpf->entity.index);
 363         }
 364 }
 365
 366 void vsp1_pipelines_resume(struct vsp1_device *vsp1)
 367 {
 368         unsigned int i;
 369
 370         /* Resume all running pipelines. */
 371         for (i = 0; i < vsp1->info->wpf_count; ++i) {
 372                 struct vsp1_rwpf *wpf = vsp1->wpf[i];
 373                 struct vsp1_pipeline *pipe;
 374
 375                 if (wpf == NULL)
 376                         continue;
 377
 378                 pipe = wpf->pipe;
 379                 if (pipe == NULL)
 380                         continue;
 381
 382                 if (vsp1_pipeline_ready(pipe))
 383                         vsp1_pipeline_run(pipe);
 384         }
 385 }