drivers/media/rc/img-ir/img-ir.h

   1 /*
   2  * ImgTec IR Decoder found in PowerDown Controller.
   3  *
   4  * Copyright 2010-2014 Imagination Technologies Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  */
  11
  12 #ifndef _IMG_IR_H_
  13 #define _IMG_IR_H_
  14
  15 #include <linux/io.h>
  16 #include <linux/spinlock.h>
  17
  18 #include "img-ir-raw.h"
  19 #include "img-ir-hw.h"
  20
  21 /* registers */
  22
  23 /* relative to the start of the IR block of registers */
  24 #define IMG_IR_CONTROL          0x00
  25 #define IMG_IR_STATUS           0x04
  26 #define IMG_IR_DATA_LW          0x08
  27 #define IMG_IR_DATA_UP          0x0c
  28 #define IMG_IR_LEAD_SYMB_TIMING 0x10
  29 #define IMG_IR_S00_SYMB_TIMING  0x14
  30 #define IMG_IR_S01_SYMB_TIMING  0x18
  31 #define IMG_IR_S10_SYMB_TIMING  0x1c
  32 #define IMG_IR_S11_SYMB_TIMING  0x20
  33 #define IMG_IR_FREE_SYMB_TIMING 0x24
  34 #define IMG_IR_POW_MOD_PARAMS   0x28
  35 #define IMG_IR_POW_MOD_ENABLE   0x2c
  36 #define IMG_IR_IRQ_MSG_DATA_LW  0x30
  37 #define IMG_IR_IRQ_MSG_DATA_UP  0x34
  38 #define IMG_IR_IRQ_MSG_MASK_LW  0x38
  39 #define IMG_IR_IRQ_MSG_MASK_UP  0x3c
  40 #define IMG_IR_IRQ_ENABLE       0x40
  41 #define IMG_IR_IRQ_STATUS       0x44
  42 #define IMG_IR_IRQ_CLEAR        0x48
  43 #define IMG_IR_IRCORE_ID        0xf0
  44 #define IMG_IR_CORE_REV         0xf4
  45 #define IMG_IR_CORE_DES1        0xf8
  46 #define IMG_IR_CORE_DES2        0xfc
  47
  48
  49 /* field masks */
  50
  51 /* IMG_IR_CONTROL */
  52 #define IMG_IR_DECODEN          0x40000000
  53 #define IMG_IR_CODETYPE         0x30000000
  54 #define IMG_IR_CODETYPE_SHIFT           28
  55 #define IMG_IR_HDRTOG           0x08000000
  56 #define IMG_IR_LDRDEC           0x04000000
  57 #define IMG_IR_DECODINPOL       0x02000000      /* active high */
  58 #define IMG_IR_BITORIEN         0x01000000      /* MSB first */
  59 #define IMG_IR_D1VALIDSEL       0x00008000
  60 #define IMG_IR_BITINV           0x00000040      /* don't invert */
  61 #define IMG_IR_DECODEND2        0x00000010
  62 #define IMG_IR_BITORIEND2       0x00000002      /* MSB first */
  63 #define IMG_IR_BITINVD2         0x00000001      /* don't invert */
  64
  65 /* IMG_IR_STATUS */
  66 #define IMG_IR_RXDVALD2         0x00001000
  67 #define IMG_IR_IRRXD            0x00000400
  68 #define IMG_IR_TOGSTATE         0x00000200
  69 #define IMG_IR_RXDVAL           0x00000040
  70 #define IMG_IR_RXDLEN           0x0000003f
  71 #define IMG_IR_RXDLEN_SHIFT             0
  72
  73 /* IMG_IR_LEAD_SYMB_TIMING, IMG_IR_Sxx_SYMB_TIMING */
  74 #define IMG_IR_PD_MAX           0xff000000
  75 #define IMG_IR_PD_MAX_SHIFT             24
  76 #define IMG_IR_PD_MIN           0x00ff0000
  77 #define IMG_IR_PD_MIN_SHIFT             16
  78 #define IMG_IR_W_MAX            0x0000ff00
  79 #define IMG_IR_W_MAX_SHIFT              8
  80 #define IMG_IR_W_MIN            0x000000ff
  81 #define IMG_IR_W_MIN_SHIFT              0
  82
  83 /* IMG_IR_FREE_SYMB_TIMING */
  84 #define IMG_IR_MAXLEN           0x0007e000
  85 #define IMG_IR_MAXLEN_SHIFT             13
  86 #define IMG_IR_MINLEN           0x00001f00
  87 #define IMG_IR_MINLEN_SHIFT             8
  88 #define IMG_IR_FT_MIN           0x000000ff
  89 #define IMG_IR_FT_MIN_SHIFT             0
  90
  91 /* IMG_IR_POW_MOD_PARAMS */
  92 #define IMG_IR_PERIOD_LEN       0x3f000000
  93 #define IMG_IR_PERIOD_LEN_SHIFT         24
  94 #define IMG_IR_PERIOD_DUTY      0x003f0000
  95 #define IMG_IR_PERIOD_DUTY_SHIFT        16
  96 #define IMG_IR_STABLE_STOP      0x00003f00
  97 #define IMG_IR_STABLE_STOP_SHIFT        8
  98 #define IMG_IR_STABLE_START     0x0000003f
  99 #define IMG_IR_STABLE_START_SHIFT       0
 100
 101 /* IMG_IR_POW_MOD_ENABLE */
 102 #define IMG_IR_POWER_OUT_EN     0x00000002
 103 #define IMG_IR_POWER_MOD_EN     0x00000001
 104
 105 /* IMG_IR_IRQ_ENABLE, IMG_IR_IRQ_STATUS, IMG_IR_IRQ_CLEAR */
 106 #define IMG_IR_IRQ_DEC2_ERR     0x00000080
 107 #define IMG_IR_IRQ_DEC_ERR      0x00000040
 108 #define IMG_IR_IRQ_ACT_LEVEL    0x00000020
 109 #define IMG_IR_IRQ_FALL_EDGE    0x00000010
 110 #define IMG_IR_IRQ_RISE_EDGE    0x00000008
 111 #define IMG_IR_IRQ_DATA_MATCH   0x00000004
 112 #define IMG_IR_IRQ_DATA2_VALID  0x00000002
 113 #define IMG_IR_IRQ_DATA_VALID   0x00000001
 114 #define IMG_IR_IRQ_ALL          0x000000ff
 115 #define IMG_IR_IRQ_EDGE         (IMG_IR_IRQ_FALL_EDGE | IMG_IR_IRQ_RISE_EDGE)
 116
 117 /* IMG_IR_CORE_ID */
 118 #define IMG_IR_CORE_ID          0x00ff0000
 119 #define IMG_IR_CORE_ID_SHIFT            16
 120 #define IMG_IR_CORE_CONFIG      0x0000ffff
 121 #define IMG_IR_CORE_CONFIG_SHIFT        0
 122
 123 /* IMG_IR_CORE_REV */
 124 #define IMG_IR_DESIGNER         0xff000000
 125 #define IMG_IR_DESIGNER_SHIFT           24
 126 #define IMG_IR_MAJOR_REV        0x00ff0000
 127 #define IMG_IR_MAJOR_REV_SHIFT          16
 128 #define IMG_IR_MINOR_REV        0x0000ff00
 129 #define IMG_IR_MINOR_REV_SHIFT          8
 130 #define IMG_IR_MAINT_REV        0x000000ff
 131 #define IMG_IR_MAINT_REV_SHIFT          0
 132
 133 struct device;
 134 struct clk;
 135
 136 /**
 137  * struct img_ir_priv - Private driver data.
 138  * @dev:                Platform device.
 139  * @irq:                IRQ number.
 140  * @clk:                Input clock.
 141  * @sys_clk:            System clock.
 142  * @reg_base:           Iomem base address of IR register block.
 143  * @lock:               Protects IR registers and variables in this struct.
 144  * @raw:                Driver data for raw decoder.
 145  * @hw:                 Driver data for hardware decoder.
 146  */
 147 struct img_ir_priv {
 148         struct device           *dev;
 149         int                     irq;
 150         struct clk              *clk;
 151         struct clk              *sys_clk;
 152         void __iomem            *reg_base;
 153         spinlock_t              lock;
 154
 155         struct img_ir_priv_raw  raw;
 156         struct img_ir_priv_hw   hw;
 157 };
 158
 159 /* Hardware access */
 160
 161 static inline void img_ir_write(struct img_ir_priv *priv,
 162                                 unsigned int reg_offs, unsigned int data)
 163 {
 164         iowrite32(data, priv->reg_base + reg_offs);
 165 }
 166
 167 static inline unsigned int img_ir_read(struct img_ir_priv *priv,
 168                                        unsigned int reg_offs)
 169 {
 170         return ioread32(priv->reg_base + reg_offs);
 171 }
 172
 173 #endif /* _IMG_IR_H_ */