projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[media] media: rc: nuvoton: remove interrupt handling for wakeup
[deliverable/linux.git] / drivers / media / rc / nuvoton-cir.c
1 /*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pnp.h>
33 #include <linux/io.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <media/rc-core.h>
38 #include <linux/pci_ids.h>
39
40 #include "nuvoton-cir.h"
41
42 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt);
43
44 static const struct nvt_chip nvt_chips[] = {
45 { "w83667hg", NVT_W83667HG },
46 { "NCT6775F", NVT_6775F },
47 { "NCT6776F", NVT_6776F },
48 { "NCT6779D", NVT_6779D },
49 };
50
51 static inline bool is_w83667hg(struct nvt_dev *nvt)
52 {
53 return nvt->chip_ver == NVT_W83667HG;
54 }
55
56 /* write val to config reg */
57 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
58 {
59 outb(reg, nvt->cr_efir);
60 outb(val, nvt->cr_efdr);
61 }
62
63 /* read val from config reg */
64 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
65 {
66 outb(reg, nvt->cr_efir);
67 return inb(nvt->cr_efdr);
68 }
69
70 /* update config register bit without changing other bits */
71 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
72 {
73 u8 tmp = nvt_cr_read(nvt, reg) | val;
74 nvt_cr_write(nvt, tmp, reg);
75 }
76
77 /* clear config register bit without changing other bits */
78 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
79 {
80 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
81 nvt_cr_write(nvt, tmp, reg);
82 }
83
84 /* enter extended function mode */
85 static inline int nvt_efm_enable(struct nvt_dev *nvt)
86 {
87 if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME))
88 return -EBUSY;
89
90 /* Enabling Extended Function Mode explicitly requires writing 2x */
91 outb(EFER_EFM_ENABLE, nvt->cr_efir);
92 outb(EFER_EFM_ENABLE, nvt->cr_efir);
93
94 return 0;
95 }
96
97 /* exit extended function mode */
98 static inline void nvt_efm_disable(struct nvt_dev *nvt)
99 {
100 outb(EFER_EFM_DISABLE, nvt->cr_efir);
101
102 release_region(nvt->cr_efir, 2);
103 }
104
105 /*
106 * When you want to address a specific logical device, write its logical
107 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
108 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
109 */
110 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
111 {
112 nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL);
113 }
114
115 /* select and enable logical device with setting EFM mode*/
116 static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev)
117 {
118 nvt_efm_enable(nvt);
119 nvt_select_logical_dev(nvt, ldev);
120 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
121 nvt_efm_disable(nvt);
122 }
123
124 /* select and disable logical device with setting EFM mode*/
125 static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev)
126 {
127 nvt_efm_enable(nvt);
128 nvt_select_logical_dev(nvt, ldev);
129 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
130 nvt_efm_disable(nvt);
131 }
132
133 /* write val to cir config register */
134 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
135 {
136 outb(val, nvt->cir_addr + offset);
137 }
138
139 /* read val from cir config register */
140 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
141 {
142 u8 val;
143
144 val = inb(nvt->cir_addr + offset);
145
146 return val;
147 }
148
149 /* write val to cir wake register */
150 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
151 u8 val, u8 offset)
152 {
153 outb(val, nvt->cir_wake_addr + offset);
154 }
155
156 /* read val from cir wake config register */
157 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
158 {
159 u8 val;
160
161 val = inb(nvt->cir_wake_addr + offset);
162
163 return val;
164 }
165
166 /* don't override io address if one is set already */
167 static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr)
168 {
169 unsigned long old_addr;
170
171 old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8;
172 old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO);
173
174 if (old_addr)
175 *ioaddr = old_addr;
176 else {
177 nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI);
178 nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO);
179 }
180 }
181
182 static ssize_t wakeup_data_show(struct device *dev,
183 struct device_attribute *attr,
184 char *buf)
185 {
186 struct rc_dev *rc_dev = to_rc_dev(dev);
187 struct nvt_dev *nvt = rc_dev->priv;
188 int fifo_len, duration;
189 unsigned long flags;
190 ssize_t buf_len = 0;
191 int i;
192
193 spin_lock_irqsave(&nvt->nvt_lock, flags);
194
195 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
196 fifo_len = min(fifo_len, WAKEUP_MAX_SIZE);
197
198 /* go to first element to be read */
199 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX))
200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
201
202 for (i = 0; i < fifo_len; i++) {
203 duration = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
204 duration = (duration & BUF_LEN_MASK) * SAMPLE_PERIOD;
205 buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len,
206 "%d ", duration);
207 }
208 buf_len += snprintf(buf + buf_len, PAGE_SIZE - buf_len, "\n");
209
210 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
211
212 return buf_len;
213 }
214
215 static ssize_t wakeup_data_store(struct device *dev,
216 struct device_attribute *attr,
217 const char *buf, size_t len)
218 {
219 struct rc_dev *rc_dev = to_rc_dev(dev);
220 struct nvt_dev *nvt = rc_dev->priv;
221 unsigned long flags;
222 u8 tolerance, config, wake_buf[WAKEUP_MAX_SIZE];
223 char **argv;
224 int i, count;
225 unsigned int val;
226 ssize_t ret;
227
228 argv = argv_split(GFP_KERNEL, buf, &count);
229 if (!argv)
230 return -ENOMEM;
231 if (!count || count > WAKEUP_MAX_SIZE) {
232 ret = -EINVAL;
233 goto out;
234 }
235
236 for (i = 0; i < count; i++) {
237 ret = kstrtouint(argv[i], 10, &val);
238 if (ret)
239 goto out;
240 val = DIV_ROUND_CLOSEST(val, SAMPLE_PERIOD);
241 if (!val || val > 0x7f) {
242 ret = -EINVAL;
243 goto out;
244 }
245 wake_buf[i] = val;
246 /* sequence must start with a pulse */
247 if (i % 2 == 0)
248 wake_buf[i] |= BUF_PULSE_BIT;
249 }
250
251 /* hardcode the tolerance to 10% */
252 tolerance = DIV_ROUND_UP(count, 10);
253
254 spin_lock_irqsave(&nvt->nvt_lock, flags);
255
256 nvt_clear_cir_wake_fifo(nvt);
257 nvt_cir_wake_reg_write(nvt, count, CIR_WAKE_FIFO_CMP_DEEP);
258 nvt_cir_wake_reg_write(nvt, tolerance, CIR_WAKE_FIFO_CMP_TOL);
259
260 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
261
262 /* enable writes to wake fifo */
263 nvt_cir_wake_reg_write(nvt, config | CIR_WAKE_IRCON_MODE1,
264 CIR_WAKE_IRCON);
265
266 for (i = 0; i < count; i++)
267 nvt_cir_wake_reg_write(nvt, wake_buf[i], CIR_WAKE_WR_FIFO_DATA);
268
269 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
270
271 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
272
273 ret = len;
274 out:
275 argv_free(argv);
276 return ret;
277 }
278 static DEVICE_ATTR_RW(wakeup_data);
279
280 /* dump current cir register contents */
281 static void cir_dump_regs(struct nvt_dev *nvt)
282 {
283 nvt_efm_enable(nvt);
284 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
285
286 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
287 pr_info(" * CR CIR ACTIVE : 0x%x\n",
288 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
289 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
290 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
291 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
292 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
293 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
294
295 nvt_efm_disable(nvt);
296
297 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
298 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
299 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
300 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
301 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
302 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
303 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
304 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
305 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
306 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
307 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
308 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
309 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
310 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
311 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
312 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
313 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
314 }
315
316 /* dump current cir wake register contents */
317 static void cir_wake_dump_regs(struct nvt_dev *nvt)
318 {
319 u8 i, fifo_len;
320
321 nvt_efm_enable(nvt);
322 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
323
324 pr_info("%s: Dump CIR WAKE logical device registers:\n",
325 NVT_DRIVER_NAME);
326 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
327 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
328 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
329 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
330 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
331 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
332 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
333
334 nvt_efm_disable(nvt);
335
336 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
337 pr_info(" * IRCON: 0x%x\n",
338 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
339 pr_info(" * IRSTS: 0x%x\n",
340 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
341 pr_info(" * IREN: 0x%x\n",
342 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
343 pr_info(" * FIFO CMP DEEP: 0x%x\n",
344 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
345 pr_info(" * FIFO CMP TOL: 0x%x\n",
346 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
347 pr_info(" * FIFO COUNT: 0x%x\n",
348 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
349 pr_info(" * SLCH: 0x%x\n",
350 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
351 pr_info(" * SLCL: 0x%x\n",
352 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
353 pr_info(" * FIFOCON: 0x%x\n",
354 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
355 pr_info(" * SRXFSTS: 0x%x\n",
356 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
357 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
358 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
359 pr_info(" * WR FIFO DATA: 0x%x\n",
360 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
361 pr_info(" * RD FIFO ONLY: 0x%x\n",
362 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
363 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
364 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
365 pr_info(" * FIFO IGNORE: 0x%x\n",
366 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
367 pr_info(" * IRFSM: 0x%x\n",
368 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
369
370 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
371 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
372 pr_info("* Contents =");
373 for (i = 0; i < fifo_len; i++)
374 pr_cont(" %02x",
375 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
376 pr_cont("\n");
377 }
378
379 static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
380 {
381 int i;
382
383 for (i = 0; i < ARRAY_SIZE(nvt_chips); i++)
384 if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) {
385 nvt->chip_ver = nvt_chips[i].chip_ver;
386 return nvt_chips[i].name;
387 }
388
389 return NULL;
390 }
391
392
393 /* detect hardware features */
394 static int nvt_hw_detect(struct nvt_dev *nvt)
395 {
396 const char *chip_name;
397 int chip_id;
398
399 nvt_efm_enable(nvt);
400
401 /* Check if we're wired for the alternate EFER setup */
402 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
403 if (nvt->chip_major == 0xff) {
404 nvt->cr_efir = CR_EFIR2;
405 nvt->cr_efdr = CR_EFDR2;
406 nvt_efm_enable(nvt);
407 nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
408 }
409 nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
410
411 nvt_efm_disable(nvt);
412
413 chip_id = nvt->chip_major << 8 | nvt->chip_minor;
414 if (chip_id == NVT_INVALID) {
415 dev_err(&nvt->pdev->dev,
416 "No device found on either EFM port\n");
417 return -ENODEV;
418 }
419
420 chip_name = nvt_find_chip(nvt, chip_id);
421
422 /* warn, but still let the driver load, if we don't know this chip */
423 if (!chip_name)
424 dev_warn(&nvt->pdev->dev,
425 "unknown chip, id: 0x%02x 0x%02x, it may not work...",
426 nvt->chip_major, nvt->chip_minor);
427 else
428 dev_info(&nvt->pdev->dev,
429 "found %s or compatible: chip id: 0x%02x 0x%02x",
430 chip_name, nvt->chip_major, nvt->chip_minor);
431
432 return 0;
433 }
434
435 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
436 {
437 u8 val, psreg, psmask, psval;
438
439 if (is_w83667hg(nvt)) {
440 psreg = CR_MULTIFUNC_PIN_SEL;
441 psmask = MULTIFUNC_PIN_SEL_MASK;
442 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
443 } else {
444 psreg = CR_OUTPUT_PIN_SEL;
445 psmask = OUTPUT_PIN_SEL_MASK;
446 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
447 }
448
449 /* output pin selection: enable CIR, with WB sensor enabled */
450 val = nvt_cr_read(nvt, psreg);
451 val &= psmask;
452 val |= psval;
453 nvt_cr_write(nvt, val, psreg);
454
455 /* Select CIR logical device */
456 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
457
458 nvt_set_ioaddr(nvt, &nvt->cir_addr);
459
460 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
461
462 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
463 nvt->cir_addr, nvt->cir_irq);
464 }
465
466 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
467 {
468 /* Select ACPI logical device and anable it */
469 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
470 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
471
472 /* Enable CIR Wake via PSOUT# (Pin60) */
473 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
474
475 /* enable pme interrupt of cir wakeup event */
476 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
477
478 /* Select CIR Wake logical device */
479 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
480
481 nvt_set_ioaddr(nvt, &nvt->cir_wake_addr);
482
483 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx",
484 nvt->cir_wake_addr);
485 }
486
487 /* clear out the hardware's cir rx fifo */
488 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
489 {
490 u8 val;
491
492 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
493 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
494 }
495
496 /* clear out the hardware's cir wake rx fifo */
497 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
498 {
499 u8 val, config;
500
501 config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
502
503 /* clearing wake fifo works in learning mode only */
504 nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0,
505 CIR_WAKE_IRCON);
506
507 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
508 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
509 CIR_WAKE_FIFOCON);
510
511 nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
512 }
513
514 /* clear out the hardware's cir tx fifo */
515 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
516 {
517 u8 val;
518
519 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
520 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
521 }
522
523 /* enable RX Trigger Level Reach and Packet End interrupts */
524 static void nvt_set_cir_iren(struct nvt_dev *nvt)
525 {
526 u8 iren;
527
528 iren = CIR_IREN_RTR | CIR_IREN_PE | CIR_IREN_RFO;
529 nvt_cir_reg_write(nvt, iren, CIR_IREN);
530 }
531
532 static void nvt_cir_regs_init(struct nvt_dev *nvt)
533 {
534 /* set sample limit count (PE interrupt raised when reached) */
535 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
536 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
537
538 /* set fifo irq trigger levels */
539 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
540 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
541
542 /*
543 * Enable TX and RX, specify carrier on = low, off = high, and set
544 * sample period (currently 50us)
545 */
546 nvt_cir_reg_write(nvt,
547 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
548 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
549 CIR_IRCON);
550
551 /* clear hardware rx and tx fifos */
552 nvt_clear_cir_fifo(nvt);
553 nvt_clear_tx_fifo(nvt);
554
555 /* clear any and all stray interrupts */
556 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
557
558 /* and finally, enable interrupts */
559 nvt_set_cir_iren(nvt);
560
561 /* enable the CIR logical device */
562 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
563 }
564
565 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
566 {
567 /* set number of bytes needed for wake from s3 (default 65) */
568 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
569 CIR_WAKE_FIFO_CMP_DEEP);
570
571 /* set tolerance/variance allowed per byte during wake compare */
572 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
573 CIR_WAKE_FIFO_CMP_TOL);
574
575 /* set sample limit count (PE interrupt raised when reached) */
576 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
577 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
578
579 /* set cir wake fifo rx trigger level (currently 67) */
580 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
581 CIR_WAKE_FIFOCON);
582
583 /*
584 * Enable TX and RX, specific carrier on = low, off = high, and set
585 * sample period (currently 50us)
586 */
587 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
588 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
589 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
590 CIR_WAKE_IRCON);
591
592 /* clear cir wake rx fifo */
593 nvt_clear_cir_wake_fifo(nvt);
594
595 /* clear any and all stray interrupts */
596 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
597
598 /* enable the CIR WAKE logical device */
599 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
600 }
601
602 static void nvt_enable_wake(struct nvt_dev *nvt)
603 {
604 unsigned long flags;
605
606 nvt_efm_enable(nvt);
607
608 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
609 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
610 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
611
612 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
613 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
614
615 nvt_efm_disable(nvt);
616
617 spin_lock_irqsave(&nvt->nvt_lock, flags);
618
619 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
620 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
621 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
622 CIR_WAKE_IRCON);
623 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
624 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
625
626 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
627 }
628
629 #if 0 /* Currently unused */
630 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
631 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
632 {
633 u32 count, carrier, duration = 0;
634 int i;
635
636 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
637 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
638
639 for (i = 0; i < nvt->pkts; i++) {
640 if (nvt->buf[i] & BUF_PULSE_BIT)
641 duration += nvt->buf[i] & BUF_LEN_MASK;
642 }
643
644 duration *= SAMPLE_PERIOD;
645
646 if (!count || !duration) {
647 dev_notice(&nvt->pdev->dev,
648 "Unable to determine carrier! (c:%u, d:%u)",
649 count, duration);
650 return 0;
651 }
652
653 carrier = MS_TO_NS(count) / duration;
654
655 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
656 nvt_dbg("WTF? Carrier frequency out of range!");
657
658 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
659 carrier, count, duration);
660
661 return carrier;
662 }
663 #endif
664 /*
665 * set carrier frequency
666 *
667 * set carrier on 2 registers: CP & CC
668 * always set CP as 0x81
669 * set CC by SPEC, CC = 3MHz/carrier - 1
670 */
671 static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
672 {
673 struct nvt_dev *nvt = dev->priv;
674 u16 val;
675
676 if (carrier == 0)
677 return -EINVAL;
678
679 nvt_cir_reg_write(nvt, 1, CIR_CP);
680 val = 3000000 / (carrier) - 1;
681 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
682
683 nvt_dbg("cp: 0x%x cc: 0x%x\n",
684 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
685
686 return 0;
687 }
688
689 /*
690 * nvt_tx_ir
691 *
692 * 1) clean TX fifo first (handled by AP)
693 * 2) copy data from user space
694 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
695 * 4) send 9 packets to TX FIFO to open TTR
696 * in interrupt_handler:
697 * 5) send all data out
698 * go back to write():
699 * 6) disable TX interrupts, re-enable RX interupts
700 *
701 * The key problem of this function is user space data may larger than
702 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
703 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
704 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
705 * set TXFCONT as 0xff, until buf_count less than 0xff.
706 */
707 static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
708 {
709 struct nvt_dev *nvt = dev->priv;
710 unsigned long flags;
711 unsigned int i;
712 u8 iren;
713 int ret;
714
715 spin_lock_irqsave(&nvt->tx.lock, flags);
716
717 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
718 nvt->tx.buf_count = (ret * sizeof(unsigned));
719
720 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
721
722 nvt->tx.cur_buf_num = 0;
723
724 /* save currently enabled interrupts */
725 iren = nvt_cir_reg_read(nvt, CIR_IREN);
726
727 /* now disable all interrupts, save TFU & TTR */
728 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
729
730 nvt->tx.tx_state = ST_TX_REPLY;
731
732 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
733 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
734
735 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
736 for (i = 0; i < 9; i++)
737 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
738
739 spin_unlock_irqrestore(&nvt->tx.lock, flags);
740
741 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
742
743 spin_lock_irqsave(&nvt->tx.lock, flags);
744 nvt->tx.tx_state = ST_TX_NONE;
745 spin_unlock_irqrestore(&nvt->tx.lock, flags);
746
747 /* restore enabled interrupts to prior state */
748 nvt_cir_reg_write(nvt, iren, CIR_IREN);
749
750 return ret;
751 }
752
753 /* dump contents of the last rx buffer we got from the hw rx fifo */
754 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
755 {
756 int i;
757
758 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
759 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
760 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
761 printk(KERN_CONT "\n");
762 }
763
764 /*
765 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
766 * trigger decode when appropriate.
767 *
768 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
769 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
770 * (default 50us) intervals for that pulse/space. A discrete signal is
771 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
772 * to signal more IR coming (repeats) or end of IR, respectively. We store
773 * sample data in the raw event kfifo until we see 0x7<something> (except f)
774 * or 0x80, at which time, we trigger a decode operation.
775 */
776 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
777 {
778 DEFINE_IR_RAW_EVENT(rawir);
779 u8 sample;
780 int i;
781
782 nvt_dbg_verbose("%s firing", __func__);
783
784 if (debug)
785 nvt_dump_rx_buf(nvt);
786
787 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
788
789 init_ir_raw_event(&rawir);
790
791 for (i = 0; i < nvt->pkts; i++) {
792 sample = nvt->buf[i];
793
794 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
795 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
796 * SAMPLE_PERIOD);
797
798 nvt_dbg("Storing %s with duration %d",
799 rawir.pulse ? "pulse" : "space", rawir.duration);
800
801 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
802
803 /*
804 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
805 * indicates end of IR signal, but new data incoming. In both
806 * cases, it means we're ready to call ir_raw_event_handle
807 */
808 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
809 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
810 ir_raw_event_handle(nvt->rdev);
811 }
812 }
813
814 nvt->pkts = 0;
815
816 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
817 ir_raw_event_handle(nvt->rdev);
818
819 nvt_dbg_verbose("%s done", __func__);
820 }
821
822 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
823 {
824 dev_warn(&nvt->pdev->dev, "RX FIFO overrun detected, flushing data!");
825
826 nvt->pkts = 0;
827 nvt_clear_cir_fifo(nvt);
828 ir_raw_event_reset(nvt->rdev);
829 }
830
831 /* copy data from hardware rx fifo into driver buffer */
832 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
833 {
834 u8 fifocount, val;
835 unsigned int b_idx;
836 int i;
837
838 /* Get count of how many bytes to read from RX FIFO */
839 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
840 /* if we get 0xff, probably means the logical dev is disabled */
841 if (fifocount == 0xff)
842 return;
843
844 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
845
846 b_idx = nvt->pkts;
847
848 /* This should never happen, but lets check anyway... */
849 if (b_idx + fifocount > RX_BUF_LEN) {
850 nvt_process_rx_ir_data(nvt);
851 b_idx = 0;
852 }
853
854 /* Read fifocount bytes from CIR Sample RX FIFO register */
855 for (i = 0; i < fifocount; i++) {
856 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
857 nvt->buf[b_idx + i] = val;
858 }
859
860 nvt->pkts += fifocount;
861 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
862
863 nvt_process_rx_ir_data(nvt);
864 }
865
866 static void nvt_cir_log_irqs(u8 status, u8 iren)
867 {
868 nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
869 status, iren,
870 status & CIR_IRSTS_RDR ? " RDR" : "",
871 status & CIR_IRSTS_RTR ? " RTR" : "",
872 status & CIR_IRSTS_PE ? " PE" : "",
873 status & CIR_IRSTS_RFO ? " RFO" : "",
874 status & CIR_IRSTS_TE ? " TE" : "",
875 status & CIR_IRSTS_TTR ? " TTR" : "",
876 status & CIR_IRSTS_TFU ? " TFU" : "",
877 status & CIR_IRSTS_GH ? " GH" : "",
878 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
879 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
880 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
881 }
882
883 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
884 {
885 unsigned long flags;
886 u8 tx_state;
887
888 spin_lock_irqsave(&nvt->tx.lock, flags);
889 tx_state = nvt->tx.tx_state;
890 spin_unlock_irqrestore(&nvt->tx.lock, flags);
891
892 return tx_state == ST_TX_NONE;
893 }
894
895 /* interrupt service routine for incoming and outgoing CIR data */
896 static irqreturn_t nvt_cir_isr(int irq, void *data)
897 {
898 struct nvt_dev *nvt = data;
899 u8 status, iren, cur_state;
900 unsigned long flags;
901
902 nvt_dbg_verbose("%s firing", __func__);
903
904 spin_lock_irqsave(&nvt->nvt_lock, flags);
905
906 /*
907 * Get IR Status register contents. Write 1 to ack/clear
908 *
909 * bit: reg name - description
910 * 7: CIR_IRSTS_RDR - RX Data Ready
911 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
912 * 5: CIR_IRSTS_PE - Packet End
913 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
914 * 3: CIR_IRSTS_TE - TX FIFO Empty
915 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
916 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
917 * 0: CIR_IRSTS_GH - Min Length Detected
918 */
919 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
920 iren = nvt_cir_reg_read(nvt, CIR_IREN);
921
922 /* IRQ may be shared with CIR WAKE, therefore check for each
923 * status bit whether the related interrupt source is enabled
924 */
925 if (!(status & iren)) {
926 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
927 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
928 return IRQ_NONE;
929 }
930
931 /* ack/clear all irq flags we've got */
932 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
933 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
934
935 nvt_cir_log_irqs(status, iren);
936
937 if (status & CIR_IRSTS_RFO)
938 nvt_handle_rx_fifo_overrun(nvt);
939
940 if (status & CIR_IRSTS_RTR) {
941 /* FIXME: add code for study/learn mode */
942 /* We only do rx if not tx'ing */
943 if (nvt_cir_tx_inactive(nvt))
944 nvt_get_rx_ir_data(nvt);
945 }
946
947 if (status & CIR_IRSTS_PE) {
948 if (nvt_cir_tx_inactive(nvt))
949 nvt_get_rx_ir_data(nvt);
950
951 cur_state = nvt->study_state;
952
953 if (cur_state == ST_STUDY_NONE)
954 nvt_clear_cir_fifo(nvt);
955 }
956
957 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
958
959 if (status & CIR_IRSTS_TE)
960 nvt_clear_tx_fifo(nvt);
961
962 if (status & CIR_IRSTS_TTR) {
963 unsigned int pos, count;
964 u8 tmp;
965
966 spin_lock_irqsave(&nvt->tx.lock, flags);
967
968 pos = nvt->tx.cur_buf_num;
969 count = nvt->tx.buf_count;
970
971 /* Write data into the hardware tx fifo while pos < count */
972 if (pos < count) {
973 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
974 nvt->tx.cur_buf_num++;
975 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
976 } else {
977 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
978 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
979 }
980
981 spin_unlock_irqrestore(&nvt->tx.lock, flags);
982
983 }
984
985 if (status & CIR_IRSTS_TFU) {
986 spin_lock_irqsave(&nvt->tx.lock, flags);
987 if (nvt->tx.tx_state == ST_TX_REPLY) {
988 nvt->tx.tx_state = ST_TX_REQUEST;
989 wake_up(&nvt->tx.queue);
990 }
991 spin_unlock_irqrestore(&nvt->tx.lock, flags);
992 }
993
994 nvt_dbg_verbose("%s done", __func__);
995 return IRQ_HANDLED;
996 }
997
998 static void nvt_disable_cir(struct nvt_dev *nvt)
999 {
1000 unsigned long flags;
1001
1002 spin_lock_irqsave(&nvt->nvt_lock, flags);
1003
1004 /* disable CIR interrupts */
1005 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1006
1007 /* clear any and all pending interrupts */
1008 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
1009
1010 /* clear all function enable flags */
1011 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
1012
1013 /* clear hardware rx and tx fifos */
1014 nvt_clear_cir_fifo(nvt);
1015 nvt_clear_tx_fifo(nvt);
1016
1017 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1018
1019 /* disable the CIR logical device */
1020 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
1021 }
1022
1023 static int nvt_open(struct rc_dev *dev)
1024 {
1025 struct nvt_dev *nvt = dev->priv;
1026 unsigned long flags;
1027
1028 spin_lock_irqsave(&nvt->nvt_lock, flags);
1029
1030 /* set function enable flags */
1031 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
1032 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
1033 CIR_IRCON);
1034
1035 /* clear all pending interrupts */
1036 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
1037
1038 /* enable interrupts */
1039 nvt_set_cir_iren(nvt);
1040
1041 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1042
1043 /* enable the CIR logical device */
1044 nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
1045
1046 return 0;
1047 }
1048
1049 static void nvt_close(struct rc_dev *dev)
1050 {
1051 struct nvt_dev *nvt = dev->priv;
1052
1053 nvt_disable_cir(nvt);
1054 }
1055
1056 /* Allocate memory, probe hardware, and initialize everything */
1057 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
1058 {
1059 struct nvt_dev *nvt;
1060 struct rc_dev *rdev;
1061 int ret = -ENOMEM;
1062
1063 nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
1064 if (!nvt)
1065 return ret;
1066
1067 /* input device for IR remote (and tx) */
1068 rdev = rc_allocate_device();
1069 if (!rdev)
1070 goto exit_free_dev_rdev;
1071
1072 ret = -ENODEV;
1073 /* activate pnp device */
1074 if (pnp_activate_dev(pdev) < 0) {
1075 dev_err(&pdev->dev, "Could not activate PNP device!\n");
1076 goto exit_free_dev_rdev;
1077 }
1078
1079 /* validate pnp resources */
1080 if (!pnp_port_valid(pdev, 0) ||
1081 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
1082 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1083 goto exit_free_dev_rdev;
1084 }
1085
1086 if (!pnp_irq_valid(pdev, 0)) {
1087 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1088 goto exit_free_dev_rdev;
1089 }
1090
1091 if (!pnp_port_valid(pdev, 1) ||
1092 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1093 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1094 goto exit_free_dev_rdev;
1095 }
1096
1097 nvt->cir_addr = pnp_port_start(pdev, 0);
1098 nvt->cir_irq = pnp_irq(pdev, 0);
1099
1100 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1101
1102 nvt->cr_efir = CR_EFIR;
1103 nvt->cr_efdr = CR_EFDR;
1104
1105 spin_lock_init(&nvt->nvt_lock);
1106 spin_lock_init(&nvt->tx.lock);
1107
1108 pnp_set_drvdata(pdev, nvt);
1109 nvt->pdev = pdev;
1110
1111 init_waitqueue_head(&nvt->tx.queue);
1112
1113 ret = nvt_hw_detect(nvt);
1114 if (ret)
1115 goto exit_free_dev_rdev;
1116
1117 /* Initialize CIR & CIR Wake Logical Devices */
1118 nvt_efm_enable(nvt);
1119 nvt_cir_ldev_init(nvt);
1120 nvt_cir_wake_ldev_init(nvt);
1121 nvt_efm_disable(nvt);
1122
1123 /*
1124 * Initialize CIR & CIR Wake Config Registers
1125 * and enable logical devices
1126 */
1127 nvt_cir_regs_init(nvt);
1128 nvt_cir_wake_regs_init(nvt);
1129
1130 /* Set up the rc device */
1131 rdev->priv = nvt;
1132 rdev->driver_type = RC_DRIVER_IR_RAW;
1133 rdev->allowed_protocols = RC_BIT_ALL;
1134 rdev->open = nvt_open;
1135 rdev->close = nvt_close;
1136 rdev->tx_ir = nvt_tx_ir;
1137 rdev->s_tx_carrier = nvt_set_tx_carrier;
1138 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1139 rdev->input_phys = "nuvoton/cir0";
1140 rdev->input_id.bustype = BUS_HOST;
1141 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1142 rdev->input_id.product = nvt->chip_major;
1143 rdev->input_id.version = nvt->chip_minor;
1144 rdev->dev.parent = &pdev->dev;
1145 rdev->driver_name = NVT_DRIVER_NAME;
1146 rdev->map_name = RC_MAP_RC6_MCE;
1147 rdev->timeout = MS_TO_NS(100);
1148 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1149 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
1150 #if 0
1151 rdev->min_timeout = XYZ;
1152 rdev->max_timeout = XYZ;
1153 /* tx bits */
1154 rdev->tx_resolution = XYZ;
1155 #endif
1156 nvt->rdev = rdev;
1157
1158 ret = rc_register_device(rdev);
1159 if (ret)
1160 goto exit_free_dev_rdev;
1161
1162 ret = -EBUSY;
1163 /* now claim resources */
1164 if (!devm_request_region(&pdev->dev, nvt->cir_addr,
1165 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1166 goto exit_unregister_device;
1167
1168 if (devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1169 IRQF_SHARED, NVT_DRIVER_NAME, (void *)nvt))
1170 goto exit_unregister_device;
1171
1172 if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
1173 CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake"))
1174 goto exit_unregister_device;
1175
1176 ret = device_create_file(&rdev->dev, &dev_attr_wakeup_data);
1177 if (ret)
1178 goto exit_unregister_device;
1179
1180 device_init_wakeup(&pdev->dev, true);
1181
1182 dev_notice(&pdev->dev, "driver has been successfully loaded\n");
1183 if (debug) {
1184 cir_dump_regs(nvt);
1185 cir_wake_dump_regs(nvt);
1186 }
1187
1188 return 0;
1189
1190 exit_unregister_device:
1191 rc_unregister_device(rdev);
1192 rdev = NULL;
1193 exit_free_dev_rdev:
1194 rc_free_device(rdev);
1195
1196 return ret;
1197 }
1198
1199 static void nvt_remove(struct pnp_dev *pdev)
1200 {
1201 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1202
1203 device_remove_file(&nvt->rdev->dev, &dev_attr_wakeup_data);
1204
1205 nvt_disable_cir(nvt);
1206
1207 /* enable CIR Wake (for IR power-on) */
1208 nvt_enable_wake(nvt);
1209
1210 rc_unregister_device(nvt->rdev);
1211 }
1212
1213 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1214 {
1215 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1216 unsigned long flags;
1217
1218 nvt_dbg("%s called", __func__);
1219
1220 spin_lock_irqsave(&nvt->tx.lock, flags);
1221 nvt->tx.tx_state = ST_TX_NONE;
1222 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1223
1224 spin_lock_irqsave(&nvt->nvt_lock, flags);
1225
1226 /* zero out misc state tracking */
1227 nvt->study_state = ST_STUDY_NONE;
1228 nvt->wake_state = ST_WAKE_NONE;
1229
1230 /* disable all CIR interrupts */
1231 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1232
1233 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1234
1235 /* disable cir logical dev */
1236 nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
1237
1238 /* make sure wake is enabled */
1239 nvt_enable_wake(nvt);
1240
1241 return 0;
1242 }
1243
1244 static int nvt_resume(struct pnp_dev *pdev)
1245 {
1246 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1247
1248 nvt_dbg("%s called", __func__);
1249
1250 nvt_cir_regs_init(nvt);
1251 nvt_cir_wake_regs_init(nvt);
1252
1253 return 0;
1254 }
1255
1256 static void nvt_shutdown(struct pnp_dev *pdev)
1257 {
1258 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1259
1260 nvt_enable_wake(nvt);
1261 }
1262
1263 static const struct pnp_device_id nvt_ids[] = {
1264 { "WEC0530", 0 }, /* CIR */
1265 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1266 { "", 0 },
1267 };
1268
1269 static struct pnp_driver nvt_driver = {
1270 .name = NVT_DRIVER_NAME,
1271 .id_table = nvt_ids,
1272 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1273 .probe = nvt_probe,
1274 .remove = nvt_remove,
1275 .suspend = nvt_suspend,
1276 .resume = nvt_resume,
1277 .shutdown = nvt_shutdown,
1278 };
1279
1280 module_param(debug, int, S_IRUGO | S_IWUSR);
1281 MODULE_PARM_DESC(debug, "Enable debugging output");
1282
1283 MODULE_DEVICE_TABLE(pnp, nvt_ids);
1284 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1285
1286 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1287 MODULE_LICENSE("GPL");
1288
1289 module_pnp_driver(nvt_driver);
Linux kernel - Deliverables
This page took 0.059183 seconds and 5 git commands to generate.