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[media] nuvoton-cir: get rid of warning: no previous prototype
[deliverable/linux.git] / drivers / media / rc / nuvoton-cir.c
1 /*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pnp.h>
33 #include <linux/io.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <media/rc-core.h>
38 #include <linux/pci_ids.h>
39
40 #include "nuvoton-cir.h"
41
42 /* write val to config reg */
43 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
44 {
45 outb(reg, nvt->cr_efir);
46 outb(val, nvt->cr_efdr);
47 }
48
49 /* read val from config reg */
50 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
51 {
52 outb(reg, nvt->cr_efir);
53 return inb(nvt->cr_efdr);
54 }
55
56 /* update config register bit without changing other bits */
57 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
58 {
59 u8 tmp = nvt_cr_read(nvt, reg) | val;
60 nvt_cr_write(nvt, tmp, reg);
61 }
62
63 /* clear config register bit without changing other bits */
64 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
65 {
66 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
67 nvt_cr_write(nvt, tmp, reg);
68 }
69
70 /* enter extended function mode */
71 static inline void nvt_efm_enable(struct nvt_dev *nvt)
72 {
73 /* Enabling Extended Function Mode explicitly requires writing 2x */
74 outb(EFER_EFM_ENABLE, nvt->cr_efir);
75 outb(EFER_EFM_ENABLE, nvt->cr_efir);
76 }
77
78 /* exit extended function mode */
79 static inline void nvt_efm_disable(struct nvt_dev *nvt)
80 {
81 outb(EFER_EFM_DISABLE, nvt->cr_efir);
82 }
83
84 /*
85 * When you want to address a specific logical device, write its logical
86 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
87 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
88 */
89 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
90 {
91 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
92 outb(ldev, nvt->cr_efdr);
93 }
94
95 /* write val to cir config register */
96 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
97 {
98 outb(val, nvt->cir_addr + offset);
99 }
100
101 /* read val from cir config register */
102 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
103 {
104 u8 val;
105
106 val = inb(nvt->cir_addr + offset);
107
108 return val;
109 }
110
111 /* write val to cir wake register */
112 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
113 u8 val, u8 offset)
114 {
115 outb(val, nvt->cir_wake_addr + offset);
116 }
117
118 /* read val from cir wake config register */
119 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
120 {
121 u8 val;
122
123 val = inb(nvt->cir_wake_addr + offset);
124
125 return val;
126 }
127
128 /* dump current cir register contents */
129 static void cir_dump_regs(struct nvt_dev *nvt)
130 {
131 nvt_efm_enable(nvt);
132 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
133
134 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
135 pr_info(" * CR CIR ACTIVE : 0x%x\n",
136 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
137 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
138 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
139 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
140 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
141 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
142
143 nvt_efm_disable(nvt);
144
145 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
146 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
147 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
148 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
149 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
150 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
151 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
152 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
153 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
154 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
155 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
156 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
157 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
158 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
159 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
160 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
161 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
162 }
163
164 /* dump current cir wake register contents */
165 static void cir_wake_dump_regs(struct nvt_dev *nvt)
166 {
167 u8 i, fifo_len;
168
169 nvt_efm_enable(nvt);
170 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
171
172 pr_info("%s: Dump CIR WAKE logical device registers:\n",
173 NVT_DRIVER_NAME);
174 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
175 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
176 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
177 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
178 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
179 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
180 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
181
182 nvt_efm_disable(nvt);
183
184 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
185 pr_info(" * IRCON: 0x%x\n",
186 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
187 pr_info(" * IRSTS: 0x%x\n",
188 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
189 pr_info(" * IREN: 0x%x\n",
190 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
191 pr_info(" * FIFO CMP DEEP: 0x%x\n",
192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
193 pr_info(" * FIFO CMP TOL: 0x%x\n",
194 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
195 pr_info(" * FIFO COUNT: 0x%x\n",
196 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
197 pr_info(" * SLCH: 0x%x\n",
198 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
199 pr_info(" * SLCL: 0x%x\n",
200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
201 pr_info(" * FIFOCON: 0x%x\n",
202 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
203 pr_info(" * SRXFSTS: 0x%x\n",
204 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
205 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
206 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
207 pr_info(" * WR FIFO DATA: 0x%x\n",
208 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
209 pr_info(" * RD FIFO ONLY: 0x%x\n",
210 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
211 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
212 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
213 pr_info(" * FIFO IGNORE: 0x%x\n",
214 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
215 pr_info(" * IRFSM: 0x%x\n",
216 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
217
218 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
219 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
220 pr_info("* Contents =");
221 for (i = 0; i < fifo_len; i++)
222 pr_cont(" %02x",
223 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
224 pr_cont("\n");
225 }
226
227 /* detect hardware features */
228 static int nvt_hw_detect(struct nvt_dev *nvt)
229 {
230 unsigned long flags;
231 u8 chip_major, chip_minor;
232 int ret = 0;
233 char chip_id[12];
234 bool chip_unknown = false;
235
236 nvt_efm_enable(nvt);
237
238 /* Check if we're wired for the alternate EFER setup */
239 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
240 if (chip_major == 0xff) {
241 nvt->cr_efir = CR_EFIR2;
242 nvt->cr_efdr = CR_EFDR2;
243 nvt_efm_enable(nvt);
244 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
245 }
246
247 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
248
249 /* these are the known working chip revisions... */
250 switch (chip_major) {
251 case CHIP_ID_HIGH_667:
252 strcpy(chip_id, "w83667hg\0");
253 if (chip_minor != CHIP_ID_LOW_667)
254 chip_unknown = true;
255 break;
256 case CHIP_ID_HIGH_677B:
257 strcpy(chip_id, "w83677hg\0");
258 if (chip_minor != CHIP_ID_LOW_677B2 &&
259 chip_minor != CHIP_ID_LOW_677B3)
260 chip_unknown = true;
261 break;
262 case CHIP_ID_HIGH_677C:
263 strcpy(chip_id, "w83677hg-c\0");
264 if (chip_minor != CHIP_ID_LOW_677C)
265 chip_unknown = true;
266 break;
267 default:
268 strcpy(chip_id, "w836x7hg\0");
269 chip_unknown = true;
270 break;
271 }
272
273 /* warn, but still let the driver load, if we don't know this chip */
274 if (chip_unknown)
275 nvt_pr(KERN_WARNING, "%s: unknown chip, id: 0x%02x 0x%02x, "
276 "it may not work...", chip_id, chip_major, chip_minor);
277 else
278 nvt_dbg("%s: chip id: 0x%02x 0x%02x",
279 chip_id, chip_major, chip_minor);
280
281 nvt_efm_disable(nvt);
282
283 spin_lock_irqsave(&nvt->nvt_lock, flags);
284 nvt->chip_major = chip_major;
285 nvt->chip_minor = chip_minor;
286 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
287
288 return ret;
289 }
290
291 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
292 {
293 u8 val, psreg, psmask, psval;
294
295 if (nvt->chip_major == CHIP_ID_HIGH_667) {
296 psreg = CR_MULTIFUNC_PIN_SEL;
297 psmask = MULTIFUNC_PIN_SEL_MASK;
298 psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
299 } else {
300 psreg = CR_OUTPUT_PIN_SEL;
301 psmask = OUTPUT_PIN_SEL_MASK;
302 psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
303 }
304
305 /* output pin selection: enable CIR, with WB sensor enabled */
306 val = nvt_cr_read(nvt, psreg);
307 val &= psmask;
308 val |= psval;
309 nvt_cr_write(nvt, val, psreg);
310
311 /* Select CIR logical device and enable */
312 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
313 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
314
315 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
316 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
317
318 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
319
320 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
321 nvt->cir_addr, nvt->cir_irq);
322 }
323
324 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
325 {
326 /* Select ACPI logical device, enable it and CIR Wake */
327 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
328 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
329
330 /* Enable CIR Wake via PSOUT# (Pin60) */
331 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
332
333 /* enable cir interrupt of mouse/keyboard IRQ event */
334 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
335
336 /* enable pme interrupt of cir wakeup event */
337 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
338
339 /* Select CIR Wake logical device and enable */
340 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
341 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
342
343 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
344 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
345
346 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
347
348 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
349 nvt->cir_wake_addr, nvt->cir_wake_irq);
350 }
351
352 /* clear out the hardware's cir rx fifo */
353 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
354 {
355 u8 val;
356
357 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
358 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
359 }
360
361 /* clear out the hardware's cir wake rx fifo */
362 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
363 {
364 u8 val;
365
366 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
367 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
368 CIR_WAKE_FIFOCON);
369 }
370
371 /* clear out the hardware's cir tx fifo */
372 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
373 {
374 u8 val;
375
376 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
377 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
378 }
379
380 /* enable RX Trigger Level Reach and Packet End interrupts */
381 static void nvt_set_cir_iren(struct nvt_dev *nvt)
382 {
383 u8 iren;
384
385 iren = CIR_IREN_RTR | CIR_IREN_PE;
386 nvt_cir_reg_write(nvt, iren, CIR_IREN);
387 }
388
389 static void nvt_cir_regs_init(struct nvt_dev *nvt)
390 {
391 /* set sample limit count (PE interrupt raised when reached) */
392 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
393 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
394
395 /* set fifo irq trigger levels */
396 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
397 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
398
399 /*
400 * Enable TX and RX, specify carrier on = low, off = high, and set
401 * sample period (currently 50us)
402 */
403 nvt_cir_reg_write(nvt,
404 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
405 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
406 CIR_IRCON);
407
408 /* clear hardware rx and tx fifos */
409 nvt_clear_cir_fifo(nvt);
410 nvt_clear_tx_fifo(nvt);
411
412 /* clear any and all stray interrupts */
413 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
414
415 /* and finally, enable interrupts */
416 nvt_set_cir_iren(nvt);
417 }
418
419 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
420 {
421 /* set number of bytes needed for wake from s3 (default 65) */
422 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_CMP_BYTES,
423 CIR_WAKE_FIFO_CMP_DEEP);
424
425 /* set tolerance/variance allowed per byte during wake compare */
426 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
427 CIR_WAKE_FIFO_CMP_TOL);
428
429 /* set sample limit count (PE interrupt raised when reached) */
430 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
431 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
432
433 /* set cir wake fifo rx trigger level (currently 67) */
434 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
435 CIR_WAKE_FIFOCON);
436
437 /*
438 * Enable TX and RX, specific carrier on = low, off = high, and set
439 * sample period (currently 50us)
440 */
441 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
442 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
443 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
444 CIR_WAKE_IRCON);
445
446 /* clear cir wake rx fifo */
447 nvt_clear_cir_wake_fifo(nvt);
448
449 /* clear any and all stray interrupts */
450 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
451 }
452
453 static void nvt_enable_wake(struct nvt_dev *nvt)
454 {
455 nvt_efm_enable(nvt);
456
457 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
458 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
459 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
460 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
461
462 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
463 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
464
465 nvt_efm_disable(nvt);
466
467 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
468 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
469 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
470 CIR_WAKE_IRCON);
471 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
472 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
473 }
474
475 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
476 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
477 {
478 u32 count, carrier, duration = 0;
479 int i;
480
481 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
482 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
483
484 for (i = 0; i < nvt->pkts; i++) {
485 if (nvt->buf[i] & BUF_PULSE_BIT)
486 duration += nvt->buf[i] & BUF_LEN_MASK;
487 }
488
489 duration *= SAMPLE_PERIOD;
490
491 if (!count || !duration) {
492 nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)",
493 count, duration);
494 return 0;
495 }
496
497 carrier = MS_TO_NS(count) / duration;
498
499 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
500 nvt_dbg("WTF? Carrier frequency out of range!");
501
502 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
503 carrier, count, duration);
504
505 return carrier;
506 }
507
508 /*
509 * set carrier frequency
510 *
511 * set carrier on 2 registers: CP & CC
512 * always set CP as 0x81
513 * set CC by SPEC, CC = 3MHz/carrier - 1
514 */
515 static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
516 {
517 struct nvt_dev *nvt = dev->priv;
518 u16 val;
519
520 if (carrier == 0)
521 return -EINVAL;
522
523 nvt_cir_reg_write(nvt, 1, CIR_CP);
524 val = 3000000 / (carrier) - 1;
525 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
526
527 nvt_dbg("cp: 0x%x cc: 0x%x\n",
528 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
529
530 return 0;
531 }
532
533 /*
534 * nvt_tx_ir
535 *
536 * 1) clean TX fifo first (handled by AP)
537 * 2) copy data from user space
538 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
539 * 4) send 9 packets to TX FIFO to open TTR
540 * in interrupt_handler:
541 * 5) send all data out
542 * go back to write():
543 * 6) disable TX interrupts, re-enable RX interupts
544 *
545 * The key problem of this function is user space data may larger than
546 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
547 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
548 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
549 * set TXFCONT as 0xff, until buf_count less than 0xff.
550 */
551 static int nvt_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned n)
552 {
553 struct nvt_dev *nvt = dev->priv;
554 unsigned long flags;
555 unsigned int i;
556 u8 iren;
557 int ret;
558
559 spin_lock_irqsave(&nvt->tx.lock, flags);
560
561 ret = min((unsigned)(TX_BUF_LEN / sizeof(unsigned)), n);
562 nvt->tx.buf_count = (ret * sizeof(unsigned));
563
564 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
565
566 nvt->tx.cur_buf_num = 0;
567
568 /* save currently enabled interrupts */
569 iren = nvt_cir_reg_read(nvt, CIR_IREN);
570
571 /* now disable all interrupts, save TFU & TTR */
572 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
573
574 nvt->tx.tx_state = ST_TX_REPLY;
575
576 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
577 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
578
579 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
580 for (i = 0; i < 9; i++)
581 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
582
583 spin_unlock_irqrestore(&nvt->tx.lock, flags);
584
585 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
586
587 spin_lock_irqsave(&nvt->tx.lock, flags);
588 nvt->tx.tx_state = ST_TX_NONE;
589 spin_unlock_irqrestore(&nvt->tx.lock, flags);
590
591 /* restore enabled interrupts to prior state */
592 nvt_cir_reg_write(nvt, iren, CIR_IREN);
593
594 return ret;
595 }
596
597 /* dump contents of the last rx buffer we got from the hw rx fifo */
598 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
599 {
600 int i;
601
602 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
603 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
604 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
605 printk(KERN_CONT "\n");
606 }
607
608 /*
609 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
610 * trigger decode when appropriate.
611 *
612 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
613 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
614 * (default 50us) intervals for that pulse/space. A discrete signal is
615 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
616 * to signal more IR coming (repeats) or end of IR, respectively. We store
617 * sample data in the raw event kfifo until we see 0x7<something> (except f)
618 * or 0x80, at which time, we trigger a decode operation.
619 */
620 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
621 {
622 DEFINE_IR_RAW_EVENT(rawir);
623 u32 carrier;
624 u8 sample;
625 int i;
626
627 nvt_dbg_verbose("%s firing", __func__);
628
629 if (debug)
630 nvt_dump_rx_buf(nvt);
631
632 if (nvt->carrier_detect_enabled)
633 carrier = nvt_rx_carrier_detect(nvt);
634
635 nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
636
637 init_ir_raw_event(&rawir);
638
639 for (i = 0; i < nvt->pkts; i++) {
640 sample = nvt->buf[i];
641
642 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
643 rawir.duration = US_TO_NS((sample & BUF_LEN_MASK)
644 * SAMPLE_PERIOD);
645
646 nvt_dbg("Storing %s with duration %d",
647 rawir.pulse ? "pulse" : "space", rawir.duration);
648
649 ir_raw_event_store_with_filter(nvt->rdev, &rawir);
650
651 /*
652 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
653 * indicates end of IR signal, but new data incoming. In both
654 * cases, it means we're ready to call ir_raw_event_handle
655 */
656 if ((sample == BUF_PULSE_BIT) && (i + 1 < nvt->pkts)) {
657 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
658 ir_raw_event_handle(nvt->rdev);
659 }
660 }
661
662 nvt->pkts = 0;
663
664 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
665 ir_raw_event_handle(nvt->rdev);
666
667 nvt_dbg_verbose("%s done", __func__);
668 }
669
670 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
671 {
672 nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!");
673
674 nvt->pkts = 0;
675 nvt_clear_cir_fifo(nvt);
676 ir_raw_event_reset(nvt->rdev);
677 }
678
679 /* copy data from hardware rx fifo into driver buffer */
680 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
681 {
682 unsigned long flags;
683 u8 fifocount, val;
684 unsigned int b_idx;
685 bool overrun = false;
686 int i;
687
688 /* Get count of how many bytes to read from RX FIFO */
689 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
690 /* if we get 0xff, probably means the logical dev is disabled */
691 if (fifocount == 0xff)
692 return;
693 /* watch out for a fifo overrun condition */
694 else if (fifocount > RX_BUF_LEN) {
695 overrun = true;
696 fifocount = RX_BUF_LEN;
697 }
698
699 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
700
701 spin_lock_irqsave(&nvt->nvt_lock, flags);
702
703 b_idx = nvt->pkts;
704
705 /* This should never happen, but lets check anyway... */
706 if (b_idx + fifocount > RX_BUF_LEN) {
707 nvt_process_rx_ir_data(nvt);
708 b_idx = 0;
709 }
710
711 /* Read fifocount bytes from CIR Sample RX FIFO register */
712 for (i = 0; i < fifocount; i++) {
713 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
714 nvt->buf[b_idx + i] = val;
715 }
716
717 nvt->pkts += fifocount;
718 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
719
720 nvt_process_rx_ir_data(nvt);
721
722 if (overrun)
723 nvt_handle_rx_fifo_overrun(nvt);
724
725 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
726 }
727
728 static void nvt_cir_log_irqs(u8 status, u8 iren)
729 {
730 nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
731 status, iren,
732 status & CIR_IRSTS_RDR ? " RDR" : "",
733 status & CIR_IRSTS_RTR ? " RTR" : "",
734 status & CIR_IRSTS_PE ? " PE" : "",
735 status & CIR_IRSTS_RFO ? " RFO" : "",
736 status & CIR_IRSTS_TE ? " TE" : "",
737 status & CIR_IRSTS_TTR ? " TTR" : "",
738 status & CIR_IRSTS_TFU ? " TFU" : "",
739 status & CIR_IRSTS_GH ? " GH" : "",
740 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
741 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
742 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
743 }
744
745 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
746 {
747 unsigned long flags;
748 bool tx_inactive;
749 u8 tx_state;
750
751 spin_lock_irqsave(&nvt->tx.lock, flags);
752 tx_state = nvt->tx.tx_state;
753 spin_unlock_irqrestore(&nvt->tx.lock, flags);
754
755 tx_inactive = (tx_state == ST_TX_NONE);
756
757 return tx_inactive;
758 }
759
760 /* interrupt service routine for incoming and outgoing CIR data */
761 static irqreturn_t nvt_cir_isr(int irq, void *data)
762 {
763 struct nvt_dev *nvt = data;
764 u8 status, iren, cur_state;
765 unsigned long flags;
766
767 nvt_dbg_verbose("%s firing", __func__);
768
769 nvt_efm_enable(nvt);
770 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
771 nvt_efm_disable(nvt);
772
773 /*
774 * Get IR Status register contents. Write 1 to ack/clear
775 *
776 * bit: reg name - description
777 * 7: CIR_IRSTS_RDR - RX Data Ready
778 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
779 * 5: CIR_IRSTS_PE - Packet End
780 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
781 * 3: CIR_IRSTS_TE - TX FIFO Empty
782 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
783 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
784 * 0: CIR_IRSTS_GH - Min Length Detected
785 */
786 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
787 if (!status) {
788 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
789 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
790 return IRQ_RETVAL(IRQ_NONE);
791 }
792
793 /* ack/clear all irq flags we've got */
794 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
795 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
796
797 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
798 iren = nvt_cir_reg_read(nvt, CIR_IREN);
799 if (!iren) {
800 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
801 return IRQ_RETVAL(IRQ_NONE);
802 }
803
804 if (debug)
805 nvt_cir_log_irqs(status, iren);
806
807 if (status & CIR_IRSTS_RTR) {
808 /* FIXME: add code for study/learn mode */
809 /* We only do rx if not tx'ing */
810 if (nvt_cir_tx_inactive(nvt))
811 nvt_get_rx_ir_data(nvt);
812 }
813
814 if (status & CIR_IRSTS_PE) {
815 if (nvt_cir_tx_inactive(nvt))
816 nvt_get_rx_ir_data(nvt);
817
818 spin_lock_irqsave(&nvt->nvt_lock, flags);
819
820 cur_state = nvt->study_state;
821
822 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
823
824 if (cur_state == ST_STUDY_NONE)
825 nvt_clear_cir_fifo(nvt);
826 }
827
828 if (status & CIR_IRSTS_TE)
829 nvt_clear_tx_fifo(nvt);
830
831 if (status & CIR_IRSTS_TTR) {
832 unsigned int pos, count;
833 u8 tmp;
834
835 spin_lock_irqsave(&nvt->tx.lock, flags);
836
837 pos = nvt->tx.cur_buf_num;
838 count = nvt->tx.buf_count;
839
840 /* Write data into the hardware tx fifo while pos < count */
841 if (pos < count) {
842 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
843 nvt->tx.cur_buf_num++;
844 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
845 } else {
846 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
847 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
848 }
849
850 spin_unlock_irqrestore(&nvt->tx.lock, flags);
851
852 }
853
854 if (status & CIR_IRSTS_TFU) {
855 spin_lock_irqsave(&nvt->tx.lock, flags);
856 if (nvt->tx.tx_state == ST_TX_REPLY) {
857 nvt->tx.tx_state = ST_TX_REQUEST;
858 wake_up(&nvt->tx.queue);
859 }
860 spin_unlock_irqrestore(&nvt->tx.lock, flags);
861 }
862
863 nvt_dbg_verbose("%s done", __func__);
864 return IRQ_RETVAL(IRQ_HANDLED);
865 }
866
867 /* Interrupt service routine for CIR Wake */
868 static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
869 {
870 u8 status, iren, val;
871 struct nvt_dev *nvt = data;
872 unsigned long flags;
873
874 nvt_dbg_wake("%s firing", __func__);
875
876 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
877 if (!status)
878 return IRQ_RETVAL(IRQ_NONE);
879
880 if (status & CIR_WAKE_IRSTS_IR_PENDING)
881 nvt_clear_cir_wake_fifo(nvt);
882
883 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
884 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
885
886 /* Interrupt may be shared with CIR, bail if Wake not enabled */
887 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
888 if (!iren) {
889 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
890 return IRQ_RETVAL(IRQ_HANDLED);
891 }
892
893 if ((status & CIR_WAKE_IRSTS_PE) &&
894 (nvt->wake_state == ST_WAKE_START)) {
895 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
896 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
897 nvt_dbg("setting wake up key: 0x%x", val);
898 }
899
900 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
901 spin_lock_irqsave(&nvt->nvt_lock, flags);
902 nvt->wake_state = ST_WAKE_FINISH;
903 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
904 }
905
906 nvt_dbg_wake("%s done", __func__);
907 return IRQ_RETVAL(IRQ_HANDLED);
908 }
909
910 static void nvt_enable_cir(struct nvt_dev *nvt)
911 {
912 /* set function enable flags */
913 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
914 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
915 CIR_IRCON);
916
917 nvt_efm_enable(nvt);
918
919 /* enable the CIR logical device */
920 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
921 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
922
923 nvt_efm_disable(nvt);
924
925 /* clear all pending interrupts */
926 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
927
928 /* enable interrupts */
929 nvt_set_cir_iren(nvt);
930 }
931
932 static void nvt_disable_cir(struct nvt_dev *nvt)
933 {
934 /* disable CIR interrupts */
935 nvt_cir_reg_write(nvt, 0, CIR_IREN);
936
937 /* clear any and all pending interrupts */
938 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
939
940 /* clear all function enable flags */
941 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
942
943 /* clear hardware rx and tx fifos */
944 nvt_clear_cir_fifo(nvt);
945 nvt_clear_tx_fifo(nvt);
946
947 nvt_efm_enable(nvt);
948
949 /* disable the CIR logical device */
950 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
951 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
952
953 nvt_efm_disable(nvt);
954 }
955
956 static int nvt_open(struct rc_dev *dev)
957 {
958 struct nvt_dev *nvt = dev->priv;
959 unsigned long flags;
960
961 spin_lock_irqsave(&nvt->nvt_lock, flags);
962 nvt_enable_cir(nvt);
963 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
964
965 return 0;
966 }
967
968 static void nvt_close(struct rc_dev *dev)
969 {
970 struct nvt_dev *nvt = dev->priv;
971 unsigned long flags;
972
973 spin_lock_irqsave(&nvt->nvt_lock, flags);
974 nvt_disable_cir(nvt);
975 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
976 }
977
978 /* Allocate memory, probe hardware, and initialize everything */
979 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
980 {
981 struct nvt_dev *nvt;
982 struct rc_dev *rdev;
983 int ret = -ENOMEM;
984
985 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL);
986 if (!nvt)
987 return ret;
988
989 /* input device for IR remote (and tx) */
990 rdev = rc_allocate_device();
991 if (!rdev)
992 goto failure;
993
994 ret = -ENODEV;
995 /* validate pnp resources */
996 if (!pnp_port_valid(pdev, 0) ||
997 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
998 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
999 goto failure;
1000 }
1001
1002 if (!pnp_irq_valid(pdev, 0)) {
1003 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1004 goto failure;
1005 }
1006
1007 if (!pnp_port_valid(pdev, 1) ||
1008 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1009 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1010 goto failure;
1011 }
1012
1013 nvt->cir_addr = pnp_port_start(pdev, 0);
1014 nvt->cir_irq = pnp_irq(pdev, 0);
1015
1016 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1017 /* irq is always shared between cir and cir wake */
1018 nvt->cir_wake_irq = nvt->cir_irq;
1019
1020 nvt->cr_efir = CR_EFIR;
1021 nvt->cr_efdr = CR_EFDR;
1022
1023 spin_lock_init(&nvt->nvt_lock);
1024 spin_lock_init(&nvt->tx.lock);
1025
1026 pnp_set_drvdata(pdev, nvt);
1027 nvt->pdev = pdev;
1028
1029 init_waitqueue_head(&nvt->tx.queue);
1030
1031 ret = nvt_hw_detect(nvt);
1032 if (ret)
1033 goto failure;
1034
1035 /* Initialize CIR & CIR Wake Logical Devices */
1036 nvt_efm_enable(nvt);
1037 nvt_cir_ldev_init(nvt);
1038 nvt_cir_wake_ldev_init(nvt);
1039 nvt_efm_disable(nvt);
1040
1041 /* Initialize CIR & CIR Wake Config Registers */
1042 nvt_cir_regs_init(nvt);
1043 nvt_cir_wake_regs_init(nvt);
1044
1045 /* Set up the rc device */
1046 rdev->priv = nvt;
1047 rdev->driver_type = RC_DRIVER_IR_RAW;
1048 rdev->allowed_protos = RC_BIT_ALL;
1049 rdev->open = nvt_open;
1050 rdev->close = nvt_close;
1051 rdev->tx_ir = nvt_tx_ir;
1052 rdev->s_tx_carrier = nvt_set_tx_carrier;
1053 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1054 rdev->input_phys = "nuvoton/cir0";
1055 rdev->input_id.bustype = BUS_HOST;
1056 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1057 rdev->input_id.product = nvt->chip_major;
1058 rdev->input_id.version = nvt->chip_minor;
1059 rdev->dev.parent = &pdev->dev;
1060 rdev->driver_name = NVT_DRIVER_NAME;
1061 rdev->map_name = RC_MAP_RC6_MCE;
1062 rdev->timeout = MS_TO_NS(100);
1063 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1064 rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
1065 #if 0
1066 rdev->min_timeout = XYZ;
1067 rdev->max_timeout = XYZ;
1068 /* tx bits */
1069 rdev->tx_resolution = XYZ;
1070 #endif
1071
1072 ret = -EBUSY;
1073 /* now claim resources */
1074 if (!request_region(nvt->cir_addr,
1075 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1076 goto failure;
1077
1078 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED,
1079 NVT_DRIVER_NAME, (void *)nvt))
1080 goto failure2;
1081
1082 if (!request_region(nvt->cir_wake_addr,
1083 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1084 goto failure3;
1085
1086 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED,
1087 NVT_DRIVER_NAME, (void *)nvt))
1088 goto failure4;
1089
1090 ret = rc_register_device(rdev);
1091 if (ret)
1092 goto failure5;
1093
1094 device_init_wakeup(&pdev->dev, true);
1095 nvt->rdev = rdev;
1096 nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1097 if (debug) {
1098 cir_dump_regs(nvt);
1099 cir_wake_dump_regs(nvt);
1100 }
1101
1102 return 0;
1103
1104 failure5:
1105 free_irq(nvt->cir_wake_irq, nvt);
1106 failure4:
1107 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1108 failure3:
1109 free_irq(nvt->cir_irq, nvt);
1110 failure2:
1111 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1112 failure:
1113 rc_free_device(rdev);
1114 kfree(nvt);
1115
1116 return ret;
1117 }
1118
1119 static void __devexit nvt_remove(struct pnp_dev *pdev)
1120 {
1121 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1122 unsigned long flags;
1123
1124 spin_lock_irqsave(&nvt->nvt_lock, flags);
1125 /* disable CIR */
1126 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1127 nvt_disable_cir(nvt);
1128 /* enable CIR Wake (for IR power-on) */
1129 nvt_enable_wake(nvt);
1130 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1131
1132 /* free resources */
1133 free_irq(nvt->cir_irq, nvt);
1134 free_irq(nvt->cir_wake_irq, nvt);
1135 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1136 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1137
1138 rc_unregister_device(nvt->rdev);
1139
1140 kfree(nvt);
1141 }
1142
1143 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1144 {
1145 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1146 unsigned long flags;
1147
1148 nvt_dbg("%s called", __func__);
1149
1150 /* zero out misc state tracking */
1151 spin_lock_irqsave(&nvt->nvt_lock, flags);
1152 nvt->study_state = ST_STUDY_NONE;
1153 nvt->wake_state = ST_WAKE_NONE;
1154 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1155
1156 spin_lock_irqsave(&nvt->tx.lock, flags);
1157 nvt->tx.tx_state = ST_TX_NONE;
1158 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1159
1160 /* disable all CIR interrupts */
1161 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1162
1163 nvt_efm_enable(nvt);
1164
1165 /* disable cir logical dev */
1166 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1167 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1168
1169 nvt_efm_disable(nvt);
1170
1171 /* make sure wake is enabled */
1172 nvt_enable_wake(nvt);
1173
1174 return 0;
1175 }
1176
1177 static int nvt_resume(struct pnp_dev *pdev)
1178 {
1179 int ret = 0;
1180 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1181
1182 nvt_dbg("%s called", __func__);
1183
1184 /* open interrupt */
1185 nvt_set_cir_iren(nvt);
1186
1187 /* Enable CIR logical device */
1188 nvt_efm_enable(nvt);
1189 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1190 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1191
1192 nvt_efm_disable(nvt);
1193
1194 nvt_cir_regs_init(nvt);
1195 nvt_cir_wake_regs_init(nvt);
1196
1197 return ret;
1198 }
1199
1200 static void nvt_shutdown(struct pnp_dev *pdev)
1201 {
1202 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1203 nvt_enable_wake(nvt);
1204 }
1205
1206 static const struct pnp_device_id nvt_ids[] = {
1207 { "WEC0530", 0 }, /* CIR */
1208 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1209 { "", 0 },
1210 };
1211
1212 static struct pnp_driver nvt_driver = {
1213 .name = NVT_DRIVER_NAME,
1214 .id_table = nvt_ids,
1215 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1216 .probe = nvt_probe,
1217 .remove = __devexit_p(nvt_remove),
1218 .suspend = nvt_suspend,
1219 .resume = nvt_resume,
1220 .shutdown = nvt_shutdown,
1221 };
1222
1223 static int nvt_init(void)
1224 {
1225 return pnp_register_driver(&nvt_driver);
1226 }
1227
1228 static void nvt_exit(void)
1229 {
1230 pnp_unregister_driver(&nvt_driver);
1231 }
1232
1233 module_param(debug, int, S_IRUGO | S_IWUSR);
1234 MODULE_PARM_DESC(debug, "Enable debugging output");
1235
1236 MODULE_DEVICE_TABLE(pnp, nvt_ids);
1237 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1238
1239 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1240 MODULE_LICENSE("GPL");
1241
1242 module_init(nvt_init);
1243 module_exit(nvt_exit);
Linux kernel - Deliverables
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