drivers/media/rc/nuvoton-cir.h

   1 /*
   2  * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
   3  *
   4  * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
   5  * Copyright (C) 2009 Nuvoton PS Team
   6  *
   7  * Special thanks to Nuvoton for providing hardware, spec sheets and
   8  * sample code upon which portions of this driver are based. Indirect
   9  * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
  10  * modeled after.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of the
  15  * License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful, but
  18  * WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  20  * General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  25  * USA
  26  */
  27
  28 #include <linux/spinlock.h>
  29 #include <linux/ioctl.h>
  30
  31 /* platform driver name to register */
  32 #define NVT_DRIVER_NAME "nuvoton-cir"
  33
  34 /* debugging module parameter */
  35 static int debug;
  36
  37
  38 #define nvt_dbg(text, ...) \
  39         if (debug) \
  40                 printk(KERN_DEBUG \
  41                         KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  42
  43 #define nvt_dbg_verbose(text, ...) \
  44         if (debug > 1) \
  45                 printk(KERN_DEBUG \
  46                         KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  47
  48 #define nvt_dbg_wake(text, ...) \
  49         if (debug > 2) \
  50                 printk(KERN_DEBUG \
  51                         KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
  52
  53
  54 /*
  55  * Original lirc driver said min value of 76, and recommended value of 256
  56  * for the buffer length, but then used 2048. Never mind that the size of the
  57  * RX FIFO is 32 bytes... So I'm using 32 for RX and 256 for TX atm, but I'm
  58  * not sure if maybe that TX value is off by a factor of 8 (bits vs. bytes),
  59  * and I don't have TX-capable hardware to test/debug on...
  60  */
  61 #define TX_BUF_LEN 256
  62 #define RX_BUF_LEN 32
  63
  64 #define SIO_ID_MASK 0xfff0
  65
  66 enum nvt_chip_ver {
  67         NVT_UNKNOWN     = 0,
  68         NVT_W83667HG    = 0xa510,
  69         NVT_6775F       = 0xb470,
  70         NVT_6776F       = 0xc330,
  71         NVT_6779D       = 0xc560
  72 };
  73
  74 struct nvt_chip {
  75         const char *name;
  76         enum nvt_chip_ver chip_ver;
  77 };
  78
  79 struct nvt_dev {
  80         struct pnp_dev *pdev;
  81         struct rc_dev *rdev;
  82
  83         spinlock_t nvt_lock;
  84
  85         /* for rx */
  86         u8 buf[RX_BUF_LEN];
  87         unsigned int pkts;
  88
  89         struct {
  90                 spinlock_t lock;
  91                 u8 buf[TX_BUF_LEN];
  92                 unsigned int buf_count;
  93                 unsigned int cur_buf_num;
  94                 wait_queue_head_t queue;
  95                 u8 tx_state;
  96         } tx;
  97
  98         /* EFER Config register index/data pair */
  99         u32 cr_efir;
 100         u32 cr_efdr;
 101
 102         /* hardware I/O settings */
 103         unsigned long cir_addr;
 104         unsigned long cir_wake_addr;
 105         int cir_irq;
 106         int cir_wake_irq;
 107
 108         enum nvt_chip_ver chip_ver;
 109         /* hardware id */
 110         u8 chip_major;
 111         u8 chip_minor;
 112
 113         /* hardware features */
 114         bool hw_learning_capable;
 115         bool hw_tx_capable;
 116
 117         /* rx settings */
 118         bool learning_enabled;
 119
 120         /* track cir wake state */
 121         u8 wake_state;
 122         /* for study */
 123         u8 study_state;
 124         /* carrier period = 1 / frequency */
 125         u32 carrier;
 126 };
 127
 128 /* study states */
 129 #define ST_STUDY_NONE      0x0
 130 #define ST_STUDY_START     0x1
 131 #define ST_STUDY_CARRIER   0x2
 132 #define ST_STUDY_ALL_RECV  0x4
 133
 134 /* wake states */
 135 #define ST_WAKE_NONE    0x0
 136 #define ST_WAKE_START   0x1
 137 #define ST_WAKE_FINISH  0x2
 138
 139 /* receive states */
 140 #define ST_RX_WAIT_7F           0x1
 141 #define ST_RX_WAIT_HEAD         0x2
 142 #define ST_RX_WAIT_SILENT_END   0x4
 143
 144 /* send states */
 145 #define ST_TX_NONE      0x0
 146 #define ST_TX_REQUEST   0x2
 147 #define ST_TX_REPLY     0x4
 148
 149 /* buffer packet constants */
 150 #define BUF_PULSE_BIT   0x80
 151 #define BUF_LEN_MASK    0x7f
 152 #define BUF_REPEAT_BYTE 0x70
 153 #define BUF_REPEAT_MASK 0xf0
 154
 155 /* CIR settings */
 156
 157 /* total length of CIR and CIR WAKE */
 158 #define CIR_IOREG_LENGTH        0x0f
 159
 160 /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL (0x7d0 = 2000) */
 161 #define CIR_RX_LIMIT_COUNT      0x7d0
 162
 163 /* CIR Regs */
 164 #define CIR_IRCON       0x00
 165 #define CIR_IRSTS       0x01
 166 #define CIR_IREN        0x02
 167 #define CIR_RXFCONT     0x03
 168 #define CIR_CP          0x04
 169 #define CIR_CC          0x05
 170 #define CIR_SLCH        0x06
 171 #define CIR_SLCL        0x07
 172 #define CIR_FIFOCON     0x08
 173 #define CIR_IRFIFOSTS   0x09
 174 #define CIR_SRXFIFO     0x0a
 175 #define CIR_TXFCONT     0x0b
 176 #define CIR_STXFIFO     0x0c
 177 #define CIR_FCCH        0x0d
 178 #define CIR_FCCL        0x0e
 179 #define CIR_IRFSM       0x0f
 180
 181 /* CIR IRCON settings */
 182 #define CIR_IRCON_RECV   0x80
 183 #define CIR_IRCON_WIREN  0x40
 184 #define CIR_IRCON_TXEN   0x20
 185 #define CIR_IRCON_RXEN   0x10
 186 #define CIR_IRCON_WRXINV 0x08
 187 #define CIR_IRCON_RXINV  0x04
 188
 189 #define CIR_IRCON_SAMPLE_PERIOD_SEL_1   0x00
 190 #define CIR_IRCON_SAMPLE_PERIOD_SEL_25  0x01
 191 #define CIR_IRCON_SAMPLE_PERIOD_SEL_50  0x02
 192 #define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03
 193
 194 /* FIXME: make this a runtime option */
 195 /* select sample period as 50us */
 196 #define CIR_IRCON_SAMPLE_PERIOD_SEL     CIR_IRCON_SAMPLE_PERIOD_SEL_50
 197
 198 /* CIR IRSTS settings */
 199 #define CIR_IRSTS_RDR   0x80
 200 #define CIR_IRSTS_RTR   0x40
 201 #define CIR_IRSTS_PE    0x20
 202 #define CIR_IRSTS_RFO   0x10
 203 #define CIR_IRSTS_TE    0x08
 204 #define CIR_IRSTS_TTR   0x04
 205 #define CIR_IRSTS_TFU   0x02
 206 #define CIR_IRSTS_GH    0x01
 207
 208 /* CIR IREN settings */
 209 #define CIR_IREN_RDR    0x80
 210 #define CIR_IREN_RTR    0x40
 211 #define CIR_IREN_PE     0x20
 212 #define CIR_IREN_RFO    0x10
 213 #define CIR_IREN_TE     0x08
 214 #define CIR_IREN_TTR    0x04
 215 #define CIR_IREN_TFU    0x02
 216 #define CIR_IREN_GH     0x01
 217
 218 /* CIR FIFOCON settings */
 219 #define CIR_FIFOCON_TXFIFOCLR           0x80
 220
 221 #define CIR_FIFOCON_TX_TRIGGER_LEV_31   0x00
 222 #define CIR_FIFOCON_TX_TRIGGER_LEV_24   0x10
 223 #define CIR_FIFOCON_TX_TRIGGER_LEV_16   0x20
 224 #define CIR_FIFOCON_TX_TRIGGER_LEV_8    0x30
 225
 226 /* FIXME: make this a runtime option */
 227 /* select TX trigger level as 16 */
 228 #define CIR_FIFOCON_TX_TRIGGER_LEV      CIR_FIFOCON_TX_TRIGGER_LEV_16
 229
 230 #define CIR_FIFOCON_RXFIFOCLR           0x08
 231
 232 #define CIR_FIFOCON_RX_TRIGGER_LEV_1    0x00
 233 #define CIR_FIFOCON_RX_TRIGGER_LEV_8    0x01
 234 #define CIR_FIFOCON_RX_TRIGGER_LEV_16   0x02
 235 #define CIR_FIFOCON_RX_TRIGGER_LEV_24   0x03
 236
 237 /* FIXME: make this a runtime option */
 238 /* select RX trigger level as 24 */
 239 #define CIR_FIFOCON_RX_TRIGGER_LEV      CIR_FIFOCON_RX_TRIGGER_LEV_24
 240
 241 /* CIR IRFIFOSTS settings */
 242 #define CIR_IRFIFOSTS_IR_PENDING        0x80
 243 #define CIR_IRFIFOSTS_RX_GS             0x40
 244 #define CIR_IRFIFOSTS_RX_FTA            0x20
 245 #define CIR_IRFIFOSTS_RX_EMPTY          0x10
 246 #define CIR_IRFIFOSTS_RX_FULL           0x08
 247 #define CIR_IRFIFOSTS_TX_FTA            0x04
 248 #define CIR_IRFIFOSTS_TX_EMPTY          0x02
 249 #define CIR_IRFIFOSTS_TX_FULL           0x01
 250
 251
 252 /* CIR WAKE UP Regs */
 253 #define CIR_WAKE_IRCON                  0x00
 254 #define CIR_WAKE_IRSTS                  0x01
 255 #define CIR_WAKE_IREN                   0x02
 256 #define CIR_WAKE_FIFO_CMP_DEEP          0x03
 257 #define CIR_WAKE_FIFO_CMP_TOL           0x04
 258 #define CIR_WAKE_FIFO_COUNT             0x05
 259 #define CIR_WAKE_SLCH                   0x06
 260 #define CIR_WAKE_SLCL                   0x07
 261 #define CIR_WAKE_FIFOCON                0x08
 262 #define CIR_WAKE_SRXFSTS                0x09
 263 #define CIR_WAKE_SAMPLE_RX_FIFO         0x0a
 264 #define CIR_WAKE_WR_FIFO_DATA           0x0b
 265 #define CIR_WAKE_RD_FIFO_ONLY           0x0c
 266 #define CIR_WAKE_RD_FIFO_ONLY_IDX       0x0d
 267 #define CIR_WAKE_FIFO_IGNORE            0x0e
 268 #define CIR_WAKE_IRFSM                  0x0f
 269
 270 /* CIR WAKE UP IRCON settings */
 271 #define CIR_WAKE_IRCON_DEC_RST          0x80
 272 #define CIR_WAKE_IRCON_MODE1            0x40
 273 #define CIR_WAKE_IRCON_MODE0            0x20
 274 #define CIR_WAKE_IRCON_RXEN             0x10
 275 #define CIR_WAKE_IRCON_R                0x08
 276 #define CIR_WAKE_IRCON_RXINV            0x04
 277
 278 /* FIXME/jarod: make this a runtime option */
 279 /* select a same sample period like cir register */
 280 #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL        CIR_IRCON_SAMPLE_PERIOD_SEL_50
 281
 282 /* CIR WAKE IRSTS Bits */
 283 #define CIR_WAKE_IRSTS_RDR              0x80
 284 #define CIR_WAKE_IRSTS_RTR              0x40
 285 #define CIR_WAKE_IRSTS_PE               0x20
 286 #define CIR_WAKE_IRSTS_RFO              0x10
 287 #define CIR_WAKE_IRSTS_GH               0x08
 288 #define CIR_WAKE_IRSTS_IR_PENDING       0x01
 289
 290 /* CIR WAKE UP IREN Bits */
 291 #define CIR_WAKE_IREN_RDR               0x80
 292 #define CIR_WAKE_IREN_RTR               0x40
 293 #define CIR_WAKE_IREN_PE                0x20
 294 #define CIR_WAKE_IREN_RFO               0x10
 295 #define CIR_WAKE_IREN_TE                0x08
 296 #define CIR_WAKE_IREN_TTR               0x04
 297 #define CIR_WAKE_IREN_TFU               0x02
 298 #define CIR_WAKE_IREN_GH                0x01
 299
 300 /* CIR WAKE FIFOCON settings */
 301 #define CIR_WAKE_FIFOCON_RXFIFOCLR      0x08
 302
 303 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67      0x00
 304 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66      0x01
 305 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65      0x02
 306 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64      0x03
 307
 308 /* FIXME: make this a runtime option */
 309 /* select WAKE UP RX trigger level as 67 */
 310 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67
 311
 312 /* CIR WAKE SRXFSTS settings */
 313 #define CIR_WAKE_IRFIFOSTS_RX_GS        0x80
 314 #define CIR_WAKE_IRFIFOSTS_RX_FTA       0x40
 315 #define CIR_WAKE_IRFIFOSTS_RX_EMPTY     0x20
 316 #define CIR_WAKE_IRFIFOSTS_RX_FULL      0x10
 317
 318 /*
 319  * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes
 320  * the system comparing only 65 bytes (fails with this set to 67)
 321  */
 322 #define CIR_WAKE_FIFO_CMP_BYTES         65
 323 /* CIR Wake byte comparison tolerance */
 324 #define CIR_WAKE_CMP_TOLERANCE          5
 325
 326 /*
 327  * Extended Function Enable Registers:
 328  *  Extended Function Index Register
 329  *  Extended Function Data Register
 330  */
 331 #define CR_EFIR                 0x2e
 332 #define CR_EFDR                 0x2f
 333
 334 /* Possible alternate EFER values, depends on how the chip is wired */
 335 #define CR_EFIR2                0x4e
 336 #define CR_EFDR2                0x4f
 337
 338 /* Extended Function Mode enable/disable magic values */
 339 #define EFER_EFM_ENABLE         0x87
 340 #define EFER_EFM_DISABLE        0xaa
 341
 342 /* Config regs we need to care about */
 343 #define CR_SOFTWARE_RESET       0x02
 344 #define CR_LOGICAL_DEV_SEL      0x07
 345 #define CR_CHIP_ID_HI           0x20
 346 #define CR_CHIP_ID_LO           0x21
 347 #define CR_DEV_POWER_DOWN       0x22 /* bit 2 is CIR power, default power on */
 348 #define CR_OUTPUT_PIN_SEL       0x27
 349 #define CR_MULTIFUNC_PIN_SEL    0x2c
 350 #define CR_LOGICAL_DEV_EN       0x30 /* valid for all logical devices */
 351 /* next three regs valid for both the CIR and CIR_WAKE logical devices */
 352 #define CR_CIR_BASE_ADDR_HI     0x60
 353 #define CR_CIR_BASE_ADDR_LO     0x61
 354 #define CR_CIR_IRQ_RSRC         0x70
 355 /* next three regs valid only for ACPI logical dev */
 356 #define CR_ACPI_CIR_WAKE        0xe0
 357 #define CR_ACPI_IRQ_EVENTS      0xf6
 358 #define CR_ACPI_IRQ_EVENTS2     0xf7
 359
 360 /* Logical devices that we need to care about */
 361 #define LOGICAL_DEV_LPT         0x01
 362 #define LOGICAL_DEV_CIR         0x06
 363 #define LOGICAL_DEV_ACPI        0x0a
 364 #define LOGICAL_DEV_CIR_WAKE    0x0e
 365
 366 #define LOGICAL_DEV_DISABLE     0x00
 367 #define LOGICAL_DEV_ENABLE      0x01
 368
 369 #define CIR_WAKE_ENABLE_BIT     0x08
 370 #define PME_INTR_CIR_PASS_BIT   0x08
 371
 372 /* w83677hg CIR pin config */
 373 #define OUTPUT_PIN_SEL_MASK     0xbc
 374 #define OUTPUT_ENABLE_CIR       0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
 375 #define OUTPUT_ENABLE_CIRWB     0x40 /* enable wide-band sensor */
 376
 377 /* w83667hg CIR pin config */
 378 #define MULTIFUNC_PIN_SEL_MASK  0x1f
 379 #define MULTIFUNC_ENABLE_CIR    0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
 380 #define MULTIFUNC_ENABLE_CIRWB  0x20 /* enable wide-band sensor */
 381
 382 /* MCE CIR signal length, related on sample period */
 383
 384 /* MCE CIR controller signal length: about 43ms
 385  * 43ms / 50us (sample period) * 0.85 (inaccuracy)
 386  */
 387 #define CONTROLLER_BUF_LEN_MIN 830
 388
 389 /* MCE CIR keyboard signal length: about 26ms
 390  * 26ms / 50us (sample period) * 0.85 (inaccuracy)
 391  */
 392 #define KEYBOARD_BUF_LEN_MAX 650
 393 #define KEYBOARD_BUF_LEN_MIN 610
 394
 395 /* MCE CIR mouse signal length: about 24ms
 396  * 24ms / 50us (sample period) * 0.85 (inaccuracy)
 397  */
 398 #define MOUSE_BUF_LEN_MIN 565
 399
 400 #define CIR_SAMPLE_PERIOD 50
 401 #define CIR_SAMPLE_LOW_INACCURACY 0.85
 402
 403 /* MAX silence time that driver will sent to lirc */
 404 #define MAX_SILENCE_TIME 60000
 405
 406 #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100
 407 #define SAMPLE_PERIOD 100
 408
 409 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50
 410 #define SAMPLE_PERIOD 50
 411
 412 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25
 413 #define SAMPLE_PERIOD 25
 414
 415 #else
 416 #define SAMPLE_PERIOD 1
 417 #endif
 418
 419 /* as VISTA MCE definition, valid carrier value */
 420 #define MAX_CARRIER 60000
 421 #define MIN_CARRIER 30000